testbench.sv.bak

`timescale 1ns/1ps

module uart_tb();

	localparam CLOCKS_PER_PULSE = 16,
	logic [7:0] data_in = 0;
	logic clk = 0;
	logic rstn = 1;
	logic enable = 1;

	logic tx_busy;
	logic ready;
	logic [7:0] data_out;

	logic loopback;
	logic ready_clr = 1;

	uart #(.CLOCKS_PER_PULSE(CLOCKS_PER_PULSE)) 
			test_uart(.data_in(data_in),
						.data_en(enable),
						.clk(clk),
						.tx(loopback),
						.tx_busy(tx_busy),
						.rx(loopback),
						.ready(ready),
						.ready_clr(ready_clr),
						.data_out(data_out),
						.rstn(rstn)
						);
	initial begin
		$dumpfile("uart.vcd");
		$dumpvars(0, uart_tb);
		enable <= 1'b0;
		#2 enable <= 1'b1;
	end
	always begin
		#1 clk = ~clk;
	end
	always @(posedge ready) begin
		#2 ready_clr <= 0;
		#2 ready_clr <= 1;
		if (data_out != data_in) begin
			$display("FAIL: rx data %x does not match tx %x", data_out, data_in);
			$finish;
		end 
		else begin
			if (data_out == 8'h2) begin //Check if received data is 11111111
				$display("SUCCESS: all bytes verified");
				$finish();
			end
			data <= data + 1'b1;
			enable <= 1'b0;
			#2 enable <= 1'b1;
		end
	end
endmodule