Sata 2 Host Controller for FPGA implimentation. SATA is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives and optical drives .The SATA Host Controller IP is able to transfer data to and from a SATA device.
Features of the IP core are
- Fully compliant with the Serial ATA specification revision 2.0
- Simple transaction interface with Host processor
- 32-bit internal data path
- IP Core system clock of 37.5MHz and PHY clock 75MHz for SATA-I
- IP Core system clock of 75.0MHz and PHY clock 150MHz for SATA-II
- Supports 1.5 Gbit/s and 3.0 Gbit/s data transfer rates
- Supports DMA and PIO commands
- Hardware support for Speed auto negotiation for SATA I/II
- 48-bit address set
- Detection of OOB, COMWAKE, K28.5, etc.
- 8b/10b coding and decoding
- CRC generation and checking
- Implements the shadow register block and the SATA status and control registers
- Target FPGA : Xilinx Virtex5