diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 81966ac06..49279a20f 100755 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -6,12 +6,21 @@ on: - main - dev - scala_opencb + paths-ignore: + - 'docs/**' + - 'docs_overrides/**' + - 'mkdocs.yml' + - '.github/workflows/dfdocs.yml' pull_request: branches: - main - dev - scala_opencb - + paths-ignore: + - 'docs/**' + - 'docs_overrides/**' + - 'mkdocs.yml' + - '.github/workflows/dfdocs.yml' jobs: build: runs-on: ubuntu-latest diff --git a/.github/workflows/dfdocs.yml b/.github/workflows/dfdocs.yml index c5692d78d..0a6b0689d 100755 --- a/.github/workflows/dfdocs.yml +++ b/.github/workflows/dfdocs.yml @@ -5,10 +5,24 @@ on: branches: - main - dev + paths: + - 'docs/**' + - 'docs_overrides/**' + - 'mkdocs.yml' + - '.github/workflows/dfdocs.yml' + - 'lib/src/test/scala/docExamples/**' + - 'lib/src/test/resources/ref/**' pull_request: branches: - main - dev + paths: + - 'docs/**' + - 'docs_overrides/**' + - 'mkdocs.yml' + - '.github/workflows/dfdocs.yml' + - 'lib/src/test/scala/docExamples/**' + - 'lib/src/test/resources/ref/**' jobs: build: diff --git a/build.sbt b/build.sbt index 9b3287c63..e775b9710 100755 --- a/build.sbt +++ b/build.sbt @@ -1,4 +1,5 @@ commands += DFHDLCommands.quickTestSetup +commands += DFHDLCommands.docExamplesRefUpdate // format: off val projectName = "dfhdl" diff --git a/docs/css/user-guide.css b/docs/css/user-guide.css new file mode 100644 index 000000000..036b10233 --- /dev/null +++ b/docs/css/user-guide.css @@ -0,0 +1,4 @@ +/* different styles for tabs inside tabs */ +html.js-focus-visible.js body div.md-container main.md-main div.md-main__inner.md-grid div.md-content article.md-content__inner.md-typeset div.admonition div.tabbed-set.tabbed-alternate div.tabbed-content div.tabbed-block div.tabbed-set.tabbed-alternate div.tabbed-labels.tabbed-labels--linked label a { + font-size: smaller; +} \ No newline at end of file diff --git a/docs/user-guide/connectivity/index.md b/docs/user-guide/connectivity/index.md index be52cb7b1..547acfece 100755 --- a/docs/user-guide/connectivity/index.md +++ b/docs/user-guide/connectivity/index.md @@ -117,17 +117,7 @@ The DFHDL code below implements a two-bits left shifter design named `LeftShift2
```scala -import dfhdl.* -//optionally set the default backend configuration option -//(can be overridden by the top-app CLI) -given options.CompilerOptions.Backend = backends.verilog -/** A two-bits left shifter */ -@top class LeftShift2 extends RTDesign: - /** bits input */ - val iBits = Bits(8) <> IN - /** bits output */ - val oBits = Bits(8) <> OUT - oBits := iBits << 2 +--8<-- "lib/src/test/scala/docExamples/ugdemos/demo1/LeftShift2.scala:3" ``` ```hdelk width=100% @@ -151,64 +141,21 @@ children = [ This design is also a top-app design, since it's annotated with `@top`. This means that we have an executable Scala program that compiles the design and generates a Verilog or VHDL backend code. The backend configuration option can be set via a CLI argument, or alternatively, be set via an implicit backend setting like in the code above. The `@top` annotation captures the [implicit/given](https://docs.scala-lang.org/scala3/book/ca-context-parameters.html#given-instances-implicit-definitions-in-scala-2){target="_blank"} options within its scope and feeds them to the top-app CLI program as default to run when no CLI arguments are given. /// tab | Generated Verilog - ```verilog -/* A two-bits left shifter */ -`default_nettype none -`timescale 1ns/1ps -`include "LeftShift2_defs.svh" - -module LeftShift2( - /* bits input */ - input wire logic [7:0] iBits, - /* bits output */ - output logic [7:0] oBits -); - `include "dfhdl_defs.svh" - assign oBits = iBits << 2; -endmodule +--8<-- "lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.sv2009/hdl/LeftShift2.sv" ``` /// /// tab | Generated VHDL ```vhdl --- A two-bits left shifter -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.dfhdl_pkg.all; -use work.LeftShift2_pkg.all; - -entity LeftShift2 is -port ( - -- bits input - iBits : in std_logic_vector(7 downto 0); - -- bits output - oBits : out std_logic_vector(7 downto 0) -); -end LeftShift2; - -architecture LeftShift2_arch of LeftShift2 is -begin - oBits <= slv_sll(iBits, 2); -end LeftShift2_arch; +--8<-- "lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v2008/hdl/LeftShift2.vhd" ``` /// /// details | Runnable example type: dfhdl ```scastie -import dfhdl.* -//optionally set the default backend configuration option -//(can be overridden by the top-app CLI) -given options.CompilerOptions.Backend = backends.verilog -/** A two-bits left shifter */ -@top class LeftShift2 extends RTDesign: - /** bits input */ - val iBits = Bits(8) <> IN - /** bits output */ - val oBits = Bits(8) <> OUT - oBits := iBits << 2 +--8<-- "lib/src/test/scala/docExamples/ugdemos/demo1/LeftShift2.scala:3" ``` /// /// @@ -236,17 +183,7 @@ The DFHDL code below implements a basic left shifter design named `LeftShiftBasi
```scala -/** A basic left shifter */ -@top class LeftShiftBasic( - val width: Int = 8, -) extends RTDesign: - /** bits input */ - val iBits = Bits(width) <> IN - /** requested shift */ - val shift = UInt.until(width) <> IN - /** bits output */ - val oBits = Bits(width) <> OUT - oBits := iBits << shift +--8<-- "lib/src/test/scala/docExamples/ugdemos/demo2/LeftShiftBasic.scala:6" ``` ```hdelk width=90% @@ -271,70 +208,21 @@ children = [
/// tab | Generated Verilog - ```verilog -/* A basic left shifter */ -`default_nettype none -`timescale 1ns/1ps -`include "LeftShiftBasic_defs.svh" - -module LeftShiftBasic( - /* bits input */ - input wire logic [7:0] iBits, - /* requested shift */ - input wire logic [2:0] shift, - /* bits output */ - output logic [7:0] oBits -); - `include "dfhdl_defs.svh" - assign oBits = iBits << shift; -endmodule +--8<-- "lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.sv2009/hdl/LeftShiftBasic.sv" ``` /// /// tab | Generated VHDL ```vhdl --- A basic left shifter -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.dfhdl_pkg.all; -use work.LeftShiftBasic_pkg.all; - -entity LeftShiftBasic is -port ( - -- bits input - iBits : in std_logic_vector(7 downto 0); - -- requested shift - shift : in unsigned(2 downto 0); - -- bits output - oBits : out std_logic_vector(7 downto 0) -); -end LeftShiftBasic; - -architecture LeftShiftBasic_arch of LeftShiftBasic is -begin - oBits <= slv_sll(iBits, to_integer(shift)); -end LeftShiftBasic_arch; +--8<-- "lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v2008/hdl/LeftShiftBasic.vhd" ``` /// /// details | Runnable example type: dfhdl ```scastie -import dfhdl.* -given options.CompilerOptions.Backend = backends.verilog -/** A basic left shifter */ -@top class LeftShiftBasic( - val width: Int = 8, -) extends RTDesign: - /** bits input */ - val iBits = Bits(width) <> IN - /** requested shift */ - val shift = UInt.until(width) <> IN - /** bits output */ - val oBits = Bits(width) <> OUT - oBits := iBits << shift +--8<-- "lib/src/test/scala/docExamples/ugdemos/demo2/LeftShiftBasic.scala:3" ``` /// /// @@ -345,21 +233,7 @@ The DFHDL code below implements a generic left shifter design named `LeftShiftGe
```scala -/** A generic left shifter - * - * @param width - * the width of the input and output bits - */ -@top class LeftShiftGen( - val width: Int <> CONST = 8, -) extends RTDesign: - /** bits input */ - val iBits = Bits(width) <> IN - /** requested shift */ - val shift = UInt.until(width) <> IN - /** bits output */ - val oBits = Bits(width) <> OUT - oBits := iBits << shift +--8<-- "lib/src/test/scala/docExamples/ugdemos/demo3/LeftShiftGen.scala:6" ``` ```hdelk width=90% @@ -384,84 +258,21 @@ children = [
/// tab | Generated Verilog - ```verilog -/* A generic left shifter - - @param width - the width of the input and output bits - */ -`default_nettype none -`timescale 1ns/1ps -`include "LeftShiftGen_defs.svh" - -module LeftShiftGen#(parameter int width = 8)( - /* bits input */ - input wire logic [width - 1:0] iBits, - /* requested shift */ - input wire logic [$clog2(width) - 1:0] shift, - /* bits output */ - output logic [width - 1:0] oBits -); - `include "dfhdl_defs.svh" - assign oBits = iBits << shift; -endmodule +--8<-- "lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.sv2009/hdl/LeftShiftGen.sv" ``` /// /// tab | Generated VHDL ```vhdl --- A generic left shifter --- --- @param width --- the width of the input and output bits -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.dfhdl_pkg.all; -use work.LeftShiftGen_pkg.all; - -entity LeftShiftGen is -generic ( - width : integer := 8 -); -port ( - -- bits input - iBits : in std_logic_vector(width - 1 downto 0); - -- requested shift - shift : in unsigned(clog2(width) - 1 downto 0); - -- bits output - oBits : out std_logic_vector(width - 1 downto 0) -); -end LeftShiftGen; - -architecture LeftShiftGen_arch of LeftShiftGen is -begin - oBits <= slv_sll(iBits, to_integer(shift)); -end LeftShiftGen_arch; +--8<-- "lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v2008/hdl/LeftShiftGen.vhd" ``` /// /// details | Runnable example type: dfhdl ```scastie -import dfhdl.* -given options.CompilerOptions.Backend = backends.verilog -/** A generic left shifter - * - * @param width - * the width of the input and output bits - */ -@top class LeftShiftGen( - val width: Int <> CONST = 8, -) extends RTDesign: - /** bits input */ - val iBits = Bits(width) <> IN - /** requested shift */ - val shift = UInt.until(width) <> IN - /** bits output */ - val oBits = Bits(width) <> OUT - oBits := iBits << shift +--8<-- "lib/src/test/scala/docExamples/ugdemos/demo3/LeftShiftGen.scala:3" ``` /// /// diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.sv2009/hdl/ALU.sv b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.sv2009/hdl/ALU.sv new file mode 100644 index 000000000..778e12d6f --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.sv2009/hdl/ALU.sv @@ -0,0 +1,33 @@ +`default_nettype none +`timescale 1ns/1ps +`include "ALU_defs.svh" + +module ALU( + input wire logic [31:0] op1, + input wire logic [31:0] op2, + input wire t_enum_ALUSel aluSel, + output logic [31:0] aluOut +); + `include "dfhdl_defs.svh" + logic [4:0] shamt; + logic [31:0] outCalc; + always_comb + begin + case (aluSel) + ALUSel_ADD: outCalc = op1 + op2; + ALUSel_SUB: outCalc = op1 - op2; + ALUSel_AND: outCalc = op1 & op2; + ALUSel_OR: outCalc = op1 | op2; + ALUSel_XOR: outCalc = op1 ^ op2; + ALUSel_SLT: outCalc = {{(32-1){1'b0}}, {$signed(op1) < $signed(op2)}}; + ALUSel_SLTU: outCalc = {{(32-1){1'b0}}, {op1 < op2}}; + ALUSel_SLL: outCalc = op1 << shamt; + ALUSel_SRL: outCalc = op1 >> shamt; + ALUSel_SRA: outCalc = {$signed(op1) >>> shamt}; + ALUSel_COPY1: outCalc = op1; + default: outCalc = 32'h????????; + endcase + end + assign shamt = op2[4:0]; + assign aluOut = outCalc; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.sv2009/hdl/ALU_defs.svh b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.sv2009/hdl/ALU_defs.svh new file mode 100644 index 000000000..35abc79da --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.sv2009/hdl/ALU_defs.svh @@ -0,0 +1,17 @@ +`ifndef ALU_DEFS +`define ALU_DEFS +typedef enum logic [3:0] { + ALUSel_ADD = 0, + ALUSel_SUB = 1, + ALUSel_SLL = 2, + ALUSel_SRL = 3, + ALUSel_SRA = 4, + ALUSel_AND = 5, + ALUSel_OR = 6, + ALUSel_XOR = 7, + ALUSel_SLT = 8, + ALUSel_SLTU = 9, + ALUSel_COPY1 = 10 +} t_enum_ALUSel; + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v2001/hdl/ALU.v b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v2001/hdl/ALU.v new file mode 100644 index 000000000..7f2301fae --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v2001/hdl/ALU.v @@ -0,0 +1,33 @@ +`default_nettype none +`timescale 1ns/1ps +`include "ALU_defs.vh" + +module ALU( + input wire [31:0] op1, + input wire [31:0] op2, + input wire [3:0] aluSel, + output wire [31:0] aluOut +); + `include "dfhdl_defs.vh" + wire [4:0] shamt; + reg [31:0] outCalc; + always @(*) + begin + case (aluSel) + `ALUSel_ADD: outCalc = op1 + op2; + `ALUSel_SUB: outCalc = op1 - op2; + `ALUSel_AND: outCalc = op1 & op2; + `ALUSel_OR: outCalc = op1 | op2; + `ALUSel_XOR: outCalc = op1 ^ op2; + `ALUSel_SLT: outCalc = {{(32-1){1'b0}}, {$signed(op1) < $signed(op2)}}; + `ALUSel_SLTU: outCalc = {{(32-1){1'b0}}, {op1 < op2}}; + `ALUSel_SLL: outCalc = op1 << shamt; + `ALUSel_SRL: outCalc = op1 >> shamt; + `ALUSel_SRA: outCalc = {$signed(op1) >>> shamt}; + `ALUSel_COPY1: outCalc = op1; + default: outCalc = 32'h????????; + endcase + end + assign shamt = op2[4:0]; + assign aluOut = outCalc; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v2001/hdl/ALU_defs.vh b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v2001/hdl/ALU_defs.vh new file mode 100644 index 000000000..8ace9dea7 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v2001/hdl/ALU_defs.vh @@ -0,0 +1,15 @@ +`ifndef ALU_DEFS +`define ALU_DEFS +`define ALUSel_ADD 0 +`define ALUSel_SUB 1 +`define ALUSel_SLL 2 +`define ALUSel_SRL 3 +`define ALUSel_SRA 4 +`define ALUSel_AND 5 +`define ALUSel_OR 6 +`define ALUSel_XOR 7 +`define ALUSel_SLT 8 +`define ALUSel_SLTU 9 +`define ALUSel_COPY1 10 + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v95/hdl/ALU.v b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v95/hdl/ALU.v new file mode 100644 index 000000000..c000dc2fb --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v95/hdl/ALU.v @@ -0,0 +1,37 @@ +`default_nettype none +`timescale 1ns/1ps +`include "ALU_defs.vh" + +module ALU( + op1, + op2, + aluSel, + aluOut +); + `include "dfhdl_defs.vh" + input wire [31:0] op1; + input wire [31:0] op2; + input wire [3:0] aluSel; + output wire [31:0] aluOut; + wire [4:0] shamt; + reg [31:0] outCalc; + always @(aluSel or op1 or op2 or shamt) + begin + case (aluSel) + `ALUSel_ADD: outCalc = op1 + op2; + `ALUSel_SUB: outCalc = op1 - op2; + `ALUSel_AND: outCalc = op1 & op2; + `ALUSel_OR: outCalc = op1 | op2; + `ALUSel_XOR: outCalc = op1 ^ op2; + `ALUSel_SLT: outCalc = {{(32-1){1'b0}}, {`SIGNED_LESS_THAN(op1, op2, 32)}}; + `ALUSel_SLTU: outCalc = {{(32-1){1'b0}}, {op1 < op2}}; + `ALUSel_SLL: outCalc = op1 << shamt; + `ALUSel_SRL: outCalc = op1 >> shamt; + `ALUSel_SRA: outCalc = {`SIGNED_SHIFT_RIGHT(op1, shamt, 32)}; + `ALUSel_COPY1: outCalc = op1; + default: outCalc = 32'h????????; + endcase + end + assign shamt = op2[4:0]; + assign aluOut = outCalc; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v95/hdl/ALU_defs.vh b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v95/hdl/ALU_defs.vh new file mode 100644 index 000000000..8ace9dea7 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/verilog.v95/hdl/ALU_defs.vh @@ -0,0 +1,15 @@ +`ifndef ALU_DEFS +`define ALU_DEFS +`define ALUSel_ADD 0 +`define ALUSel_SUB 1 +`define ALUSel_SLL 2 +`define ALUSel_SRL 3 +`define ALUSel_SRA 4 +`define ALUSel_AND 5 +`define ALUSel_OR 6 +`define ALUSel_XOR 7 +`define ALUSel_SLT 8 +`define ALUSel_SLTU 9 +`define ALUSel_COPY1 10 + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v2008/hdl/ALU.vhd b/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v2008/hdl/ALU.vhd new file mode 100644 index 000000000..a581175a2 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v2008/hdl/ALU.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.ALU_pkg.all; + +entity ALU is +port ( + op1 : in std_logic_vector(31 downto 0); + op2 : in std_logic_vector(31 downto 0); + aluSel : in t_enum_ALUSel; + aluOut : out std_logic_vector(31 downto 0) +); +end ALU; + +architecture ALU_arch of ALU is + signal shamt : std_logic_vector(4 downto 0); + signal outCalc : std_logic_vector(31 downto 0); +begin + process (all) + begin + case aluSel is + when ALUSel_ADD => outCalc <= to_slv(unsigned(op1) + unsigned(op2)); + when ALUSel_SUB => outCalc <= to_slv(unsigned(op1) - unsigned(op2)); + when ALUSel_AND => outCalc <= op1 and op2; + when ALUSel_OR => outCalc <= op1 or op2; + when ALUSel_XOR => outCalc <= op1 xor op2; + when ALUSel_SLT => outCalc <= resize(to_slv(signed(op1) < signed(op2)), 32); + when ALUSel_SLTU => outCalc <= resize(to_slv(unsigned(op1) < unsigned(op2)), 32); + when ALUSel_SLL => outCalc <= slv_sll(op1, to_integer(unsigned(shamt))); + when ALUSel_SRL => outCalc <= slv_srl(op1, to_integer(unsigned(shamt))); + when ALUSel_SRA => outCalc <= to_slv(signed_sra(signed(op1), to_integer(unsigned(shamt)))); + when ALUSel_COPY1 => outCalc <= op1; + when others => outCalc <= x"--------"; + end case; + end process; + shamt <= op2(4 downto 0); + aluOut <= outCalc; +end ALU_arch; diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v2008/hdl/ALU_pkg.vhd b/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v2008/hdl/ALU_pkg.vhd new file mode 100644 index 000000000..b68c41b0b --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v2008/hdl/ALU_pkg.vhd @@ -0,0 +1,69 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package ALU_pkg is +type t_enum_ALUSel is ( + ALUSel_ADD, ALUSel_SUB, ALUSel_SLL, ALUSel_SRL, ALUSel_SRA, ALUSel_AND, ALUSel_OR, ALUSel_XOR, ALUSel_SLT, ALUSel_SLTU, ALUSel_COPY1 +); +function bitWidth(A: t_enum_ALUSel) return integer; +function to_slv(A: t_enum_ALUSel) return std_logic_vector; +function to_t_enum_ALUSel(A: std_logic_vector) return t_enum_ALUSel; +function bool_sel(C : boolean; T : t_enum_ALUSel; F : t_enum_ALUSel) return t_enum_ALUSel; + + +end package ALU_pkg; + +package body ALU_pkg is +function bitWidth(A : t_enum_ALUSel) return integer is +begin + return 4; +end; +function to_slv(A : t_enum_ALUSel) return std_logic_vector is + variable int_val : integer; +begin + case A is + when ALUSel_ADD => int_val := 0; + when ALUSel_SUB => int_val := 1; + when ALUSel_SLL => int_val := 2; + when ALUSel_SRL => int_val := 3; + when ALUSel_SRA => int_val := 4; + when ALUSel_AND => int_val := 5; + when ALUSel_OR => int_val := 6; + when ALUSel_XOR => int_val := 7; + when ALUSel_SLT => int_val := 8; + when ALUSel_SLTU => int_val := 9; + when ALUSel_COPY1 => int_val := 10; + end case; + return resize(to_slv(int_val), 4); +end; +function to_t_enum_ALUSel(A : std_logic_vector) return t_enum_ALUSel is +begin + case to_integer(unsigned(A)) is + when 0 => return ALUSel_ADD; + when 1 => return ALUSel_SUB; + when 2 => return ALUSel_SLL; + when 3 => return ALUSel_SRL; + when 4 => return ALUSel_SRA; + when 5 => return ALUSel_AND; + when 6 => return ALUSel_OR; + when 7 => return ALUSel_XOR; + when 8 => return ALUSel_SLT; + when 9 => return ALUSel_SLTU; + when 10 => return ALUSel_COPY1; + when others => + assert false report "Unknown state detected!" severity error; + return ALUSel_ADD; + end case; +end; +function bool_sel(C : boolean; T : t_enum_ALUSel; F : t_enum_ALUSel) return t_enum_ALUSel is +begin + if C then + return T; + else + return F; + end if; +end; + +end package body ALU_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v93/hdl/ALU.vhd b/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v93/hdl/ALU.vhd new file mode 100644 index 000000000..41d76caec --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v93/hdl/ALU.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.ALU_pkg.all; + +entity ALU is +port ( + op1 : in std_logic_vector(31 downto 0); + op2 : in std_logic_vector(31 downto 0); + aluSel : in t_enum_ALUSel; + aluOut : out std_logic_vector(31 downto 0) +); +end ALU; + +architecture ALU_arch of ALU is + signal shamt : std_logic_vector(4 downto 0); + signal outCalc : std_logic_vector(31 downto 0); +begin + process (aluSel, op1, op2, shamt) + begin + case aluSel is + when ALUSel_ADD => outCalc <= to_slv(unsigned(op1) + unsigned(op2)); + when ALUSel_SUB => outCalc <= to_slv(unsigned(op1) - unsigned(op2)); + when ALUSel_AND => outCalc <= op1 and op2; + when ALUSel_OR => outCalc <= op1 or op2; + when ALUSel_XOR => outCalc <= op1 xor op2; + when ALUSel_SLT => outCalc <= resize(to_slv(signed(op1) < signed(op2)), 32); + when ALUSel_SLTU => outCalc <= resize(to_slv(unsigned(op1) < unsigned(op2)), 32); + when ALUSel_SLL => outCalc <= slv_sll(op1, to_integer(unsigned(shamt))); + when ALUSel_SRL => outCalc <= slv_srl(op1, to_integer(unsigned(shamt))); + when ALUSel_SRA => outCalc <= to_slv(signed_sra(signed(op1), to_integer(unsigned(shamt)))); + when ALUSel_COPY1 => outCalc <= op1; + when others => outCalc <= "--------------------------------"; + end case; + end process; + shamt <= op2(4 downto 0); + aluOut <= outCalc; +end ALU_arch; diff --git a/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v93/hdl/ALU_pkg.vhd b/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v93/hdl/ALU_pkg.vhd new file mode 100644 index 000000000..b68c41b0b --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ALUSpec/vhdl.v93/hdl/ALU_pkg.vhd @@ -0,0 +1,69 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package ALU_pkg is +type t_enum_ALUSel is ( + ALUSel_ADD, ALUSel_SUB, ALUSel_SLL, ALUSel_SRL, ALUSel_SRA, ALUSel_AND, ALUSel_OR, ALUSel_XOR, ALUSel_SLT, ALUSel_SLTU, ALUSel_COPY1 +); +function bitWidth(A: t_enum_ALUSel) return integer; +function to_slv(A: t_enum_ALUSel) return std_logic_vector; +function to_t_enum_ALUSel(A: std_logic_vector) return t_enum_ALUSel; +function bool_sel(C : boolean; T : t_enum_ALUSel; F : t_enum_ALUSel) return t_enum_ALUSel; + + +end package ALU_pkg; + +package body ALU_pkg is +function bitWidth(A : t_enum_ALUSel) return integer is +begin + return 4; +end; +function to_slv(A : t_enum_ALUSel) return std_logic_vector is + variable int_val : integer; +begin + case A is + when ALUSel_ADD => int_val := 0; + when ALUSel_SUB => int_val := 1; + when ALUSel_SLL => int_val := 2; + when ALUSel_SRL => int_val := 3; + when ALUSel_SRA => int_val := 4; + when ALUSel_AND => int_val := 5; + when ALUSel_OR => int_val := 6; + when ALUSel_XOR => int_val := 7; + when ALUSel_SLT => int_val := 8; + when ALUSel_SLTU => int_val := 9; + when ALUSel_COPY1 => int_val := 10; + end case; + return resize(to_slv(int_val), 4); +end; +function to_t_enum_ALUSel(A : std_logic_vector) return t_enum_ALUSel is +begin + case to_integer(unsigned(A)) is + when 0 => return ALUSel_ADD; + when 1 => return ALUSel_SUB; + when 2 => return ALUSel_SLL; + when 3 => return ALUSel_SRL; + when 4 => return ALUSel_SRA; + when 5 => return ALUSel_AND; + when 6 => return ALUSel_OR; + when 7 => return ALUSel_XOR; + when 8 => return ALUSel_SLT; + when 9 => return ALUSel_SLTU; + when 10 => return ALUSel_COPY1; + when others => + assert false report "Unknown state detected!" severity error; + return ALUSel_ADD; + end case; +end; +function bool_sel(C : boolean; T : t_enum_ALUSel; F : t_enum_ALUSel) return t_enum_ALUSel is +begin + if C then + return T; + else + return F; + end if; +end; + +end package body ALU_pkg; diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.sv2009/hdl/Blinker.sv b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.sv2009/hdl/Blinker.sv new file mode 100644 index 000000000..894901300 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.sv2009/hdl/Blinker.sv @@ -0,0 +1,33 @@ +/* This is a led blinker */ +`default_nettype none +`timescale 1ns/1ps +`include "Blinker_defs.svh" + +module Blinker#( + parameter int CLK_FREQ_KHz = 50000, + parameter int LED_FREQ_Hz = 1 +)( + input wire logic clk, + input wire logic rst, + /* LED output */ + output logic led +); + `include "dfhdl_defs.svh" + /* Half-count of the toggle for 50% duty cycle */ + parameter int HALF_PERIOD = (CLK_FREQ_KHz * 1000) / (LED_FREQ_Hz * 2); + logic [$clog2(HALF_PERIOD) - 1:0] cnt; + always_ff @(posedge clk) + begin + if (rst == 1'b1) begin + led <= 1'b1; + cnt <= $clog2(HALF_PERIOD)'(0); + end + else begin + if (cnt == $clog2(HALF_PERIOD)'(HALF_PERIOD - 1)) begin + cnt <= $clog2(HALF_PERIOD)'(0); + led <= !led; + end + else cnt <= cnt + $clog2(HALF_PERIOD)'(1); + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.sv2009/hdl/Blinker_defs.svh b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.sv2009/hdl/Blinker_defs.svh new file mode 100644 index 000000000..f75b6fe25 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.sv2009/hdl/Blinker_defs.svh @@ -0,0 +1,4 @@ +`ifndef BLINKER_DEFS +`define BLINKER_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v2001/hdl/Blinker.v b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v2001/hdl/Blinker.v new file mode 100644 index 000000000..1542f850b --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v2001/hdl/Blinker.v @@ -0,0 +1,33 @@ +/* This is a led blinker */ +`default_nettype none +`timescale 1ns/1ps +`include "Blinker_defs.vh" + +module Blinker#( + parameter integer CLK_FREQ_KHz = 50000, + parameter integer LED_FREQ_Hz = 1 +)( + input wire clk, + input wire rst, + /* LED output */ + output reg led +); + `include "dfhdl_defs.vh" + /* Half-count of the toggle for 50% duty cycle */ + parameter integer HALF_PERIOD = (CLK_FREQ_KHz * 1000) / (LED_FREQ_Hz * 2); + reg [clog2(HALF_PERIOD) - 1:0] cnt; + always @(posedge clk) + begin + if (rst == 1'b1) begin + led <= 1'b1; + cnt <= `TO_UNSIGNED(0, 1, clog2(HALF_PERIOD)); + end + else begin + if (cnt == (HALF_PERIOD - 1)) begin + cnt <= `TO_UNSIGNED(0, 1, clog2(HALF_PERIOD)); + led <= !led; + end + else cnt <= cnt + `TO_UNSIGNED(1, 1, clog2(HALF_PERIOD)); + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v2001/hdl/Blinker_defs.vh b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v2001/hdl/Blinker_defs.vh new file mode 100644 index 000000000..f75b6fe25 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v2001/hdl/Blinker_defs.vh @@ -0,0 +1,4 @@ +`ifndef BLINKER_DEFS +`define BLINKER_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v95/hdl/Blinker.v b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v95/hdl/Blinker.v new file mode 100644 index 000000000..3e0eb039e --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v95/hdl/Blinker.v @@ -0,0 +1,35 @@ +/* This is a led blinker */ +`default_nettype none +`timescale 1ns/1ps +`include "Blinker_defs.vh" + +module Blinker( + clk, + rst, + led +); + `include "dfhdl_defs.vh" + parameter integer CLK_FREQ_KHz = 50000; + parameter integer LED_FREQ_Hz = 1; + /* Half-count of the toggle for 50% duty cycle */ + parameter integer HALF_PERIOD = (CLK_FREQ_KHz * 1000) / (LED_FREQ_Hz * 2); + input wire clk; + input wire rst; + /* LED output */ + output reg led; + reg [clog2(HALF_PERIOD) - 1:0] cnt; + always @(posedge clk) + begin + if (rst == 1'b1) begin + led <= 1'b1; + cnt <= `TO_UNSIGNED(0, 1, clog2(HALF_PERIOD)); + end + else begin + if (cnt == (HALF_PERIOD - 1)) begin + cnt <= `TO_UNSIGNED(0, 1, clog2(HALF_PERIOD)); + led <= !led; + end + else cnt <= cnt + `TO_UNSIGNED(1, 1, clog2(HALF_PERIOD)); + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v95/hdl/Blinker_defs.vh b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v95/hdl/Blinker_defs.vh new file mode 100644 index 000000000..f75b6fe25 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/verilog.v95/hdl/Blinker_defs.vh @@ -0,0 +1,4 @@ +`ifndef BLINKER_DEFS +`define BLINKER_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v2008/hdl/Blinker.vhd b/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v2008/hdl/Blinker.vhd new file mode 100644 index 000000000..1246ffb7e --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v2008/hdl/Blinker.vhd @@ -0,0 +1,41 @@ +-- This is a led blinker +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.Blinker_pkg.all; + +entity Blinker is +generic ( + CLK_FREQ_KHz : integer := 50000; + LED_FREQ_Hz : integer := 1 +); +port ( + clk : in std_logic; + rst : in std_logic; + -- LED output + led : out std_logic +); +end Blinker; + +architecture Blinker_arch of Blinker is + -- Half-count of the toggle for 50% duty cycle + constant HALF_PERIOD : integer := (CLK_FREQ_KHz * 1000) / (LED_FREQ_Hz * 2); + signal cnt : unsigned(clog2(HALF_PERIOD) - 1 downto 0); +begin + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then + led <= '1'; + cnt <= resize(d"0", clog2(HALF_PERIOD)); + else + if cnt = to_unsigned(HALF_PERIOD - 1, clog2(HALF_PERIOD)) then + cnt <= resize(d"0", clog2(HALF_PERIOD)); + led <= not led; + else cnt <= cnt + resize(d"1", clog2(HALF_PERIOD)); + end if; + end if; + end if; + end process; +end Blinker_arch; diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v2008/hdl/Blinker_pkg.vhd b/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v2008/hdl/Blinker_pkg.vhd new file mode 100644 index 000000000..9703c8522 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v2008/hdl/Blinker_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package Blinker_pkg is + +end package Blinker_pkg; + +package body Blinker_pkg is + +end package body Blinker_pkg; diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v93/hdl/Blinker.vhd b/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v93/hdl/Blinker.vhd new file mode 100644 index 000000000..cec07a688 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v93/hdl/Blinker.vhd @@ -0,0 +1,43 @@ +-- This is a led blinker +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.Blinker_pkg.all; + +entity Blinker is +generic ( + CLK_FREQ_KHz : integer := 50000; + LED_FREQ_Hz : integer := 1 +); +port ( + clk : in std_logic; + rst : in std_logic; + -- LED output + led : out std_logic +); +end Blinker; + +architecture Blinker_arch of Blinker is + -- Half-count of the toggle for 50% duty cycle + constant HALF_PERIOD : integer := (CLK_FREQ_KHz * 1000) / (LED_FREQ_Hz * 2); + signal led_sig : std_logic; + signal cnt : unsigned(clog2(HALF_PERIOD) - 1 downto 0); +begin + led <= led_sig; + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then + led_sig <= '1'; + cnt <= to_unsigned(0, clog2(HALF_PERIOD)); + else + if cnt = to_unsigned(HALF_PERIOD - 1, clog2(HALF_PERIOD)) then + cnt <= to_unsigned(0, clog2(HALF_PERIOD)); + led_sig <= not led_sig; + else cnt <= cnt + to_unsigned(1, clog2(HALF_PERIOD)); + end if; + end if; + end if; + end process; +end Blinker_arch; diff --git a/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v93/hdl/Blinker_pkg.vhd b/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v93/hdl/Blinker_pkg.vhd new file mode 100644 index 000000000..9703c8522 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.BlinkerSpec/vhdl.v93/hdl/Blinker_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package Blinker_pkg is + +end package Blinker_pkg; + +package body Blinker_pkg is + +end package body Blinker_pkg; diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.sv2009/hdl/Counter.sv b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.sv2009/hdl/Counter.sv new file mode 100644 index 000000000..fb082b6f9 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.sv2009/hdl/Counter.sv @@ -0,0 +1,19 @@ +`default_nettype none +`timescale 1ns/1ps +`include "Counter_defs.svh" + +module Counter#(parameter int width = 8)( + input wire logic clk, + input wire logic rst, + input wire logic en, + output logic [width - 1:0] cnt +); + `include "dfhdl_defs.svh" + always_ff @(posedge clk) + begin + if (rst == 1'b1) cnt <= width'(0); + else begin + if (en) cnt <= cnt + width'(1); + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.sv2009/hdl/Counter_defs.svh b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.sv2009/hdl/Counter_defs.svh new file mode 100644 index 000000000..652926d34 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.sv2009/hdl/Counter_defs.svh @@ -0,0 +1,4 @@ +`ifndef COUNTER_DEFS +`define COUNTER_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v2001/hdl/Counter.v b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v2001/hdl/Counter.v new file mode 100644 index 000000000..ab2cab126 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v2001/hdl/Counter.v @@ -0,0 +1,19 @@ +`default_nettype none +`timescale 1ns/1ps +`include "Counter_defs.vh" + +module Counter#(parameter integer width = 8)( + input wire clk, + input wire rst, + input wire en, + output reg [width - 1:0] cnt +); + `include "dfhdl_defs.vh" + always @(posedge clk) + begin + if (rst == 1'b1) cnt <= `TO_UNSIGNED(0, 1, width); + else begin + if (en) cnt <= cnt + `TO_UNSIGNED(1, 1, width); + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v2001/hdl/Counter_defs.vh b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v2001/hdl/Counter_defs.vh new file mode 100644 index 000000000..652926d34 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v2001/hdl/Counter_defs.vh @@ -0,0 +1,4 @@ +`ifndef COUNTER_DEFS +`define COUNTER_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v95/hdl/Counter.v b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v95/hdl/Counter.v new file mode 100644 index 000000000..b9f5035ec --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v95/hdl/Counter.v @@ -0,0 +1,24 @@ +`default_nettype none +`timescale 1ns/1ps +`include "Counter_defs.vh" + +module Counter( + clk, + rst, + en, + cnt +); + `include "dfhdl_defs.vh" + parameter integer width = 8; + input wire clk; + input wire rst; + input wire en; + output reg [width - 1:0] cnt; + always @(posedge clk) + begin + if (rst == 1'b1) cnt <= `TO_UNSIGNED(0, 1, width); + else begin + if (en) cnt <= cnt + `TO_UNSIGNED(1, 1, width); + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v95/hdl/Counter_defs.vh b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v95/hdl/Counter_defs.vh new file mode 100644 index 000000000..652926d34 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/verilog.v95/hdl/Counter_defs.vh @@ -0,0 +1,4 @@ +`ifndef COUNTER_DEFS +`define COUNTER_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v2008/hdl/Counter.vhd b/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v2008/hdl/Counter.vhd new file mode 100644 index 000000000..42a8f4403 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v2008/hdl/Counter.vhd @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.Counter_pkg.all; + +entity Counter is +generic ( + width : integer := 8 +); +port ( + clk : in std_logic; + rst : in std_logic; + en : in std_logic; + cnt : out unsigned(width - 1 downto 0) +); +end Counter; + +architecture Counter_arch of Counter is +begin + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then cnt <= resize(d"0", width); + else + if en then cnt <= cnt + resize(d"1", width); + end if; + end if; + end if; + end process; +end Counter_arch; diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v2008/hdl/Counter_pkg.vhd b/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v2008/hdl/Counter_pkg.vhd new file mode 100644 index 000000000..c7f6d0058 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v2008/hdl/Counter_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package Counter_pkg is + +end package Counter_pkg; + +package body Counter_pkg is + +end package body Counter_pkg; diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v93/hdl/Counter.vhd b/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v93/hdl/Counter.vhd new file mode 100644 index 000000000..ca06ff824 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v93/hdl/Counter.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.Counter_pkg.all; + +entity Counter is +generic ( + width : integer := 8 +); +port ( + clk : in std_logic; + rst : in std_logic; + en : in std_logic; + cnt : out unsigned(width - 1 downto 0) +); +end Counter; + +architecture Counter_arch of Counter is + signal cnt_sig : unsigned(width - 1 downto 0); +begin + cnt <= cnt_sig; + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then cnt_sig <= to_unsigned(0, width); + else + if to_bool(en) then cnt_sig <= cnt_sig + to_unsigned(1, width); + end if; + end if; + end if; + end process; +end Counter_arch; diff --git a/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v93/hdl/Counter_pkg.vhd b/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v93/hdl/Counter_pkg.vhd new file mode 100644 index 000000000..c7f6d0058 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.CounterSpec/vhdl.v93/hdl/Counter_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package Counter_pkg is + +end package Counter_pkg; + +package body Counter_pkg is + +end package body Counter_pkg; diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.sv2009/hdl/FullAdder1.sv b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.sv2009/hdl/FullAdder1.sv new file mode 100644 index 000000000..73001a45a --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.sv2009/hdl/FullAdder1.sv @@ -0,0 +1,15 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdder1_defs.svh" + +module FullAdder1( + input wire logic a, + input wire logic b, + input wire logic c_in, + output logic sum, + output logic c_out +); + `include "dfhdl_defs.svh" + assign sum = (a ^ b) ^ c_in; + assign c_out = ((a & b) | (b & c_in)) | (c_in & a); +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.sv2009/hdl/FullAdder1_defs.svh b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.sv2009/hdl/FullAdder1_defs.svh new file mode 100644 index 000000000..7ec0fd691 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.sv2009/hdl/FullAdder1_defs.svh @@ -0,0 +1,4 @@ +`ifndef FULLADDER1_DEFS +`define FULLADDER1_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v2001/hdl/FullAdder1.v b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v2001/hdl/FullAdder1.v new file mode 100644 index 000000000..ea84a2376 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v2001/hdl/FullAdder1.v @@ -0,0 +1,15 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdder1_defs.vh" + +module FullAdder1( + input wire a, + input wire b, + input wire c_in, + output wire sum, + output wire c_out +); + `include "dfhdl_defs.vh" + assign sum = (a ^ b) ^ c_in; + assign c_out = ((a & b) | (b & c_in)) | (c_in & a); +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v2001/hdl/FullAdder1_defs.vh b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v2001/hdl/FullAdder1_defs.vh new file mode 100644 index 000000000..7ec0fd691 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v2001/hdl/FullAdder1_defs.vh @@ -0,0 +1,4 @@ +`ifndef FULLADDER1_DEFS +`define FULLADDER1_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v95/hdl/FullAdder1.v b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v95/hdl/FullAdder1.v new file mode 100644 index 000000000..93ef263cf --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v95/hdl/FullAdder1.v @@ -0,0 +1,20 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdder1_defs.vh" + +module FullAdder1( + a, + b, + c_in, + sum, + c_out +); + `include "dfhdl_defs.vh" + input wire a; + input wire b; + input wire c_in; + output wire sum; + output wire c_out; + assign sum = (a ^ b) ^ c_in; + assign c_out = ((a & b) | (b & c_in)) | (c_in & a); +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v95/hdl/FullAdder1_defs.vh b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v95/hdl/FullAdder1_defs.vh new file mode 100644 index 000000000..7ec0fd691 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/verilog.v95/hdl/FullAdder1_defs.vh @@ -0,0 +1,4 @@ +`ifndef FULLADDER1_DEFS +`define FULLADDER1_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v2008/hdl/FullAdder1.vhd b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v2008/hdl/FullAdder1.vhd new file mode 100644 index 000000000..5fb6396f8 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v2008/hdl/FullAdder1.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.FullAdder1_pkg.all; + +entity FullAdder1 is +port ( + a : in std_logic; + b : in std_logic; + c_in : in std_logic; + sum : out std_logic; + c_out : out std_logic +); +end FullAdder1; + +architecture FullAdder1_arch of FullAdder1 is +begin + sum <= (a xor b) xor c_in; + c_out <= ((a and b) or (b and c_in)) or (c_in and a); +end FullAdder1_arch; diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v2008/hdl/FullAdder1_pkg.vhd b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v2008/hdl/FullAdder1_pkg.vhd new file mode 100644 index 000000000..c9b845671 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v2008/hdl/FullAdder1_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package FullAdder1_pkg is + +end package FullAdder1_pkg; + +package body FullAdder1_pkg is + +end package body FullAdder1_pkg; diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v93/hdl/FullAdder1.vhd b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v93/hdl/FullAdder1.vhd new file mode 100644 index 000000000..5fb6396f8 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v93/hdl/FullAdder1.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.FullAdder1_pkg.all; + +entity FullAdder1 is +port ( + a : in std_logic; + b : in std_logic; + c_in : in std_logic; + sum : out std_logic; + c_out : out std_logic +); +end FullAdder1; + +architecture FullAdder1_arch of FullAdder1 is +begin + sum <= (a xor b) xor c_in; + c_out <= ((a and b) or (b and c_in)) or (c_in and a); +end FullAdder1_arch; diff --git a/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v93/hdl/FullAdder1_pkg.vhd b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v93/hdl/FullAdder1_pkg.vhd new file mode 100644 index 000000000..c9b845671 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdder1Spec/vhdl.v93/hdl/FullAdder1_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package FullAdder1_pkg is + +end package FullAdder1_pkg; + +package body FullAdder1_pkg is + +end package body FullAdder1_pkg; diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdder1.sv b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdder1.sv new file mode 100644 index 000000000..7689a1359 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdder1.sv @@ -0,0 +1,15 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdderN_defs.svh" + +module FullAdder1( + input wire logic a, + input wire logic b, + input wire logic c_in, + output logic sum, + output logic c_out +); + `include "dfhdl_defs.svh" + assign sum = (a ^ b) ^ c_in; + assign c_out = ((a & b) | (b & c_in)) | (c_in & a); +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdderN.sv b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdderN.sv new file mode 100644 index 000000000..36f54e96c --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdderN.sv @@ -0,0 +1,78 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdderN_defs.svh" + +module FullAdderN( + input wire logic [3:0] a, + input wire logic [3:0] b, + input wire logic c_in, + output logic [3:0] sum, + output logic c_out +); + `include "dfhdl_defs.svh" + logic adder_0_a; + logic adder_0_b; + logic adder_0_c_in; + logic adder_0_sum; + logic adder_0_c_out; + logic adder_1_a; + logic adder_1_b; + logic adder_1_c_in; + logic adder_1_sum; + logic adder_1_c_out; + logic adder_2_a; + logic adder_2_b; + logic adder_2_c_in; + logic adder_2_sum; + logic adder_2_c_out; + logic adder_3_a; + logic adder_3_b; + logic adder_3_c_in; + logic adder_3_sum; + logic adder_3_c_out; + FullAdder1 adder_0( + .a /*<--*/ (adder_0_a), + .b /*<--*/ (adder_0_b), + .c_in /*<--*/ (adder_0_c_in), + .sum /*-->*/ (adder_0_sum), + .c_out /*-->*/ (adder_0_c_out) + ); + FullAdder1 adder_1( + .a /*<--*/ (adder_1_a), + .b /*<--*/ (adder_1_b), + .c_in /*<--*/ (adder_1_c_in), + .sum /*-->*/ (adder_1_sum), + .c_out /*-->*/ (adder_1_c_out) + ); + FullAdder1 adder_2( + .a /*<--*/ (adder_2_a), + .b /*<--*/ (adder_2_b), + .c_in /*<--*/ (adder_2_c_in), + .sum /*-->*/ (adder_2_sum), + .c_out /*-->*/ (adder_2_c_out) + ); + FullAdder1 adder_3( + .a /*<--*/ (adder_3_a), + .b /*<--*/ (adder_3_b), + .c_in /*<--*/ (adder_3_c_in), + .sum /*-->*/ (adder_3_sum), + .c_out /*-->*/ (adder_3_c_out) + ); + assign adder_0_a = a[0]; + assign adder_0_b = b[0]; + assign sum[0] = adder_0_sum; + assign adder_1_c_in = adder_0_c_out; + assign adder_1_a = a[1]; + assign adder_1_b = b[1]; + assign sum[1] = adder_1_sum; + assign adder_2_c_in = adder_1_c_out; + assign adder_2_a = a[2]; + assign adder_2_b = b[2]; + assign sum[2] = adder_2_sum; + assign adder_3_c_in = adder_2_c_out; + assign adder_3_a = a[3]; + assign adder_3_b = b[3]; + assign sum[3] = adder_3_sum; + assign adder_0_c_in = c_in; + assign c_out = adder_3_c_out; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdderN_defs.svh b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdderN_defs.svh new file mode 100644 index 000000000..d061ee9df --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.sv2009/hdl/FullAdderN_defs.svh @@ -0,0 +1,4 @@ +`ifndef FULLADDERN_DEFS +`define FULLADDERN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdder1.v b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdder1.v new file mode 100644 index 000000000..75a8b5a62 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdder1.v @@ -0,0 +1,15 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdderN_defs.vh" + +module FullAdder1( + input wire a, + input wire b, + input wire c_in, + output wire sum, + output wire c_out +); + `include "dfhdl_defs.vh" + assign sum = (a ^ b) ^ c_in; + assign c_out = ((a & b) | (b & c_in)) | (c_in & a); +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdderN.v b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdderN.v new file mode 100644 index 000000000..48c170a12 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdderN.v @@ -0,0 +1,78 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdderN_defs.vh" + +module FullAdderN( + input wire [3:0] a, + input wire [3:0] b, + input wire c_in, + output wire [3:0] sum, + output wire c_out +); + `include "dfhdl_defs.vh" + wire adder_0_a; + wire adder_0_b; + wire adder_0_c_in; + wire adder_0_sum; + wire adder_0_c_out; + wire adder_1_a; + wire adder_1_b; + wire adder_1_c_in; + wire adder_1_sum; + wire adder_1_c_out; + wire adder_2_a; + wire adder_2_b; + wire adder_2_c_in; + wire adder_2_sum; + wire adder_2_c_out; + wire adder_3_a; + wire adder_3_b; + wire adder_3_c_in; + wire adder_3_sum; + wire adder_3_c_out; + FullAdder1 adder_0( + .a /*<--*/ (adder_0_a), + .b /*<--*/ (adder_0_b), + .c_in /*<--*/ (adder_0_c_in), + .sum /*-->*/ (adder_0_sum), + .c_out /*-->*/ (adder_0_c_out) + ); + FullAdder1 adder_1( + .a /*<--*/ (adder_1_a), + .b /*<--*/ (adder_1_b), + .c_in /*<--*/ (adder_1_c_in), + .sum /*-->*/ (adder_1_sum), + .c_out /*-->*/ (adder_1_c_out) + ); + FullAdder1 adder_2( + .a /*<--*/ (adder_2_a), + .b /*<--*/ (adder_2_b), + .c_in /*<--*/ (adder_2_c_in), + .sum /*-->*/ (adder_2_sum), + .c_out /*-->*/ (adder_2_c_out) + ); + FullAdder1 adder_3( + .a /*<--*/ (adder_3_a), + .b /*<--*/ (adder_3_b), + .c_in /*<--*/ (adder_3_c_in), + .sum /*-->*/ (adder_3_sum), + .c_out /*-->*/ (adder_3_c_out) + ); + assign adder_0_a = a[0]; + assign adder_0_b = b[0]; + assign sum[0] = adder_0_sum; + assign adder_1_c_in = adder_0_c_out; + assign adder_1_a = a[1]; + assign adder_1_b = b[1]; + assign sum[1] = adder_1_sum; + assign adder_2_c_in = adder_1_c_out; + assign adder_2_a = a[2]; + assign adder_2_b = b[2]; + assign sum[2] = adder_2_sum; + assign adder_3_c_in = adder_2_c_out; + assign adder_3_a = a[3]; + assign adder_3_b = b[3]; + assign sum[3] = adder_3_sum; + assign adder_0_c_in = c_in; + assign c_out = adder_3_c_out; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdderN_defs.vh b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdderN_defs.vh new file mode 100644 index 000000000..d061ee9df --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v2001/hdl/FullAdderN_defs.vh @@ -0,0 +1,4 @@ +`ifndef FULLADDERN_DEFS +`define FULLADDERN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdder1.v b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdder1.v new file mode 100644 index 000000000..31c5ec372 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdder1.v @@ -0,0 +1,20 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdderN_defs.vh" + +module FullAdder1( + a, + b, + c_in, + sum, + c_out +); + `include "dfhdl_defs.vh" + input wire a; + input wire b; + input wire c_in; + output wire sum; + output wire c_out; + assign sum = (a ^ b) ^ c_in; + assign c_out = ((a & b) | (b & c_in)) | (c_in & a); +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdderN.v b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdderN.v new file mode 100644 index 000000000..f209cf875 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdderN.v @@ -0,0 +1,83 @@ +`default_nettype none +`timescale 1ns/1ps +`include "FullAdderN_defs.vh" + +module FullAdderN( + a, + b, + c_in, + sum, + c_out +); + `include "dfhdl_defs.vh" + input wire [3:0] a; + input wire [3:0] b; + input wire c_in; + output wire [3:0] sum; + output wire c_out; + wire adder_0_a; + wire adder_0_b; + wire adder_0_c_in; + wire adder_0_sum; + wire adder_0_c_out; + wire adder_1_a; + wire adder_1_b; + wire adder_1_c_in; + wire adder_1_sum; + wire adder_1_c_out; + wire adder_2_a; + wire adder_2_b; + wire adder_2_c_in; + wire adder_2_sum; + wire adder_2_c_out; + wire adder_3_a; + wire adder_3_b; + wire adder_3_c_in; + wire adder_3_sum; + wire adder_3_c_out; + FullAdder1 adder_0( + .a /*<--*/ (adder_0_a), + .b /*<--*/ (adder_0_b), + .c_in /*<--*/ (adder_0_c_in), + .sum /*-->*/ (adder_0_sum), + .c_out /*-->*/ (adder_0_c_out) + ); + FullAdder1 adder_1( + .a /*<--*/ (adder_1_a), + .b /*<--*/ (adder_1_b), + .c_in /*<--*/ (adder_1_c_in), + .sum /*-->*/ (adder_1_sum), + .c_out /*-->*/ (adder_1_c_out) + ); + FullAdder1 adder_2( + .a /*<--*/ (adder_2_a), + .b /*<--*/ (adder_2_b), + .c_in /*<--*/ (adder_2_c_in), + .sum /*-->*/ (adder_2_sum), + .c_out /*-->*/ (adder_2_c_out) + ); + FullAdder1 adder_3( + .a /*<--*/ (adder_3_a), + .b /*<--*/ (adder_3_b), + .c_in /*<--*/ (adder_3_c_in), + .sum /*-->*/ (adder_3_sum), + .c_out /*-->*/ (adder_3_c_out) + ); + assign adder_0_a = a[0]; + assign adder_0_b = b[0]; + assign sum[0] = adder_0_sum; + assign adder_1_c_in = adder_0_c_out; + assign adder_1_a = a[1]; + assign adder_1_b = b[1]; + assign sum[1] = adder_1_sum; + assign adder_2_c_in = adder_1_c_out; + assign adder_2_a = a[2]; + assign adder_2_b = b[2]; + assign sum[2] = adder_2_sum; + assign adder_3_c_in = adder_2_c_out; + assign adder_3_a = a[3]; + assign adder_3_b = b[3]; + assign sum[3] = adder_3_sum; + assign adder_0_c_in = c_in; + assign c_out = adder_3_c_out; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdderN_defs.vh b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdderN_defs.vh new file mode 100644 index 000000000..d061ee9df --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/verilog.v95/hdl/FullAdderN_defs.vh @@ -0,0 +1,4 @@ +`ifndef FULLADDERN_DEFS +`define FULLADDERN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdder1.vhd b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdder1.vhd new file mode 100644 index 000000000..3dc80d3de --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdder1.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.FullAdderN_pkg.all; + +entity FullAdder1 is +port ( + a : in std_logic; + b : in std_logic; + c_in : in std_logic; + sum : out std_logic; + c_out : out std_logic +); +end FullAdder1; + +architecture FullAdder1_arch of FullAdder1 is +begin + sum <= (a xor b) xor c_in; + c_out <= ((a and b) or (b and c_in)) or (c_in and a); +end FullAdder1_arch; diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdderN.vhd b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdderN.vhd new file mode 100644 index 000000000..b0b2f60bf --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdderN.vhd @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.FullAdderN_pkg.all; + +entity FullAdderN is +port ( + a : in std_logic_vector(3 downto 0); + b : in std_logic_vector(3 downto 0); + c_in : in std_logic; + sum : out std_logic_vector(3 downto 0); + c_out : out std_logic +); +end FullAdderN; + +architecture FullAdderN_arch of FullAdderN is + signal adder_0_a : std_logic; + signal adder_0_b : std_logic; + signal adder_0_c_in : std_logic; + signal adder_0_sum : std_logic; + signal adder_0_c_out : std_logic; + signal adder_1_a : std_logic; + signal adder_1_b : std_logic; + signal adder_1_c_in : std_logic; + signal adder_1_sum : std_logic; + signal adder_1_c_out : std_logic; + signal adder_2_a : std_logic; + signal adder_2_b : std_logic; + signal adder_2_c_in : std_logic; + signal adder_2_sum : std_logic; + signal adder_2_c_out : std_logic; + signal adder_3_a : std_logic; + signal adder_3_b : std_logic; + signal adder_3_c_in : std_logic; + signal adder_3_sum : std_logic; + signal adder_3_c_out : std_logic; +begin + adder_0 : entity work.FullAdder1(FullAdder1_arch) port map ( + a => adder_0_a, + b => adder_0_b, + c_in => adder_0_c_in, + sum => adder_0_sum, + c_out => adder_0_c_out + ); + adder_1 : entity work.FullAdder1(FullAdder1_arch) port map ( + a => adder_1_a, + b => adder_1_b, + c_in => adder_1_c_in, + sum => adder_1_sum, + c_out => adder_1_c_out + ); + adder_2 : entity work.FullAdder1(FullAdder1_arch) port map ( + a => adder_2_a, + b => adder_2_b, + c_in => adder_2_c_in, + sum => adder_2_sum, + c_out => adder_2_c_out + ); + adder_3 : entity work.FullAdder1(FullAdder1_arch) port map ( + a => adder_3_a, + b => adder_3_b, + c_in => adder_3_c_in, + sum => adder_3_sum, + c_out => adder_3_c_out + ); + adder_0_a <= a(0); + adder_0_b <= b(0); + sum(0) <= adder_0_sum; + adder_1_c_in <= adder_0_c_out; + adder_1_a <= a(1); + adder_1_b <= b(1); + sum(1) <= adder_1_sum; + adder_2_c_in <= adder_1_c_out; + adder_2_a <= a(2); + adder_2_b <= b(2); + sum(2) <= adder_2_sum; + adder_3_c_in <= adder_2_c_out; + adder_3_a <= a(3); + adder_3_b <= b(3); + sum(3) <= adder_3_sum; + adder_0_c_in <= c_in; + c_out <= adder_3_c_out; +end FullAdderN_arch; diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdderN_pkg.vhd b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdderN_pkg.vhd new file mode 100644 index 000000000..ab4fe8a22 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v2008/hdl/FullAdderN_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package FullAdderN_pkg is + +end package FullAdderN_pkg; + +package body FullAdderN_pkg is + +end package body FullAdderN_pkg; diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdder1.vhd b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdder1.vhd new file mode 100644 index 000000000..3dc80d3de --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdder1.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.FullAdderN_pkg.all; + +entity FullAdder1 is +port ( + a : in std_logic; + b : in std_logic; + c_in : in std_logic; + sum : out std_logic; + c_out : out std_logic +); +end FullAdder1; + +architecture FullAdder1_arch of FullAdder1 is +begin + sum <= (a xor b) xor c_in; + c_out <= ((a and b) or (b and c_in)) or (c_in and a); +end FullAdder1_arch; diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdderN.vhd b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdderN.vhd new file mode 100644 index 000000000..56085de99 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdderN.vhd @@ -0,0 +1,78 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.FullAdderN_pkg.all; + +entity FullAdderN is +port ( + a : in std_logic_vector(3 downto 0); + b : in std_logic_vector(3 downto 0); + c_in : in std_logic; + sum : out std_logic_vector(3 downto 0); + c_out : out std_logic +); +end FullAdderN; + +architecture FullAdderN_arch of FullAdderN is + signal sum_sig : std_logic_vector(3 downto 0); + signal adder_0_a : std_logic; + signal adder_0_b : std_logic; + signal adder_0_c_in : std_logic; + signal adder_0_c_out : std_logic; + signal adder_1_a : std_logic; + signal adder_1_b : std_logic; + signal adder_1_c_in : std_logic; + signal adder_1_c_out : std_logic; + signal adder_2_a : std_logic; + signal adder_2_b : std_logic; + signal adder_2_c_in : std_logic; + signal adder_2_c_out : std_logic; + signal adder_3_a : std_logic; + signal adder_3_b : std_logic; + signal adder_3_c_in : std_logic; + signal adder_3_c_out : std_logic; +begin + adder_0 : entity work.FullAdder1(FullAdder1_arch) port map ( + a => adder_0_a, + b => adder_0_b, + c_in => adder_0_c_in, + c_out => adder_0_c_out, + sum => sum_sig(0) + ); + adder_1 : entity work.FullAdder1(FullAdder1_arch) port map ( + a => adder_1_a, + b => adder_1_b, + c_in => adder_1_c_in, + c_out => adder_1_c_out, + sum => sum_sig(1) + ); + adder_2 : entity work.FullAdder1(FullAdder1_arch) port map ( + a => adder_2_a, + b => adder_2_b, + c_in => adder_2_c_in, + c_out => adder_2_c_out, + sum => sum_sig(2) + ); + adder_3 : entity work.FullAdder1(FullAdder1_arch) port map ( + a => adder_3_a, + b => adder_3_b, + c_in => adder_3_c_in, + c_out => adder_3_c_out, + sum => sum_sig(3) + ); + sum <= sum_sig; + adder_0_a <= a(0); + adder_0_b <= b(0); + adder_1_c_in <= adder_0_c_out; + adder_1_a <= a(1); + adder_1_b <= b(1); + adder_2_c_in <= adder_1_c_out; + adder_2_a <= a(2); + adder_2_b <= b(2); + adder_3_c_in <= adder_2_c_out; + adder_3_a <= a(3); + adder_3_b <= b(3); + adder_0_c_in <= c_in; + c_out <= adder_3_c_out; +end FullAdderN_arch; diff --git a/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdderN_pkg.vhd b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdderN_pkg.vhd new file mode 100644 index 000000000..ab4fe8a22 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.FullAdderNSpec/vhdl.v93/hdl/FullAdderN_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package FullAdderN_pkg is + +end package FullAdderN_pkg; + +package body FullAdderN_pkg is + +end package body FullAdderN_pkg; diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.sv2009/hdl/RegFile.sv b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.sv2009/hdl/RegFile.sv new file mode 100644 index 000000000..32d8138c0 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.sv2009/hdl/RegFile.sv @@ -0,0 +1,33 @@ +`default_nettype none +`timescale 1ns/1ps +`include "RegFile_defs.svh" + +module RegFile#( + parameter int DATA_WIDTH = 32, + parameter int REG_NUM = 32 +)( + input wire logic clk, + input wire logic [$clog2(REG_NUM) - 1:0] rs1_addr, + output logic [DATA_WIDTH - 1:0] rs1_data, + input wire logic [$clog2(REG_NUM) - 1:0] rs2_addr, + output logic [DATA_WIDTH - 1:0] rs2_data, + input wire logic [$clog2(REG_NUM) - 1:0] rd_addr, + input wire logic [DATA_WIDTH - 1:0] rd_data, + input wire logic rd_wren +); + `include "dfhdl_defs.svh" + logic [DATA_WIDTH - 1:0] regs [0:REG_NUM - 1]; + always_ff @(posedge clk) + begin + rs1_data <= regs[rs1_addr]; + end + always_ff @(posedge clk) + begin + rs2_data <= regs[rs2_addr]; + end + always_ff @(posedge clk) + begin + if (rd_wren) regs[rd_addr] <= rd_data; + regs[0] <= {DATA_WIDTH{1'b0}}; + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.sv2009/hdl/RegFile_defs.svh b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.sv2009/hdl/RegFile_defs.svh new file mode 100644 index 000000000..2f0194a45 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.sv2009/hdl/RegFile_defs.svh @@ -0,0 +1,4 @@ +`ifndef REGFILE_DEFS +`define REGFILE_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v2001/hdl/RegFile.v b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v2001/hdl/RegFile.v new file mode 100644 index 000000000..fa9179b3c --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v2001/hdl/RegFile.v @@ -0,0 +1,33 @@ +`default_nettype none +`timescale 1ns/1ps +`include "RegFile_defs.vh" + +module RegFile#( + parameter integer DATA_WIDTH = 32, + parameter integer REG_NUM = 32 +)( + input wire clk, + input wire [clog2(REG_NUM) - 1:0] rs1_addr, + output reg [DATA_WIDTH - 1:0] rs1_data, + input wire [clog2(REG_NUM) - 1:0] rs2_addr, + output reg [DATA_WIDTH - 1:0] rs2_data, + input wire [clog2(REG_NUM) - 1:0] rd_addr, + input wire [DATA_WIDTH - 1:0] rd_data, + input wire rd_wren +); + `include "dfhdl_defs.vh" + reg [DATA_WIDTH - 1:0] regs [0:REG_NUM - 1]; + always @(posedge clk) + begin + rs1_data <= regs[rs1_addr]; + end + always @(posedge clk) + begin + rs2_data <= regs[rs2_addr]; + end + always @(posedge clk) + begin + if (rd_wren) regs[rd_addr] <= rd_data; + regs[0] <= {DATA_WIDTH{1'b0}}; + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v2001/hdl/RegFile_defs.vh b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v2001/hdl/RegFile_defs.vh new file mode 100644 index 000000000..2f0194a45 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v2001/hdl/RegFile_defs.vh @@ -0,0 +1,4 @@ +`ifndef REGFILE_DEFS +`define REGFILE_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v95/hdl/RegFile.v b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v95/hdl/RegFile.v new file mode 100644 index 000000000..d226635ab --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v95/hdl/RegFile.v @@ -0,0 +1,40 @@ +`default_nettype none +`timescale 1ns/1ps +`include "RegFile_defs.vh" + +module RegFile( + clk, + rs1_addr, + rs1_data, + rs2_addr, + rs2_data, + rd_addr, + rd_data, + rd_wren +); + `include "dfhdl_defs.vh" + parameter integer DATA_WIDTH = 32; + parameter integer REG_NUM = 32; + input wire clk; + input wire [clog2(REG_NUM) - 1:0] rs1_addr; + output reg [DATA_WIDTH - 1:0] rs1_data; + input wire [clog2(REG_NUM) - 1:0] rs2_addr; + output reg [DATA_WIDTH - 1:0] rs2_data; + input wire [clog2(REG_NUM) - 1:0] rd_addr; + input wire [DATA_WIDTH - 1:0] rd_data; + input wire rd_wren; + reg [DATA_WIDTH - 1:0] regs [0:REG_NUM - 1]; + always @(posedge clk) + begin + rs1_data <= regs[rs1_addr]; + end + always @(posedge clk) + begin + rs2_data <= regs[rs2_addr]; + end + always @(posedge clk) + begin + if (rd_wren) regs[rd_addr] <= rd_data; + regs[0] <= {DATA_WIDTH{1'b0}}; + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v95/hdl/RegFile_defs.vh b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v95/hdl/RegFile_defs.vh new file mode 100644 index 000000000..2f0194a45 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/verilog.v95/hdl/RegFile_defs.vh @@ -0,0 +1,4 @@ +`ifndef REGFILE_DEFS +`define REGFILE_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v2008/hdl/RegFile.vhd b/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v2008/hdl/RegFile.vhd new file mode 100644 index 000000000..b9ad459b4 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v2008/hdl/RegFile.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.RegFile_pkg.all; + +entity RegFile is +generic ( + DATA_WIDTH : integer := 32; + REG_NUM : integer := 32 +); +port ( + clk : in std_logic; + rs1_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); + rs1_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); + rs2_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); + rs2_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); + rd_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); + rd_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); + rd_wren : in std_logic +); +end RegFile; + +architecture RegFile_arch of RegFile is + type t_arrX1_std_logic_vector is array (natural range <>) of std_logic_vector; + signal regs : t_arrX1_std_logic_vector(0 to REG_NUM - 1)(DATA_WIDTH - 1 downto 0); +begin + process (clk) + begin + if rising_edge(clk) then rs1_data <= regs(to_integer(unsigned(rs1_addr))); + end if; + end process; + process (clk) + begin + if rising_edge(clk) then rs2_data <= regs(to_integer(unsigned(rs2_addr))); + end if; + end process; + process (clk) + begin + if rising_edge(clk) then + if rd_wren then regs(to_integer(unsigned(rd_addr))) <= rd_data; + end if; + regs(0) <= repeat("0", DATA_WIDTH); + end if; + end process; +end RegFile_arch; diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v2008/hdl/RegFile_pkg.vhd b/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v2008/hdl/RegFile_pkg.vhd new file mode 100644 index 000000000..eae97e00a --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v2008/hdl/RegFile_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package RegFile_pkg is + +end package RegFile_pkg; + +package body RegFile_pkg is + +end package body RegFile_pkg; diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v93/hdl/RegFile.vhd b/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v93/hdl/RegFile.vhd new file mode 100644 index 000000000..df815655b --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v93/hdl/RegFile.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.RegFile_pkg.all; + +entity RegFile is +generic ( + DATA_WIDTH : integer := 32; + REG_NUM : integer := 32 +); +port ( + clk : in std_logic; + rs1_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); + rs1_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); + rs2_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); + rs2_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); + rd_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); + rd_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); + rd_wren : in std_logic +); +end RegFile; + +architecture RegFile_arch of RegFile is + type t_arrXPREG_NUM_slvPDATA_WIDTH is array (0 to REG_NUM - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); + signal regs : t_arrXPREG_NUM_slvPDATA_WIDTH; +begin + process (clk) + begin + if rising_edge(clk) then rs1_data <= regs(to_integer(unsigned(rs1_addr))); + end if; + end process; + process (clk) + begin + if rising_edge(clk) then rs2_data <= regs(to_integer(unsigned(rs2_addr))); + end if; + end process; + process (clk) + begin + if rising_edge(clk) then + if to_bool(rd_wren) then regs(to_integer(unsigned(rd_addr))) <= rd_data; + end if; + regs(0) <= repeat("0", DATA_WIDTH); + end if; + end process; +end RegFile_arch; diff --git a/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v93/hdl/RegFile_pkg.vhd b/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v93/hdl/RegFile_pkg.vhd new file mode 100644 index 000000000..eae97e00a --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.RegFileSpec/vhdl.v93/hdl/RegFile_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package RegFile_pkg is + +end package RegFile_pkg; + +package body RegFile_pkg is + +end package body RegFile_pkg; diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.sv2009/hdl/TrueDPR.sv b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.sv2009/hdl/TrueDPR.sv new file mode 100644 index 000000000..581c6e3ab --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.sv2009/hdl/TrueDPR.sv @@ -0,0 +1,40 @@ +`default_nettype none +`timescale 1ns/1ps +`include "TrueDPR_defs.svh" + +module TrueDPR#( + parameter int DATA_WIDTH = 8, + parameter int ADDR_WIDTH = 8 +)( + input wire logic a_clk, + input wire logic [DATA_WIDTH - 1:0] a_data, + input wire logic [ADDR_WIDTH - 1:0] a_addr, + output logic [DATA_WIDTH - 1:0] a_q, + input wire logic a_we, + input wire logic b_clk, + input wire logic [DATA_WIDTH - 1:0] b_data, + input wire logic [ADDR_WIDTH - 1:0] b_addr, + output logic [DATA_WIDTH - 1:0] b_q, + input wire logic b_we +); + `include "dfhdl_defs.svh" + logic [DATA_WIDTH - 1:0] ram [0:2 ** ADDR_WIDTH - 1]; + always_ff @(posedge a_clk) + begin + if (a_we) begin + /* verilator lint_off BLKSEQ */ + ram[a_addr] = a_data; + /* verilator lint_on BLKSEQ */ + end + a_q <= ram[a_addr]; + end + always_ff @(posedge b_clk) + begin + if (b_we) begin + /* verilator lint_off BLKSEQ */ + ram[b_addr] = b_data; + /* verilator lint_on BLKSEQ */ + end + b_q <= ram[b_addr]; + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.sv2009/hdl/TrueDPR_defs.svh b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.sv2009/hdl/TrueDPR_defs.svh new file mode 100644 index 000000000..a6384486f --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.sv2009/hdl/TrueDPR_defs.svh @@ -0,0 +1,4 @@ +`ifndef TRUEDPR_DEFS +`define TRUEDPR_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v2001/hdl/TrueDPR.v b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v2001/hdl/TrueDPR.v new file mode 100644 index 000000000..6b63074f5 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v2001/hdl/TrueDPR.v @@ -0,0 +1,40 @@ +`default_nettype none +`timescale 1ns/1ps +`include "TrueDPR_defs.vh" + +module TrueDPR#( + parameter integer DATA_WIDTH = 8, + parameter integer ADDR_WIDTH = 8 +)( + input wire a_clk, + input wire [DATA_WIDTH - 1:0] a_data, + input wire [ADDR_WIDTH - 1:0] a_addr, + output reg [DATA_WIDTH - 1:0] a_q, + input wire a_we, + input wire b_clk, + input wire [DATA_WIDTH - 1:0] b_data, + input wire [ADDR_WIDTH - 1:0] b_addr, + output reg [DATA_WIDTH - 1:0] b_q, + input wire b_we +); + `include "dfhdl_defs.vh" + reg [DATA_WIDTH - 1:0] ram [0:2 ** ADDR_WIDTH - 1]; + always @(posedge a_clk) + begin + if (a_we) begin + /* verilator lint_off BLKSEQ */ + ram[a_addr] = a_data; + /* verilator lint_on BLKSEQ */ + end + a_q <= ram[a_addr]; + end + always @(posedge b_clk) + begin + if (b_we) begin + /* verilator lint_off BLKSEQ */ + ram[b_addr] = b_data; + /* verilator lint_on BLKSEQ */ + end + b_q <= ram[b_addr]; + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v2001/hdl/TrueDPR_defs.vh b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v2001/hdl/TrueDPR_defs.vh new file mode 100644 index 000000000..a6384486f --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v2001/hdl/TrueDPR_defs.vh @@ -0,0 +1,4 @@ +`ifndef TRUEDPR_DEFS +`define TRUEDPR_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v95/hdl/TrueDPR.v b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v95/hdl/TrueDPR.v new file mode 100644 index 000000000..936cc5610 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v95/hdl/TrueDPR.v @@ -0,0 +1,49 @@ +`default_nettype none +`timescale 1ns/1ps +`include "TrueDPR_defs.vh" + +module TrueDPR( + a_clk, + a_data, + a_addr, + a_q, + a_we, + b_clk, + b_data, + b_addr, + b_q, + b_we +); + `include "dfhdl_defs.vh" + parameter integer DATA_WIDTH = 8; + parameter integer ADDR_WIDTH = 8; + input wire a_clk; + input wire [DATA_WIDTH - 1:0] a_data; + input wire [ADDR_WIDTH - 1:0] a_addr; + output reg [DATA_WIDTH - 1:0] a_q; + input wire a_we; + input wire b_clk; + input wire [DATA_WIDTH - 1:0] b_data; + input wire [ADDR_WIDTH - 1:0] b_addr; + output reg [DATA_WIDTH - 1:0] b_q; + input wire b_we; + reg [DATA_WIDTH - 1:0] ram [0:power(2, ADDR_WIDTH) - 1]; + always @(posedge a_clk) + begin + if (a_we) begin + /* verilator lint_off BLKSEQ */ + ram[a_addr] = a_data; + /* verilator lint_on BLKSEQ */ + end + a_q <= ram[a_addr]; + end + always @(posedge b_clk) + begin + if (b_we) begin + /* verilator lint_off BLKSEQ */ + ram[b_addr] = b_data; + /* verilator lint_on BLKSEQ */ + end + b_q <= ram[b_addr]; + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v95/hdl/TrueDPR_defs.vh b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v95/hdl/TrueDPR_defs.vh new file mode 100644 index 000000000..a6384486f --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/verilog.v95/hdl/TrueDPR_defs.vh @@ -0,0 +1,4 @@ +`ifndef TRUEDPR_DEFS +`define TRUEDPR_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v2008/hdl/TrueDPR.vhd b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v2008/hdl/TrueDPR.vhd new file mode 100644 index 000000000..f760c08aa --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v2008/hdl/TrueDPR.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.TrueDPR_pkg.all; + +entity TrueDPR is +generic ( + DATA_WIDTH : integer := 8; + ADDR_WIDTH : integer := 8 +); +port ( + a_clk : in std_logic; + a_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); + a_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + a_q : out std_logic_vector(DATA_WIDTH - 1 downto 0); + a_we : in std_logic; + b_clk : in std_logic; + b_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); + b_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + b_q : out std_logic_vector(DATA_WIDTH - 1 downto 0); + b_we : in std_logic +); +end TrueDPR; + +architecture TrueDPR_arch of TrueDPR is + type t_arrX1_std_logic_vector is array (natural range <>) of std_logic_vector; + shared variable ram : t_arrX1_std_logic_vector(0 to 2 ** ADDR_WIDTH - 1)(DATA_WIDTH - 1 downto 0); +begin + process (a_clk) + begin + if rising_edge(a_clk) then + if a_we then ram(to_integer(unsigned(a_addr))) := a_data; + end if; + a_q <= ram(to_integer(unsigned(a_addr))); + end if; + end process; + process (b_clk) + begin + if rising_edge(b_clk) then + if b_we then ram(to_integer(unsigned(b_addr))) := b_data; + end if; + b_q <= ram(to_integer(unsigned(b_addr))); + end if; + end process; +end TrueDPR_arch; diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v2008/hdl/TrueDPR_pkg.vhd b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v2008/hdl/TrueDPR_pkg.vhd new file mode 100644 index 000000000..08e26ee54 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v2008/hdl/TrueDPR_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package TrueDPR_pkg is + +end package TrueDPR_pkg; + +package body TrueDPR_pkg is + +end package body TrueDPR_pkg; diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v93/hdl/TrueDPR.vhd b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v93/hdl/TrueDPR.vhd new file mode 100644 index 000000000..5bfabb3a6 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v93/hdl/TrueDPR.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.TrueDPR_pkg.all; + +entity TrueDPR is +generic ( + DATA_WIDTH : integer := 8; + ADDR_WIDTH : integer := 8 +); +port ( + a_clk : in std_logic; + a_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); + a_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + a_q : out std_logic_vector(DATA_WIDTH - 1 downto 0); + a_we : in std_logic; + b_clk : in std_logic; + b_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); + b_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + b_q : out std_logic_vector(DATA_WIDTH - 1 downto 0); + b_we : in std_logic +); +end TrueDPR; + +architecture TrueDPR_arch of TrueDPR is + type t_arrXP1_slvPDATA_WIDTH is array (0 to 2 ** ADDR_WIDTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); + shared variable ram : t_arrXP1_slvPDATA_WIDTH; +begin + process (a_clk) + begin + if rising_edge(a_clk) then + if to_bool(a_we) then ram(to_integer(unsigned(a_addr))) := a_data; + end if; + a_q <= ram(to_integer(unsigned(a_addr))); + end if; + end process; + process (b_clk) + begin + if rising_edge(b_clk) then + if to_bool(b_we) then ram(to_integer(unsigned(b_addr))) := b_data; + end if; + b_q <= ram(to_integer(unsigned(b_addr))); + end if; + end process; +end TrueDPR_arch; diff --git a/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v93/hdl/TrueDPR_pkg.vhd b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v93/hdl/TrueDPR_pkg.vhd new file mode 100644 index 000000000..08e26ee54 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.TrueDPRSpec/vhdl.v93/hdl/TrueDPR_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package TrueDPR_pkg is + +end package TrueDPR_pkg; + +package body TrueDPR_pkg is + +end package body TrueDPR_pkg; diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.sv2009/hdl/UART_Tx.sv b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.sv2009/hdl/UART_Tx.sv new file mode 100644 index 000000000..d8037460d --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.sv2009/hdl/UART_Tx.sv @@ -0,0 +1,89 @@ +`default_nettype none +`timescale 1ns/1ps +`include "UART_Tx_defs.svh" + +module UART_Tx#( + parameter int CLK_FREQ_KHz = 50000, + parameter int BAUD_RATE_BPS = 115200 +)( + input wire logic clk, + input wire logic rst, + input wire logic data_en, + input wire logic [7:0] data, + output logic tx, + output logic tx_en, + output logic tx_done +); + `include "dfhdl_defs.svh" + parameter int BIT_CLOCKS = (CLK_FREQ_KHz * 1000) / BAUD_RATE_BPS; + typedef enum { + Status_Idle = 1, + Status_StartBit = 2, + Status_DataBits = 4, + Status_StopBit = 8, + Status_Finalize = 16 + } t_enum_Status; + t_enum_Status status; + logic [$clog2(BIT_CLOCKS) - 1:0] bitClkCnt; + logic [2:0] dataBitCnt; + logic [7:0] shiftData; + always_ff @(posedge clk) + begin + if (rst == 1'b1) begin + status <= Status_Idle; + bitClkCnt <= $clog2(BIT_CLOCKS)'(0); + dataBitCnt <= 3'd0; + end + else begin + case (status) + Status_Idle: begin + tx_en <= 1'b0; + tx <= 1'b1; + tx_done <= 1'b0; + bitClkCnt <= $clog2(BIT_CLOCKS)'(0); + dataBitCnt <= 3'd0; + if (data_en) begin + shiftData <= data; + status <= Status_StartBit; + end + end + Status_StartBit: begin + tx_en <= 1'b1; + tx <= 1'b0; + if (bitClkCnt == $clog2(BIT_CLOCKS)'(BIT_CLOCKS - 1)) begin + bitClkCnt <= $clog2(BIT_CLOCKS)'(0); + status <= Status_DataBits; + end + else bitClkCnt <= bitClkCnt + $clog2(BIT_CLOCKS)'(1); + end + Status_DataBits: begin + tx <= shiftData[0]; + if (bitClkCnt == $clog2(BIT_CLOCKS)'(BIT_CLOCKS - 1)) begin + bitClkCnt <= $clog2(BIT_CLOCKS)'(0); + shiftData <= shiftData >> 1; + if (dataBitCnt == 3'd7) begin + dataBitCnt <= 3'd0; + status <= Status_StopBit; + end + else dataBitCnt <= dataBitCnt + 3'd1; + end + else bitClkCnt <= bitClkCnt + $clog2(BIT_CLOCKS)'(1); + end + Status_StopBit: begin + tx <= 1'b1; + if (bitClkCnt == $clog2(BIT_CLOCKS)'(BIT_CLOCKS - 1)) begin + bitClkCnt <= $clog2(BIT_CLOCKS)'(0); + tx_done <= 1'b1; + status <= Status_Finalize; + end + else bitClkCnt <= bitClkCnt + $clog2(BIT_CLOCKS)'(1); + end + Status_Finalize: begin + tx_en <= 1'b0; + tx_done <= 1'b1; + status <= Status_Idle; + end + endcase + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.sv2009/hdl/UART_Tx_defs.svh b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.sv2009/hdl/UART_Tx_defs.svh new file mode 100644 index 000000000..aff0ed698 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.sv2009/hdl/UART_Tx_defs.svh @@ -0,0 +1,4 @@ +`ifndef UART_TX_DEFS +`define UART_TX_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v2001/hdl/UART_Tx.v b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v2001/hdl/UART_Tx.v new file mode 100644 index 000000000..93292b63c --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v2001/hdl/UART_Tx.v @@ -0,0 +1,87 @@ +`default_nettype none +`timescale 1ns/1ps +`include "UART_Tx_defs.vh" + +module UART_Tx#( + parameter integer CLK_FREQ_KHz = 50000, + parameter integer BAUD_RATE_BPS = 115200 +)( + input wire clk, + input wire rst, + input wire data_en, + input wire [7:0] data, + output reg tx, + output reg tx_en, + output reg tx_done +); + `include "dfhdl_defs.vh" + parameter integer BIT_CLOCKS = (CLK_FREQ_KHz * 1000) / BAUD_RATE_BPS; + `define Status_Idle 1 + `define Status_StartBit 2 + `define Status_DataBits 4 + `define Status_StopBit 8 + `define Status_Finalize 16 + reg [4:0] status; + reg [clog2(BIT_CLOCKS) - 1:0] bitClkCnt; + reg [2:0] dataBitCnt; + reg [7:0] shiftData; + always @(posedge clk) + begin + if (rst == 1'b1) begin + status <= `Status_Idle; + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + dataBitCnt <= 3'd0; + end + else begin + case (status) + `Status_Idle: begin + tx_en <= 1'b0; + tx <= 1'b1; + tx_done <= 1'b0; + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + dataBitCnt <= 3'd0; + if (data_en) begin + shiftData <= data; + status <= `Status_StartBit; + end + end + `Status_StartBit: begin + tx_en <= 1'b1; + tx <= 1'b0; + if (bitClkCnt == (BIT_CLOCKS - 1)) begin + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + status <= `Status_DataBits; + end + else bitClkCnt <= bitClkCnt + `TO_UNSIGNED(1, 1, clog2(BIT_CLOCKS)); + end + `Status_DataBits: begin + tx <= shiftData[0]; + if (bitClkCnt == (BIT_CLOCKS - 1)) begin + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + shiftData <= shiftData >> 1; + if (dataBitCnt == 3'd7) begin + dataBitCnt <= 3'd0; + status <= `Status_StopBit; + end + else dataBitCnt <= dataBitCnt + 3'd1; + end + else bitClkCnt <= bitClkCnt + `TO_UNSIGNED(1, 1, clog2(BIT_CLOCKS)); + end + `Status_StopBit: begin + tx <= 1'b1; + if (bitClkCnt == (BIT_CLOCKS - 1)) begin + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + tx_done <= 1'b1; + status <= `Status_Finalize; + end + else bitClkCnt <= bitClkCnt + `TO_UNSIGNED(1, 1, clog2(BIT_CLOCKS)); + end + `Status_Finalize: begin + tx_en <= 1'b0; + tx_done <= 1'b1; + status <= `Status_Idle; + end + endcase + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v2001/hdl/UART_Tx_defs.vh b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v2001/hdl/UART_Tx_defs.vh new file mode 100644 index 000000000..aff0ed698 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v2001/hdl/UART_Tx_defs.vh @@ -0,0 +1,4 @@ +`ifndef UART_TX_DEFS +`define UART_TX_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v95/hdl/UART_Tx.v b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v95/hdl/UART_Tx.v new file mode 100644 index 000000000..9df34c595 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v95/hdl/UART_Tx.v @@ -0,0 +1,93 @@ +`default_nettype none +`timescale 1ns/1ps +`include "UART_Tx_defs.vh" + +module UART_Tx( + clk, + rst, + data_en, + data, + tx, + tx_en, + tx_done +); + `include "dfhdl_defs.vh" + parameter integer CLK_FREQ_KHz = 50000; + parameter integer BAUD_RATE_BPS = 115200; + parameter integer BIT_CLOCKS = (CLK_FREQ_KHz * 1000) / BAUD_RATE_BPS; + `define Status_Idle 1 + `define Status_StartBit 2 + `define Status_DataBits 4 + `define Status_StopBit 8 + `define Status_Finalize 16 + input wire clk; + input wire rst; + input wire data_en; + input wire [7:0] data; + output reg tx; + output reg tx_en; + output reg tx_done; + reg [4:0] status; + reg [clog2(BIT_CLOCKS) - 1:0] bitClkCnt; + reg [2:0] dataBitCnt; + reg [7:0] shiftData; + always @(posedge clk) + begin + if (rst == 1'b1) begin + status <= `Status_Idle; + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + dataBitCnt <= 3'd0; + end + else begin + case (status) + `Status_Idle: begin + tx_en <= 1'b0; + tx <= 1'b1; + tx_done <= 1'b0; + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + dataBitCnt <= 3'd0; + if (data_en) begin + shiftData <= data; + status <= `Status_StartBit; + end + end + `Status_StartBit: begin + tx_en <= 1'b1; + tx <= 1'b0; + if (bitClkCnt == (BIT_CLOCKS - 1)) begin + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + status <= `Status_DataBits; + end + else bitClkCnt <= bitClkCnt + `TO_UNSIGNED(1, 1, clog2(BIT_CLOCKS)); + end + `Status_DataBits: begin + tx <= shiftData[0]; + if (bitClkCnt == (BIT_CLOCKS - 1)) begin + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + shiftData <= shiftData >> 1; + if (dataBitCnt == 3'd7) begin + dataBitCnt <= 3'd0; + status <= `Status_StopBit; + end + else dataBitCnt <= dataBitCnt + 3'd1; + end + else bitClkCnt <= bitClkCnt + `TO_UNSIGNED(1, 1, clog2(BIT_CLOCKS)); + end + `Status_StopBit: begin + tx <= 1'b1; + if (bitClkCnt == (BIT_CLOCKS - 1)) begin + bitClkCnt <= `TO_UNSIGNED(0, 1, clog2(BIT_CLOCKS)); + tx_done <= 1'b1; + status <= `Status_Finalize; + end + else bitClkCnt <= bitClkCnt + `TO_UNSIGNED(1, 1, clog2(BIT_CLOCKS)); + end + `Status_Finalize: begin + tx_en <= 1'b0; + tx_done <= 1'b1; + status <= `Status_Idle; + end + endcase + end + end +endmodule diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v95/hdl/UART_Tx_defs.vh b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v95/hdl/UART_Tx_defs.vh new file mode 100644 index 000000000..aff0ed698 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/verilog.v95/hdl/UART_Tx_defs.vh @@ -0,0 +1,4 @@ +`ifndef UART_TX_DEFS +`define UART_TX_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v2008/hdl/UART_Tx.vhd b/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v2008/hdl/UART_Tx.vhd new file mode 100644 index 000000000..96a786908 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v2008/hdl/UART_Tx.vhd @@ -0,0 +1,88 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.UART_Tx_pkg.all; + +entity UART_Tx is +generic ( + CLK_FREQ_KHz : integer := 50000; + BAUD_RATE_BPS : integer := 115200 +); +port ( + clk : in std_logic; + rst : in std_logic; + data_en : in std_logic; + data : in std_logic_vector(7 downto 0); + tx : out std_logic; + tx_en : out std_logic; + tx_done : out std_logic +); +end UART_Tx; + +architecture UART_Tx_arch of UART_Tx is + constant BIT_CLOCKS : integer := (CLK_FREQ_KHz * 1000) / BAUD_RATE_BPS; + type t_enum_Status is ( + Status_Idle, Status_StartBit, Status_DataBits, Status_StopBit, Status_Finalize + ); + signal status : t_enum_Status; + signal bitClkCnt : unsigned(clog2(BIT_CLOCKS) - 1 downto 0); + signal dataBitCnt : unsigned(2 downto 0); + signal shiftData : std_logic_vector(7 downto 0); +begin + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then + status <= Status_Idle; + bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); + dataBitCnt <= 3d"0"; + else + case status is + when Status_Idle => + tx_en <= '0'; + tx <= '1'; + tx_done <= '0'; + bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); + dataBitCnt <= 3d"0"; + if data_en then + shiftData <= data; + status <= Status_StartBit; + end if; + when Status_StartBit => + tx_en <= '1'; + tx <= '0'; + if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then + bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); + status <= Status_DataBits; + else bitClkCnt <= bitClkCnt + resize(d"1", clog2(BIT_CLOCKS)); + end if; + when Status_DataBits => + tx <= shiftData(0); + if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then + bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); + shiftData <= slv_srl(shiftData, 1); + if dataBitCnt = 3d"7" then + dataBitCnt <= 3d"0"; + status <= Status_StopBit; + else dataBitCnt <= dataBitCnt + 3d"1"; + end if; + else bitClkCnt <= bitClkCnt + resize(d"1", clog2(BIT_CLOCKS)); + end if; + when Status_StopBit => + tx <= '1'; + if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then + bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); + tx_done <= '1'; + status <= Status_Finalize; + else bitClkCnt <= bitClkCnt + resize(d"1", clog2(BIT_CLOCKS)); + end if; + when Status_Finalize => + tx_en <= '0'; + tx_done <= '1'; + status <= Status_Idle; + end case; + end if; + end if; + end process; +end UART_Tx_arch; diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v2008/hdl/UART_Tx_pkg.vhd b/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v2008/hdl/UART_Tx_pkg.vhd new file mode 100644 index 000000000..00ff59a52 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v2008/hdl/UART_Tx_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package UART_Tx_pkg is + +end package UART_Tx_pkg; + +package body UART_Tx_pkg is + +end package body UART_Tx_pkg; diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v93/hdl/UART_Tx.vhd b/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v93/hdl/UART_Tx.vhd new file mode 100644 index 000000000..15e99debc --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v93/hdl/UART_Tx.vhd @@ -0,0 +1,88 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.UART_Tx_pkg.all; + +entity UART_Tx is +generic ( + CLK_FREQ_KHz : integer := 50000; + BAUD_RATE_BPS : integer := 115200 +); +port ( + clk : in std_logic; + rst : in std_logic; + data_en : in std_logic; + data : in std_logic_vector(7 downto 0); + tx : out std_logic; + tx_en : out std_logic; + tx_done : out std_logic +); +end UART_Tx; + +architecture UART_Tx_arch of UART_Tx is + constant BIT_CLOCKS : integer := (CLK_FREQ_KHz * 1000) / BAUD_RATE_BPS; + type t_enum_Status is ( + Status_Idle, Status_StartBit, Status_DataBits, Status_StopBit, Status_Finalize + ); + signal status : t_enum_Status; + signal bitClkCnt : unsigned(clog2(BIT_CLOCKS) - 1 downto 0); + signal dataBitCnt : unsigned(2 downto 0); + signal shiftData : std_logic_vector(7 downto 0); +begin + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then + status <= Status_Idle; + bitClkCnt <= to_unsigned(0, clog2(BIT_CLOCKS)); + dataBitCnt <= to_unsigned(0, 3); + else + case status is + when Status_Idle => + tx_en <= '0'; + tx <= '1'; + tx_done <= '0'; + bitClkCnt <= to_unsigned(0, clog2(BIT_CLOCKS)); + dataBitCnt <= to_unsigned(0, 3); + if to_bool(data_en) then + shiftData <= data; + status <= Status_StartBit; + end if; + when Status_StartBit => + tx_en <= '1'; + tx <= '0'; + if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then + bitClkCnt <= to_unsigned(0, clog2(BIT_CLOCKS)); + status <= Status_DataBits; + else bitClkCnt <= bitClkCnt + to_unsigned(1, clog2(BIT_CLOCKS)); + end if; + when Status_DataBits => + tx <= shiftData(0); + if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then + bitClkCnt <= to_unsigned(0, clog2(BIT_CLOCKS)); + shiftData <= slv_srl(shiftData, 1); + if dataBitCnt = to_unsigned(7, 3) then + dataBitCnt <= to_unsigned(0, 3); + status <= Status_StopBit; + else dataBitCnt <= dataBitCnt + to_unsigned(1, 3); + end if; + else bitClkCnt <= bitClkCnt + to_unsigned(1, clog2(BIT_CLOCKS)); + end if; + when Status_StopBit => + tx <= '1'; + if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then + bitClkCnt <= to_unsigned(0, clog2(BIT_CLOCKS)); + tx_done <= '1'; + status <= Status_Finalize; + else bitClkCnt <= bitClkCnt + to_unsigned(1, clog2(BIT_CLOCKS)); + end if; + when Status_Finalize => + tx_en <= '0'; + tx_done <= '1'; + status <= Status_Idle; + end case; + end if; + end if; + end process; +end UART_Tx_arch; diff --git a/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v93/hdl/UART_Tx_pkg.vhd b/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v93/hdl/UART_Tx_pkg.vhd new file mode 100644 index 000000000..00ff59a52 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.UART_TxSpec/vhdl.v93/hdl/UART_Tx_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package UART_Tx_pkg is + +end package UART_Tx_pkg; + +package body UART_Tx_pkg is + +end package body UART_Tx_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.sv2009/hdl/LeftShift2.sv b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.sv2009/hdl/LeftShift2.sv new file mode 100644 index 000000000..a7b381e2e --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.sv2009/hdl/LeftShift2.sv @@ -0,0 +1,14 @@ +/* A two-bits left shifter */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShift2_defs.svh" + +module LeftShift2( + /* bits input */ + input wire logic [7:0] iBits, + /* bits output */ + output logic [7:0] oBits +); + `include "dfhdl_defs.svh" + assign oBits = iBits << 2; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.sv2009/hdl/LeftShift2_defs.svh b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.sv2009/hdl/LeftShift2_defs.svh new file mode 100644 index 000000000..0a11905a5 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.sv2009/hdl/LeftShift2_defs.svh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFT2_DEFS +`define LEFTSHIFT2_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v2001/hdl/LeftShift2.v b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v2001/hdl/LeftShift2.v new file mode 100644 index 000000000..3c1573ea9 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v2001/hdl/LeftShift2.v @@ -0,0 +1,14 @@ +/* A two-bits left shifter */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShift2_defs.vh" + +module LeftShift2( + /* bits input */ + input wire [7:0] iBits, + /* bits output */ + output wire [7:0] oBits +); + `include "dfhdl_defs.vh" + assign oBits = iBits << 2; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v2001/hdl/LeftShift2_defs.vh b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v2001/hdl/LeftShift2_defs.vh new file mode 100644 index 000000000..0a11905a5 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v2001/hdl/LeftShift2_defs.vh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFT2_DEFS +`define LEFTSHIFT2_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v95/hdl/LeftShift2.v b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v95/hdl/LeftShift2.v new file mode 100644 index 000000000..b9c4c884f --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v95/hdl/LeftShift2.v @@ -0,0 +1,16 @@ +/* A two-bits left shifter */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShift2_defs.vh" + +module LeftShift2( + iBits, + oBits +); + `include "dfhdl_defs.vh" + /* bits input */ + input wire [7:0] iBits; + /* bits output */ + output wire [7:0] oBits; + assign oBits = iBits << 2; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v95/hdl/LeftShift2_defs.vh b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v95/hdl/LeftShift2_defs.vh new file mode 100644 index 000000000..0a11905a5 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/verilog.v95/hdl/LeftShift2_defs.vh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFT2_DEFS +`define LEFTSHIFT2_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v2008/hdl/LeftShift2.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v2008/hdl/LeftShift2.vhd new file mode 100644 index 000000000..dafcd564d --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v2008/hdl/LeftShift2.vhd @@ -0,0 +1,20 @@ +-- A two-bits left shifter +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.LeftShift2_pkg.all; + +entity LeftShift2 is +port ( + -- bits input + iBits : in std_logic_vector(7 downto 0); + -- bits output + oBits : out std_logic_vector(7 downto 0) +); +end LeftShift2; + +architecture LeftShift2_arch of LeftShift2 is +begin + oBits <= slv_sll(iBits, 2); +end LeftShift2_arch; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v2008/hdl/LeftShift2_pkg.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v2008/hdl/LeftShift2_pkg.vhd new file mode 100644 index 000000000..8f5ebeae8 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v2008/hdl/LeftShift2_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package LeftShift2_pkg is + +end package LeftShift2_pkg; + +package body LeftShift2_pkg is + +end package body LeftShift2_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v93/hdl/LeftShift2.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v93/hdl/LeftShift2.vhd new file mode 100644 index 000000000..dafcd564d --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v93/hdl/LeftShift2.vhd @@ -0,0 +1,20 @@ +-- A two-bits left shifter +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.LeftShift2_pkg.all; + +entity LeftShift2 is +port ( + -- bits input + iBits : in std_logic_vector(7 downto 0); + -- bits output + oBits : out std_logic_vector(7 downto 0) +); +end LeftShift2; + +architecture LeftShift2_arch of LeftShift2 is +begin + oBits <= slv_sll(iBits, 2); +end LeftShift2_arch; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v93/hdl/LeftShift2_pkg.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v93/hdl/LeftShift2_pkg.vhd new file mode 100644 index 000000000..8f5ebeae8 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo1.LeftShift2Spec/vhdl.v93/hdl/LeftShift2_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package LeftShift2_pkg is + +end package LeftShift2_pkg; + +package body LeftShift2_pkg is + +end package body LeftShift2_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.sv2009/hdl/LeftShiftBasic.sv b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.sv2009/hdl/LeftShiftBasic.sv new file mode 100644 index 000000000..0e47cdaa0 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.sv2009/hdl/LeftShiftBasic.sv @@ -0,0 +1,16 @@ +/* A basic left shifter */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftBasic_defs.svh" + +module LeftShiftBasic( + /* bits input */ + input wire logic [7:0] iBits, + /* requested shift */ + input wire logic [2:0] shift, + /* bits output */ + output logic [7:0] oBits +); + `include "dfhdl_defs.svh" + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.sv2009/hdl/LeftShiftBasic_defs.svh b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.sv2009/hdl/LeftShiftBasic_defs.svh new file mode 100644 index 000000000..4bd027569 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.sv2009/hdl/LeftShiftBasic_defs.svh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTBASIC_DEFS +`define LEFTSHIFTBASIC_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v2001/hdl/LeftShiftBasic.v b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v2001/hdl/LeftShiftBasic.v new file mode 100644 index 000000000..152122289 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v2001/hdl/LeftShiftBasic.v @@ -0,0 +1,16 @@ +/* A basic left shifter */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftBasic_defs.vh" + +module LeftShiftBasic( + /* bits input */ + input wire [7:0] iBits, + /* requested shift */ + input wire [2:0] shift, + /* bits output */ + output wire [7:0] oBits +); + `include "dfhdl_defs.vh" + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v2001/hdl/LeftShiftBasic_defs.vh b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v2001/hdl/LeftShiftBasic_defs.vh new file mode 100644 index 000000000..4bd027569 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v2001/hdl/LeftShiftBasic_defs.vh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTBASIC_DEFS +`define LEFTSHIFTBASIC_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v95/hdl/LeftShiftBasic.v b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v95/hdl/LeftShiftBasic.v new file mode 100644 index 000000000..8d3a797bb --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v95/hdl/LeftShiftBasic.v @@ -0,0 +1,19 @@ +/* A basic left shifter */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftBasic_defs.vh" + +module LeftShiftBasic( + iBits, + shift, + oBits +); + `include "dfhdl_defs.vh" + /* bits input */ + input wire [7:0] iBits; + /* requested shift */ + input wire [2:0] shift; + /* bits output */ + output wire [7:0] oBits; + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v95/hdl/LeftShiftBasic_defs.vh b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v95/hdl/LeftShiftBasic_defs.vh new file mode 100644 index 000000000..4bd027569 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/verilog.v95/hdl/LeftShiftBasic_defs.vh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTBASIC_DEFS +`define LEFTSHIFTBASIC_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v2008/hdl/LeftShiftBasic.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v2008/hdl/LeftShiftBasic.vhd new file mode 100644 index 000000000..1f7627399 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v2008/hdl/LeftShiftBasic.vhd @@ -0,0 +1,22 @@ +-- A basic left shifter +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.LeftShiftBasic_pkg.all; + +entity LeftShiftBasic is +port ( + -- bits input + iBits : in std_logic_vector(7 downto 0); + -- requested shift + shift : in unsigned(2 downto 0); + -- bits output + oBits : out std_logic_vector(7 downto 0) +); +end LeftShiftBasic; + +architecture LeftShiftBasic_arch of LeftShiftBasic is +begin + oBits <= slv_sll(iBits, to_integer(shift)); +end LeftShiftBasic_arch; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v2008/hdl/LeftShiftBasic_pkg.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v2008/hdl/LeftShiftBasic_pkg.vhd new file mode 100644 index 000000000..57bd9c05e --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v2008/hdl/LeftShiftBasic_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package LeftShiftBasic_pkg is + +end package LeftShiftBasic_pkg; + +package body LeftShiftBasic_pkg is + +end package body LeftShiftBasic_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v93/hdl/LeftShiftBasic.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v93/hdl/LeftShiftBasic.vhd new file mode 100644 index 000000000..1f7627399 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v93/hdl/LeftShiftBasic.vhd @@ -0,0 +1,22 @@ +-- A basic left shifter +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.LeftShiftBasic_pkg.all; + +entity LeftShiftBasic is +port ( + -- bits input + iBits : in std_logic_vector(7 downto 0); + -- requested shift + shift : in unsigned(2 downto 0); + -- bits output + oBits : out std_logic_vector(7 downto 0) +); +end LeftShiftBasic; + +architecture LeftShiftBasic_arch of LeftShiftBasic is +begin + oBits <= slv_sll(iBits, to_integer(shift)); +end LeftShiftBasic_arch; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v93/hdl/LeftShiftBasic_pkg.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v93/hdl/LeftShiftBasic_pkg.vhd new file mode 100644 index 000000000..57bd9c05e --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo2.LeftShiftBasicSpec/vhdl.v93/hdl/LeftShiftBasic_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package LeftShiftBasic_pkg is + +end package LeftShiftBasic_pkg; + +package body LeftShiftBasic_pkg is + +end package body LeftShiftBasic_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.sv2009/hdl/LeftShiftGen.sv b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.sv2009/hdl/LeftShiftGen.sv new file mode 100644 index 000000000..fad9cc77b --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.sv2009/hdl/LeftShiftGen.sv @@ -0,0 +1,20 @@ +/* A generic left shifter + + @param width + the width of the input and output bits + */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftGen_defs.svh" + +module LeftShiftGen#(parameter int width = 8)( + /* bits input */ + input wire logic [width - 1:0] iBits, + /* requested shift */ + input wire logic [$clog2(width) - 1:0] shift, + /* bits output */ + output logic [width - 1:0] oBits +); + `include "dfhdl_defs.svh" + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.sv2009/hdl/LeftShiftGen_defs.svh b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.sv2009/hdl/LeftShiftGen_defs.svh new file mode 100644 index 000000000..0c188abc2 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.sv2009/hdl/LeftShiftGen_defs.svh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTGEN_DEFS +`define LEFTSHIFTGEN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v2001/hdl/LeftShiftGen.v b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v2001/hdl/LeftShiftGen.v new file mode 100644 index 000000000..aad0f0fec --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v2001/hdl/LeftShiftGen.v @@ -0,0 +1,20 @@ +/* A generic left shifter + + @param width + the width of the input and output bits + */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftGen_defs.vh" + +module LeftShiftGen#(parameter integer width = 8)( + /* bits input */ + input wire [width - 1:0] iBits, + /* requested shift */ + input wire [clog2(width) - 1:0] shift, + /* bits output */ + output wire [width - 1:0] oBits +); + `include "dfhdl_defs.vh" + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v2001/hdl/LeftShiftGen_defs.vh b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v2001/hdl/LeftShiftGen_defs.vh new file mode 100644 index 000000000..0c188abc2 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v2001/hdl/LeftShiftGen_defs.vh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTGEN_DEFS +`define LEFTSHIFTGEN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v95/hdl/LeftShiftGen.v b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v95/hdl/LeftShiftGen.v new file mode 100644 index 000000000..0776169c5 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v95/hdl/LeftShiftGen.v @@ -0,0 +1,24 @@ +/* A generic left shifter + + @param width + the width of the input and output bits + */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftGen_defs.vh" + +module LeftShiftGen( + iBits, + shift, + oBits +); + `include "dfhdl_defs.vh" + parameter integer width = 8; + /* bits input */ + input wire [width - 1:0] iBits; + /* requested shift */ + input wire [clog2(width) - 1:0] shift; + /* bits output */ + output wire [width - 1:0] oBits; + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v95/hdl/LeftShiftGen_defs.vh b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v95/hdl/LeftShiftGen_defs.vh new file mode 100644 index 000000000..0c188abc2 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/verilog.v95/hdl/LeftShiftGen_defs.vh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTGEN_DEFS +`define LEFTSHIFTGEN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v2008/hdl/LeftShiftGen.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v2008/hdl/LeftShiftGen.vhd new file mode 100644 index 000000000..92a5b0696 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v2008/hdl/LeftShiftGen.vhd @@ -0,0 +1,28 @@ +-- A generic left shifter +-- +-- @param width +-- the width of the input and output bits +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.LeftShiftGen_pkg.all; + +entity LeftShiftGen is +generic ( + width : integer := 8 +); +port ( + -- bits input + iBits : in std_logic_vector(width - 1 downto 0); + -- requested shift + shift : in unsigned(clog2(width) - 1 downto 0); + -- bits output + oBits : out std_logic_vector(width - 1 downto 0) +); +end LeftShiftGen; + +architecture LeftShiftGen_arch of LeftShiftGen is +begin + oBits <= slv_sll(iBits, to_integer(shift)); +end LeftShiftGen_arch; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v2008/hdl/LeftShiftGen_pkg.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v2008/hdl/LeftShiftGen_pkg.vhd new file mode 100644 index 000000000..7cd1789a1 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v2008/hdl/LeftShiftGen_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package LeftShiftGen_pkg is + +end package LeftShiftGen_pkg; + +package body LeftShiftGen_pkg is + +end package body LeftShiftGen_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v93/hdl/LeftShiftGen.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v93/hdl/LeftShiftGen.vhd new file mode 100644 index 000000000..92a5b0696 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v93/hdl/LeftShiftGen.vhd @@ -0,0 +1,28 @@ +-- A generic left shifter +-- +-- @param width +-- the width of the input and output bits +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.LeftShiftGen_pkg.all; + +entity LeftShiftGen is +generic ( + width : integer := 8 +); +port ( + -- bits input + iBits : in std_logic_vector(width - 1 downto 0); + -- requested shift + shift : in unsigned(clog2(width) - 1 downto 0); + -- bits output + oBits : out std_logic_vector(width - 1 downto 0) +); +end LeftShiftGen; + +architecture LeftShiftGen_arch of LeftShiftGen is +begin + oBits <= slv_sll(iBits, to_integer(shift)); +end LeftShiftGen_arch; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v93/hdl/LeftShiftGen_pkg.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v93/hdl/LeftShiftGen_pkg.vhd new file mode 100644 index 000000000..7cd1789a1 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftBasicGen/vhdl.v93/hdl/LeftShiftGen_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package LeftShiftGen_pkg is + +end package LeftShiftGen_pkg; + +package body LeftShiftGen_pkg is + +end package body LeftShiftGen_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.sv2009/hdl/LeftShiftGen.sv b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.sv2009/hdl/LeftShiftGen.sv new file mode 100644 index 000000000..fad9cc77b --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.sv2009/hdl/LeftShiftGen.sv @@ -0,0 +1,20 @@ +/* A generic left shifter + + @param width + the width of the input and output bits + */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftGen_defs.svh" + +module LeftShiftGen#(parameter int width = 8)( + /* bits input */ + input wire logic [width - 1:0] iBits, + /* requested shift */ + input wire logic [$clog2(width) - 1:0] shift, + /* bits output */ + output logic [width - 1:0] oBits +); + `include "dfhdl_defs.svh" + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.sv2009/hdl/LeftShiftGen_defs.svh b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.sv2009/hdl/LeftShiftGen_defs.svh new file mode 100644 index 000000000..0c188abc2 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.sv2009/hdl/LeftShiftGen_defs.svh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTGEN_DEFS +`define LEFTSHIFTGEN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v2001/hdl/LeftShiftGen.v b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v2001/hdl/LeftShiftGen.v new file mode 100644 index 000000000..aad0f0fec --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v2001/hdl/LeftShiftGen.v @@ -0,0 +1,20 @@ +/* A generic left shifter + + @param width + the width of the input and output bits + */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftGen_defs.vh" + +module LeftShiftGen#(parameter integer width = 8)( + /* bits input */ + input wire [width - 1:0] iBits, + /* requested shift */ + input wire [clog2(width) - 1:0] shift, + /* bits output */ + output wire [width - 1:0] oBits +); + `include "dfhdl_defs.vh" + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v2001/hdl/LeftShiftGen_defs.vh b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v2001/hdl/LeftShiftGen_defs.vh new file mode 100644 index 000000000..0c188abc2 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v2001/hdl/LeftShiftGen_defs.vh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTGEN_DEFS +`define LEFTSHIFTGEN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v95/hdl/LeftShiftGen.v b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v95/hdl/LeftShiftGen.v new file mode 100644 index 000000000..0776169c5 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v95/hdl/LeftShiftGen.v @@ -0,0 +1,24 @@ +/* A generic left shifter + + @param width + the width of the input and output bits + */ +`default_nettype none +`timescale 1ns/1ps +`include "LeftShiftGen_defs.vh" + +module LeftShiftGen( + iBits, + shift, + oBits +); + `include "dfhdl_defs.vh" + parameter integer width = 8; + /* bits input */ + input wire [width - 1:0] iBits; + /* requested shift */ + input wire [clog2(width) - 1:0] shift; + /* bits output */ + output wire [width - 1:0] oBits; + assign oBits = iBits << shift; +endmodule diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v95/hdl/LeftShiftGen_defs.vh b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v95/hdl/LeftShiftGen_defs.vh new file mode 100644 index 000000000..0c188abc2 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/verilog.v95/hdl/LeftShiftGen_defs.vh @@ -0,0 +1,4 @@ +`ifndef LEFTSHIFTGEN_DEFS +`define LEFTSHIFTGEN_DEFS + +`endif diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v2008/hdl/LeftShiftGen.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v2008/hdl/LeftShiftGen.vhd new file mode 100644 index 000000000..92a5b0696 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v2008/hdl/LeftShiftGen.vhd @@ -0,0 +1,28 @@ +-- A generic left shifter +-- +-- @param width +-- the width of the input and output bits +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.LeftShiftGen_pkg.all; + +entity LeftShiftGen is +generic ( + width : integer := 8 +); +port ( + -- bits input + iBits : in std_logic_vector(width - 1 downto 0); + -- requested shift + shift : in unsigned(clog2(width) - 1 downto 0); + -- bits output + oBits : out std_logic_vector(width - 1 downto 0) +); +end LeftShiftGen; + +architecture LeftShiftGen_arch of LeftShiftGen is +begin + oBits <= slv_sll(iBits, to_integer(shift)); +end LeftShiftGen_arch; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v2008/hdl/LeftShiftGen_pkg.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v2008/hdl/LeftShiftGen_pkg.vhd new file mode 100644 index 000000000..7cd1789a1 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v2008/hdl/LeftShiftGen_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package LeftShiftGen_pkg is + +end package LeftShiftGen_pkg; + +package body LeftShiftGen_pkg is + +end package body LeftShiftGen_pkg; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v93/hdl/LeftShiftGen.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v93/hdl/LeftShiftGen.vhd new file mode 100644 index 000000000..92a5b0696 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v93/hdl/LeftShiftGen.vhd @@ -0,0 +1,28 @@ +-- A generic left shifter +-- +-- @param width +-- the width of the input and output bits +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; +use work.LeftShiftGen_pkg.all; + +entity LeftShiftGen is +generic ( + width : integer := 8 +); +port ( + -- bits input + iBits : in std_logic_vector(width - 1 downto 0); + -- requested shift + shift : in unsigned(clog2(width) - 1 downto 0); + -- bits output + oBits : out std_logic_vector(width - 1 downto 0) +); +end LeftShiftGen; + +architecture LeftShiftGen_arch of LeftShiftGen is +begin + oBits <= slv_sll(iBits, to_integer(shift)); +end LeftShiftGen_arch; diff --git a/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v93/hdl/LeftShiftGen_pkg.vhd b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v93/hdl/LeftShiftGen_pkg.vhd new file mode 100644 index 000000000..7cd1789a1 --- /dev/null +++ b/lib/src/test/resources/ref/docExamples.ugdemos.demo3.LeftShiftGenSpec/vhdl.v93/hdl/LeftShiftGen_pkg.vhd @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.dfhdl_pkg.all; + +package LeftShiftGen_pkg is + +end package LeftShiftGen_pkg; + +package body LeftShiftGen_pkg is + +end package body LeftShiftGen_pkg; diff --git a/lib/src/test/scala/AES/CipherSpec.scala b/lib/src/test/scala/AES/CipherSpec.scala index 5be35eb74..6777f9265 100644 --- a/lib/src/test/scala/AES/CipherSpec.scala +++ b/lib/src/test/scala/AES/CipherSpec.scala @@ -6,8 +6,6 @@ import dfhdl.options.LinterOptions.VerilogLinter class CipherSpecWithOpaques extends util.FullCompileSpec: def dut: core.Design = Cipher() - def expectedVerilogCS: String = "" - def expectedVHDLCS: String = "" // TODO: need to fix Cipher verilog compilation errors override def verilogLinters: List[VerilogLinter] = Nil end CipherSpecWithOpaques diff --git a/lib/src/test/scala/docExamples/ALUSpec.scala b/lib/src/test/scala/docExamples/ALUSpec.scala index 1b68818e9..15f37e269 100644 --- a/lib/src/test/scala/docExamples/ALUSpec.scala +++ b/lib/src/test/scala/docExamples/ALUSpec.scala @@ -2,98 +2,4 @@ package docExamples class ALUSpec extends util.FullCompileSpec: def dut = alu.ALU() - - def expectedVerilogCS = - """|typedef enum logic [3:0] { - | ALUSel_ADD = 0, - | ALUSel_SUB = 1, - | ALUSel_SLL = 2, - | ALUSel_SRL = 3, - | ALUSel_SRA = 4, - | ALUSel_AND = 5, - | ALUSel_OR = 6, - | ALUSel_XOR = 7, - | ALUSel_SLT = 8, - | ALUSel_SLTU = 9, - | ALUSel_COPY1 = 10 - |} t_enum_ALUSel; - | - |`default_nettype none - |`timescale 1ns/1ps - |`include "ALU_defs.svh" - | - |module ALU( - | input wire logic [31:0] op1, - | input wire logic [31:0] op2, - | input wire t_enum_ALUSel aluSel, - | output logic [31:0] aluOut - |); - | `include "dfhdl_defs.svh" - | logic [4:0] shamt; - | logic [31:0] outCalc; - | always_comb - | begin - | case (aluSel) - | ALUSel_ADD: outCalc = op1 + op2; - | ALUSel_SUB: outCalc = op1 - op2; - | ALUSel_AND: outCalc = op1 & op2; - | ALUSel_OR: outCalc = op1 | op2; - | ALUSel_XOR: outCalc = op1 ^ op2; - | ALUSel_SLT: outCalc = {{(32-1){1'b0}}, {$signed(op1) < $signed(op2)}}; - | ALUSel_SLTU: outCalc = {{(32-1){1'b0}}, {op1 < op2}}; - | ALUSel_SLL: outCalc = op1 << shamt; - | ALUSel_SRL: outCalc = op1 >> shamt; - | ALUSel_SRA: outCalc = {$signed(op1) >>> shamt}; - | ALUSel_COPY1: outCalc = op1; - | default: outCalc = 32'h????????; - | endcase - | end - | assign shamt = op2[4:0]; - | assign aluOut = outCalc; - |endmodule""".stripMargin - - def expectedVHDLCS = - """|type t_enum_ALUSel is ( - | ALUSel_ADD, ALUSel_SUB, ALUSel_SLL, ALUSel_SRL, ALUSel_SRA, ALUSel_AND, ALUSel_OR, ALUSel_XOR, ALUSel_SLT, ALUSel_SLTU, ALUSel_COPY1 - |); - | - |library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.ALU_pkg.all; - | - |entity ALU is - |port ( - | op1 : in std_logic_vector(31 downto 0); - | op2 : in std_logic_vector(31 downto 0); - | aluSel : in t_enum_ALUSel; - | aluOut : out std_logic_vector(31 downto 0) - |); - |end ALU; - | - |architecture ALU_arch of ALU is - | signal shamt : std_logic_vector(4 downto 0); - | signal outCalc : std_logic_vector(31 downto 0); - |begin - | process (all) - | begin - | case aluSel is - | when ALUSel_ADD => outCalc <= to_slv(unsigned(op1) + unsigned(op2)); - | when ALUSel_SUB => outCalc <= to_slv(unsigned(op1) - unsigned(op2)); - | when ALUSel_AND => outCalc <= op1 and op2; - | when ALUSel_OR => outCalc <= op1 or op2; - | when ALUSel_XOR => outCalc <= op1 xor op2; - | when ALUSel_SLT => outCalc <= resize(to_slv(signed(op1) < signed(op2)), 32); - | when ALUSel_SLTU => outCalc <= resize(to_slv(unsigned(op1) < unsigned(op2)), 32); - | when ALUSel_SLL => outCalc <= slv_sll(op1, to_integer(unsigned(shamt))); - | when ALUSel_SRL => outCalc <= slv_srl(op1, to_integer(unsigned(shamt))); - | when ALUSel_SRA => outCalc <= to_slv(signed_sra(signed(op1), to_integer(unsigned(shamt)))); - | when ALUSel_COPY1 => outCalc <= op1; - | when others => outCalc <= x"--------"; - | end case; - | end process; - | shamt <= op2(4 downto 0); - | aluOut <= outCalc; - |end ALU_arch;""".stripMargin end ALUSpec diff --git a/lib/src/test/scala/docExamples/BlinkerSpec.scala b/lib/src/test/scala/docExamples/BlinkerSpec.scala index fe8c01055..1be521636 100644 --- a/lib/src/test/scala/docExamples/BlinkerSpec.scala +++ b/lib/src/test/scala/docExamples/BlinkerSpec.scala @@ -2,83 +2,4 @@ package docExamples class BlinkerSpec extends util.FullCompileSpec: def dut = led_blinker.Blinker() - - def expectedVerilogCS = - """|/* This is a led blinker */ - |`default_nettype none - |`timescale 1ns/1ps - |`include "Blinker_defs.svh" - | - |module Blinker#( - | parameter int CLK_FREQ_KHz = 50000, - | parameter int LED_FREQ_Hz = 1 - |)( - | input wire logic clk, - | input wire logic rst, - | /* LED output */ - | output logic led - |); - | `include "dfhdl_defs.svh" - | /* Half-count of the toggle for 50% duty cycle */ - | parameter int HALF_PERIOD = (CLK_FREQ_KHz * 1000) / (LED_FREQ_Hz * 2); - | logic [$clog2(HALF_PERIOD) - 1:0] cnt; - | always_ff @(posedge clk) - | begin - | if (rst == 1'b1) begin - | led <= 1'b1; - | cnt <= $clog2(HALF_PERIOD)'(0); - | end - | else begin - | if (cnt == $clog2(HALF_PERIOD)'(HALF_PERIOD - 1)) begin - | cnt <= $clog2(HALF_PERIOD)'(0); - | led <= !led; - | end - | else cnt <= cnt + $clog2(HALF_PERIOD)'(1); - | end - | end - |endmodule - |""".stripMargin - - def expectedVHDLCS = - """|-- This is a led blinker - |library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.Blinker_pkg.all; - | - |entity Blinker is - |generic ( - | CLK_FREQ_KHz : integer := 50000; - | LED_FREQ_Hz : integer := 1 - |); - |port ( - | clk : in std_logic; - | rst : in std_logic; - | -- LED output - | led : out std_logic - |); - |end Blinker; - | - |architecture Blinker_arch of Blinker is - | -- Half-count of the toggle for 50% duty cycle - | constant HALF_PERIOD : integer := (CLK_FREQ_KHz * 1000) / (LED_FREQ_Hz * 2); - | signal cnt : unsigned(clog2(HALF_PERIOD) - 1 downto 0); - |begin - | process (clk) - | begin - | if rising_edge(clk) then - | if rst = '1' then - | led <= '1'; - | cnt <= resize(d"0", clog2(HALF_PERIOD)); - | else - | if cnt = to_unsigned(HALF_PERIOD - 1, clog2(HALF_PERIOD)) then - | cnt <= resize(d"0", clog2(HALF_PERIOD)); - | led <= not led; - | else cnt <= cnt + resize(d"1", clog2(HALF_PERIOD)); - | end if; - | end if; - | end if; - | end process; - |end Blinker_arch;""".stripMargin end BlinkerSpec diff --git a/lib/src/test/scala/docExamples/CounterSpec.scala b/lib/src/test/scala/docExamples/CounterSpec.scala index 6a63fa25e..2ca360bb7 100644 --- a/lib/src/test/scala/docExamples/CounterSpec.scala +++ b/lib/src/test/scala/docExamples/CounterSpec.scala @@ -2,60 +2,4 @@ package docExamples class CounterSpec extends util.FullCompileSpec: def dut = counter.Counter() - - def expectedVerilogCS = - """|`default_nettype none - |`timescale 1ns/1ps - |`include "Counter_defs.svh" - | - |module Counter#(parameter int width = 8)( - | input wire logic clk, - | input wire logic rst, - | input wire logic en, - | output logic [width - 1:0] cnt - |); - | `include "dfhdl_defs.svh" - | always_ff @(posedge clk) - | begin - | if (rst == 1'b1) cnt <= width'(0); - | else begin - | if (en) cnt <= cnt + width'(1); - | end - | end - |endmodule - |""".stripMargin - - def expectedVHDLCS = - """|library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.Counter_pkg.all; - | - |entity Counter is - |generic ( - | width : integer := 8 - |); - |port ( - | clk : in std_logic; - | rst : in std_logic; - | en : in std_logic; - | cnt : out unsigned(width - 1 downto 0) - |); - |end Counter; - | - |architecture Counter_arch of Counter is - |begin - | process (clk) - | begin - | if rising_edge(clk) then - | if rst = '1' then cnt <= resize(d"0", width); - | else - | if en then cnt <= cnt + resize(d"1", width); - | end if; - | end if; - | end if; - | end process; - |end Counter_arch; - |""".stripMargin end CounterSpec diff --git a/lib/src/test/scala/docExamples/FullAdder1Spec.scala b/lib/src/test/scala/docExamples/FullAdder1Spec.scala index e63c6014f..aa30a07c2 100644 --- a/lib/src/test/scala/docExamples/FullAdder1Spec.scala +++ b/lib/src/test/scala/docExamples/FullAdder1Spec.scala @@ -2,46 +2,4 @@ package docExamples class FullAdder1Spec extends util.FullCompileSpec: def dut = fullAdder1.FullAdder1() - - def expectedVerilogCS = - """|`default_nettype none - |`timescale 1ns/1ps - |`include "FullAdder1_defs.svh" - | - |module FullAdder1( - | input wire logic a, - | input wire logic b, - | input wire logic c_in, - | output logic sum, - | output logic c_out - |); - | `include "dfhdl_defs.svh" - | assign sum = (a ^ b) ^ c_in; - | assign c_out = ((a & b) | (b & c_in)) | (c_in & a); - |endmodule - |""".stripMargin - - def expectedVHDLCS = - """|library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.FullAdder1_pkg.all; - | - |entity FullAdder1 is - |port ( - | a : in std_logic; - | b : in std_logic; - | c_in : in std_logic; - | sum : out std_logic; - | c_out : out std_logic - |); - |end FullAdder1; - | - |architecture FullAdder1_arch of FullAdder1 is - |begin - | sum <= (a xor b) xor c_in; - | c_out <= ((a and b) or (b and c_in)) or (c_in and a); - |end FullAdder1_arch; - |""".stripMargin end FullAdder1Spec diff --git a/lib/src/test/scala/docExamples/FullAdderNSpec.scala b/lib/src/test/scala/docExamples/FullAdderNSpec.scala index bc5d2a135..4a57d454d 100644 --- a/lib/src/test/scala/docExamples/FullAdderNSpec.scala +++ b/lib/src/test/scala/docExamples/FullAdderNSpec.scala @@ -2,208 +2,4 @@ package docExamples class FullAdderNSpec extends util.FullCompileSpec: def dut = fullAdderN.FullAdderN() - - def expectedVerilogCS = - """|`default_nettype none - |`timescale 1ns/1ps - |`include "FullAdderN_defs.svh" - | - |module FullAdder1( - | input wire logic a, - | input wire logic b, - | input wire logic c_in, - | output logic sum, - | output logic c_out - |); - | `include "dfhdl_defs.svh" - | assign sum = (a ^ b) ^ c_in; - | assign c_out = ((a & b) | (b & c_in)) | (c_in & a); - |endmodule - | - |`default_nettype none - |`timescale 1ns/1ps - |`include "FullAdderN_defs.svh" - | - |module FullAdderN( - | input wire logic [3:0] a, - | input wire logic [3:0] b, - | input wire logic c_in, - | output logic [3:0] sum, - | output logic c_out - |); - | `include "dfhdl_defs.svh" - | logic adder_0_a; - | logic adder_0_b; - | logic adder_0_c_in; - | logic adder_0_sum; - | logic adder_0_c_out; - | logic adder_1_a; - | logic adder_1_b; - | logic adder_1_c_in; - | logic adder_1_sum; - | logic adder_1_c_out; - | logic adder_2_a; - | logic adder_2_b; - | logic adder_2_c_in; - | logic adder_2_sum; - | logic adder_2_c_out; - | logic adder_3_a; - | logic adder_3_b; - | logic adder_3_c_in; - | logic adder_3_sum; - | logic adder_3_c_out; - | FullAdder1 adder_0( - | .a /*<--*/ (adder_0_a), - | .b /*<--*/ (adder_0_b), - | .c_in /*<--*/ (adder_0_c_in), - | .sum /*-->*/ (adder_0_sum), - | .c_out /*-->*/ (adder_0_c_out) - | ); - | FullAdder1 adder_1( - | .a /*<--*/ (adder_1_a), - | .b /*<--*/ (adder_1_b), - | .c_in /*<--*/ (adder_1_c_in), - | .sum /*-->*/ (adder_1_sum), - | .c_out /*-->*/ (adder_1_c_out) - | ); - | FullAdder1 adder_2( - | .a /*<--*/ (adder_2_a), - | .b /*<--*/ (adder_2_b), - | .c_in /*<--*/ (adder_2_c_in), - | .sum /*-->*/ (adder_2_sum), - | .c_out /*-->*/ (adder_2_c_out) - | ); - | FullAdder1 adder_3( - | .a /*<--*/ (adder_3_a), - | .b /*<--*/ (adder_3_b), - | .c_in /*<--*/ (adder_3_c_in), - | .sum /*-->*/ (adder_3_sum), - | .c_out /*-->*/ (adder_3_c_out) - | ); - | assign adder_0_a = a[0]; - | assign adder_0_b = b[0]; - | assign sum[0] = adder_0_sum; - | assign adder_1_c_in = adder_0_c_out; - | assign adder_1_a = a[1]; - | assign adder_1_b = b[1]; - | assign sum[1] = adder_1_sum; - | assign adder_2_c_in = adder_1_c_out; - | assign adder_2_a = a[2]; - | assign adder_2_b = b[2]; - | assign sum[2] = adder_2_sum; - | assign adder_3_c_in = adder_2_c_out; - | assign adder_3_a = a[3]; - | assign adder_3_b = b[3]; - | assign sum[3] = adder_3_sum; - | assign adder_0_c_in = c_in; - | assign c_out = adder_3_c_out; - |endmodule""".stripMargin - - def expectedVHDLCS = - """|library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.FullAdderN_pkg.all; - | - |entity FullAdder1 is - |port ( - | a : in std_logic; - | b : in std_logic; - | c_in : in std_logic; - | sum : out std_logic; - | c_out : out std_logic - |); - |end FullAdder1; - | - |architecture FullAdder1_arch of FullAdder1 is - |begin - | sum <= (a xor b) xor c_in; - | c_out <= ((a and b) or (b and c_in)) or (c_in and a); - |end FullAdder1_arch; - | - |library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.FullAdderN_pkg.all; - | - |entity FullAdderN is - |port ( - | a : in std_logic_vector(3 downto 0); - | b : in std_logic_vector(3 downto 0); - | c_in : in std_logic; - | sum : out std_logic_vector(3 downto 0); - | c_out : out std_logic - |); - |end FullAdderN; - | - |architecture FullAdderN_arch of FullAdderN is - | signal adder_0_a : std_logic; - | signal adder_0_b : std_logic; - | signal adder_0_c_in : std_logic; - | signal adder_0_sum : std_logic; - | signal adder_0_c_out : std_logic; - | signal adder_1_a : std_logic; - | signal adder_1_b : std_logic; - | signal adder_1_c_in : std_logic; - | signal adder_1_sum : std_logic; - | signal adder_1_c_out : std_logic; - | signal adder_2_a : std_logic; - | signal adder_2_b : std_logic; - | signal adder_2_c_in : std_logic; - | signal adder_2_sum : std_logic; - | signal adder_2_c_out : std_logic; - | signal adder_3_a : std_logic; - | signal adder_3_b : std_logic; - | signal adder_3_c_in : std_logic; - | signal adder_3_sum : std_logic; - | signal adder_3_c_out : std_logic; - |begin - | adder_0 : entity work.FullAdder1(FullAdder1_arch) port map ( - | a => adder_0_a, - | b => adder_0_b, - | c_in => adder_0_c_in, - | sum => adder_0_sum, - | c_out => adder_0_c_out - | ); - | adder_1 : entity work.FullAdder1(FullAdder1_arch) port map ( - | a => adder_1_a, - | b => adder_1_b, - | c_in => adder_1_c_in, - | sum => adder_1_sum, - | c_out => adder_1_c_out - | ); - | adder_2 : entity work.FullAdder1(FullAdder1_arch) port map ( - | a => adder_2_a, - | b => adder_2_b, - | c_in => adder_2_c_in, - | sum => adder_2_sum, - | c_out => adder_2_c_out - | ); - | adder_3 : entity work.FullAdder1(FullAdder1_arch) port map ( - | a => adder_3_a, - | b => adder_3_b, - | c_in => adder_3_c_in, - | sum => adder_3_sum, - | c_out => adder_3_c_out - | ); - | adder_0_a <= a(0); - | adder_0_b <= b(0); - | sum(0) <= adder_0_sum; - | adder_1_c_in <= adder_0_c_out; - | adder_1_a <= a(1); - | adder_1_b <= b(1); - | sum(1) <= adder_1_sum; - | adder_2_c_in <= adder_1_c_out; - | adder_2_a <= a(2); - | adder_2_b <= b(2); - | sum(2) <= adder_2_sum; - | adder_3_c_in <= adder_2_c_out; - | adder_3_a <= a(3); - | adder_3_b <= b(3); - | sum(3) <= adder_3_sum; - | adder_0_c_in <= c_in; - | c_out <= adder_3_c_out; - |end FullAdderN_arch;""".stripMargin end FullAdderNSpec diff --git a/lib/src/test/scala/docExamples/RegFileSpec.scala b/lib/src/test/scala/docExamples/RegFileSpec.scala index 57eb0b38e..f70c7fb9d 100644 --- a/lib/src/test/scala/docExamples/RegFileSpec.scala +++ b/lib/src/test/scala/docExamples/RegFileSpec.scala @@ -2,87 +2,4 @@ package docExamples class RegFileSpec extends util.FullCompileSpec: def dut = regfile.RegFile() - - def expectedVerilogCS = - """|`default_nettype none - |`timescale 1ns/1ps - |`include "RegFile_defs.svh" - | - |module RegFile#( - | parameter int DATA_WIDTH = 32, - | parameter int REG_NUM = 32 - |)( - | input wire logic clk, - | input wire logic [$clog2(REG_NUM) - 1:0] rs1_addr, - | output logic [DATA_WIDTH - 1:0] rs1_data, - | input wire logic [$clog2(REG_NUM) - 1:0] rs2_addr, - | output logic [DATA_WIDTH - 1:0] rs2_data, - | input wire logic [$clog2(REG_NUM) - 1:0] rd_addr, - | input wire logic [DATA_WIDTH - 1:0] rd_data, - | input wire logic rd_wren - |); - | `include "dfhdl_defs.svh" - | logic [DATA_WIDTH - 1:0] regs [0:REG_NUM - 1]; - | always_ff @(posedge clk) - | begin - | rs1_data <= regs[rs1_addr]; - | end - | always_ff @(posedge clk) - | begin - | rs2_data <= regs[rs2_addr]; - | end - | always_ff @(posedge clk) - | begin - | if (rd_wren) regs[rd_addr] <= rd_data; - | regs[0] <= {DATA_WIDTH{1'b0}}; - | end - |endmodule""".stripMargin - - def expectedVHDLCS = - """|library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.RegFile_pkg.all; - | - |entity RegFile is - |generic ( - | DATA_WIDTH : integer := 32; - | REG_NUM : integer := 32 - |); - |port ( - | clk : in std_logic; - | rs1_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); - | rs1_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); - | rs2_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); - | rs2_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); - | rd_addr : in std_logic_vector(clog2(REG_NUM) - 1 downto 0); - | rd_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); - | rd_wren : in std_logic - |); - |end RegFile; - | - |architecture RegFile_arch of RegFile is - | type t_arrX1_std_logic_vector is array (natural range <>) of std_logic_vector; - | signal regs : t_arrX1_std_logic_vector(0 to REG_NUM - 1)(DATA_WIDTH - 1 downto 0); - |begin - | process (clk) - | begin - | if rising_edge(clk) then rs1_data <= regs(to_integer(unsigned(rs1_addr))); - | end if; - | end process; - | process (clk) - | begin - | if rising_edge(clk) then rs2_data <= regs(to_integer(unsigned(rs2_addr))); - | end if; - | end process; - | process (clk) - | begin - | if rising_edge(clk) then - | if rd_wren then regs(to_integer(unsigned(rd_addr))) <= rd_data; - | end if; - | regs(0) <= repeat("0", DATA_WIDTH); - | end if; - | end process; - |end RegFile_arch;""".stripMargin end RegFileSpec diff --git a/lib/src/test/scala/docExamples/TrueDPRSpec.scala b/lib/src/test/scala/docExamples/TrueDPRSpec.scala index 0dc44d20f..1cf2aba6f 100644 --- a/lib/src/test/scala/docExamples/TrueDPRSpec.scala +++ b/lib/src/test/scala/docExamples/TrueDPRSpec.scala @@ -2,94 +2,4 @@ package docExamples class TrueDPRSpec extends util.FullCompileSpec: def dut = trueDPR.TrueDPR() - - def expectedVerilogCS = - """|`default_nettype none - |`timescale 1ns/1ps - |`include "TrueDPR_defs.svh" - | - |module TrueDPR#( - | parameter int DATA_WIDTH = 8, - | parameter int ADDR_WIDTH = 8 - |)( - | input wire logic a_clk, - | input wire logic [DATA_WIDTH - 1:0] a_data, - | input wire logic [ADDR_WIDTH - 1:0] a_addr, - | output logic [DATA_WIDTH - 1:0] a_q, - | input wire logic a_we, - | input wire logic b_clk, - | input wire logic [DATA_WIDTH - 1:0] b_data, - | input wire logic [ADDR_WIDTH - 1:0] b_addr, - | output logic [DATA_WIDTH - 1:0] b_q, - | input wire logic b_we - |); - | `include "dfhdl_defs.svh" - | logic [DATA_WIDTH - 1:0] ram [0:2 ** ADDR_WIDTH - 1]; - | always_ff @(posedge a_clk) - | begin - | if (a_we) begin - | /* verilator lint_off BLKSEQ */ - | ram[a_addr] = a_data; - | /* verilator lint_on BLKSEQ */ - | end - | a_q <= ram[a_addr]; - | end - | always_ff @(posedge b_clk) - | begin - | if (b_we) begin - | /* verilator lint_off BLKSEQ */ - | ram[b_addr] = b_data; - | /* verilator lint_on BLKSEQ */ - | end - | b_q <= ram[b_addr]; - | end - |endmodule""".stripMargin - - def expectedVHDLCS = - """|library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.TrueDPR_pkg.all; - | - |entity TrueDPR is - |generic ( - | DATA_WIDTH : integer := 8; - | ADDR_WIDTH : integer := 8 - |); - |port ( - | a_clk : in std_logic; - | a_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); - | a_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - | a_q : out std_logic_vector(DATA_WIDTH - 1 downto 0); - | a_we : in std_logic; - | b_clk : in std_logic; - | b_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); - | b_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); - | b_q : out std_logic_vector(DATA_WIDTH - 1 downto 0); - | b_we : in std_logic - |); - |end TrueDPR; - | - |architecture TrueDPR_arch of TrueDPR is - | type t_arrX1_std_logic_vector is array (natural range <>) of std_logic_vector; - | shared variable ram : t_arrX1_std_logic_vector(0 to 2 ** ADDR_WIDTH - 1)(DATA_WIDTH - 1 downto 0); - |begin - | process (a_clk) - | begin - | if rising_edge(a_clk) then - | if a_we then ram(to_integer(unsigned(a_addr))) := a_data; - | end if; - | a_q <= ram(to_integer(unsigned(a_addr))); - | end if; - | end process; - | process (b_clk) - | begin - | if rising_edge(b_clk) then - | if b_we then ram(to_integer(unsigned(b_addr))) := b_data; - | end if; - | b_q <= ram(to_integer(unsigned(b_addr))); - | end if; - | end process; - |end TrueDPR_arch;""".stripMargin end TrueDPRSpec diff --git a/lib/src/test/scala/docExamples/UART_TxSpec.scala b/lib/src/test/scala/docExamples/UART_TxSpec.scala index 8ced701dc..e481a133d 100644 --- a/lib/src/test/scala/docExamples/UART_TxSpec.scala +++ b/lib/src/test/scala/docExamples/UART_TxSpec.scala @@ -2,185 +2,4 @@ package docExamples class UART_TxSpec extends util.FullCompileSpec: def dut = uart_tx.UART_Tx() - - def expectedVerilogCS = - """|`default_nettype none - |`timescale 1ns/1ps - |`include "UART_Tx_defs.svh" - | - |module UART_Tx#( - | parameter int CLK_FREQ_KHz = 50000, - | parameter int BAUD_RATE_BPS = 115200 - |)( - | input wire logic clk, - | input wire logic rst, - | input wire logic data_en, - | input wire logic [7:0] data, - | output logic tx, - | output logic tx_en, - | output logic tx_done - |); - | `include "dfhdl_defs.svh" - | parameter int BIT_CLOCKS = (CLK_FREQ_KHz * 1000) / BAUD_RATE_BPS; - | typedef enum { - | Status_Idle = 1, - | Status_StartBit = 2, - | Status_DataBits = 4, - | Status_StopBit = 8, - | Status_Finalize = 16 - | } t_enum_Status; - | t_enum_Status status; - | logic [$clog2(BIT_CLOCKS) - 1:0] bitClkCnt; - | logic [2:0] dataBitCnt; - | logic [7:0] shiftData; - | always_ff @(posedge clk) - | begin - | if (rst == 1'b1) begin - | status <= Status_Idle; - | bitClkCnt <= $clog2(BIT_CLOCKS)'(0); - | dataBitCnt <= 3'd0; - | end - | else begin - | case (status) - | Status_Idle: begin - | tx_en <= 1'b0; - | tx <= 1'b1; - | tx_done <= 1'b0; - | bitClkCnt <= $clog2(BIT_CLOCKS)'(0); - | dataBitCnt <= 3'd0; - | if (data_en) begin - | shiftData <= data; - | status <= Status_StartBit; - | end - | end - | Status_StartBit: begin - | tx_en <= 1'b1; - | tx <= 1'b0; - | if (bitClkCnt == $clog2(BIT_CLOCKS)'(BIT_CLOCKS - 1)) begin - | bitClkCnt <= $clog2(BIT_CLOCKS)'(0); - | status <= Status_DataBits; - | end - | else bitClkCnt <= bitClkCnt + $clog2(BIT_CLOCKS)'(1); - | end - | Status_DataBits: begin - | tx <= shiftData[0]; - | if (bitClkCnt == $clog2(BIT_CLOCKS)'(BIT_CLOCKS - 1)) begin - | bitClkCnt <= $clog2(BIT_CLOCKS)'(0); - | shiftData <= shiftData >> 1; - | if (dataBitCnt == 3'd7) begin - | dataBitCnt <= 3'd0; - | status <= Status_StopBit; - | end - | else dataBitCnt <= dataBitCnt + 3'd1; - | end - | else bitClkCnt <= bitClkCnt + $clog2(BIT_CLOCKS)'(1); - | end - | Status_StopBit: begin - | tx <= 1'b1; - | if (bitClkCnt == $clog2(BIT_CLOCKS)'(BIT_CLOCKS - 1)) begin - | bitClkCnt <= $clog2(BIT_CLOCKS)'(0); - | tx_done <= 1'b1; - | status <= Status_Finalize; - | end - | else bitClkCnt <= bitClkCnt + $clog2(BIT_CLOCKS)'(1); - | end - | Status_Finalize: begin - | tx_en <= 1'b0; - | tx_done <= 1'b1; - | status <= Status_Idle; - | end - | endcase - | end - | end - |endmodule""".stripMargin - - def expectedVHDLCS = - """|library ieee; - |use ieee.std_logic_1164.all; - |use ieee.numeric_std.all; - |use work.dfhdl_pkg.all; - |use work.UART_Tx_pkg.all; - | - |entity UART_Tx is - |generic ( - | CLK_FREQ_KHz : integer := 50000; - | BAUD_RATE_BPS : integer := 115200 - |); - |port ( - | clk : in std_logic; - | rst : in std_logic; - | data_en : in std_logic; - | data : in std_logic_vector(7 downto 0); - | tx : out std_logic; - | tx_en : out std_logic; - | tx_done : out std_logic - |); - |end UART_Tx; - | - |architecture UART_Tx_arch of UART_Tx is - | constant BIT_CLOCKS : integer := (CLK_FREQ_KHz * 1000) / BAUD_RATE_BPS; - | type t_enum_Status is ( - | Status_Idle, Status_StartBit, Status_DataBits, Status_StopBit, Status_Finalize - | ); - | signal status : t_enum_Status; - | signal bitClkCnt : unsigned(clog2(BIT_CLOCKS) - 1 downto 0); - | signal dataBitCnt : unsigned(2 downto 0); - | signal shiftData : std_logic_vector(7 downto 0); - |begin - | process (clk) - | begin - | if rising_edge(clk) then - | if rst = '1' then - | status <= Status_Idle; - | bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); - | dataBitCnt <= 3d"0"; - | else - | case status is - | when Status_Idle => - | tx_en <= '0'; - | tx <= '1'; - | tx_done <= '0'; - | bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); - | dataBitCnt <= 3d"0"; - | if data_en then - | shiftData <= data; - | status <= Status_StartBit; - | end if; - | when Status_StartBit => - | tx_en <= '1'; - | tx <= '0'; - | if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then - | bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); - | status <= Status_DataBits; - | else bitClkCnt <= bitClkCnt + resize(d"1", clog2(BIT_CLOCKS)); - | end if; - | when Status_DataBits => - | tx <= shiftData(0); - | if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then - | bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); - | shiftData <= slv_srl(shiftData, 1); - | if dataBitCnt = 3d"7" then - | dataBitCnt <= 3d"0"; - | status <= Status_StopBit; - | else dataBitCnt <= dataBitCnt + 3d"1"; - | end if; - | else bitClkCnt <= bitClkCnt + resize(d"1", clog2(BIT_CLOCKS)); - | end if; - | when Status_StopBit => - | tx <= '1'; - | if bitClkCnt = to_unsigned(BIT_CLOCKS - 1, clog2(BIT_CLOCKS)) then - | bitClkCnt <= resize(d"0", clog2(BIT_CLOCKS)); - | tx_done <= '1'; - | status <= Status_Finalize; - | else bitClkCnt <= bitClkCnt + resize(d"1", clog2(BIT_CLOCKS)); - | end if; - | when Status_Finalize => - | tx_en <= '0'; - | tx_done <= '1'; - | status <= Status_Idle; - | end case; - | end if; - | end if; - | end process; - |end UART_Tx_arch;""".stripMargin end UART_TxSpec diff --git a/lib/src/test/scala/docExamples/ugdemos/demo1/LeftShift2.scala b/lib/src/test/scala/docExamples/ugdemos/demo1/LeftShift2.scala new file mode 100644 index 000000000..22b0aca37 --- /dev/null +++ b/lib/src/test/scala/docExamples/ugdemos/demo1/LeftShift2.scala @@ -0,0 +1,14 @@ +//format: off +package docExamples.ugdemos.demo1 +import dfhdl.* +//optionally set the default backend configuration option +//(can be overridden by the top-app CLI) +given options.CompilerOptions.Backend = backends.verilog + +/** A two-bits left shifter */ +@top class LeftShift2 extends RTDesign: + /** bits input */ + val iBits = Bits(8) <> IN + /** bits output */ + val oBits = Bits(8) <> OUT + oBits := iBits << 2 diff --git a/lib/src/test/scala/docExamples/ugdemos/demo1/LeftShift2Spec.scala b/lib/src/test/scala/docExamples/ugdemos/demo1/LeftShift2Spec.scala new file mode 100644 index 000000000..2a11775c4 --- /dev/null +++ b/lib/src/test/scala/docExamples/ugdemos/demo1/LeftShift2Spec.scala @@ -0,0 +1,5 @@ +package docExamples.ugdemos.demo1 + +class LeftShift2Spec extends util.FullCompileSpec: + def dut = LeftShift2() +end LeftShift2Spec diff --git a/lib/src/test/scala/docExamples/ugdemos/demo2/LeftShiftBasic.scala b/lib/src/test/scala/docExamples/ugdemos/demo2/LeftShiftBasic.scala new file mode 100644 index 000000000..ad15a2640 --- /dev/null +++ b/lib/src/test/scala/docExamples/ugdemos/demo2/LeftShiftBasic.scala @@ -0,0 +1,16 @@ +//format: off +package docExamples.ugdemos.demo2 +import dfhdl.* +given options.CompilerOptions.Backend = backends.verilog + +/** A basic left shifter */ +@top class LeftShiftBasic( + val width: Int = 8 +) extends RTDesign: + /** bits input */ + val iBits = Bits(width) <> IN + /** requested shift */ + val shift = UInt.until(width) <> IN + /** bits output */ + val oBits = Bits(width) <> OUT + oBits := iBits << shift diff --git a/lib/src/test/scala/docExamples/ugdemos/demo2/LeftShiftBasicSpec.scala b/lib/src/test/scala/docExamples/ugdemos/demo2/LeftShiftBasicSpec.scala new file mode 100644 index 000000000..28a7fe8f3 --- /dev/null +++ b/lib/src/test/scala/docExamples/ugdemos/demo2/LeftShiftBasicSpec.scala @@ -0,0 +1,5 @@ +package docExamples.ugdemos.demo2 + +class LeftShiftBasicSpec extends util.FullCompileSpec: + def dut = LeftShiftBasic() + def expectedVHDLCS = "" diff --git a/lib/src/test/scala/docExamples/ugdemos/demo3/LeftShiftGen.scala b/lib/src/test/scala/docExamples/ugdemos/demo3/LeftShiftGen.scala new file mode 100644 index 000000000..f8ac1d609 --- /dev/null +++ b/lib/src/test/scala/docExamples/ugdemos/demo3/LeftShiftGen.scala @@ -0,0 +1,20 @@ +//format: off +package docExamples.ugdemos.demo3 +import dfhdl.* +given options.CompilerOptions.Backend = backends.verilog + +/** A generic left shifter + * + * @param width + * the width of the input and output bits + */ +@top class LeftShiftGen( + val width: Int <> CONST = 8, +) extends RTDesign: + /** bits input */ + val iBits = Bits(width) <> IN + /** requested shift */ + val shift = UInt.until(width) <> IN + /** bits output */ + val oBits = Bits(width) <> OUT + oBits := iBits << shift diff --git a/lib/src/test/scala/docExamples/ugdemos/demo3/LeftShiftGenSpec.scala b/lib/src/test/scala/docExamples/ugdemos/demo3/LeftShiftGenSpec.scala new file mode 100644 index 000000000..f60fb68c8 --- /dev/null +++ b/lib/src/test/scala/docExamples/ugdemos/demo3/LeftShiftGenSpec.scala @@ -0,0 +1,4 @@ +package docExamples.ugdemos.demo3 + +class LeftShiftGenSpec extends util.FullCompileSpec: + def dut = LeftShiftGen() diff --git a/lib/src/test/scala/util/FullCompileSpec.scala b/lib/src/test/scala/util/FullCompileSpec.scala index 8171f613e..ca1d9ee40 100644 --- a/lib/src/test/scala/util/FullCompileSpec.scala +++ b/lib/src/test/scala/util/FullCompileSpec.scala @@ -2,14 +2,23 @@ package util import munit.* import dfhdl.* -import dfhdl.compiler.stages.{getCompiledCodeString, CompiledDesign} +import dfhdl.compiler.stages.{CompiledDesign} import dfhdl.options.{CompilerOptions, LinterOptions} import tools.linters.* +import java.io.File.separatorChar as S +import java.nio.file.{Files, Paths, Path} +import java.nio.charset.StandardCharsets +import scala.jdk.CollectionConverters.* +import munit.Location abstract class FullCompileSpec extends FunSuite: def dut: core.Design - def expectedVerilogCS: String - def expectedVHDLCS: String + given options.CompilerOptions.NewFolderForTop = false + def projectFolderName = s"${this.getClass.getPackageName()}.${this.getClass.getSimpleName()}" + def projectSandboxFolder = s"sandbox$S$projectFolderName" + def projectResourceFolder = s"lib${S}src${S}test${S}resources${S}ref$S$projectFolderName" + inline given options.CompilerOptions.CommitFolder = + s"$projectSandboxFolder$S${compiletime.summonInline[options.CompilerOptions.Backend]}" given options.OnError = options.OnError.Exception given options.LinterOptions.FatalWarnings = true def verilogLinters: List[LinterOptions.VerilogLinter] = @@ -35,9 +44,7 @@ abstract class FullCompileSpec extends FunSuite: test("verilog[default = sv2009] compilation with no error"): given options.CompilerOptions.Backend = backends.verilog - val compiled = dut.compile.lintVerilog - if (expectedVerilogCS.nonEmpty) - assertNoDiff(compiled.getCompiledCodeString, expectedVerilogCS) + dut.compile.lintVerilog test("verilog.v2001 compilation with no error"): given options.CompilerOptions.Backend = backends.verilog.v2001 @@ -49,11 +56,65 @@ abstract class FullCompileSpec extends FunSuite: test("vhdl[default = v2008] compilation with no error"): given options.CompilerOptions.Backend = backends.vhdl - val compiled = dut.compile.lintVerilog - if (expectedVHDLCS.nonEmpty) - assertNoDiff(compiled.getCompiledCodeString, expectedVHDLCS) + dut.compile.lintVHDL test("vhdl.v93 compilation with no error"): given options.CompilerOptions.Backend = backends.vhdl.v93 dut.compile.lintVHDL + + def compareDirectories( + obtainedDir: String, + expectedDir: String, + filter: String => Boolean = _ => true + )(using Location): Unit = + val obtainedPath = Paths.get(obtainedDir) + val expectedPath = Paths.get(expectedDir) + + val obtainedFiles = + if (Files.exists(obtainedPath)) + Files.walk(obtainedPath).iterator().asScala.filter(Files.isRegularFile(_)).filter(file => + filter(obtainedPath.relativize(file).toString) + ).toList + else + List.empty + val expectedFiles = + if (Files.exists(expectedPath)) + Files.walk(expectedPath).iterator().asScala.filter(Files.isRegularFile(_)).filter(file => + filter(expectedPath.relativize(file).toString) + ).toList + else + List.empty + + val obtainedFileNames = obtainedFiles.map(file => obtainedPath.relativize(file).toString).toSet + val expectedFileNames = expectedFiles.map(file => expectedPath.relativize(file).toString).toSet + + assertEquals( + obtainedFileNames, + expectedFileNames, + s"Files in $obtainedDir and $expectedDir do not match" + ) + + obtainedFiles.foreach { obtainedFile => + val relativePath = obtainedPath.relativize(obtainedFile).toString + val expectedFile = expectedPath.resolve(relativePath) + val obtainedContents = + Files.readAllLines(obtainedFile, StandardCharsets.UTF_8).asScala.mkString("\n") + val expectedContents = + Files.readAllLines(expectedFile, StandardCharsets.UTF_8).asScala.mkString("\n") + assertNoDiff( + obtainedContents, + expectedContents, + s"Contents of $relativePath do not match" + ) + } + end compareDirectories + + test("same generated files in verilog and vhdl folders"): + compareDirectories( + projectSandboxFolder, + projectResourceFolder, + fileName => + """.*\.(v|sv|vh|svh|vhd)$""".r.matches(fileName) && + !""".*(dfhdl_pkg|dfhdl_defs)\.(vh|svh|vhd)$""".r.matches(fileName) + ) end FullCompileSpec diff --git a/mkdocs.yml b/mkdocs.yml index 407bf2d63..18853c1e0 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -76,7 +76,7 @@ nav: # - Designs & Hierarchies: user-guide/designs/index.md # - Type System: user-guide/type-system/index.md # - Functions/Methods: user-guide/methods/index.md - # - Connectivity: user-guide/connectivity/index.md + # - Hierarchy and Connectivity: user-guide/connectivity/index.md # - State/Registers/Memory: user-guide/state/index.md # - Conditionals: user-guide/conditionals/index.md # - Processes: user-guide/processes/index.md @@ -155,6 +155,7 @@ extra_javascript: extra_css: - css/scastie.css - css/vs.css + - css/user-guide.css - css/lhs-permalink.css - css/dfhdl-admonition.css - css/verilog-admonition.css @@ -177,3 +178,7 @@ plugins: - redirects: redirect_maps: 'LEGaTO/index.md': 'index.md' + +watch: + - lib/src/test/scala/docExamples + - lib/src/test/resources/ref diff --git a/project/DFHDLCommands.scala b/project/DFHDLCommands.scala index f013d871c..cb7d41405 100644 --- a/project/DFHDLCommands.scala +++ b/project/DFHDLCommands.scala @@ -1,6 +1,8 @@ //format: off import sbt._ import Keys._ +import java.nio.file.{Files, Paths, StandardCopyOption, Path} +import scala.jdk.CollectionConverters._ object DFHDLCommands { val quickTestSetup = Command.command("quickTestSetup") { state => @@ -13,4 +15,46 @@ object DFHDLCommands { ), state) newState } + + val docExamplesRefUpdate = Command.command("docExamplesRefUpdate") { state => + val sandboxDir = Paths.get("sandbox") + val targetDir = Paths.get("lib/src/test/resources/ref") + val filter: String => Boolean = + fileName => + fileName.matches("""docExamples\..*\.(v|sv|vh|svh|vhd)$""") && + !fileName.matches(""".*(dfhdl_pkg|dfhdl_defs)\.(vh|svh|vhd)$""") + + def copyFiles(source: Path, target: Path, filter: String => Boolean): Unit = { + if (Files.isDirectory(source)) { + if (!Files.exists(target)) { + Files.createDirectories(target) + } + val sourceFiles = Files.walk(source).iterator().asScala.filter(Files.isRegularFile(_)).filter(file => filter(source.relativize(file).toString)).toList + val targetFiles = Files.walk(target).iterator().asScala.filter(Files.isRegularFile(_)).toList + + // Copy or overwrite files from source to target + sourceFiles.foreach { file => + val relativePath = source.relativize(file) + val targetFile = target.resolve(relativePath) + if (!Files.exists(targetFile.getParent)) { + Files.createDirectories(targetFile.getParent) + } + Files.copy(file.toAbsolutePath(), targetFile.toAbsolutePath(), StandardCopyOption.REPLACE_EXISTING) + } + + // Remove files in target that are not in source + val sourceFileNames = sourceFiles.map(file => source.relativize(file).toString).toSet + targetFiles.foreach { file => + val relativePath = target.relativize(file).toString + if (!sourceFileNames.contains(relativePath)) { + Files.delete(file) + } + } + } + } + + copyFiles(sandboxDir, targetDir, filter) + + state + } } \ No newline at end of file