Description

This project involves the design and verification of a custom keyboard using SystemVerilog. The keyboard uses a Mealy Finite State Machine to model keypress states and a synchronizer and decoder for scan code conversion. A class-based testbench and custom driver code were implemented to handle a variety of test cases, including normal and edge cases such as key changes and multiple key presses. This comprehensive testing approach ensures the robustness and reliability of the keyboard design.

Specification

Requirements

3x3 Keyboard
List of supported keys:
- 0,1,2,3,4,5,6,7,8

Working

Matrix keyboard scanner
Display key pressed

Test Cases

Invalid cases (2 or more keys pressed)

2 keys pressed in the same column
2 keys presses in different columns
Completely random number generated

Valid (only 1 key pressed)

Single valid key pressed
Key changed when scanning
Key removed during scanning

State Diagram

graph LR;
Sensitive--  Key Pressed --> Shift
Sensitive-- Key Not Pressed --> Sensitive
Shift-- Found --> Hold
Shift-- Not Found --> Shift
Shift-- Not Found at all --> Sensitive
Hold-- Key Pressed --> Hold
Hold-- Key Released --> Sensitive

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A General Order of Development of Files

DUT.sv
Interface.sv
Packet.sv
TestCases.sv
Generator.sv
Driver.sv
Monitor.sv
Scoreboard.sv
Environment.sv
Test.sv
Top.sv

Design Graph

graph TD;
Top.sv --> Test.sv
Test.sv --> Environment.sv
Environment.sv --> Generator.sv
Environment.sv --> Driver.sv
Environment.sv --> Monitor.sv
Environment.sv --> Scoreboard.sv
Environment.sv --> TestCases.sv
TestCases.sv -- Packet.sv --> Generator.sv
Generator.sv -- Packet.sv --> Driver.sv
Monitor.sv -- Packet.sv --> Scoreboard.sv
Driver.sv <-- Interface.sv --> DUT.sv
DUT.sv <-- Interface.sv --> Monitor.sv
DUT.sv --> Top.sv