New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

VHDL design entry via GHDL Yosys plugin #233

Open

PPlinux opened this issue May 26, 2021 · 1 comment

PPlinux commented May 26, 2021

Dear,

is there already support for VHDL design entry via GHDL Yosys plugin ?

Hoping to receive a positive reaction, I remain,

Greetings,

Patrick Pelgrims

Member

Obijuan commented May 26, 2021

Not yet. It is on the roadmap, but we still have not started it

FPGAwars deleted a comment from manuelpas

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment