From 2280fe448bf213f39a0d5f9aa7c015131e9a38b4 Mon Sep 17 00:00:00 2001 From: Lucas Steuernagel <38472950+LucasSte@users.noreply.github.com> Date: Thu, 4 Jan 2024 08:38:55 -0300 Subject: [PATCH] [SOL] Add feature flag for disabling `lddw` (#77) * Fix incorrect obj-dump * Read flag from elf --- .../SBF/Disassembler/SBFDisassembler.cpp | 5 ++++ llvm/lib/Target/SBF/SBF.td | 5 +++- llvm/lib/Target/SBF/SBFInstrInfo.td | 28 +++++++++++-------- llvm/lib/Target/SBF/SBFSubtarget.h | 4 +++ llvm/test/CodeGen/SBF/objdump_cond_op.ll | 6 ++-- llvm/test/CodeGen/SBF/objdump_imm_hex.ll | 16 +++++------ llvm/test/CodeGen/SBF/objdump_static_var.ll | 4 +-- llvm/test/MC/SBF/insn-unit-32.s | 10 ++++--- llvm/test/MC/SBF/sbf-alu.s | 2 +- llvm/tools/llvm-objdump/llvm-objdump.cpp | 9 ++++++ 10 files changed, 58 insertions(+), 31 deletions(-) diff --git a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp index c5f454c783f903..0feacc69869567 100644 --- a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp +++ b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp @@ -67,6 +67,7 @@ class SBFDisassembler : public MCDisassembler { uint8_t getInstClass(uint64_t Inst) const { return (Inst >> 56) & 0x7; }; uint8_t getInstSize(uint64_t Inst) const { return (Inst >> 59) & 0x3; }; uint8_t getInstMode(uint64_t Inst) const { return (Inst >> 61) & 0x7; }; + bool isMov32(uint64_t Inst) const { return (Inst >> 56) == 0xb4; } }; } // end anonymous namespace @@ -175,6 +176,10 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, STI.getFeatureBits()[SBF::ALU32]) Result = decodeInstruction(DecoderTableSBFALU3264, Instr, Insn, Address, this, STI); + else if (isMov32(Insn) && !STI.getFeatureBits()[SBF::ALU32] && + STI.getFeatureBits()[SBF::FeatureDisableLddw]) + Result = + decodeInstruction(DecoderTableSBFv264, Instr, Insn, Address, this, STI); else Result = decodeInstruction(DecoderTableSBF64, Instr, Insn, Address, this, STI); diff --git a/llvm/lib/Target/SBF/SBF.td b/llvm/lib/Target/SBF/SBF.td index c718c9f92bbad6..3dddd614e82cd1 100644 --- a/llvm/lib/Target/SBF/SBF.td +++ b/llvm/lib/Target/SBF/SBF.td @@ -44,6 +44,9 @@ def FeatureDisableNeg : SubtargetFeature<"no-neg", "DisableNeg", "true", def FeatureReverseSubImm : SubtargetFeature<"reverse-sub", "ReverseSubImm", "true", "Reverse the operands in the 'sub reg, imm' instruction">; +def FeatureDisableLddw : SubtargetFeature<"no-lddw", "NoLddw", "true", + "Disable the lddw instruction">; + class Proc Features> : Processor; @@ -53,7 +56,7 @@ def : Proc<"v2", []>; def : Proc<"v3", []>; def : Proc<"probe", []>; def : Proc<"sbfv2", [FeatureSolana, FeatureDynamicFrames, FeatureSdiv, FeatureRelocAbs64, FeatureStaticSyscalls, - FeatureDisableNeg, FeatureReverseSubImm]>; + FeatureDisableNeg, FeatureReverseSubImm, FeatureDisableLddw]>; //===----------------------------------------------------------------------===// // Assembly printer diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td index 9874b80e23e20a..3c363416a1884a 100644 --- a/llvm/lib/Target/SBF/SBFInstrInfo.td +++ b/llvm/lib/Target/SBF/SBFInstrInfo.td @@ -54,6 +54,9 @@ def SBFIsBigEndian : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">; def SBFHasALU32 : Predicate<"Subtarget->getHasAlu32()">; def SBFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">; def SBFSubtargetSolana : Predicate<"Subtarget->isSolana()">; +def SBFHasLddw : Predicate<"!Subtarget->getNoLddw()">; +def SBFNoLddw : Predicate<"Subtarget->getNoLddw()">; + def SBFv2 : Predicate<"Subtarget->isSBFv2()">; def NoSBFv2 : Predicate<"!Subtarget->isSBFv2()">; def SBFHasNeg : Predicate<"!Subtarget->getDisableNeg()">; @@ -322,13 +325,13 @@ let Constraints = "$dst = $src2" in { defm XOR : ALU; defm SRA : ALU; - let Predicates = [SBFv2] in { + let Predicates = [SBFNoLddw] in { def HOR : ALU_RI; - let DecoderNamespace = "AddrLoad" in { + let DecoderNamespace = "SBFv2" in { def HOR_addr : ALU_RI Pseudo, string Mnemonic> } let isReMaterializable = 1, isAsCheapAsAMove = 1 in { -def LD_imm64 : LD_IMM64<0, "lddw">, Requires<[NoSBFv2]>; +def LD_imm64 : LD_IMM64<0, "lddw">, Requires<[SBFHasLddw]>; def MOV_rr : ALU_RR; - let Predicates = [SBFv2] in { - def MOV_32_64_imm : ALU_RI, Requires<[SBFNoLddw]>; +} + +let DecoderNamespace = "SBFv2", Predicates = [SBFNoLddw] in { + def MOV_32_64_imm : ALU_RI; - def MOV_32_64_addr : ALU_RI; - } } // In SBFv2, a CopyToReg of a 64-bit value is split in two instructions: @@ -950,14 +954,14 @@ let isCodeGenOnly = 1 in { // These instructions copy the value 0x1122334455667788 to a register. def : Pat<(i64 imm:$imm), (HOR (MOV_32_64_imm (i32 (Lower32 $imm))), - (i32 (Upper32 $imm)))>, Requires<[SBFv2]>; + (i32 (Upper32 $imm)))>, Requires<[SBFNoLddw]>; // load 64-bit global address into register. def : Pat<(SBFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>, - Requires<[NoSBFv2]>; + Requires<[SBFHasLddw]>; def : Pat<(SBFWrapper tglobaladdr:$in), (HOR_addr (MOV_32_64_addr tglobaladdr:$in), - tglobaladdr:$in)>, Requires<[SBFv2]>; + tglobaladdr:$in)>, Requires<[SBFNoLddw]>; def : Pat<(i64 (sext GPR32:$src)), diff --git a/llvm/lib/Target/SBF/SBFSubtarget.h b/llvm/lib/Target/SBF/SBFSubtarget.h index 0f1fb78f2522e5..f979e4a9ca064f 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.h +++ b/llvm/lib/Target/SBF/SBFSubtarget.h @@ -82,6 +82,9 @@ class SBFSubtarget : public SBFGenSubtargetInfo { // reg - imm'. bool ReverseSubImm; + // wether we should use the LDDW instruction + bool NoLddw; + public: // This constructor initializes the data members to match that // of the specified triple. @@ -104,6 +107,7 @@ class SBFSubtarget : public SBFGenSubtargetInfo { bool isSBFv2() const { return IsSBFv2; } bool getDisableNeg() const { return DisableNeg; } bool getReverseSubImm() const { return ReverseSubImm; } + bool getNoLddw() const { return NoLddw; } const SBFInstrInfo *getInstrInfo() const override { return &InstrInfo; } const SBFFrameLowering *getFrameLowering() const override { diff --git a/llvm/test/CodeGen/SBF/objdump_cond_op.ll b/llvm/test/CodeGen/SBF/objdump_cond_op.ll index dc32f30c01a8b5..d753f24656512f 100644 --- a/llvm/test/CodeGen/SBF/objdump_cond_op.ll +++ b/llvm/test/CodeGen/SBF/objdump_cond_op.ll @@ -34,7 +34,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 { %10 = load i32, i32* @gbl, align 4 br i1 %9, label %15, label %11 -; CHECK: mov32 w1, 0x0 +; CHECK: mov32 r1, 0x0 ; CHECK: hor64 r1, 0x0 ; CHECK: ldxw r0, [r1 + 0x0] ; CHECK: mul64 r0, r0 @@ -46,7 +46,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 { br label %13 ; CHECK-LABEL: : -; CHECK: mov32 w3, 0x0 +; CHECK: mov32 r3, 0x0 ; CHECK: hor64 r3, 0x0 ; CHECK: ldxw r0, [r3 + 0x0] ; CHECK: lsh64 r2, 0x20 @@ -59,7 +59,7 @@ define i32 @test(i32, i32) local_unnamed_addr #0 { store i32 %14, i32* @gbl, align 4 br label %15 ; CHECK-LABEL: : -; CHECK: mov32 w1, 0x0 +; CHECK: mov32 r1, 0x0 ; CHECK: hor64 r1, 0x0 ; CHECK: stxw [r1 + 0x0], r0 diff --git a/llvm/test/CodeGen/SBF/objdump_imm_hex.ll b/llvm/test/CodeGen/SBF/objdump_imm_hex.ll index 0fe239eaf1780e..a840258825c799 100644 --- a/llvm/test/CodeGen/SBF/objdump_imm_hex.ll +++ b/llvm/test/CodeGen/SBF/objdump_imm_hex.ll @@ -26,17 +26,17 @@ define i32 @test(i64, i64) local_unnamed_addr #0 { ; CHECK-LABEL: test %3 = icmp eq i64 %0, -6067004223159161907 br i1 %3, label %4, label %8 -; CHECK-DEC: b4 03 00 00 cd ab cd ab mov32 w3, -0x54325433 +; CHECK-DEC: b4 03 00 00 cd ab cd ab mov32 r3, -0x54325433 ; CHECK-DEC: f7 03 00 00 cd ab cd ab hor64 r3, -0x54325433 ; CHECK-DEC: 5d 31 07 00 00 00 00 00 jne r1, r3, +0x7 -; CHECK-HEX: b4 03 00 00 cd ab cd ab mov32 w3, -0x54325433 +; CHECK-HEX: b4 03 00 00 cd ab cd ab mov32 r3, -0x54325433 ; CHECK-HEX: f7 03 00 00 cd ab cd ab hor64 r3, -0x54325433 ; CHECK-HEX: 5d 31 07 00 00 00 00 00 jne r1, r3, +0x7 ;