Fixes for ML tests

MikeOpenHWGroup · May 30, 2020 · f06a400 · f06a400
1 parent bf180fc
commit f06a400
Showing 1 changed file with 0 additions and 4 deletions.
diff --git a/test/riscv_instr_test_lib.sv b/test/riscv_instr_test_lib.sv
@@ -47,10 +47,6 @@ class riscv_ml_test extends riscv_instr_base_test;
   `uvm_component_new
 
   virtual function void randomize_cfg();
-    cfg.no_fence = 0;
-    cfg.init_privileged_mode = MACHINE_MODE;
-    cfg.init_privileged_mode.rand_mode(0);
-    cfg.enable_unaligned_load_store = 1'b1;
     cfg.addr_translaction_rnd_order_c.constraint_mode(0);
     `DV_CHECK_RANDOMIZE_FATAL(cfg)
     cfg.addr_translaction_rnd_order_c.constraint_mode(1);