unnamed.qsys

<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
 <component
   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="" />
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element $${FILENAME}
   {
   }
   element sram_0
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
 <parameter name="device" value="5CSEMA5F31C6" />
 <parameter name="deviceFamily" value="Cyclone V" />
 <parameter name="deviceSpeedGrade" value="6" />
 <parameter name="fabricMode" value="QSYS" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="false" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="hideFromIPCatalog" value="true" />
 <parameter name="lockedInterfaceDefinition" value="" />
 <parameter name="maxAdditionalLatency" value="1" />
 <parameter name="projectName" value="" />
 <parameter name="sopcBorderPoints" value="false" />
 <parameter name="systemHash" value="0" />
 <parameter name="testBenchDutName" value="" />
 <parameter name="timeStamp" value="0" />
 <parameter name="useTestBenchNamingPattern" value="false" />
 <instanceScript></instanceScript>
 <interface
   name="avalon_sram_slave"
   internal="sram_0.avalon_sram_slave"
   type="avalon"
   dir="end">
  <port name="address" internal="address" />
  <port name="byteenable" internal="byteenable" />
  <port name="read" internal="read" />
  <port name="write" internal="write" />
  <port name="writedata" internal="writedata" />
  <port name="readdata" internal="readdata" />
  <port name="readdatavalid" internal="readdatavalid" />
 </interface>
 <interface name="clk" internal="sram_0.clk" type="clock" dir="end">
  <port name="clk" internal="clk" />
 </interface>
 <interface
   name="external_interface"
   internal="sram_0.external_interface"
   type="conduit"
   dir="end">
  <port name="SRAM_DQ" internal="SRAM_DQ" />
  <port name="SRAM_ADDR" internal="SRAM_ADDR" />
  <port name="SRAM_LB_N" internal="SRAM_LB_N" />
  <port name="SRAM_UB_N" internal="SRAM_UB_N" />
  <port name="SRAM_CE_N" internal="SRAM_CE_N" />
  <port name="SRAM_OE_N" internal="SRAM_OE_N" />
  <port name="SRAM_WE_N" internal="SRAM_WE_N" />
 </interface>
 <interface name="reset" internal="sram_0.reset" type="reset" dir="end">
  <port name="reset" internal="reset" />
 </interface>
 <module
   name="sram_0"
   kind="altera_up_avalon_sram"
   version="15.0"
   enabled="1"
   autoexport="1">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="board" value="DE2-115" />
  <parameter name="pixel_buffer" value="false" />
 </module>
 <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
 <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
 <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
 <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>