From 06d28cea865cf21a4b7de4c0d9d86afefa02fc03 Mon Sep 17 00:00:00 2001
From: Huaqi Fang <578567190@qq.com>
Date: Mon, 16 Dec 2024 10:53:05 +0800
Subject: [PATCH] SoC/evalsoc: Only initialize ECLIC SMode related registers
 when TEE really present

Previous this is only controlled by __TEE_PRESENT macro, now it will do runtime
check to avoid initializaton access this register when it is not present to cause
exception like below.

MCAUSE : 0x30000002
MDCAUSE: 0x0
MEPC   : 0x80002958
MTVAL  : 0x10761073
HARTID : 0
ra: 0x80002894, tp: 0x90000890, t0: 0x80003514, t1: 0xf, t2: 0x0, t3: 0x0, t4: 0x0, t5: 0x0, t6: 0x0
a0: 0x900010f8, a1: 0x1, a2: 0x80000200, a3: 0x18020000, a4: 0x7, a5: 0x20000, a6: 0x90000000, a7: 0x0
cause: 0x30000002, epc: 0x80002958
msubm: 0x80

Signed-off-by: Huaqi Fang <578567190@qq.com>
---
 SoC/evalsoc/Common/Source/system_evalsoc.c | 38 ++++++++++++----------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/SoC/evalsoc/Common/Source/system_evalsoc.c b/SoC/evalsoc/Common/Source/system_evalsoc.c
index 9d4661ba..097f193c 100644
--- a/SoC/evalsoc/Common/Source/system_evalsoc.c
+++ b/SoC/evalsoc/Common/Source/system_evalsoc.c
@@ -752,24 +752,26 @@ void ECLIC_Interrupt_Init(void)
         ECLIC_SetCfgNlbits(__ECLIC_INTCTLBITS);
 
 #if defined(__TEE_PRESENT) && (__TEE_PRESENT == 1)
-        /*
-         * Intialize ECLIC supervisor mode vector interrupt
-         * base address stvt to vector_table_s
-         */
-        __RV_CSR_WRITE(CSR_STVT, (unsigned long)vector_table_s);
-        /*
-         * Set ECLIC supervisor mode non-vector entry to be controlled
-         * by stvt2 CSR register.
-         * Intialize supervisor mode ECLIC non-vector interrupt
-         * base address stvt2 to irq_entry_s.
-        */
-        __RV_CSR_WRITE(CSR_STVT2, (unsigned long)irq_entry_s);
-        __RV_CSR_SET(CSR_STVT2, 0x01);
-        /*
-         * Set supervisor exception entry stvec to exc_entry_s */
-        __RV_CSR_WRITE(CSR_STVEC, (unsigned long)exc_entry_s);
-        /* Global Configuration about STH */
-        ECLIC_SetSth(0);
+        if (mcfg_info & MCFG_INFO_TEE) {
+            /*
+             * Intialize ECLIC supervisor mode vector interrupt
+             * base address stvt to vector_table_s
+             */
+            __RV_CSR_WRITE(CSR_STVT, (unsigned long)vector_table_s);
+            /*
+             * Set ECLIC supervisor mode non-vector entry to be controlled
+             * by stvt2 CSR register.
+             * Intialize supervisor mode ECLIC non-vector interrupt
+             * base address stvt2 to irq_entry_s.
+            */
+            __RV_CSR_WRITE(CSR_STVT2, (unsigned long)irq_entry_s);
+            __RV_CSR_SET(CSR_STVT2, 0x01);
+            /*
+             * Set supervisor exception entry stvec to exc_entry_s */
+            __RV_CSR_WRITE(CSR_STVEC, (unsigned long)exc_entry_s);
+            /* Global Configuration about STH */
+            ECLIC_SetSth(0);
+        }
 #endif
     } else {
         /* Set as CLINT interrupt mode */