diff --git a/SoC/evalsoc/Common/Source/system_evalsoc.c b/SoC/evalsoc/Common/Source/system_evalsoc.c
index 53f3ef4c..951beb36 100644
--- a/SoC/evalsoc/Common/Source/system_evalsoc.c
+++ b/SoC/evalsoc/Common/Source/system_evalsoc.c
@@ -802,7 +802,7 @@ void _premain_init(void)
     // __CCM_PRESENT is still default to 0 in evalsoc.h, since it is used in core_feature_eclic.h to register interrupt, if set to 1, it might cause exception
     // but in the cpu, icache or dcache might not exist due to cpu configuration, so here
     // we need to check whether icache/dcache really exist, if yes, then turn on it
-#if defined(__ICACHE_PRESENT) || defined(RUNMODE_ECC_EN)
+#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
     if (ICachePresent()) { // Check whether icache real present or not
 #if defined(RUNMODE_ECC_EN)
 #if RUNMODE_ECC_EN == 0
@@ -811,13 +811,10 @@ void _premain_init(void)
         __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EN | MCACHE_CTL_IC_ECC_EXCP_EN | MCACHE_CTL_IC_ECC_CHK_EN);
 #endif
 #endif
-
-#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
         EnableICache();
-#endif
     }
 #endif
-#if defined(__DCACHE_PRESENT) || defined(RUNMODE_ECC_EN)
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
     if (DCachePresent()) { // Check whether dcache real present or not
 #if defined(RUNMODE_ECC_EN)
 #if RUNMODE_ECC_EN == 0
@@ -826,9 +823,7 @@ void _premain_init(void)
         __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EN | MCACHE_CTL_DC_ECC_EXCP_EN | MCACHE_CTL_DC_ECC_CHK_EN);
 #endif
 #endif
-#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
         EnableDCache();
-#endif
     }
 #endif