Shlcofideleg extension question

[fly-1011]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

Describe：

When using spike as a reference model to test Xiangshan, the following inconsistencies occurred

The inconsistency is in the 13th bit of the hideleg register. I found the following explanation in the rsicv specification:

Extension Shlcofideleg supports delegating LCOFI interrupts to VS-mode. If the Shlcofideleg
extension is implemented, hideleg bit 13 is writable; otherwise, it is read-only zero. When bit 13 of
hideleg is zero, vsip.LCOFIP and vsie.LCOFIE are read-only zeros. Else, vsip.LCOFIP and vsie.LCOFIE
are aliases of sip.LCOFIP and sie.LCOFIE.

Has Xiangshan achieved the Shlcofideleg expansion? The extension was not found in the following files

XiangShan/src/main/scala/xiangshan/Parameters.scala

Lines 365 to 377 in 2e5ebf5

	def ISAExtensions = Seq(
	// single letter extensions, in canonical order
	"i", "m", "a", "f", "d", "c", /* "b", */ "v", "h",
	// multi-letter extensions, sorted alphanumerically
	"sdtrig", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd",
	"smaia", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssstateen",
	"sstc", "sstvala", "sstvecd", "ssu64xl", "sv39", "sv48", "svade", "svbare", "svinval",
	"svpbmt", "za64rs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop",
	"zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccif", "zicclsm",
	"ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zimop", "zkn",
	"zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt",
	"zvl128b", "zvl32b", "zvl64b"
	)

Environmental Information

xiangshan:commit fcefab3 (HEAD -> master, origin/master, origin/HEAD)
ready-to-run: commit c1dc496545b9d62bb10264cd4485cb6fe7c60798 (HEAD -> master, origin/master, origin/HEAD)

[Tang-Haojin]

Thank you for your report. I will handle this.

[Tang-Haojin]

XiangShan does implement Shlcofideleg extension, but spike does not support this yet. Waiting for this PR: riscv-software-src/riscv-isa-sim#1847.

[Tang-Haojin]

We will add corresponding isa string to our parameter.

[fly-1011]

😊Thank you for your reply and PR submission