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agc_engine.c
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/*
Copyright 2003-2005,2009 Ronald S. Burkey <[email protected]>
This file is part of yaAGC.
yaAGC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
yaAGC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with yaAGC; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
In addition, as a special exception, Ronald S. Burkey gives permission to
link the code of this program with the Orbiter SDK library (or with
modified versions of the Orbiter SDK library that use the same license as
the Orbiter SDK library), and distribute linked combinations including
the two. You must obey the GNU General Public License in all respects for
all of the code used other than the Orbiter SDK library. If you modify
this file, you may extend this exception to your version of the file,
but you are not obligated to do so. If you do not wish to do so, delete
this exception statement from your version.
Filename: agc_engine.c
Purpose: This is the main engine for binary simulation of the Apollo AGC
computer. It is separate from the Display/Keyboard (DSKY)
simulation and Apollo hardware simulation, though compatible
with them. The executable binary may be created using the
yayul (Yet Another YUL) assembler.
Compiler: GNU gcc.
Contact: Ron Burkey <[email protected]>
Reference: http://www.ibiblio.org/apollo/index.html
Mods: 04/05/03 RSB. Began.
08/20/03 RSB. Now bitmasks are handled on input channels.
11/26/03 RSB. Up to now, a pseudo-linear space was used to
model internal AGC memory. This was simply too
tricky to work with, because it was too hard to
understand the address conversions that were
taking place. I now use a banked model much
closer to the true AGC memory map.
11/28/03 RSB. Added code for a bunch of instruction types,
and fixed a bunch of bugs.
11/29/03 RSB. Finished out all of the instruction types.
Still a lot of uncertainty if Overflow
and/or editing has been handled properly.
Undoubtedly many bugs.
05/01/04 RSB Now makes sure that in --debug-dsky mode
doesn't execute any AGC code (since there
isn't any loaded anyhow).
05/03/04 RSB Added a workaround for "TC Q". It's not
right, but it has to be more right than
what was there before.
05/04/04 RSB Fixed a bug in CS, where the unused bit
could get set and thereforem mess up
later comparisons. Fixed an addressing bug
(was 10-bit but should have been 12-bit) in
the AD instruction. DCA was completely
messed up (still don't know about overflow).
05/05/04 RSB INDEX'ing was messed up because the pending
index was zeroed before being completely
used up. Fixed the "CCS A" instruction.
Fixed CCS in the case of negative compare-
values.
05/06/04 RSB Added rfopen. The operation of "DXCH L"
(which is ambiguous in the docs but actually
used --- at Luminary131 address 33,03514) ---
has been redefined in accordance with the
Luminary program's comments. Adjusted
"CS A" and "CA A", though I don't actually
think they work differently. Fixed a
potential divide-by-0 in DV.
05/10/04 RSB Fixed up i/o channel operations so that they
properly use AGC-formatted integers rather
than the simulator's native-format integers.
05/12/04 RSB Added the data collection for backtraces.
05/13/04 RSB Corrected calculation of the superbank address.
05/14/04 RSB Added interrupt service and hopefully fixed the
RESUME instruction. Fixed a bunch of instructions
(but not all, since I couldn't figure out how to
consistently do it) that modify the Z register.
05/15/04 RSB Repaired the interrupt vector and the RESUME
instruction, so that they do not automatically
save/restore A, L, Q, and BB to/from
ARUPUT, LRUPT, QRUPT, and BBRUPT. The ISR
is supposed to do that itself, if it wants
it done. And (sigh!) the RESUME instruction
wasn't working, but was treated as INDEX 017.
05/17/04 RSB Added MasterInterruptEnable. Added updates of
timer-registers TIME1 and TIME2, of TIME3 and
TIME4, and of SCALER1 and SCALER2.
05/18/04 RSB The mask used for writing to channel 7 have
changed from 0100 to 0160, because the
Luminary131 source (p.59) claims that bits
5-7 are used. I don't know what bits 5-6
are for, though.
05/19/04 RSB I'm beginning to grasp now what to do for
overflow. The AD instruction (in which
overflow was messed up) and the TS instruction
(which was completely bollixed) have hopefully
been fixed now.
05/30/04 RSB Now have a spec to work from (my assembly-
language manual). Working to bring this code
up to v0.50 of the spec.
05/31/04 RSB The instruction set has basically been completely
rewritten.
06/01/04 RSB Corrected the indexing of instructions
for negative indices. Oops! The instruction
executed on RESUME was taken from BBRUPT
instead of BRUPT.
06/02/04 RSB Found that I was using an unsigned datatype
for EB, FB, and BB, thus causing comparisons of
them to registers to fail. Now autozero the
unused bits of EB, FB, and BB.
06/04/04 RSB Separated ServerStuff function from agc_engine
function.
06/05/04 RSB Fixed the TCAA, ZQ, and ZL instructions.
06/11/04 RSB Added a definition for uint16_t in Win32.
06/30/04 RSB Made SignExtend, AddSP16, and
OverflowCorrected non-static.
07/02/04 RSB Fixed major bug in SU instruction, in which it
not only used the wrong value, but overwrote
the wrong location.
07/04/04 RSB Fixed bug (I hope) in converting "decent"
to "DP". The DAS instruction did not leave the
proper values in the A,L registers.
07/05/04 RSB Changed DXCH to do overflow-correction on the
accumulator. Also, the special cases "DXCH A"
and "DXCH L" were being checked improperly
before, and therefore were not treated
properly.
07/07/04 RSB Some cases of DP arithmetic with the MS word
or LS word being -0 were fixed.
07/08/04 RSB CA and CS fixed to re-edit after doing their work.
Instead of using the overflow-corrected
accumulator, BZF and BZMF now use the complete
accumulator. Either positive or negative
overflow blocks BZF, while positive overflow
blocks BZMF.
07/09/04 RSB The DAS instruction has been completely rewritten
to alter the relative signs of the output.
Previously they were normalized to be identical,
and this is wrong. In the DV instruction, the
case of remainder==0 needed to be fixed up to
distinguish between +0 and -0.
07/10/04 RSB Completely replaced MSU. And ... whoops! ...
forgot to inhibit interrupts while the
accumulator contains overflow. The special
cases "DCA L" and "DCS L" have been addressed.
"CCS A" has been changed similarly to BZF and
BZMF w.r.t. overflow.
07/12/04 RSB Q is now 16 bits.
07/15/04 RSB Pretty massive rewrites: Data alignment changed
to bit 0 rather than 1. All registers at
addresses less than REG16 are now 16 bits,
rather than just A and Q.
07/17/04 RSB The final contents of L with DXCH, DCA, and
DCS are now overflow-corrected.
07/19/04 RSB Added SocketInterlace/Reload.
08/12/04 RSB Now account for output ports that are latched
externally, and for updating newly-attached
peripherals with current i/o-port values.
08/13/04 RSB The Win32 version of yaAGC now recognizes when
socket-disconnects have occurred, and allows
the port to be reused.
08/18/04 RSB Split off all socket-related stuff into
SocketAPI.c, so that a cleaner API could be
available for integrators.
02/27/05 RSB Added the license exception, as required by
the GPL, for linking to Orbiter SDK libraries.
05/14/05 RSB Corrected website references.
05/15/05 RSB Oops! The unprogrammed counter increments were
hooked up to i/o space rather than to
erasable. So incoming counter commands were
ignored.
06/11/05 RSB Implemented the fictitious output channel 0177
used to make it easier to implement an
emulation of the gyros.
06/12/05 RSB Fixed the CounterDINC function to emit a
POUT, MOUT, or ZOUT, as it is supposed to.
06/16/05 RSB Implemented IMU CDU drive output pulses.
06/18/05 RSB Fixed PINC/MINC at +0 to -1 and -0 to +1
transitions.
06/25/05 RSB Fixed the DOWNRUPT interrupt requests.
06/30/05 RSB Hopefully fixed fine-alignment, by making
the gyro torquing depend on the GYROCTR
register as well as elapsed time.
07/01/05 RSB Replaced the gyro-torquing code, to
avoid simulating the timing of the
3200 pps. pulses, which was conflicting
somehow with the timing Luminary wanted
to impose.
07/02/05 RSB OPTXCMD & OPTYCMD.
07/04/05 RSB Fix for writes to channel 033.
08/17/05 RSB Fixed an embarrassing bug in SpToDecent,
thanks to Christian Bucher.
08/20/05 RSB I no longer allow interrupts when the
program counter is in the range 0-060.
I do this principally to guard against the
case Z=0,1,2, since I'm not sure that all of
the AGC code saves registers properly in this
case. Now I inhibit interrupts prior to
INHINT, RELINT, and EXTEND (as we're supposed
to), as well as RESUME (as we're not supposed
to). The intent of the latter is to take
care of problems that occur when EDRUPT is used.
(Specifically, an interrupt can occur between
RELINT and RESUME after an EDRUPT, and this
messes up the return address in ZRUPT used by
the RESUME.)
08/21/05 RSB Removed the interrupt inhibition from the
address range 0-060, because it prevented
recovery from certain conditions.
08/28/05 RSB Oops! Had been using PINC sequences on
TIME6 rather than DINC sequences.
10/05/05 RSB FIFOs were introduced for PCDU or MCDU
commands on the registers CDUX, CDUY, CDUZ.
The purpose of these FIFOs is to make sure
that CDUX, CDUY, CDUZ are updated at no
more than an 800 cps rate, in order to
avoid problems with the Kalman filter in the
DAP, which is otherwise likely to reject
counts that change too quickly.
10/07/05 RSB FIFOs changed from 800 cps to either 400 cps
("low rate") or 6400 cps ("high rate"),
depending on the variable CduHighRate.
At the moment, CduHighRate is stuck at 0,
because we've worked out no way to plausibly
change it.
11/13/05 RSB Took care of auto-adjust buffer timing for
high-rate and low-rate CDU counter updates.
PCDU/MCDU commands 1/3 are slow mode, and
PCDU/MCDU commands 021/023 are fast mode.
02/26/06 RSB Oops! This wouldn't build under Win32 because
of the lack of an int32_t datatype. Fixed.
03/30/09 RSB Moved Downlink local static variable from
CpuWriteIO() to agc_t, trying to overcome the
lack of resumption of telemetry after an AGC
resumption in Windows.
The technical documentation for the Apollo Guidance & Navigation (G&N) system,
or more particularly for the Apollo Guidance Computer (AGC) may be found at
http://hrst.mit.edu/hrs/apollo/public. That is, to the extent that the
documentation exists online it may be found there. I'm sure -- or rather
HOPE -- that there's more documentation at NASA and MIT than has been made
available yet. I personally had no knowledge of the AGC, other than what
I had seen in the movie "Apollo 13" and the HBO series "From the Earth to
the Moon", before I conceived this project last night at midnight and
started doing web searches. So, bear with me; it's a learning experience!
Also at hrst.mit.edu are the actual programs for the Command Module (CM) and
Lunar Module (LM) AGCs. Or rather, what's there are scans of 1700-page
printouts of assembly-language listings of SOME versions of those programs.
(Respectively, called "Colossus" and "Luminary".) I'll worry about how to
get those into a usable version only after I get the CPU simulator working!
What THIS file contains is basicly a pure simulation of the CPU, without any
input and output as such. (I/O, to the DSKY or to CM or LM hardware
simulations occurs through the mechanism of sockets, and hence the DSKY
front-end and hardware back-end simulations may be implemented as complete
stand-alone programs and replaced at will.) There is a single globally
interesting function, called agc_engine, which is intended to be called once
per AGC instruction cycle -- i.e., every 11.7 microseconds. (Yes, that's
right, the CPU clock speed was a little over 85 KILOhertz. That's a factor
that obviously makes the simulation much easier!) The function may be called
more or less often than this, to speed up or slow down the apparent passage
of time.
This function is intended to be completely portable, so that it may be run in
a PC environment (Microsoft Windows) or in any *NIX environment, or indeed in
an embedded target if anybody should wish to create an actual physical
replacement for an AGC. Also, multiple copies of the simulation may be run
on the same PC -- for example to simulation a CM and LM simultaneously.
*/
#define AGC_ENGINE_C
//#include <errno.h>
//#include <stdlib.h>
#include <stdio.h>
#ifdef WIN32
typedef unsigned short uint16_t;
typedef int int32_t;
#endif
#include "yaAGC.h"
#include "agc_engine.h"
#include "agc_symtab.h"
// If COARSE_SMOOTH is 1, then the timing of coarse-alignment (in terms of
// bursting and separation of bursts) is according to the Delco manual.
// However, since the simulated IMU has no physical inertia, it adjusts
// instantly (and therefore jerkily). The COARSE_SMOOTH constant creates
// smaller bursts, and therefore smoother FDAI motion. Normally, there are
// 192 pulses in a burst. In the simulation, there are 192/COARSE_SMOOTH
// pulses in a burst. COARSE_SMOOTH should be in integral divisor of both
// 192 and of 50*1024. This constrains it to be any power of 2, up to 64.
#define COARSE_SMOOTH 8
// Some helpful macros for manipulating registers.
#define c(Reg) State->Erasable[0][Reg]
#define IsA(Address) ((Address) == RegA)
#define IsL(Address) ((Address) == RegL)
#define IsQ(Address) ((Address) == RegQ)
#define IsEB(Address) ((Address) == RegEB)
#define IsZ(Address) ((Address) == RegZ)
#define IsReg(Address,Reg) ((Address) == (Reg))
// Some helpful constants in parsing the "address" field from an instruction
// or from the Z register.
#define SIGNAL_00 000000
#define SIGNAL_01 002000
#define SIGNAL_10 004000
#define SIGNAL_11 006000
#define SIGNAL_0011 001400
#define MASK9 000777
#define MASK10 001777
#define MASK12 007777
// Some numerical constant, in AGC format.
#define AGC_P0 ((int16_t) 0)
#define AGC_M0 ((int16_t) 077777)
#define AGC_P1 ((int16_t) 1)
#define AGC_M1 ((int16_t) 077776)
// Here are arrays which tell (for each instruction, as determined by the
// uppermost 5 bits of the instruction) how many extra machine cycles are
// needed to execute the instruction. (In other words, the total number of
// machine cycles for the instruction, minus 1.) The opcode and quartercode
// are taken into account. There are two arrays -- one for normal
// instructions and one for "extracode" instructions.
static const int InstructionTiming[32] = {
0, 0, 0, 0, // Opcode = 00.
1, 0, 0, 0, // Opcode = 01.
2, 1, 1, 1, // Opcode = 02.
1, 1, 1, 1, // Opcode = 03.
1, 1, 1, 1, // Opcode = 04.
1, 2, 1, 1, // Opcode = 05.
1, 1, 1, 1, // Opcode = 06.
1, 1, 1, 1 // Opcode = 07.
};
// Note that the following table does not properly handle the EDRUPT or
// BZF/BZMF instructions, and extra delay may need to be added specially for
// those cases. The table figures 2 MCT for EDRUPT and 1 MCT for BZF/BZMF.
static const int ExtracodeTiming[32] = {
1, 1, 1, 1, // Opcode = 010.
5, 0, 0, 0, // Opcode = 011.
1, 1, 1, 1, // Opcode = 012.
2, 2, 2, 2, // Opcode = 013.
2, 2, 2, 2, // Opcode = 014.
1, 1, 1, 1, // Opcode = 015.
1, 0, 0, 0, // Opcode = 016.
2, 2, 2, 2 // Opcode = 017.
};
// A way, for debugging, to disable interrupts. The 0th entry disables
// everything if 0. Entries 1-10 disable individual interrupts.
int DebuggerInterruptMasks[11] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
//-----------------------------------------------------------------------------
// Stuff for doing structural coverage analysis. Yes, I know it could be done
// much more cleverly.
int CoverageCounts = 0; // Increment coverage counts is != 0.
unsigned ErasableReadCounts[8][0400];
unsigned ErasableWriteCounts[8][0400];
unsigned ErasableInstructionCounts[8][0400];
unsigned FixedAccessCounts[40][02000];
unsigned IoReadCounts[01000];
unsigned IoWriteCounts[01000];
// For debugging the CDUX,Y,Z inputs.
FILE *CduLog = NULL;
//-----------------------------------------------------------------------------
// Functions for reading or writing from/to i/o channels. The reason we have
// to provide a function for this rather than accessing the i/o-channel buffer
// directly is that the L and Q registers appear in both memory and i/o space,
// at the same addresses.
int
ReadIO (agc_t * State, int Address)
{
if (Address < 0 || Address > 0777)
return (0);
if (CoverageCounts)
IoReadCounts[Address]++;
if (Address == RegL || Address == RegQ)
return (State->Erasable[0][Address]);
return (State->InputChannel[Address]);
}
void
WriteIO (agc_t * State, int Address, int Value)
{
// The value should be in AGC format.
Value &= 077777;
if (Address < 0 || Address > 0777)
return;
if (CoverageCounts)
IoWriteCounts[Address]++;
if (Address == RegL || Address == RegQ)
State->Erasable[0][Address] = Value;
// 2005-07-04 RSB. The necessity for this was pointed out by Mark
// Grant via Markus Joachim. Although channel 033 is an input channel,
// the CPU writes to it from time to time, to "reset" bits 11-15 to 1.
// Apparently, these are latched inputs, and this resets the latches.
if (Address == 033)
Value = (State->InputChannel[Address] | 076000);
State->InputChannel[Address] = Value;
if (Address == 010)
{
// Channel 10 is converted externally to the CPU into up to 16 ports,
// by means of latching relays. We need to capture this data.
State->OutputChannel10[(Value >> 11) & 017] = Value;
}
}
void
CpuWriteIO (agc_t * State, int Address, int Value)
{
//static int Downlink = 0;
WriteIO (State, Address, Value);
ChannelOutput (State, Address, Value & 077777);
// 2005-06-25 RSB. DOWNRUPT stuff. I assume that the 20 ms. between
// downlink transmissions is due to the time needed for transmitting,
// so I don't interrupt at a regular rate, Instead, I make sure that
// there are 20 ms. between transmissions
if (Address == 034)
State->Downlink |= 1;
else if (Address == 035)
State->Downlink |= 2;
if (State->Downlink == 3)
{
//State->InterruptRequests[8] = 1; // DOWNRUPT.
State->DownruptTimeValid = 1;
State->DownruptTime = State->CycleCounter + (AGC_PER_SECOND / 50);
State->Downlink = 0;
}
}
//-----------------------------------------------------------------------------
// This function does all of the processing associated with converting a
// 12-bit "address" as used within instructions or in the Z register, to a
// pointer to the actual word in the simulated memory. In other words, here
// we take memory bank-selection into account.
static int16_t *
FindMemoryWord (agc_t * State, int Address12)
{
//int PseudoAddress;
int AdjustmentEB, AdjustmentFB;
// Get rid of the parity bit.
Address12 = Address12;
// Make sure the darn thing really is 12 bits.
Address12 &= 07777;
// It should be noted as far as unswitched-erasable and common-fixed memory
// is concerned, that the following rules actually do result in continuous
// block of memory that don't have problems in crossing bank boundaries.
if (Address12 < 00400) // Unswitched-erasable.
return (&State->Erasable[0][Address12 & 00377]);
else if (Address12 < 01000) // Unswitched-erasable (continued).
return (&State->Erasable[1][Address12 & 00377]);
else if (Address12 < 01400) // Unswitched-erasable (continued).
return (&State->Erasable[2][Address12 & 00377]);
else if (Address12 < 02000) // Switched-erasable.
{
// Recall that the parity bit is accounted for in the shift below.
AdjustmentEB = (7 & (c (RegEB) >> 8));
return (&State->Erasable[AdjustmentEB][Address12 & 00377]);
}
else if (Address12 < 04000) // Fixed-switchable.
{
AdjustmentFB = (037 & (c (RegFB) >> 10));
// Account for the superbank bit.
if (030 == (AdjustmentFB & 030) && (State->OutputChannel7 & 0100) != 0)
AdjustmentFB += 010;
return (&State->Fixed[AdjustmentFB][Address12 & 01777]);
}
else if (Address12 < 06000) // Fixed-fixed.
return (&State->Fixed[2][Address12 & 01777]);
else // Fixed-fixed (continued).
return (&State->Fixed[3][Address12 & 01777]);
}
// Same thing, basically, but for collecting coverage data.
#if 0
static void
CollectCoverage (agc_t * State, int Address12, int Read, int Write, int Instruction)
{
int AdjustmentEB, AdjustmentFB;
if (!CoverageCounts)
return;
// Get rid of the parity bit.
Address12 = Address12;
// Make sure the darn thing really is 12 bits.
Address12 &= 07777;
if (Address12 < 00400) // Unswitched-erasable.
{
AdjustmentEB = 0;
goto Erasable;
}
else if (Address12 < 01000) // Unswitched-erasable (continued).
{
AdjustmentEB = 1;
goto Erasable;
}
else if (Address12 < 01400) // Unswitched-erasable (continued).
{
AdjustmentEB = 2;
goto Erasable;
}
else if (Address12 < 02000) // Switched-erasable.
{
// Recall that the parity bit is accounted for in the shift below.
AdjustmentEB = (7 & (c (RegEB) >> 8));
Erasable:
Address12 &= 00377;
if (Read)
ErasableReadCounts[AdjustmentEB][Address12]++;
if (Write)
ErasableWriteCounts[AdjustmentEB][Address12]++;
if (Instruction)
ErasableInstructionCounts[AdjustmentEB][Address12]++;
}
else if (Address12 < 04000) // Fixed-switchable.
{
AdjustmentFB = (037 & (c (RegFB) >> 10));
// Account for the superbank bit.
if (030 == (AdjustmentFB & 030) && (State->OutputChannel7 & 0100) != 0)
AdjustmentFB += 010;
Fixed:
FixedAccessCounts[AdjustmentFB][Address12 & 01777]++;
}
else if (Address12 < 06000) // Fixed-fixed.
{
AdjustmentFB = 2;
goto Fixed;
}
else // Fixed-fixed (continued).
{
AdjustmentFB = 3;
goto Fixed;
}
return;
}
#endif //0
//-----------------------------------------------------------------------------
// Assign a new value to "erasable" memory, performing editing as necessary
// if the destination address is one of the 4 editing registers. The value to
// be written is a properly formatted AGC value in D1-15. The difference between
// Assign and AssignFromPointer is simply that Assign needs a memory bank number
// and an offset into that bank, while AssignFromPointer simply uses a pointer
// directly to the simulated memory location.
static int NextZ;
static void
Assign (agc_t * State, int Bank, int Offset, int Value)
{
if (Bank < 0 || Bank >= 8)
return; // Non-erasable memory.
if (Offset < 0 || Offset >= 0400)
return;
if (CoverageCounts)
ErasableWriteCounts[Bank][Offset]++;
if (Bank == 0)
{
switch (Offset)
{
case RegZ:
NextZ = Value & 07777;
break;
case RegCYR:
Value &= 077777;
if (0 != (Value & 1))
Value = (Value >> 1) | 040000;
else
Value = (Value >> 1);
break;
case RegSR:
Value &= 077777;
if (0 != (Value & 040000))
Value = (Value >> 1) | 040000;
else
Value = (Value >> 1);
break;
case RegCYL:
Value &= 077777;
if (0 != (Value & 040000))
Value = (Value << 1) + 1;
else
Value = (Value << 1);
break;
case RegEDOP:
Value &= 077777;
Value = ((Value >> 7) & 0177);
break;
case RegZERO:
Value = AGC_P0;
break;
default:
// No editing of the Value is needed in this case.
break;
}
if (Offset >= REG16 || (Offset >= 020 && Offset <= 023))
State->Erasable[0][Offset] = Value & 077777;
else
State->Erasable[0][Offset] = Value & 0177777;
}
else
State->Erasable[Bank][Offset] = Value & 077777;
}
static void
AssignFromPointer (agc_t * State, int16_t * Pointer, int Value)
{
int Address;
Address = Pointer - State->Erasable[0];
if (Address >= 0 && Address < 04000)
{
Assign (State, Address / 0400, Address & 0377, Value);
return;
}
}
//-----------------------------------------------------------------------------
// Compute the "diminished absolute value". The input data and output data
// are both in AGC 1's-complement format.
static int16_t
dabs (int16_t Input)
{
if (0 != (040000 & Input))
Input = 037777 & ~Input; // Input was negative, but now is positive.
if (Input > 1) // "diminish" it if >1.
Input--;
else
Input = AGC_P0;
return (Input);
}
// Same, but for 16-bit registers.
static int
odabs (int Input)
{
if (0 != (0100000 & Input))
Input = (0177777 & ~Input); // Input was negative, but now is positive.
if (Input > 1) // "diminish" it if >1.
Input--;
else
Input = AGC_P0;
return (Input);
}
//-----------------------------------------------------------------------------
// Convert an AGC-formatted word to CPU-native format.
static int
agc2cpu (int Input)
{
if (0 != (040000 & Input))
return (-(037777 & ~Input));
else
return (037777 & Input);
}
//-----------------------------------------------------------------------------
// Convert a native CPU-formatted word to AGC format. If the input value is
// out of range, it is truncated by discarding high-order bits.
static int
cpu2agc (int Input)
{
if (Input < 0)
return (077777 & ~(-Input));
else
return (077777 & Input);
}
//-----------------------------------------------------------------------------
// Double-length versions of the same.
static int
agc2cpu2 (int Input)
{
if (0 != (02000000000 & Input))
return (-(01777777777 & ~Input));
else
return (01777777777 & Input);
}
static int
cpu2agc2 (int Input)
{
if (Input < 0)
return (03777777777 & ~(01777777777 & (-Input)));
else
return (01777777777 & Input);
}
//----------------------------------------------------------------------------
// Here is a small suite of functions for converting back and forth between
// 15-bit SP values and 16-bit accumulator values.
#if 0
// Gets the full 16-bit value of the accumulator (plus parity bit).
static int
GetAccumulator (agc_t * State)
{
int Value;
Value = State->Erasable[0][RegA];
Value &= 0177777;
return (Value);
}
// Gets the full 16-bit value of Q (plus parity bit).
static int
GetQ (agc_t * State)
{
int Value;
Value = State->Erasable[0][RegQ];
Value &= 0177777;
return (Value);
}
// Store a 16-bit value (plus parity) into the accumulator.
static void
PutAccumulator (agc_t * State, int Value)
{
c (RegA) = (Value & 0177777);
}
// Store a 16-bit value (plus parity) into Q.
static void
PutQ (agc_t * State, int Value)
{
c (RegQ) = (Value & 0177777);
}
#endif // 0
// Returns +1, -1, or +0 (in SP) format, on the basis of whether an
// accumulator-style "16-bit" value (really 17 bits including parity)
// contains overflow or not. To do this for the accumulator itself,
// use ValueOverflowed(GetAccumulator(State)).
static int16_t
ValueOverflowed (int Value)
{
switch (Value & 0140000)
{
case 0040000:
return (AGC_P1);
case 0100000:
return (AGC_M1);
default:
return (AGC_P0);
}
}
// Return an overflow-corrected value from a 16-bit (plus parity ) SP word.
// This involves just moving bit 16 down to bit 15.
int16_t OverflowCorrected (int Value)
{
return ((Value & 037777) | ((Value >> 1) & 040000));
}
// Sign-extend a 15-bit SP value so that it can go into the 16-bit (plus parity)
// accumulator.
int
SignExtend (int16_t Word)
{
return ((Word & 077777) | ((Word << 1) & 0100000));
}
//-----------------------------------------------------------------------------
// Here are functions to convert a DP into a more-decent 1's-
// complement format in which there's not an extra sign-bit to contend with.
// (In other words, a 29-bit format in which there's a single sign bit, rather
// than a 30-bit format in which there are two sign bits.) And vice-versa.
// The DP value consists of two adjacent SP values, MSW first and LSW second,
// and we're given a pointer to the second word. The main difficulty here
// is dealing with the case when the two SP words don't have the same sign,
// and making sure all of the signs are okay when one or more words are zero.
// A sign-extension is added a la the normal accumulator.
static int
SpToDecent (int16_t * LsbSP)
{
int16_t Msb, Lsb;
int Value, Complement;
Msb = LsbSP[-1];
Lsb = *LsbSP;
if (Msb == AGC_P0 || Msb == AGC_M0) // Msb is zero.
{
// As far as the case of the sign of +0-0 or -0+0 is concerned,
// we follow the convention of the DV instruction, in which the
// overall sign is the sign of the less-significant word.
Value = SignExtend (Lsb);
if (Value & 0100000)
Value |= ~0177777;
return (07777777777 & Value); // Eliminate extra sign-ext. bits.
}
// If signs of Msb and Lsb words don't match, then make them match.
if ((040000 & Lsb) != (040000 & Msb))
{
if (Lsb == AGC_P0 || Lsb == AGC_M0) // Lsb is zero.
{
// Adjust sign of Lsb to match Msb.
if (0 == (040000 & Msb))
Lsb = AGC_P0;
else
Lsb = AGC_M0; // 2005-08-17 RSB. Was "Msb". Oops!
}
else // Lsb is not zero.
{
// The logic will be easier if the Msb is positive.
Complement = (040000 & Msb);
if (Complement)
{
Msb = (077777 & ~Msb);
Lsb = (077777 & ~Lsb);
}
// We now have Msb positive non-zero and Lsb negative non-zero.
// Subtracting 1 from Msb is equivalent to adding 2**14 (i.e.,
// 0100000, accounting for the parity) to Lsb. An additional 1
// must be added to account for the negative overflow.
Msb--;
Lsb = ((Lsb + 040000 + AGC_P1) & 077777);
// Restore the signs, if necessary.
if (Complement)
{
Msb = (077777 & ~Msb);
Lsb = (077777 & ~Lsb);
}
}
}
// We now have an Msb and Lsb of the same sign; therefore,
// we can simply juxtapose them, discarding the sign bit from the
// Lsb. (And recall that the 0-position is still the parity.)
Value = (03777740000 & (Msb << 14)) | (037777 & Lsb);
// Also, sign-extend for further arithmetic.
if (02000000000 & Value)
Value |= 04000000000;
return (Value);
}
static void
DecentToSp (int Decent, int16_t * LsbSP)
{
int Sign;
Sign = (Decent & 04000000000);
*LsbSP = (037777 & Decent);
if (Sign)
*LsbSP |= 040000;
LsbSP[-1] = OverflowCorrected (0177777 & (Decent >> 14)); // Was 13.
}
// Adds two sign-extended SP values. The result may contain overflow.
int
AddSP16 (int Addend1, int Addend2)
{
int Sum;
Sum = Addend1 + Addend2;
if (Sum & 0200000)
{
Sum += AGC_P1;
Sum &= 0177777;
}
return (Sum);
}
// Absolute value of an SP value.
static int16_t
AbsSP (int16_t Value)
{
if (040000 & Value)
return (077777 & ~Value);
return (Value);
}
// Check if an SP value is negative.
//static int
//IsNegativeSP (int16_t Value)
//{
// return (0 != (0100000 & Value));
//}
// Negate an SP value.
static int16_t
NegateSP (int16_t Value)
{
return (077777 & ~Value);
}
//-----------------------------------------------------------------------------
// The following are various operations performed on counters, as defined
// in Savage & Drake (E-2052) 1.4.8. The functions all return 0 normally,
// and return 1 on overflow.
#include <stdio.h>
static int TrapPIPA = 0;
// 1's-complement increment
int
CounterPINC (int16_t * Counter)
{
int16_t i;
int Overflow = 0;
i = *Counter;
if (i == 037777)
{
Overflow = 1;
i = AGC_P0;
}
else
{
Overflow = 0;
if (TrapPIPA)
printf ("PINC: %o", i);
i = ((i + 1) & 077777);
if (TrapPIPA)
printf (" %o", i);
if (i == AGC_P0) // Account for -0 to +1 transition.
i++;
if (TrapPIPA)
printf (" %o\n", i);
}
*Counter = i;
return (Overflow);
}
// 1's-complement decrement, but only of negative integers.
int
CounterMINC (int16_t * Counter)
{
int16_t i;
int Overflow = 0;
i = *Counter;
if (i == (int16_t) 040000)
{
Overflow = 1;
i = AGC_M0;
}
else
{
Overflow = 0;
if (TrapPIPA)
printf ("MINC: %o", i);
i = ((i - 1) & 077777);
if (TrapPIPA)
printf (" %o", i);
if (i == AGC_M0) // Account for +0 to -1 transition.
i--;
if (TrapPIPA)
printf (" %o\n", i);
}
*Counter = i;
return (Overflow);
}
// 2's-complement increment.
int
CounterPCDU (int16_t * Counter)
{
int16_t i;
int Overflow = 0;
i = *Counter;
if (i == (int16_t) 077777)
Overflow = 1;
i++;
i &= 077777;
*Counter = i;
return (Overflow);
}