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Copy pathVGA_text_mode_controller_hw.tcl
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VGA_text_mode_controller_hw.tcl
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# TCL File Generated by Component Editor 18.1
# Thu Nov 11 18:23:59 CST 2021
# DO NOT MODIFY
#
# VGA_text_mode_controller "VGA Text Mode Controller" v1.0
# Kelvin Chen 2021.11.11.18:23:59
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module VGA_text_mode_controller
#
set_module_property DESCRIPTION ""
set_module_property NAME VGA_text_mode_controller
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "ECE 385 Custom IPs"
set_module_property AUTHOR "Kelvin Chen"
set_module_property DISPLAY_NAME "VGA Text Mode Controller"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL vga_text_avl_interface
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file vga_text_avl_interface.sv SYSTEM_VERILOG PATH vga_text_avl_interface.sv TOP_LEVEL_FILE
add_fileset_file VGA_controller.sv SYSTEM_VERILOG PATH VGA_controller.sv
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL vga_text_avl_interface
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file vga_text_avl_interface.sv SYSTEM_VERILOG PATH vga_text_avl_interface.sv
add_fileset_file VGA_controller.sv SYSTEM_VERILOG PATH VGA_controller.sv
#
# parameters
#
#
# display items
#
#
# connection point VGA_port
#
add_interface VGA_port conduit end
set_interface_property VGA_port associatedClock clock
set_interface_property VGA_port associatedReset reset
set_interface_property VGA_port ENABLED true
set_interface_property VGA_port EXPORT_OF ""
set_interface_property VGA_port PORT_NAME_MAP ""
set_interface_property VGA_port CMSIS_SVD_VARIABLES ""
set_interface_property VGA_port SVD_ADDRESS_GROUP ""
add_interface_port VGA_port blue blue Output 4
add_interface_port VGA_port green green Output 4
add_interface_port VGA_port hs hs Output 1
add_interface_port VGA_port red red Output 4
add_interface_port VGA_port vs vs Output 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset RESET reset Input 1
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 50000000
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock CLK clk Input 1
#
# connection point avl_mm_slave
#
add_interface avl_mm_slave avalon end
set_interface_property avl_mm_slave addressUnits WORDS
set_interface_property avl_mm_slave associatedClock clock
set_interface_property avl_mm_slave associatedReset reset
set_interface_property avl_mm_slave bitsPerSymbol 8
set_interface_property avl_mm_slave burstOnBurstBoundariesOnly false
set_interface_property avl_mm_slave burstcountUnits WORDS
set_interface_property avl_mm_slave explicitAddressSpan 0
set_interface_property avl_mm_slave holdTime 0
set_interface_property avl_mm_slave linewrapBursts false
set_interface_property avl_mm_slave maximumPendingReadTransactions 0
set_interface_property avl_mm_slave maximumPendingWriteTransactions 0
set_interface_property avl_mm_slave readLatency 0
set_interface_property avl_mm_slave readWaitStates 20
set_interface_property avl_mm_slave readWaitTime 20
set_interface_property avl_mm_slave setupTime 0
set_interface_property avl_mm_slave timingUnits Cycles
set_interface_property avl_mm_slave writeWaitTime 0
set_interface_property avl_mm_slave ENABLED true
set_interface_property avl_mm_slave EXPORT_OF ""
set_interface_property avl_mm_slave PORT_NAME_MAP ""
set_interface_property avl_mm_slave CMSIS_SVD_VARIABLES ""
set_interface_property avl_mm_slave SVD_ADDRESS_GROUP ""
add_interface_port avl_mm_slave AVL_ADDR address Input 13
add_interface_port avl_mm_slave AVL_BYTE_EN byteenable Input 4
add_interface_port avl_mm_slave AVL_CS chipselect Input 1
add_interface_port avl_mm_slave AVL_READ read Input 1
add_interface_port avl_mm_slave AVL_WRITE write Input 1
add_interface_port avl_mm_slave AVL_WRITEDATA writedata Input 32
add_interface_port avl_mm_slave AVL_READDATA readdata Output 32
set_interface_assignment avl_mm_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avl_mm_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avl_mm_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avl_mm_slave embeddedsw.configuration.isPrintableDevice 0