diff --git a/README.md b/README.md
index 259416a..2fd369e 100644
--- a/README.md
+++ b/README.md
@@ -61,7 +61,10 @@ conda XXXX
 
  * `netlistsvg`
 
-## New Directives
+## Usage
+
+The `verilog-diagram` RST directive can be used to generate a diagram from Verilog code and include it in your documentation.
+Check out the [examples](https://sphinxcontrib-verilog-diagrams.readthedocs.io/en/latest/) to see how to use it.
 
 ```rst
 
@@ -72,7 +75,9 @@ conda XXXX
 
 ```
 
-Verilog Diagram Types;
+### Options
+
+`:type:` - Verilog Diagram Types;
 
  * `yosys-blackbox` - Netlist rendered by Yosys.
  * `yosys-aig` - Verilog file run through `aigmap` before image is generated directly in Yosys.
@@ -82,6 +87,12 @@ Verilog Diagram Types;
 
 `:flatten:` - Use the Yosys `flatten` command before generating the image.
 
+### Example
+
+Here is a diagram of a 4-bit carry chain.
+
+![4-bit carry chain](diagrams/carry4-flatten.svg)
+
 
 ## Licence
 
diff --git a/diagrams/carry4-flatten.svg b/diagrams/carry4-flatten.svg
new file mode 100644
index 0000000..a7deccb
--- /dev/null
+++ b/diagrams/carry4-flatten.svg
@@ -0,0 +1,317 @@
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:s="https://github.com/nturley/netlistsvg" width="511" height="435.5">
+  <style>svg {
+    stroke:#000;
+    fill:none;
+  }
+  text {
+    fill:#000;
+    stroke:none;
+    font-size:10px;
+    font-weight: bold;
+    font-family: "Courier New", monospace;
+  }
+  .nodelabel {
+    text-anchor: middle;
+  }
+  .inputPortLabel {
+    text-anchor: end;
+  }
+  .splitjoinBody {
+    fill:#000;
+  }</style>
+  <g s:type="or" transform="translate(83,77)" s:width="30" s:height="25" id="cell_$or$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/carry4-bits.v:5$3">
+    <s:alias val="$or"/>
+    <s:alias val="$logic_or"/>
+    <s:alias val="$_OR_"/>
+    <path d="M0,25 L0,25 L15,25 A15 12.5 0 0 0 15,0 L0,0" class="cell_$or$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/carry4-bits.v:5$3"/>
+    <path d="M0,0 A30 25 0 0 1 0,25" class="cell_$or$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/carry4-bits.v:5$3"/>
+    <g s:x="3" s:y="5" s:pid="A"/>
+    <g s:x="3" s:y="20" s:pid="B"/>
+    <g s:x="30" s:y="12.5" s:pid="Y"/>
+  </g>
+  <g s:type="mux" transform="translate(163,59.5)" s:width="20" s:height="40" id="cell_$techmap\muxcy0.$ternary$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/muxcy.v:2$1">
+    <s:alias val="$pmux"/>
+    <s:alias val="$mux"/>
+    <s:alias val="$_MUX_"/>
+    <path d="M0,0 L20,10 L20,30 L0,40 Z" class="cell_$techmap\muxcy0.$ternary$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/muxcy.v:2$1"/>
+    <g s:x="0" s:y="10" s:pid="A"/>
+    <g s:x="0" s:y="30" s:pid="B"/>
+    <g s:x="10" s:y="35" s:pid="S"/>
+    <g s:x="20" s:y="20" s:pid="Y"/>
+  </g>
+  <g s:type="mux" transform="translate(223,165.5)" s:width="20" s:height="40" id="cell_$techmap\muxcy1.$ternary$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/muxcy.v:2$1">
+    <s:alias val="$pmux"/>
+    <s:alias val="$mux"/>
+    <s:alias val="$_MUX_"/>
+    <path d="M0,0 L20,10 L20,30 L0,40 Z" class="cell_$techmap\muxcy1.$ternary$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/muxcy.v:2$1"/>
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+    <g s:x="0" s:y="30" s:pid="B"/>
+    <g s:x="10" s:y="35" s:pid="S"/>
+    <g s:x="20" s:y="20" s:pid="Y"/>
+  </g>
+  <g s:type="mux" transform="translate(283,207.5)" s:width="20" s:height="40" id="cell_$techmap\muxcy2.$ternary$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/muxcy.v:2$1">
+    <s:alias val="$pmux"/>
+    <s:alias val="$mux"/>
+    <s:alias val="$_MUX_"/>
+    <path d="M0,0 L20,10 L20,30 L0,40 Z" class="cell_$techmap\muxcy2.$ternary$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/muxcy.v:2$1"/>
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+    <g s:x="0" s:y="30" s:pid="B"/>
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+    <g s:x="20" s:y="20" s:pid="Y"/>
+  </g>
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+    <s:alias val="$pmux"/>
+    <s:alias val="$mux"/>
+    <s:alias val="$_MUX_"/>
+    <path d="M0,0 L20,10 L20,30 L0,40 Z" class="cell_$techmap\muxcy3.$ternary$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/muxcy.v:2$1"/>
+    <g s:x="0" s:y="10" s:pid="A"/>
+    <g s:x="0" s:y="30" s:pid="B"/>
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+    <s:alias val="$xor"/>
+    <s:alias val="$reduce_xor"/>
+    <s:alias val="$_XOR_"/>
+    <path d="M3,0 A30 25 0 0 1 3,25 A30 25 0 0 0 33,12.5 A30 25 0 0 0 3,0" class="cell_$techmap\xorcy0.$xor$/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-verilog-diagrams/checkouts/latest/docs/verilog/xorcy.v:2$2"/>
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+    <s:alias val="$xor"/>
+    <s:alias val="$reduce_xor"/>
+    <s:alias val="$_XOR_"/>
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+    <s:alias val="$xor"/>
+    <s:alias val="$reduce_xor"/>
+    <s:alias val="$_XOR_"/>
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+    <s:alias val="$xor"/>
+    <s:alias val="$reduce_xor"/>
+    <s:alias val="$_XOR_"/>
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+    <s:alias val="$_outputExt_"/>
+    <path d="M30,0 L30,20 L15,20 L0,10 L15,0 Z" class="cell_CO"/>
+    <g s:x="0" s:y="10" s:pid="A"/>
+  </g>
+  <g s:type="outputExt" transform="translate(469,123)" s:width="30" s:height="20" id="cell_O">
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+    <s:alias val="$_outputExt_"/>
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+    <g s:x="28" s:y="10" s:pid="Y"/>
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