From 79aa3e3ef5d16a800e90b132b77dfdb95447b6c9 Mon Sep 17 00:00:00 2001 From: Joshua Mack Date: Thu, 10 Feb 2022 16:37:35 -0700 Subject: [PATCH] Added more of Eddie and Ruben's IP projects Additionally, added the initial bare metal software for transmitting packets into and receiving packets from RANC on ZCU102 Partial progress on #9 --- .../StreamingSoftware/streamingrx.c | 748 ++++++++++++++++++ .../StreamingSoftware/streamingtx.c | 403 ++++++++++ hardware/IP/AXI-StreamPacketBuffer/.gitignore | 1 + .../AXI-StreamPacketBuffer.tcl | 424 ++++++++++ .../IP/AXI-StreamPacketBuffer/component.xml | 555 +++++++++++++ .../src/design/AXI-StreamPacketBuffer.v | 89 +++ .../design/AXI-StreamPacketBuffer_M00_AXIS.v | 245 ++++++ .../src/design/DoubleBuffer.v | 82 ++ .../src/testbench/AXI-StreamPacketBuffer_tb.v | 150 ++++ .../xgui/AXIStreamPacketBuffer_v1_0.tcl | 70 ++ hardware/IP/InputRouter/component.xml | 319 ++++++++ .../IP/InputRouter/gui/InputRouter_v1_0.gtcl | 2 + .../IP/InputRouter/src/sources/InputRouter.v | 65 ++ .../IP/InputRouter/xgui/InputRouter_v1_0.tcl | 64 ++ hardware/IP/OutcomeCore/component.xml | 611 ++++++++++++++ .../src/simulation/OutcomeCore_tb.v | 363 +++++++++ hardware/IP/OutcomeCore/src/sources/FIFO.v | 84 ++ .../IP/OutcomeCore/src/sources/OutcomeCore.v | 96 +++ .../src/sources/OutcomeCoreProcessor.v | 162 ++++ .../src/sources/OutcomeCore_M00_AXIS.v | 242 ++++++ .../IP/OutcomeCore/xgui/OutcomeCore_v1_0.tcl | 100 +++ hardware/{ => IP/RANCNetwork}/Makefile | 0 hardware/{ => IP/RANCNetwork}/README.md | 0 hardware/{ => IP/RANCNetwork}/component.xml | 0 hardware/{ => IP/RANCNetwork}/rancnetwork.tcl | 0 .../RANCNetwork}/src/simulations/.gitignore | 0 .../RANCNetwork}/src/simulations/__init__.py | 0 .../src/simulations/iverilog/Makefile | 0 .../src/simulations/iverilog/myhdl.c | 0 .../src/simulations/iverilog/myhdl_20030518.c | 0 .../src/simulations/iverilog/myhdl_table.c | 0 .../memory_files/tea/128/csram_000.mem | 0 .../memory_files/tea/128/csram_001.mem | 0 .../memory_files/tea/128/csram_002.mem | 0 .../memory_files/tea/128/csram_003.mem | 0 .../memory_files/tea/128/csram_004.mem | 0 .../memory_files/tea/128/csram_005.mem | 0 .../memory_files/tea/128/csram_006.mem | 0 .../memory_files/tea/128/csram_007.mem | 0 .../memory_files/tea/128/csram_008.mem | 0 .../memory_files/tea/128/csram_009.mem | 0 .../memory_files/tea/128/csram_010.mem | 0 .../memory_files/tea/128/csram_011.mem | 0 .../memory_files/tea/128/csram_012.mem | 0 .../memory_files/tea/128/csram_013.mem | 0 .../memory_files/tea/128/csram_014.mem | 0 .../memory_files/tea/128/csram_015.mem | 0 .../memory_files/tea/128/csram_016.mem | 0 .../memory_files/tea/128/csram_017.mem | 0 .../memory_files/tea/128/csram_018.mem | 0 .../memory_files/tea/128/csram_019.mem | 0 .../memory_files/tea/128/csram_020.mem | 0 .../memory_files/tea/128/csram_021.mem | 0 .../memory_files/tea/128/csram_022.mem | 0 .../memory_files/tea/128/csram_023.mem | 0 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| 0 .../memory_files/tea/128/tc_012.mem | 0 .../memory_files/tea/128/tc_013.mem | 0 .../memory_files/tea/128/tc_014.mem | 0 .../memory_files/tea/128/tc_015.mem | 0 .../memory_files/tea/128/tc_016.mem | 0 .../memory_files/tea/128/tc_017.mem | 0 .../memory_files/tea/128/tc_018.mem | 0 .../memory_files/tea/128/tc_019.mem | 0 .../memory_files/tea/128/tc_020.mem | 0 .../memory_files/tea/128/tc_021.mem | 0 .../memory_files/tea/128/tc_022.mem | 0 .../memory_files/tea/128/tc_023.mem | 0 .../memory_files/tea/128/tc_024.mem | 0 .../memory_files/tea/128/tc_025.mem | 0 .../memory_files/tea/128/tc_026.mem | 0 .../memory_files/tea/128/tc_027.mem | 0 .../memory_files/tea/128/tc_028.mem | 0 .../memory_files/tea/128/tc_029.mem | 0 .../memory_files/tea/128/tc_030.mem | 0 .../memory_files/tea/128/tc_031.mem | 0 .../memory_files/tea/256/csram_000.mem | 0 .../memory_files/tea/256/csram_001.mem | 0 .../memory_files/tea/256/csram_002.mem | 0 .../memory_files/tea/256/csram_003.mem | 0 .../memory_files/tea/256/csram_004.mem | 0 .../memory_files/tea/256/csram_005.mem | 0 .../memory_files/tea/256/csram_006.mem | 0 .../memory_files/tea/256/csram_007.mem | 0 .../memory_files/tea/256/csram_008.mem | 0 .../memory_files/tea/256/csram_009.mem | 0 .../memory_files/tea/256/csram_010.mem | 0 .../memory_files/tea/256/csram_011.mem | 0 .../memory_files/tea/256/tb_correct.txt | 0 .../memory_files/tea/256/tb_input.txt | 0 .../memory_files/tea/256/tb_num_inputs.txt | 0 .../memory_files/tea/256/tb_num_outputs.txt | 0 .../memory_files/tea/256/tc_000.mem | 0 .../memory_files/tea/256/tc_001.mem | 0 .../memory_files/tea/256/tc_002.mem | 0 .../memory_files/tea/256/tc_003.mem | 0 .../memory_files/tea/256/tc_004.mem | 0 .../memory_files/tea/256/tc_005.mem | 0 .../memory_files/tea/256/tc_006.mem | 0 .../memory_files/tea/256/tc_007.mem | 0 .../memory_files/tea/256/tc_008.mem | 0 .../memory_files/tea/256/tc_009.mem | 0 .../memory_files/tea/256/tc_010.mem | 0 .../memory_files/tea/256/tc_011.mem | 0 .../memory_files/tea/512/csram_000.mem | 0 .../memory_files/tea/512/csram_001.mem | 0 .../memory_files/tea/512/csram_002.mem | 0 .../memory_files/tea/512/csram_003.mem | 0 .../memory_files/tea/512/csram_004.mem | 0 .../memory_files/tea/512/csram_005.mem | 0 .../memory_files/tea/512/tb_correct.txt | 0 .../memory_files/tea/512/tb_input.txt | 0 .../memory_files/tea/512/tb_num_inputs.txt | 0 .../memory_files/tea/512/tb_num_outputs.txt | 0 .../memory_files/tea/512/tc_000.mem | 0 .../memory_files/tea/512/tc_001.mem | 0 .../memory_files/tea/512/tc_002.mem | 0 .../memory_files/tea/512/tc_003.mem | 0 .../memory_files/tea/512/tc_004.mem | 0 .../memory_files/tea/512/tc_005.mem | 0 .../memory_files/tea/512_128/csram_000.mem | 0 .../memory_files/tea/512_128/csram_001.mem | 0 .../memory_files/tea/512_128/csram_002.mem | 0 .../memory_files/tea/512_128/csram_003.mem | 0 .../memory_files/tea/512_128/csram_004.mem | 0 .../memory_files/tea/512_128/csram_005.mem | 0 .../memory_files/tea/512_128/tb_correct.txt | 0 .../memory_files/tea/512_128/tb_input.txt | 0 .../tea/512_128/tb_num_inputs.txt | 0 .../tea/512_128/tb_num_outputs.txt | 0 .../memory_files/tea/512_128/tc_000.mem | 0 .../memory_files/tea/512_128/tc_001.mem | 0 .../memory_files/tea/512_128/tc_002.mem | 0 .../memory_files/tea/512_128/tc_003.mem | 0 .../memory_files/tea/512_128/tc_004.mem | 0 .../memory_files/tea/512_128/tc_005.mem | 0 .../tc_unittest_1024.mem | 0 .../tc_unittest_128.mem | 0 .../tc_unittest_2048.mem | 0 .../tc_unittest_256.mem | 0 .../tc_unittest_512.mem | 0 .../memory_files/vmm/csram_000.mem | 0 .../memory_files/vmm/csram_001.mem | 0 .../memory_files/vmm/csram_002.mem | 0 .../memory_files/vmm/csram_003.mem | 0 .../memory_files/vmm/csram_004.mem | 0 .../memory_files/vmm/csram_005.mem | 0 .../memory_files/vmm/csram_006.mem | 0 .../memory_files/vmm/csram_007.mem | 0 .../memory_files/vmm/tb_correct.txt | 0 .../simulations/memory_files/vmm/tb_input.txt | 0 .../memory_files/vmm/tb_num_inputs.txt | 0 .../memory_files/vmm/tb_num_outputs.txt | 0 .../simulations/memory_files/vmm/tc_000.mem | 0 .../simulations/memory_files/vmm/tc_001.mem | 0 .../simulations/memory_files/vmm/tc_002.mem | 0 .../simulations/memory_files/vmm/tc_003.mem | 0 .../simulations/memory_files/vmm/tc_004.mem | 0 .../simulations/memory_files/vmm/tc_005.mem | 0 .../simulations/memory_files/vmm/tc_006.mem | 0 .../simulations/memory_files/vmm/tc_007.mem | 0 .../src/simulations/networks/RANCNetwork.py | 0 .../src/simulations/networks/test_tea.py | 0 .../src/simulations/networks/test_vmm.py | 0 .../src/simulations/tests/ForwardEastWest.py | 0 .../src/simulations/tests/NeuronBlock.py | 0 .../src/simulations/tests/RANCNetwork.py | 0 .../src/simulations/tests/TokenController.py | 0 .../src/simulations/tests/buffer.py | 0 .../simulations/tests/test_ForwardEastWest.py | 0 .../simulations/tests/test_ForwardEastWest.v | 0 .../src/simulations/tests/test_NeuronBlock.py | 0 .../src/simulations/tests/test_NeuronBlock.v | 0 .../src/simulations/tests/test_RANCNetwork.py | 0 .../src/simulations/tests/test_RANCNetwork.v | 0 .../simulations/tests/test_TokenController.py | 0 .../simulations/tests/test_TokenController.v | 0 .../src/simulations/tests/test_buffer.py | 0 .../src/simulations/tests/test_buffer.v | 0 .../{ => IP/RANCNetwork}/src/sources/Adder.v | 0 .../{ => IP/RANCNetwork}/src/sources/Buffer.v | 0 .../{ => IP/RANCNetwork}/src/sources/CSRAM.v | 0 .../{ => IP/RANCNetwork}/src/sources/Comp.v | 0 .../{ => IP/RANCNetwork}/src/sources/Core.v | 0 .../RANCNetwork}/src/sources/Counter.v | 0 .../{ => IP/RANCNetwork}/src/sources/EnReg.v | 0 .../src/sources/ForwardEastWest.v | 0 .../src/sources/ForwardNorthSouth.v | 0 .../RANCNetwork}/src/sources/FromLocal.v | 0 .../RANCNetwork}/src/sources/IntegratorUnit.v | 0 .../RANCNetwork}/src/sources/LocalIn.v | 0 .../{ => IP/RANCNetwork}/src/sources/Merge2.v | 0 .../{ => IP/RANCNetwork}/src/sources/Merge3.v | 0 .../RANCNetwork}/src/sources/Mux2to1.v | 0 .../RANCNetwork}/src/sources/NeuronBlock.v | 0 .../RANCNetwork}/src/sources/OutputBus.v | 0 .../RANCNetwork}/src/sources/PacketFetch.v | 0 .../src/sources/PathDecoder2Way.v | 0 .../src/sources/PathDecoder3Way.v | 0 .../RANCNetwork}/src/sources/RANCNetwork.v | 0 .../src/sources/RANCNetworkGrid.v | 0 .../src/sources/RANCNetwork_S00_AXIS.v | 0 .../{ => IP/RANCNetwork}/src/sources/Router.v | 0 .../RANCNetwork}/src/sources/Scheduler.v | 0 .../RANCNetwork}/src/sources/SchedulerSRAM.v | 0 .../src/sources/ThresholdResetUnit.v | 0 .../src/sources/TokenController.v | 0 .../RANCNetwork}/xgui/RANCNetwork_v1_0.tcl | 0 hardware/IP/TickGenerator/.gitignore | 1 + hardware/IP/TickGenerator/TickGenerator.tcl | 422 ++++++++++ hardware/IP/TickGenerator/component.xml | 299 +++++++ .../TickGenerator/src/design/TickGenerator.v | 53 ++ .../src/testbench/TickGenerator_tb.v | 46 ++ .../TickGenerator/xgui/TickGenerator_v1_0.tcl | 55 ++ 237 files changed, 5751 insertions(+) create mode 100644 hardware/BareMetalSoftware/StreamingSoftware/streamingrx.c create mode 100644 hardware/BareMetalSoftware/StreamingSoftware/streamingtx.c create mode 100644 hardware/IP/AXI-StreamPacketBuffer/.gitignore create mode 100644 hardware/IP/AXI-StreamPacketBuffer/AXI-StreamPacketBuffer.tcl create mode 100644 hardware/IP/AXI-StreamPacketBuffer/component.xml create mode 100644 hardware/IP/AXI-StreamPacketBuffer/src/design/AXI-StreamPacketBuffer.v create mode 100644 hardware/IP/AXI-StreamPacketBuffer/src/design/AXI-StreamPacketBuffer_M00_AXIS.v create mode 100644 hardware/IP/AXI-StreamPacketBuffer/src/design/DoubleBuffer.v create mode 100644 hardware/IP/AXI-StreamPacketBuffer/src/testbench/AXI-StreamPacketBuffer_tb.v create mode 100644 hardware/IP/AXI-StreamPacketBuffer/xgui/AXIStreamPacketBuffer_v1_0.tcl create mode 100644 hardware/IP/InputRouter/component.xml create mode 100644 hardware/IP/InputRouter/gui/InputRouter_v1_0.gtcl create mode 100644 hardware/IP/InputRouter/src/sources/InputRouter.v create mode 100644 hardware/IP/InputRouter/xgui/InputRouter_v1_0.tcl create mode 100644 hardware/IP/OutcomeCore/component.xml create mode 100644 hardware/IP/OutcomeCore/src/simulation/OutcomeCore_tb.v create mode 100644 hardware/IP/OutcomeCore/src/sources/FIFO.v create mode 100644 hardware/IP/OutcomeCore/src/sources/OutcomeCore.v create mode 100644 hardware/IP/OutcomeCore/src/sources/OutcomeCoreProcessor.v create mode 100644 hardware/IP/OutcomeCore/src/sources/OutcomeCore_M00_AXIS.v create mode 100644 hardware/IP/OutcomeCore/xgui/OutcomeCore_v1_0.tcl rename hardware/{ => IP/RANCNetwork}/Makefile (100%) rename hardware/{ => IP/RANCNetwork}/README.md (100%) rename hardware/{ => IP/RANCNetwork}/component.xml (100%) rename hardware/{ => IP/RANCNetwork}/rancnetwork.tcl (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/.gitignore (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/__init__.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/iverilog/Makefile (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/iverilog/myhdl.c (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/iverilog/myhdl_20030518.c (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/iverilog/myhdl_table.c (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_006.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_007.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_008.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_009.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_010.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_011.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_012.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_013.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_014.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_015.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_016.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_017.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_018.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_019.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_020.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_021.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_022.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_023.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_024.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_025.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_026.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_027.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_028.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_029.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_030.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/csram_031.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tb_correct.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tb_input.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tb_num_inputs.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tb_num_outputs.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_006.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_007.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_008.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_009.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_010.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_011.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_012.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_013.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_014.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_015.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_016.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_017.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_018.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_019.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_020.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_021.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_022.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_023.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_024.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_025.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_026.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_027.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_028.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_029.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_030.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/128/tc_031.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_006.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_007.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_008.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_009.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_010.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/csram_011.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tb_correct.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tb_input.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tb_num_inputs.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tb_num_outputs.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_006.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_007.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_008.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_009.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_010.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/256/tc_011.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/csram_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/csram_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/csram_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/csram_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/csram_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/csram_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tb_correct.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tb_input.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tb_num_inputs.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tb_num_outputs.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tc_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tc_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tc_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tc_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tc_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512/tc_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512_128/csram_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512_128/csram_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512_128/csram_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512_128/csram_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512_128/csram_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512_128/csram_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512_128/tb_correct.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/tea/512_128/tb_input.txt (100%) rename hardware/{ => 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rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/token_controller_tests/tc_unittest_2048.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/token_controller_tests/tc_unittest_256.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/token_controller_tests/tc_unittest_512.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/csram_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/csram_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/csram_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/csram_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/csram_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/csram_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/csram_006.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/csram_007.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tb_correct.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tb_input.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tb_num_inputs.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tb_num_outputs.txt (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tc_000.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tc_001.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tc_002.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tc_003.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tc_004.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tc_005.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tc_006.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/memory_files/vmm/tc_007.mem (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/networks/RANCNetwork.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/networks/test_tea.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/networks/test_vmm.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/ForwardEastWest.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/NeuronBlock.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/RANCNetwork.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/TokenController.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/buffer.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_ForwardEastWest.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_ForwardEastWest.v (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_NeuronBlock.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_NeuronBlock.v (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_RANCNetwork.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_RANCNetwork.v (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_TokenController.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_TokenController.v (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_buffer.py (100%) rename hardware/{ => IP/RANCNetwork}/src/simulations/tests/test_buffer.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Adder.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Buffer.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/CSRAM.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Comp.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Core.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Counter.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/EnReg.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/ForwardEastWest.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/ForwardNorthSouth.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/FromLocal.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/IntegratorUnit.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/LocalIn.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Merge2.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Merge3.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Mux2to1.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/NeuronBlock.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/OutputBus.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/PacketFetch.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/PathDecoder2Way.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/PathDecoder3Way.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/RANCNetwork.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/RANCNetworkGrid.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/RANCNetwork_S00_AXIS.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Router.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/Scheduler.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/SchedulerSRAM.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/ThresholdResetUnit.v (100%) rename hardware/{ => IP/RANCNetwork}/src/sources/TokenController.v (100%) rename hardware/{ => IP/RANCNetwork}/xgui/RANCNetwork_v1_0.tcl (100%) create mode 100644 hardware/IP/TickGenerator/.gitignore create mode 100644 hardware/IP/TickGenerator/TickGenerator.tcl create mode 100644 hardware/IP/TickGenerator/component.xml create mode 100644 hardware/IP/TickGenerator/src/design/TickGenerator.v create mode 100644 hardware/IP/TickGenerator/src/testbench/TickGenerator_tb.v create mode 100644 hardware/IP/TickGenerator/xgui/TickGenerator_v1_0.tcl diff --git a/hardware/BareMetalSoftware/StreamingSoftware/streamingrx.c b/hardware/BareMetalSoftware/StreamingSoftware/streamingrx.c new file mode 100644 index 0000000..220f03d --- /dev/null +++ b/hardware/BareMetalSoftware/StreamingSoftware/streamingrx.c @@ -0,0 +1,748 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file streamingrx.c + * + * Created for Dr. Akoglu's Reconfigurable Computing Lab at the University of + * Arizona + * + * This file receives an AXI stream of packets from the RANCNetwork. + * It is meant to be used in tandem with `streamingtx.c`, and sets up + * external pointers to DMA and Interrupt flags so that the tx can operate + * correctly. + * + * To see the debug print, you need a Uart16550 or uartlite in your system, + * and please set "-DDEBUG" in your compiler options. You need to rebuild your + * software executable. + * + * Make sure that MEMORY_BASE is defined properly as per the HW system. The + * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In + * throughput mode, it is 512MB. These limits are need to ensured for + * proper operation of this code. + * + * + * *************************************************************************** + */ + +/***************************** Include Files *********************************/ + +#include "xaxidma.h" +#include "xparameters.h" +#include "xil_exception.h" +#include "xdebug.h" + +#ifdef XPAR_UARTNS550_0_BASEADDR +#include "xuartns550_l.h" /* to use uartns550 */ +#endif + + +#ifdef XPAR_INTC_0_DEVICE_ID + #include "xintc.h" +#else + #include "xscugic.h" +#endif + +/************************** Constant Definitions *****************************/ + +/* + * Device hardware build related constants. + */ + +#define DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID + +#ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR +#define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR +#elif XPAR_MIG7SERIES_0_BASEADDR +#define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR +#elif XPAR_MIG_0_BASEADDR +#define DDR_BASE_ADDR XPAR_MIG_0_BASEADDR +#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR +#define DDR_BASE_ADDR XPAR_PSU_DDR_0_S_AXI_BASEADDR +#endif + +#ifndef DDR_BASE_ADDR +#define MEM_BASE_ADDR 0x01000000 +#else +#define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000) +#endif + +#ifdef XPAR_INTC_0_DEVICE_ID +#define RX_INTR_ID XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID +#define TX_INTR_ID XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID +#else +#define RX_INTR_ID XPAR_FABRIC_AXIDMA_0_S2MM_INTROUT_VEC_ID +#define TX_INTR_ID XPAR_FABRIC_AXIDMA_0_MM2S_INTROUT_VEC_ID +#endif + +#define RX_BUFFER_BASE (MEM_BASE_ADDR + 0x00300000) +#define RX_BUFFER_HIGH (MEM_BASE_ADDR + 0x004FFFFF) + +#ifdef XPAR_INTC_0_DEVICE_ID +#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID +#else +#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID +#endif + +#define TICK_INT_ID 123U + +#ifdef XPAR_INTC_0_DEVICE_ID + #define INTC XIntc + #define INTC_HANDLER XIntc_InterruptHandler +#else + #define INTC XScuGic + #define INTC_HANDLER XScuGic_InterruptHandler +#endif + +/* Timeout loop counter for reset + */ +#define RESET_TIMEOUT_COUNTER 10000 + +/* + * Buffer and Buffer Descriptor related constant definition + */ +#define MAX_PKT_LEN 0x3E8 + +#define NUMBER_OF_TRANSFERS 21 + +/**************************** Debug Flags *******************************/ +//#define PRINT_DEBUG + +/* The interrupt coalescing threshold and delay timer threshold + * Valid range is 1 to 255 + * + * We set the coalescing threshold to be the total number of packets. + * The receive side will only get one completion interrupt for this example. + */ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +#ifndef DEBUG +extern void xil_printf(const char *format, ...); +#endif + +#ifdef XPAR_UARTNS550_0_BASEADDR +static void Uart550_Setup(void); +#endif + +static void RxIntrHandler(void *Callback); +static void TxIntrHandler(void *Callback); +static void TickIntrHandler(void *Callback); + + + + +static int SetupIntrSystem(INTC * IntcInstancePtr, + XAxiDma * AxiDmaPtr, u16 RxIntrId, u16 TxIntrId, + u16 TickIntrId); +static void DisableIntrSystem(INTC * IntcInstancePtr, + u16 RxIntrId, u16 TxIntrId, u16 TickIntrId); + + + +/************************** Variable Definitions *****************************/ +/* + * Device instance definitions + */ + + +static XAxiDma AxiDma; /* Instance of the XAxiDma */ + +static INTC Intc; /* Instance of the Interrupt Controller */ + +/* + * Flags interrupt handlers use to notify the application context the events. + */ +volatile int RxDone; +volatile int Error; + +/* + * Communication between rx and tx + */ +#define COMM_VAL (*(volatile unsigned long *)(0x800000000)) +#define TxDone (*(volatile int *)(0x800000010)) +#define TickOccurred (*(volatile int *)(0x800000020)) +#define AXI_PTR (*(volatile unsigned long *)(0x800000030)) + + +/*****************************************************************************/ +/** +* +* Main function +* +* This function is the main entry of the streaming receiving. +* It does the following: +* Set up the output terminal if UART16550 is in the hardware build +* Sets up the dma and interrupt system. +* Sets dma pointer and interrupt flag to external variables for use in tx +* Waits for the tick to start +* Loops through the following code: +* Read a transfer +* Wait for the transfer to finish +* Flush RX buffer +* Informs the tx that it is finished +* +* @param None +* +* @return +* - XST_SUCCESS if example finishes successfully +* - XST_FAILURE if example fails. +* +* @note None. +* +******************************************************************************/ +int main(void) +{ + int Status; + XAxiDma_Config *Config; + int NumTransfers = NUMBER_OF_TRANSFERS; + int Index; + int Tick; + u8 *RxBufferPtr; + + RxBufferPtr = (u8 *)RX_BUFFER_BASE; + /* Initial setup for Uart16550 */ +#ifdef XPAR_UARTNS550_0_BASEADDR + + Uart550_Setup(); + +#endif + +#ifdef PRINT_DEBUG + xil_printf("\r\n[RX] --- Entering main() --- \r\n"); +#endif + + Config = XAxiDma_LookupConfig(DMA_DEV_ID); + if (!Config) { + xil_printf("[RX] No config found for %d\r\n", DMA_DEV_ID); + + return XST_FAILURE; + } + + /* Initialize DMA engine */ + Status = XAxiDma_CfgInitialize(&AxiDma, Config); + + if (Status != XST_SUCCESS) { + xil_printf("[RX] Initialization failed %d\r\n", Status); + return XST_FAILURE; + } + + if(XAxiDma_HasSg(&AxiDma)){ + xil_printf("[RX] Device configured as SG mode \r\n"); + return XST_FAILURE; + } + + /* Send DMA pointer to TX core */ + AXI_PTR = (unsigned long) &AxiDma; + + /* Send synchronization signal */ + COMM_VAL = 1; + /* Wait for response */ + while (COMM_VAL != 0) { + /* NOP */ + } + + /* Set up Interrupt system */ + Status = SetupIntrSystem(&Intc, &AxiDma, RX_INTR_ID, TX_INTR_ID, TICK_INT_ID); + if (Status != XST_SUCCESS) { + + xil_printf("[RX] Failed interrupt setup\r\n"); + return XST_FAILURE; + } + + /* Disable all interrupts before setup */ + + XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, + XAXIDMA_DMA_TO_DEVICE); + + XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, + XAXIDMA_DEVICE_TO_DMA); + + /* Enable all interrupts */ + XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, + XAXIDMA_DMA_TO_DEVICE); + + + XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, + XAXIDMA_DEVICE_TO_DMA); + + /* Initialize flags before start transfer test */ + RxDone = 0; + Error = 0; + + + /* Flush the SrcBuffer before the DMA transfer, in case the Data Cache + * is enabled + */ +#ifdef __aarch64__ + Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN); +#endif + + /* Wait for synchronization signal */ + while (COMM_VAL != 1) { + /* NOP */ + } + /* Send response */ + COMM_VAL = 0; + + /* Send and receive data */ + for(Tick = 0; Tick < NumTransfers; Tick ++) { + + Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, + MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA); + + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Wait RX done */ + while (!RxDone && !Error) { + /* NOP */ + } + + xil_printf("Tick %d:\r\n", Tick); + + int firstZero = 1; + + for(Index = 0; Index < MAX_PKT_LEN; Index = Index + 4) { + u32 first_byte = RxBufferPtr[Index]; + u32 second_byte = RxBufferPtr[Index + 1]; + u32 third_byte = RxBufferPtr[Index + 2]; + u32 fourth_byte = RxBufferPtr[Index + 3]; + RxBufferPtr[Index + 3] = 0; + RxBufferPtr[Index + 2] = 0; + RxBufferPtr[Index + 1] = 0; + RxBufferPtr[Index] = 0; + u32 value = fourth_byte << 24 | third_byte << 16 | second_byte << 8 | first_byte; + u32 vote_val = (value & 0b00000000000000000000111111110000) >> 4; + u32 ensemble_val = (value & 0b00000000000111111111000000000000) >> 12; + if (firstZero == 1) { + firstZero = 0; + xil_printf("\tNeuron %d\r\n", 10 * ensemble_val + vote_val); + } else if (10 * ensemble_val + vote_val != 0) { + xil_printf("\tNeuron %d\r\n", 10 * ensemble_val + vote_val); + } + } + + /* Flush RX cache */ +#ifdef __aarch64__ + Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN); +#endif + + RxDone = 0; + + if (Error) { + xil_printf("[RX] Failed test transmit\r\n"); + + goto Done; + + } + } + + /* Send synchronization signal */ + COMM_VAL = 1; + /* Wait for response */ + while (COMM_VAL != 0) { + /* NOP */ + } + + /* Disable RX Ring interrupts and return success */ + DisableIntrSystem(&Intc, RX_INTR_ID, TX_INTR_ID, TICK_INT_ID); + +Done: +#ifdef PRINT_DEBUG + xil_printf("[RX] --- Exiting main() --- \r\n"); +#endif + + return XST_SUCCESS; +} + +#ifdef XPAR_UARTNS550_0_BASEADDR +/*****************************************************************************/ +/* +* +* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8 +* +* @param None +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void Uart550_Setup(void) +{ + + XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR, + XPAR_XUARTNS550_CLOCK_HZ, 9600); + + XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR, + XUN_LCR_8_DATA_BITS); +} +#endif + +/*****************************************************************************/ +/* +* +* This is the DMA RX interrupt handler function +* +* It gets the interrupt status from the hardware, acknowledges it, and if any +* error happens, it resets the hardware. Otherwise, if a completion interrupt +* is present, then it sets the RxDone flag. +* +* @param Callback is a pointer to RX channel of the DMA engine. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void RxIntrHandler(void *Callback) +{ + u32 IrqStatus; + int TimeOut; + XAxiDma *AxiDmaInst = (XAxiDma *)Callback; + + /* Read pending interrupts */ + IrqStatus = XAxiDma_IntrGetIrq(AxiDmaInst, XAXIDMA_DEVICE_TO_DMA); + + /* Acknowledge pending interrupts */ + XAxiDma_IntrAckIrq(AxiDmaInst, IrqStatus, XAXIDMA_DEVICE_TO_DMA); + + /* + * If no interrupt is asserted, we do not do anything + */ + if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) { + return; + } + + /* + * If error interrupt is asserted, raise error flag, reset the + * hardware to recover from the error, and return with no further + * processing. + */ + if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) { + + Error = 1; + + /* Reset could fail and hang + * NEED a way to handle this or do not call it?? + */ + XAxiDma_Reset(AxiDmaInst); + + TimeOut = RESET_TIMEOUT_COUNTER; + + while (TimeOut) { + if(XAxiDma_ResetIsDone(AxiDmaInst)) { + break; + } + + TimeOut -= 1; + } + + return; + } + + /* + * If completion interrupt is asserted, then set RxDone flag + */ + if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) { + + RxDone = 1; + } +} + +/*****************************************************************************/ +/* +* +* This is the DMA TX Interrupt handler function. +* +* It gets the interrupt status from the hardware, acknowledges it, and if any +* error happens, it resets the hardware. Otherwise, if a completion interrupt +* is present, then sets the TxDone.flag +* +* @param Callback is a pointer to TX channel of the DMA engine. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void TxIntrHandler(void *Callback) +{ + + u32 IrqStatus; + int TimeOut; + XAxiDma *AxiDmaInst = (XAxiDma *)Callback; + + /* Read pending interrupts */ + IrqStatus = XAxiDma_IntrGetIrq(AxiDmaInst, XAXIDMA_DMA_TO_DEVICE); + + /* Acknowledge pending interrupts */ + + + XAxiDma_IntrAckIrq(AxiDmaInst, IrqStatus, XAXIDMA_DMA_TO_DEVICE); + + /* + * If no interrupt is asserted, we do not do anything + */ + if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) { + + return; + } + + /* + * If error interrupt is asserted, raise error flag, reset the + * hardware to recover from the error, and return with no further + * processing. + */ + if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) { + + Error = 1; + + /* + * Reset should never fail for transmit channel + */ + XAxiDma_Reset(AxiDmaInst); + + TimeOut = RESET_TIMEOUT_COUNTER; + + while (TimeOut) { + if (XAxiDma_ResetIsDone(AxiDmaInst)) { + break; + } + + TimeOut -= 1; + } + + return; + } + + /* + * If Completion interrupt is asserted, then set the TxDone flag + */ + if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) { + + TxDone = 1; + } +} + +/*****************************************************************************/ +/* +* +* This is the Tick Interrupt handler function. +* +* It gets the interrupt status from the hardware, acknowledges it, and if any +* error happens, it resets the hardware. Otherwise, if a completion interrupt +* is present, then sets the TxDone.flag +* +* @param Callback is a pointer to TX channel of the DMA engine. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void TickIntrHandler(void *Callback) +{ + TickOccurred = 1; +} + +/*****************************************************************************/ +/* +* +* This function setups the interrupt system so interrupts can occur for the +* DMA, it assumes INTC component exists in the hardware system. +* +* @param IntcInstancePtr is a pointer to the instance of the INTC. +* @param AxiDmaPtr is a pointer to the instance of the DMA engine +* @param RxIntrId is the RX channel Interrupt ID. +* +* @return +* - XST_SUCCESS if successful, +* - XST_FAILURE.if not succesful +* +* @note None. +* +******************************************************************************/ +static int SetupIntrSystem(INTC * IntcInstancePtr, + XAxiDma * AxiDmaPtr, u16 RxIntrId, u16 TxIntrId, + u16 TickIntrId) +{ + int Status; + +#ifdef XPAR_INTC_0_DEVICE_ID + + /* Initialize the interrupt controller and connect the ISRs */ + Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID); + if (Status != XST_SUCCESS) { + + xil_printf("Failed init intc\r\n"); + return XST_FAILURE; + } + + Status = XIntc_Connect(IntcInstancePtr, RxIntrId, + (XInterruptHandler) RxIntrHandler, AxiDmaPtr); + if (Status != XST_SUCCESS) { + + xil_printf("Failed rx connect intc\r\n"); + return XST_FAILURE; + } + + Status = XIntc_Connect(IntcInstancePtr, TxIntrId, + (XInterruptHandler) TxIntrHandler); + if (Status != XST_SUCCESS) { + + xil_printf("Failed tx connect intc\r\n"); + return XST_FAILURE; + } + + Status = XIntc_Connect(IntcInstancePtr, TickIntrId, + (XInterruptHandler) TickIntrHandler, + NULL); + if (Status != XST_SUCCESS) { + + xil_printf("Failed tx connect intc\r\n"); + return XST_FAILURE; + } + + /* Start the interrupt controller */ + Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE); + if (Status != XST_SUCCESS) { + + xil_printf("Failed to start intc\r\n"); + return XST_FAILURE; + } + + XIntc_Enable(IntcInstancePtr, RxIntrId); + +#else + + XScuGic_Config *IntcConfig; + + + /* + * Initialize the interrupt controller driver so that it is ready to + * use. + */ + IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID); + if (NULL == IntcConfig) { + return XST_FAILURE; + } + + Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig, + IntcConfig->CpuBaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + XScuGic_SetPriorityTriggerType(IntcInstancePtr, RxIntrId, 0xA0, 0x3); + XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3); + XScuGic_SetPriorityTriggerType(IntcInstancePtr, TickIntrId, 0xA0, 0x3); + + /* + * Connect the device driver handler that will be called when an + * interrupt for the device occurs, the handler defined above performs + * the specific interrupt processing for the device. + */ + Status = XScuGic_Connect(IntcInstancePtr, RxIntrId, + (Xil_InterruptHandler)RxIntrHandler, + AxiDmaPtr); + if (Status != XST_SUCCESS) { + return Status; + } + + Status = XScuGic_Connect(IntcInstancePtr, TxIntrId, + (Xil_InterruptHandler)TxIntrHandler, + AxiDmaPtr); + if (Status != XST_SUCCESS) { + return Status; + } + + Status = XScuGic_Connect(IntcInstancePtr, TickIntrId, + (Xil_InterruptHandler)TickIntrHandler, NULL); + if (Status != XST_SUCCESS) { + return Status; + } + + XScuGic_Enable(IntcInstancePtr, RxIntrId); + XScuGic_Enable(IntcInstancePtr, TxIntrId); + XScuGic_Enable(IntcInstancePtr, TickIntrId); + + +#endif + + /* Enable interrupts from the hardware */ + + Xil_ExceptionInit(); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)INTC_HANDLER, + (void *)IntcInstancePtr); + + Xil_ExceptionEnable(); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function disables the interrupts for DMA engine. +* +* @param IntcInstancePtr is the pointer to the INTC component instance +* @param RxIntrId is interrupt ID associated w/ DMA RX channel +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void DisableIntrSystem(INTC * IntcInstancePtr, + u16 RxIntrId, u16 TxIntrId, u16 TickIntrId) +{ +#ifdef XPAR_INTC_0_DEVICE_ID + /* Disconnect the interrupts for the DMA TX and RX channels */ + XIntc_Disconnect(IntcInstancePtr, RxIntrId); + XIntc_Disconnect(IntcInstancePtr, TxIntrId); + XIntc_Disconnect(IntcInstancePtr, TickIntrId); +#else + XScuGic_Disconnect(IntcInstancePtr, RxIntrId); + XScuGic_Disconnect(IntcInstancePtr, TxIntrId); + XScuGic_Disconnect(IntcInstancePtr, TickIntrId); +#endif +} diff --git a/hardware/BareMetalSoftware/StreamingSoftware/streamingtx.c b/hardware/BareMetalSoftware/StreamingSoftware/streamingtx.c new file mode 100644 index 0000000..2051094 --- /dev/null +++ b/hardware/BareMetalSoftware/StreamingSoftware/streamingtx.c @@ -0,0 +1,403 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/*****************************************************************************/ +/** + * + * @file streamingtx.c + * + * Created for Dr. Akoglu's Reconfigurable Computing Lab at the University of + * Arizona + * + * This file sends an AXI stream of packets into the RANCNetwork. + * It is meant to be used in tandem with `streamingrx.c`, and receives + * external pointers to DMA and Interrupt flags from the rx codes so that it + * can operate correctly. + * + * To see the debug print, you need a Uart16550 or uartlite in your system, + * and please set "-DDEBUG" in your compiler options. You need to rebuild your + * software executable. + * + * Make sure that MEMORY_BASE is defined properly as per the HW system. The + * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In + * throughput mode, it is 512MB. These limits are need to ensured for + * proper operation of this code. + * + * + * *************************************************************************** + */ + +/***************************** Include Files *********************************/ + +#include "xaxidma.h" +#include "xparameters.h" +#include "xil_exception.h" +#include "xdebug.h" +#include "xgpiops.h" +#include "xsdps.h" +#include "ff.h" + +#ifdef XPAR_UARTNS550_0_BASEADDR +#include "xuartns550_l.h" /* to use uartns550 */ +#endif + + +#ifdef XPAR_INTC_0_DEVICE_ID + #include "xintc.h" +#else + #include "xscugic.h" +#endif + +/************************** Constant Definitions *****************************/ + +/* + * Device hardware build related constants. + */ + +#ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR +#define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR +#elif XPAR_MIG7SERIES_0_BASEADDR +#define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR +#elif XPAR_MIG_0_BASEADDR +#define DDR_BASE_ADDR XPAR_MIG_0_BASEADDR +#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR +#define DDR_BASE_ADDR XPAR_PSU_DDR_0_S_AXI_BASEADDR +#endif + +#ifndef DDR_BASE_ADDR +#define MEM_BASE_ADDR 0x01000000 +#else +#define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000) +#endif + +#define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000) + +/* GPIO Parameters + */ +#define EMIO_BASE 78 + +/* + * Buffer and Buffer Descriptor related constant definition + */ +#define MAX_PKT_LEN 0x3E8 + +#define NUM_TICKS 20 + +#define MAX_PACKETS_PER_IMAGE 256*4 + +/************************** Debug Definitions *****************************/ +//#define PRINT_DEBUG + +/******************************* SD CARD *************************************/ + +typedef unsigned char bool_t; + +typedef enum xilSDResult +{ + XILSD_SUCCESS = 0, + XILSD_NO_CARD, + XILSD_WRITE_PROTECTION, + XILSD_ERR_WRITING, + XILSD_ERR_READING +} xilSDResult_t; + +#define SD_DEVICE_ID XPAR_XSDPS_0_DEVICE_ID +#define SD_BASEADDR XPAR_PS7_SD_0_BASEADDR +#define SD_CLK_FREQ_HZ XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ + +#define CARD_INSERTED(a) ((a & XSDPS_PSR_CARD_INSRT_MASK) >> 16) ? TRUE : FALSE +#define WRITE_PROTECTED(a) ((a & XSDPS_PSR_WPS_PL_MASK) >> 18) ? TRUE :FALSE + +bool_t isCardInTheSocket(void); +bool_t isCardWriteProtected(void); +bool_t xilSdInit(void); +xilSDResult_t xilSdWrite(uint8_t* buff, uint32_t blkId, uint32_t numBlks); +xilSDResult_t xilSdRead(uint8_t* buff, uint32_t blkId, uint32_t numBlks); + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +#ifndef DEBUG +extern void xil_printf(const char *format, ...); +#endif + +#ifdef XPAR_UARTNS550_0_BASEADDR +static void Uart550_Setup(void); +#endif + +u32 SetupInputs(u8* base_addr, FIL* packet_count_ptr, FIL* packet_file_ptr, u8* packet_counts, u8* packets); +void SetupInputsHardcoded(u8* base_addr, int tick); + + +/************************** Variable Definitions *****************************/ +/* + * Device instance definitions + */ + +static XGpioPs pins; /* Instance of the GPIO Pins */ + +/* + * Flags interrupt handlers use to notify the application context the events. + */ +volatile int TxDone; +volatile int Error; + +/* + * Communication between tx and rx + */ +#define COMM_VAL (*(volatile unsigned long *)(0x800000000)) +#define TxDone (*(volatile int *)(0x800000010)) +#define TickOccurred (*(volatile int *)(0x800000020)) +#define AXI_PTR (*(volatile unsigned long *)(0x800000030)) + +/************************** SD Card Variable Definitions *****************************/ +static FIL PacketFileObject; /* File object */ +static FIL PacketCountFileObject; /* File object */ +static FATFS fatfs; +/* + * To test logical drive 0, FileName should be "0:/" or + * "". For logical drive 1, FileName should be "1:/" + */ +static char PacketFileName[32] = "data.bin"; +static char PacketCountFileName[32] = "count.bin"; +static char *PacketFile; +static char *PacketCountFile; + +#ifdef __ICCARM__ +#pragma data_alignment = 32 +u8 DestinationAddress[10*1024*1024]; +#pragma data_alignment = 4 +#else +u8 Packets[MAX_PACKETS_PER_IMAGE*4] __attribute__ ((aligned(32))); +u8 PacketCounts[4] __attribute__ ((aligned(32))); +#endif + +/*****************************************************************************/ +/** +* +* Main function +* +* This function is the main entry of the streaming transmission. +* It does the following: +* Waits for the dma system to be initialized by the rx code. +* Initializes GPIO +* Starts the tick +* Loops through the following code: +* Submit a transfer +* Wait for the transfer to finish +* Flush TX buffer +* Waits for the rx to finish +* Stops the tick +* +* @param None +* +* @return +* - XST_SUCCESS if example finishes successfully +* - XST_FAILURE if example fails. +* +* @note None. +* +******************************************************************************/ +int main(void) +{ + int numTicks = NUM_TICKS; + int Status; + int Tick; + u8 *TxBufferPtr; + FRESULT Res; // Result of SD Card + u32 num_packets = 0; // The number of packets to send over dma + + TxBufferPtr = (u8 *)TX_BUFFER_BASE ; +#ifdef PRINT_DEBUG + xil_printf("\r\n[TX] --- Entering main() --- \r\n"); +#endif + TCHAR *Path = "0:/"; + + // Register volume work area, initialize device + Res = f_mount(&fatfs, Path, 0); + + if (Res != FR_OK) { + xil_printf("[TX] SD Card mounting failed \r\n"); + return XST_FAILURE; + } + + PacketFile = (char *)PacketFileName; + PacketCountFile = (char *)PacketCountFileName; + + Res = f_open(&PacketCountFileObject, PacketCountFile, FA_READ); + if (Res) { + xil_printf("[TX] PacketCountFile open failed \r\n"); + return XST_FAILURE; + } + + Res = f_open(&PacketFileObject, PacketFile, FA_READ); + if (Res) { + xil_printf("[TX] PacketFile open failed \r\n"); + return XST_FAILURE; + } + + Res = f_lseek(&PacketCountFileObject, 0); + if (Res) { + xil_printf("[TX] SD Card f_lseek failed on PacketCountFileObject \r\n"); + return XST_FAILURE; + } + + // Pointer to beginning of file . + Res = f_lseek(&PacketFileObject, 0); + if (Res) { + xil_printf("[TX] SD Card f_lseek failed on PacketFileObject \r\n"); + return XST_FAILURE; + } + + /* Wait for synchronization signal */ + while (COMM_VAL != 1) { + /* NOP */ + } + /* Send response */ + COMM_VAL = 0; + + /* Setup GPIO */ + XGpioPs_Config *ConfigPtrGpio; + ConfigPtrGpio = XGpioPs_LookupConfig(0); + XGpioPs_CfgInitialize(&pins, ConfigPtrGpio, ConfigPtrGpio -> BaseAddr); + XGpioPs_SetDirectionPin(&pins, EMIO_BASE, 1); + XGpioPs_SetOutputEnablePin(&pins, EMIO_BASE, 1); + /* GPIO en is active low */ + XGpioPs_WritePin(&pins, EMIO_BASE, 0x0); + + /* FIXME: Deal with error flag */ + Error = 0; + + // Need to do this long before "XAxiDma_SimpleTransfer". Not sure why. + num_packets = SetupInputs(TxBufferPtr, &PacketCountFileObject, &PacketFileObject, PacketCounts, Packets); + Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN); + + /* Initialize flags before start transfer test */ + TxDone = 0; + TickOccurred = 0; + + /* Send synchronization signal*/ + COMM_VAL = 1; + /* Wait for response */ + while(COMM_VAL != 0) { + /* NOP */ + } + + /* Start tick */ + XGpioPs_WritePin(&pins, EMIO_BASE, 0x1); + + /* Send and receive data */ + for(Tick = 0; Tick < numTicks; Tick ++) { + + Status = XAxiDma_SimpleTransfer((XAxiDma *) AXI_PTR,(UINTPTR) TxBufferPtr, + num_packets*4, XAXIDMA_DMA_TO_DEVICE); + + if (Status != XST_SUCCESS) { + xil_printf("[TX] Failed sending dma. Tick: %d\r\n", Tick); + return XST_FAILURE; + } + + /* + * Wait TX done and RX done + */ + while (!TxDone && !Error) { + /* NOP */ + } + + /* Flush TX cache */ + Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN); + + TxDone = 0; + + if (Error) { + xil_printf("[TX] Transmission failed\r\n"); + goto Done; + } + + if (Tick < numTicks - 1) { + num_packets = SetupInputs(TxBufferPtr, &PacketCountFileObject, &PacketFileObject, PacketCounts, Packets); + } + + Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN); + + /* Wait for tick */ + while(!TickOccurred) { + /* NOP */ + } + TickOccurred = 0; + } + + /* Wait for synchronization signal */ + while (COMM_VAL != 1) { + /* NOP */ + } + /* Send response */ + COMM_VAL = 0; + + /* Turn off tick */ + XGpioPs_WritePin(&pins, EMIO_BASE, 0x0); + +Done: +#ifdef PRINT_DEBUG + xil_printf("[TX] --- Exiting main() --- \r\n"); +#endif + return XST_SUCCESS; +} + +u32 SetupInputs(u8* base_addr, FIL* packet_count_ptr, FIL* packet_file_ptr, u8* packet_counts, u8* packets) { + FRESULT Res = f_read(packet_count_ptr, (void*)packet_counts, 4, + NULL); + if (Res) { + xil_printf("[TX] PacketCountFileObject read failed \r\n"); + return 0; + } + u32 first_byte = packet_counts[0]; + u32 second_byte = packet_counts[1]; + u32 third_byte = packet_counts[2]; + u32 fourth_byte = packet_counts[3]; + u32 value = fourth_byte << 24 | third_byte << 16 | second_byte << 8 | first_byte; + // Read data from file + Res = f_read(packet_file_ptr, (void*)packets, value*4, + NULL); + if (Res) { + xil_printf("[TX] PacketFileObject read failed \r\n"); + return 0; + } + for(int i = 0; i < value * 4; i++) { + base_addr[i] = packets[i]; + } + return value; +} diff --git a/hardware/IP/AXI-StreamPacketBuffer/.gitignore b/hardware/IP/AXI-StreamPacketBuffer/.gitignore new file mode 100644 index 0000000..3a16653 --- /dev/null +++ b/hardware/IP/AXI-StreamPacketBuffer/.gitignore @@ -0,0 +1 @@ +vivado_project/* diff --git a/hardware/IP/AXI-StreamPacketBuffer/AXI-StreamPacketBuffer.tcl b/hardware/IP/AXI-StreamPacketBuffer/AXI-StreamPacketBuffer.tcl new file mode 100644 index 0000000..61b06b4 --- /dev/null +++ b/hardware/IP/AXI-StreamPacketBuffer/AXI-StreamPacketBuffer.tcl @@ -0,0 +1,424 @@ +#***************************************************************************************** +# Vivado (TM) v2018.2 (64-bit) +# +# AXI-StreamPacketBuffer.tcl: Tcl script for re-creating project 'AXI-StreamPacketBuffer' +# +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir [file dirname [info script]] + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "AXI-StreamPacketBuffer" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "AXI-StreamPacketBuffer.tcl" + +# Help information for this script +proc help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/vivado_project"]" + +# Create project +create_project ${_xil_proj_name_} $origin_dir/vivado_project -part xczu9eg-ffvb1156-2-e -quiet -force + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Reconstruct message rules +# None + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "xilinx.com:zcu102:part0:3.2" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "zcu102" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.uses_pr" -value "1" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/src/design/AXI-StreamPacketBuffer_M00_AXIS.v"] \ + [file normalize "${origin_dir}/src/design/DoubleBuffer.v"] \ + [file normalize "${origin_dir}/src/design/AXI-StreamPacketBuffer.v"] \ + [file normalize "${origin_dir}/component.xml"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/component.xml" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "IP-XACT" -objects $file_obj + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "AXIStreamPacketBuffer" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Empty (no sources present) + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +set files [list \ + [file normalize "${origin_dir}/src/testbench/AXI-StreamPacketBuffer_tb.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "AXIStreamPacketBuffer_tb" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2018" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2018" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +# Change current directory to project folder +cd [file dirname [info script]] + +puts "INFO: Project created:${_xil_proj_name_}" diff --git a/hardware/IP/AXI-StreamPacketBuffer/component.xml b/hardware/IP/AXI-StreamPacketBuffer/component.xml new file mode 100644 index 0000000..3cf02d2 --- /dev/null +++ b/hardware/IP/AXI-StreamPacketBuffer/component.xml @@ -0,0 +1,555 @@ + + + rcl.arizona.edu + RANC + AXIStreamPacketBuffer + 1.0 + + + m00_axis + + + + + + + TDATA + + + m00_axis_tdata + + + + + TSTRB + + + m00_axis_tstrb + + + + + TLAST + + + m00_axis_tlast + + + + + TVALID + + + m00_axis_tvalid + + + + + TREADY + + + m00_axis_tready + + + + + + m00_axis_aresetn + + + + + + + RST + + + m00_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + rst + + + + + + + RST + + + rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m00_axis + + + ASSOCIATED_RESET + rst + + + + + m00_axis_aclk + + + + + + + CLK + + + m00_axis_aclk + + + + + + ASSOCIATED_RESET + m00_axis_aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + AXIStreamPacketBuffer + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + b3d4f1ab + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + AXIStreamPacketBuffer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b3d4f1ab + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + AXIStreamPacketBuffer_tb + + xilinx_testbench_view_fileset + + + + viewChecksum + 8431ccf6 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 115019df + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tick + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + packet + + in + + 29 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + packet_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + buffer_overflow_error + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + buffer_to_stream_error + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tstrb + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tlast + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + PACKET_WIDTH + Packet Width + 30 + + + MAX_NUM_PACKETS + Max Num Packets + 200 + + + C_M00_AXIS_TDATA_WIDTH + C M00 Axis Tdata Width + 32 + + + C_M00_AXIS_START_COUNT + C M00 Axis Start Count + 32 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ./src/design/AXI-StreamPacketBuffer_M00_AXIS.v + verilogSource + + + ./src/design/DoubleBuffer.v + verilogSource + + + ./src/design/AXI-StreamPacketBuffer.v + verilogSource + CHECKSUM_e9422156 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ./src/design/AXI-StreamPacketBuffer_M00_AXIS.v + verilogSource + + + ./src/design/DoubleBuffer.v + verilogSource + + + ./src/design/AXI-StreamPacketBuffer.v + verilogSource + + + + xilinx_testbench_view_fileset + + ./src/testbench/AXI-StreamPacketBuffer_tb.v + verilogSource + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + + xilinx_xpgui_view_fileset + + xgui/AXIStreamPacketBuffer_v1_0.tcl + tclSource + CHECKSUM_115019df + XGUI_VERSION_2 + + + + AXIStreamPacketBuffer_v1_0 + + + PACKET_WIDTH + Packet Width + 30 + + + MAX_NUM_PACKETS + Max Num Packets + 200 + + + C_M00_AXIS_TDATA_WIDTH + C M00 Axis Tdata Width + 32 + + + C_M00_AXIS_START_COUNT + C M00 Axis Start Count + 32 + + + Component_Name + AXIStreamPacketBuffer_v1_0 + + + + + + artix7 + zynq + qzynq + azynq + zynquplus + + + /RANC + /UserIP + + AXIStreamPacketBuffer_v1_0 + package_project + University of Arizona Reconfigurable Computing Lab + http://www2.engr.arizona.edu/~rcl/ + 2 + 2019-05-22T21:29:01Z + + c:/users/rubenpurdy/developer/ranc/emulation/ip/axi-streampacketbuffer + c:/users/rubenpurdy/developer/ranc/emulation/ip/axi-streampacketbuffer + c:/users/rubenpurdy/developer/ranc/emulation/ip/axi-streampacketbuffer + + + + 2018.2 + + + + + + + + diff --git a/hardware/IP/AXI-StreamPacketBuffer/src/design/AXI-StreamPacketBuffer.v b/hardware/IP/AXI-StreamPacketBuffer/src/design/AXI-StreamPacketBuffer.v new file mode 100644 index 0000000..2445a24 --- /dev/null +++ b/hardware/IP/AXI-StreamPacketBuffer/src/design/AXI-StreamPacketBuffer.v @@ -0,0 +1,89 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// AXI-StreamPacketBuffer.v +// +// Created for Dr. Akoglu's Reconfigurable Computing Lab +// at the University of Arizona +// +// Converts packets into an AXI-Stream. +////////////////////////////////////////////////////////////////////////////////// + + +module AXIStreamPacketBuffer #( + parameter PACKET_WIDTH = 30, + parameter MAX_NUM_PACKETS = 200, + // Parameters of Axi Master Bus Interface M00_AXIS + parameter integer C_M00_AXIS_TDATA_WIDTH = 32, + parameter integer C_M00_AXIS_START_COUNT = 32 +)( + input clk, + input rst, + input tick, + input [PACKET_WIDTH-1:0] packet, + input packet_valid, + output buffer_overflow_error, + output buffer_to_stream_error, + // Ports of Axi Master Bus Interface M00_AXIS + input wire m00_axis_aclk, + input wire m00_axis_aresetn, + output wire m00_axis_tvalid, + output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata, + output wire [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb, + output wire m00_axis_tlast, + input wire m00_axis_tready +); + + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + wire [clogb2(MAX_NUM_PACKETS)-1:0] read_addr; + wire [C_M00_AXIS_TDATA_WIDTH-1:0] buffer_out; + wire [clogb2(MAX_NUM_PACKETS)-1:0] num_packets; + wire read_en; + wire [C_M00_AXIS_TDATA_WIDTH-1:0] padded_packet; + + localparam AXIS_PACKET_WIDTH_DIFFERENCE = C_M00_AXIS_TDATA_WIDTH - PACKET_WIDTH; + wire [AXIS_PACKET_WIDTH_DIFFERENCE-1:0] padding = {AXIS_PACKET_WIDTH_DIFFERENCE{1'b0}}; + + assign padded_packet = {padding, packet}; + + DoubleBuffer #( + .BUFFER_DEPTH(MAX_NUM_PACKETS), + .DATA_WIDTH(C_M00_AXIS_TDATA_WIDTH) + ) DoubleBuffer_inst ( + .clk(clk), + .rst(rst), + .tick(tick), + .din_valid(packet_valid), + .din(padded_packet), + .read_addr(read_addr), + .dout(buffer_out), + .num_packets(num_packets), + .read_en(read_en), + .buffer_overflow_error(buffer_overflow_error) + ); + + AXIStreamPacketBuffer_M00_AXIS #( + .MAX_STREAM_DEPTH(MAX_NUM_PACKETS), + .C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH), + .C_M_START_COUNT(C_M00_AXIS_START_COUNT) + ) AXIStreamPacketBuffer_M00_AXIS_inst ( + .read_en(read_en), + .data(buffer_out), + .num_packets(num_packets), + .read_addr(read_addr), + .buffer_to_stream_error(buffer_to_stream_error), + .M_AXIS_ACLK(m00_axis_aclk), + .M_AXIS_ARESETN(m00_axis_aresetn), + .M_AXIS_TVALID(m00_axis_tvalid), + .M_AXIS_TDATA(m00_axis_tdata), + .M_AXIS_TSTRB(m00_axis_tstrb), + .M_AXIS_TLAST(m00_axis_tlast), + .M_AXIS_TREADY(m00_axis_tready) + ); + +endmodule diff --git a/hardware/IP/AXI-StreamPacketBuffer/src/design/AXI-StreamPacketBuffer_M00_AXIS.v b/hardware/IP/AXI-StreamPacketBuffer/src/design/AXI-StreamPacketBuffer_M00_AXIS.v new file mode 100644 index 0000000..c522389 --- /dev/null +++ b/hardware/IP/AXI-StreamPacketBuffer/src/design/AXI-StreamPacketBuffer_M00_AXIS.v @@ -0,0 +1,245 @@ + +`timescale 1 ns / 1 ps + + module AXIStreamPacketBuffer_M00_AXIS # + ( + // Users to add parameters here + parameter integer MAX_STREAM_DEPTH = 32, + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + parameter integer C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter integer C_M_START_COUNT = 32 + ) + ( + // Users to add ports here + input wire read_en, + input wire [C_M_AXIS_TDATA_WIDTH-1:0] data, + input wire [clogb2(MAX_STREAM_DEPTH)-1:0] num_packets, + output wire [clogb2(MAX_STREAM_DEPTH)-1:0] read_addr, + output reg buffer_to_stream_error, + // User ports ends + // Do not modify the ports beyond this line + + // Global ports + input wire M_AXIS_ACLK, + // + input wire M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + output wire M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + output wire M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY + ); + // Total number of output data +// localparam NUMBER_OF_OUTPUT_WORDS = STREAM_DEPTH; + + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // WAIT_COUNT_BITS is the width of the wait counter. + localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1); + + // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO. + localparam bit_num = clogb2(MAX_STREAM_DEPTH); + + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + localparam [1:0] IDLE = 2'b00, // This is the initial/idle state + + INIT_COUNTER = 2'b01, // This state initializes the counter, once + // the counter reaches C_M_START_COUNT count, + // the state machine changes state to SEND_STREAM + SEND_STREAM = 2'b10; // In this state the + // stream data is output through M_AXIS_TDATA + // State variable + reg [1:0] mst_exec_state; + // Example design FIFO read pointer + reg [bit_num-1:0] read_pointer; + + // AXI Stream internal signals + //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer. + reg [WAIT_COUNT_BITS-1 : 0] count; + //streaming data valid + wire axis_tvalid; + //streaming data valid delayed by one clock cycle + reg axis_tvalid_delay; + //Last of the streaming data + wire axis_tlast; + //Last of the streaming data delayed by one clock cycle + reg axis_tlast_delay; + //FIFO implementation signals + reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out; + wire tx_en; + //The master has issued all the streaming data stored in FIFO + reg tx_done; + + + // I/O Connections assignments + + assign M_AXIS_TVALID = axis_tvalid_delay; + assign M_AXIS_TDATA = stream_data_out; + assign M_AXIS_TLAST = axis_tlast_delay; + assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}}; + assign read_addr = read_pointer; + + + // Control state machine implementation + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + count <= 0; + buffer_to_stream_error <= 0; + end + else + case (mst_exec_state) + IDLE: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( read_en == 1 ) + begin + mst_exec_state <= INIT_COUNTER; + end + //else + // begin + // mst_exec_state <= IDLE; + // end + + INIT_COUNTER: begin + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( count == C_M_START_COUNT - 1 ) + begin + mst_exec_state <= SEND_STREAM; + count <= 0; + end + else + begin + count <= count + 1; + mst_exec_state <= INIT_COUNTER; + end + // If read_en is high in this state, the tick has occured while packets will still being read + if ( read_en == 1 ) + buffer_to_stream_error <= 1; + + end + SEND_STREAM: begin + // The example design streaming master functionality starts + // when the master drives output tdata from the FIFO and the slave + // has finished storing the S_AXIS_TDATA + if (tx_done) + begin + mst_exec_state <= IDLE; + end + else + begin + mst_exec_state <= SEND_STREAM; + end + // If read_en is high in this state, the tick has occured while packets will still being read + if ( read_en == 1 ) + buffer_to_stream_error <= 1; + end + endcase + end + + + //tvalid generation + //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and + //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS. + assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < num_packets)); + + // AXI tlast generation + // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1 + // (0 to NUMBER_OF_OUTPUT_WORDS-1) + assign axis_tlast = (read_pointer == num_packets-1); + + + // Delay the axis_tvalid and axis_tlast signal by one clock cycle + // to match the latency of M_AXIS_TDATA + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + begin + axis_tvalid_delay <= 1'b0; + axis_tlast_delay <= 1'b0; + end + else + begin + axis_tvalid_delay <= axis_tvalid; + axis_tlast_delay <= axis_tlast; + end + end + + + //read_pointer pointer + + always@(posedge M_AXIS_ACLK) + begin + if(!M_AXIS_ARESETN) + begin + read_pointer <= 0; + tx_done <= 1'b0; + end + else + if (mst_exec_state == IDLE) begin + tx_done <= 1'b0; + read_pointer <= 0; + end + else if (read_pointer + 1 <= num_packets) + begin + if (tx_en) + // read pointer is incremented after every read from the FIFO + // when FIFO read signal is enabled. + begin + read_pointer <= read_pointer + 1; + tx_done <= 1'b0; + end + end + else if (read_pointer == num_packets) + begin + // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data + // has been out. + tx_done <= 1'b1; + end + end + + + //FIFO read enable generation + + assign tx_en = M_AXIS_TREADY && axis_tvalid; + + // Streaming output data is read from FIFO + always @( posedge M_AXIS_ACLK ) + begin + if(!M_AXIS_ARESETN) + begin + stream_data_out <= 0; + end + else if (tx_en)// && M_AXIS_TSTRB[byte_index] + begin + stream_data_out <= data; + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/hardware/IP/AXI-StreamPacketBuffer/src/design/DoubleBuffer.v b/hardware/IP/AXI-StreamPacketBuffer/src/design/DoubleBuffer.v new file mode 100644 index 0000000..9f7d3af --- /dev/null +++ b/hardware/IP/AXI-StreamPacketBuffer/src/design/DoubleBuffer.v @@ -0,0 +1,82 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// DoubleBuffer.v +// +// Created for Dr. Akoglu's Reconfigurable Computing Lab +// at the University of Arizona +// +// Buffers output packets to be sent of AXIS. +////////////////////////////////////////////////////////////////////////////////// + + +module DoubleBuffer #( + parameter BUFFER_DEPTH = 32, + parameter DATA_WIDTH = 32 +)( + input clk, + input rst, + input tick, + input din_valid, + input [DATA_WIDTH-1:0] din, + input [clogb2(BUFFER_DEPTH)-1:0] read_addr, + output [DATA_WIDTH-1:0] dout, + output reg [clogb2(BUFFER_DEPTH)-1:0] num_packets, + output reg read_en, + output reg buffer_overflow_error +); + + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + reg curr_buffer; + reg [clogb2(BUFFER_DEPTH):0] write_addr; + reg [DATA_WIDTH-1:0] buffer_0 [0:BUFFER_DEPTH-1]; + reg [DATA_WIDTH-1:0] buffer_1 [0:BUFFER_DEPTH-1]; + + integer i; + + // Read from whichever buffer is not currently being written to + assign dout = curr_buffer ? buffer_0[read_addr] : buffer_1[read_addr]; + + initial begin + read_en <= 0; + curr_buffer <= 0; + write_addr <= 0; + num_packets <= 0; + buffer_overflow_error <= 0; + end + + always@(posedge clk) begin + if (rst) begin + read_en <= 0; + curr_buffer <= 0; + write_addr <= 0; + num_packets <= 0; + buffer_overflow_error <= 0; + end + else if (tick) begin + read_en = 1; + curr_buffer = ~curr_buffer; + num_packets = write_addr; + write_addr = 0; + end + else begin + read_en <= 0; + if (din_valid) begin + if (curr_buffer == 0) + buffer_0[write_addr] = din; + else + buffer_1[write_addr] = din; + write_addr = write_addr + 1; + // If write_addr looped around, we filled up the buffer and will get an error + if (write_addr == 0) + buffer_overflow_error = 1; + end + end + end + +endmodule diff --git a/hardware/IP/AXI-StreamPacketBuffer/src/testbench/AXI-StreamPacketBuffer_tb.v b/hardware/IP/AXI-StreamPacketBuffer/src/testbench/AXI-StreamPacketBuffer_tb.v new file mode 100644 index 0000000..de44508 --- /dev/null +++ b/hardware/IP/AXI-StreamPacketBuffer/src/testbench/AXI-StreamPacketBuffer_tb.v @@ -0,0 +1,150 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// AXI-StreamPacketBuffer.v +// +// Created for Dr. Akoglu's Reconfigurable Computing Lab +// at the University of Arizona +// +// A test bench for the AXIStreamPacketBuffer +////////////////////////////////////////////////////////////////////////////////// + + +module AXIStreamPacketBuffer_tb(); + + parameter CLOCK_PERIOD_NS_tb = 20; + + parameter PACKET_WIDTH_tb = 30; + parameter AXIS_WIDTH_tb = 32; + parameter MAX_NUM_PACKETS_tb = 200; + // Parameters of Axi Master Bus Interface M00_AXIS + parameter integer C_M00_AXIS_TDATA_WIDTH_tb = 32; + parameter integer C_M00_AXIS_START_COUNT_tb = 32; + + reg clk_tb, rst_tb, tick_tb; + reg [PACKET_WIDTH_tb-1:0] packet_tb; + reg packet_valid_tb; + wire buffer_overflow_error_tb, buffer_to_stream_error_tb; + // Ports of Axi Master Bus Interface M00_AXIS + reg m00_axis_aclk_tb, m00_axis_aresetn_tb; + wire m00_axis_tvalid_tb; + wire [C_M00_AXIS_TDATA_WIDTH_tb-1 : 0] m00_axis_tdata_tb; + wire [(C_M00_AXIS_TDATA_WIDTH_tb/8)-1 : 0] m00_axis_tstrb_tb; + wire m00_axis_tlast_tb; + reg m00_axis_tready_tb; + + AXIStreamPacketBuffer #( + .PACKET_WIDTH(PACKET_WIDTH_tb), + .AXIS_WIDTH(AXIS_WIDTH_tb), + .MAX_NUM_PACKETS(MAX_NUM_PACKETS_tb), + .C_M00_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH_tb), + .C_M00_AXIS_START_COUNT(C_M00_AXIS_START_COUNT_tb) + ) AXIStreamPacketBuffer_tb ( + .clk(clk_tb), + .rst(rst_tb), + .tick(tick_tb), + .packet(packet_tb), + .packet_valid(packet_valid_tb), + .buffer_overflow_error(buffer_overflow_error_tb), + .buffer_to_stream_error(buffer_to_stream_error_tb), + // Ports of Axi Master Bus Interface M00_AXIS + .m00_axis_aclk(m00_axis_aclk_tb), + .m00_axis_aresetn(m00_axis_aresetn_tb), + .m00_axis_tvalid(m00_axis_tvalid_tb), + .m00_axis_tdata(m00_axis_tdata_tb), + .m00_axis_tstrb(m00_axis_tstrb_tb), + .m00_axis_tlast(m00_axis_tlast_tb), + .m00_axis_tready(m00_axis_tready_tb) + ); + + integer i; + + always begin + clk_tb <= ~clk_tb; + m00_axis_aclk_tb <= ~m00_axis_aclk_tb; + #(CLOCK_PERIOD_NS_tb / 2); + end + + initial begin + // Initialize everything + clk_tb <= 0; + rst_tb <= 1; + tick_tb <= 0; + packet_tb <= 0; + packet_valid_tb <= 0; + m00_axis_aclk_tb <= 0; + m00_axis_aresetn_tb <= 0; + m00_axis_tready_tb <= 1; + for (i = 0; i < 10; i = i + 1) begin + @(posedge clk_tb); + end + @(posedge clk_tb) #2; + // End resets + rst_tb <= 0; + m00_axis_aresetn_tb <= 1; + // Send in packets from 1 to 10 + @(posedge clk_tb) #2 + packet_valid_tb <= 1; + for (i = 1; i < 11; i = i + 1) begin + packet_tb <= i; + @(posedge clk_tb) #2; + end + packet_valid_tb <= 0; + // Cycle tick + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + // Send in packets from 11 to 21 + @(posedge clk_tb) #2 + packet_valid_tb <= 1; + for (i = 11; i < 22; i = i + 1) begin + packet_tb <= i; + @(posedge clk_tb) #2; + end + packet_valid_tb <= 0; + // Wait for AXIS + wait(m00_axis_tlast_tb); + @(posedge clk_tb); + @(posedge clk_tb); + // Cycle tick + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + // Send in packets from 22 to 32 + @(posedge clk_tb) #2 + packet_valid_tb <= 1; + for (i = 22; i < 33; i = i + 1) begin + packet_tb <= i; + @(posedge clk_tb) #2; + end + packet_valid_tb <= 0; + // Wait for AXIS + wait(m00_axis_tlast_tb); + @(posedge clk_tb); + @(posedge clk_tb); + // Cycle tick + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + // Send in packets from 33 to 43 + @(posedge clk_tb) #2 + packet_valid_tb <= 1; + for (i = 33; i < 44; i = i + 1) begin + packet_tb <= i; + @(posedge clk_tb) #2; + end + packet_valid_tb <= 0; + // Wait for AXIS + wait(m00_axis_tlast_tb); + @(posedge clk_tb); + @(posedge clk_tb); + // Cycle tick + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + end + +endmodule diff --git a/hardware/IP/AXI-StreamPacketBuffer/xgui/AXIStreamPacketBuffer_v1_0.tcl b/hardware/IP/AXI-StreamPacketBuffer/xgui/AXIStreamPacketBuffer_v1_0.tcl new file mode 100644 index 0000000..bc0fde7 --- /dev/null +++ b/hardware/IP/AXI-StreamPacketBuffer/xgui/AXIStreamPacketBuffer_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_M00_AXIS_START_COUNT" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXIS_TDATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "MAX_NUM_PACKETS" -parent ${Page_0} + ipgui::add_param $IPINST -name "PACKET_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_M00_AXIS_START_COUNT { PARAM_VALUE.C_M00_AXIS_START_COUNT } { + # Procedure called to update C_M00_AXIS_START_COUNT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXIS_START_COUNT { PARAM_VALUE.C_M00_AXIS_START_COUNT } { + # Procedure called to validate C_M00_AXIS_START_COUNT + return true +} + +proc update_PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH } { + # Procedure called to update C_M00_AXIS_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH } { + # Procedure called to validate C_M00_AXIS_TDATA_WIDTH + return true +} + +proc update_PARAM_VALUE.MAX_NUM_PACKETS { PARAM_VALUE.MAX_NUM_PACKETS } { + # Procedure called to update MAX_NUM_PACKETS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MAX_NUM_PACKETS { PARAM_VALUE.MAX_NUM_PACKETS } { + # Procedure called to validate MAX_NUM_PACKETS + return true +} + +proc update_PARAM_VALUE.PACKET_WIDTH { PARAM_VALUE.PACKET_WIDTH } { + # Procedure called to update PACKET_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PACKET_WIDTH { PARAM_VALUE.PACKET_WIDTH } { + # Procedure called to validate PACKET_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.PACKET_WIDTH { MODELPARAM_VALUE.PACKET_WIDTH PARAM_VALUE.PACKET_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PACKET_WIDTH}] ${MODELPARAM_VALUE.PACKET_WIDTH} +} + +proc update_MODELPARAM_VALUE.MAX_NUM_PACKETS { MODELPARAM_VALUE.MAX_NUM_PACKETS PARAM_VALUE.MAX_NUM_PACKETS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MAX_NUM_PACKETS}] ${MODELPARAM_VALUE.MAX_NUM_PACKETS} +} + +proc update_MODELPARAM_VALUE.C_M00_AXIS_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_TDATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXIS_START_COUNT { MODELPARAM_VALUE.C_M00_AXIS_START_COUNT PARAM_VALUE.C_M00_AXIS_START_COUNT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_START_COUNT}] ${MODELPARAM_VALUE.C_M00_AXIS_START_COUNT} +} + diff --git a/hardware/IP/InputRouter/component.xml b/hardware/IP/InputRouter/component.xml new file mode 100644 index 0000000..87f4add --- /dev/null +++ b/hardware/IP/InputRouter/component.xml @@ -0,0 +1,319 @@ + + + arizona.edu + user + InputRouter + 1.0 + + + rst + + + + + + + RST + + + rst + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + rst + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + InputRouter + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + df63bbba + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + InputRouter + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + df63bbba + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 8e1d11d7 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + add57609 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + buffer_full + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + captured + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + out_spike + + out + + 29 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + out_valid + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + FILENAME + Filename + ir_file.mem + + + NUM_PACKETS + Num Packets + 256 + + + bitwidth + Bitwidth + 8 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../../../../../Users/rubenpurdy/Developer/RANC/InputRouter/src/sources/InputRouter.v + verilogSource + CHECKSUM_df63bbba + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../../../../Users/rubenpurdy/Developer/RANC/InputRouter/src/sources/InputRouter.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/InputRouter_v1_0.tcl + tclSource + CHECKSUM_8e1d11d7 + XGUI_VERSION_2 + + + + xilinx_utilityxitfiles_view_fileset + + gui/InputRouter_v1_0.gtcl + GTCL + + + + InputRouter + + + FILENAME + Input File Path + ir_file.mem + + + NUM_PACKETS + Num Packets + 256 + + + bitwidth + Bitwidth + 8 + + + + false + + + + + + Component_Name + InputRouter_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + kintexuplus + kintexu + + + /RANC + /UserIP + + Input Router + package_project + 2 + 2018-11-05T05:42:15Z + + c:/users/rubenpurdy/developer/ranc/inputrouter + + + + 2018.2 + + + + + + + + diff --git a/hardware/IP/InputRouter/gui/InputRouter_v1_0.gtcl b/hardware/IP/InputRouter/gui/InputRouter_v1_0.gtcl new file mode 100644 index 0000000..a15ab58 --- /dev/null +++ b/hardware/IP/InputRouter/gui/InputRouter_v1_0.gtcl @@ -0,0 +1,2 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_bitwidth_VALUE {NUM_PACKETS } {expr $NUM_PACKETS} diff --git a/hardware/IP/InputRouter/src/sources/InputRouter.v b/hardware/IP/InputRouter/src/sources/InputRouter.v new file mode 100644 index 0000000..bae79aa --- /dev/null +++ b/hardware/IP/InputRouter/src/sources/InputRouter.v @@ -0,0 +1,65 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/21/2018 10:34:19 AM +// Design Name: +// Module Name: InputRouter +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module InputRouter( + input clk, + input rst, + input buffer_full, + input captured, + output reg [29:0] out_spike, + output reg out_valid +); + parameter FILENAME = "ir_file.mem"; + parameter NUM_PACKETS = 256; + parameter bitwidth = $clog2(NUM_PACKETS); + + reg [29:0] input_mem [bitwidth-1:0]; + reg [bitwidth-1:0] counter; + + initial begin + counter <= 0; + $readmemb(FILENAME, input_mem); + out_spike <= 30'd0; + end + + always@(negedge clk) begin + if (rst) begin + counter <= 0; + out_spike <= 30'd0; + out_valid <= 0; + end + else begin + if (!buffer_full) begin + if (captured) + out_valid <= 0; + + out_spike <= input_mem[counter]; + out_valid <= 1; + + if (counter != (NUM_PACKETS)) + counter <= counter + 1; + + else + out_valid <= 0; + end + end + end +endmodule diff --git a/hardware/IP/InputRouter/xgui/InputRouter_v1_0.tcl b/hardware/IP/InputRouter/xgui/InputRouter_v1_0.tcl new file mode 100644 index 0000000..441bdb4 --- /dev/null +++ b/hardware/IP/InputRouter/xgui/InputRouter_v1_0.tcl @@ -0,0 +1,64 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/InputRouter_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set FILENAME [ipgui::add_param $IPINST -name "FILENAME" -parent ${Page_0}] + set_property tooltip {Path to input file} ${FILENAME} + ipgui::add_param $IPINST -name "NUM_PACKETS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.bitwidth { PARAM_VALUE.bitwidth PARAM_VALUE.NUM_PACKETS } { + # Procedure called to update bitwidth when any of the dependent parameters in the arguments change + + set bitwidth ${PARAM_VALUE.bitwidth} + set NUM_PACKETS ${PARAM_VALUE.NUM_PACKETS} + set values(NUM_PACKETS) [get_property value $NUM_PACKETS] + set_property value [gen_USERPARAMETER_bitwidth_VALUE $values(NUM_PACKETS)] $bitwidth +} + +proc validate_PARAM_VALUE.bitwidth { PARAM_VALUE.bitwidth } { + # Procedure called to validate bitwidth + return true +} + +proc update_PARAM_VALUE.FILENAME { PARAM_VALUE.FILENAME } { + # Procedure called to update FILENAME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FILENAME { PARAM_VALUE.FILENAME } { + # Procedure called to validate FILENAME + return true +} + +proc update_PARAM_VALUE.NUM_PACKETS { PARAM_VALUE.NUM_PACKETS } { + # Procedure called to update NUM_PACKETS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_PACKETS { PARAM_VALUE.NUM_PACKETS } { + # Procedure called to validate NUM_PACKETS + return true +} + + +proc update_MODELPARAM_VALUE.FILENAME { MODELPARAM_VALUE.FILENAME PARAM_VALUE.FILENAME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FILENAME}] ${MODELPARAM_VALUE.FILENAME} +} + +proc update_MODELPARAM_VALUE.NUM_PACKETS { MODELPARAM_VALUE.NUM_PACKETS PARAM_VALUE.NUM_PACKETS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_PACKETS}] ${MODELPARAM_VALUE.NUM_PACKETS} +} + +proc update_MODELPARAM_VALUE.bitwidth { MODELPARAM_VALUE.bitwidth PARAM_VALUE.bitwidth } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.bitwidth}] ${MODELPARAM_VALUE.bitwidth} +} + diff --git a/hardware/IP/OutcomeCore/component.xml b/hardware/IP/OutcomeCore/component.xml new file mode 100644 index 0000000..30702d3 --- /dev/null +++ b/hardware/IP/OutcomeCore/component.xml @@ -0,0 +1,611 @@ + + + arizona.edu + user + OutcomeCore + 1.0 + + + m00_axis + + + + + + + TDATA + + + m00_axis_tdata + + + + + TSTRB + + + m00_axis_tstrb + + + + + TLAST + + + m00_axis_tlast + + + + + TVALID + + + m00_axis_tvalid + + + + + TREADY + + + m00_axis_tready + + + + + + m00_axis_aresetn + + + + + + + RST + + + m00_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + rst + + + + + + + RST + + + rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + rst + + + + + m00_axis_aclk + + + + + + + CLK + + + m00_axis_aclk + + + + + + ASSOCIATED_RESET + m00_axis_aresetn + + + ASSOCIATED_BUSIF + m00_axis + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + OutcomeCore + + xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + fe821628 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + OutcomeCore + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + fe821628 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3ed11fca + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tick + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + packet + + in + + 29 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + packet_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + packet_captured + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + fifo_full + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + outcome_error + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_aclk + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_aresetn + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tvalid + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tdata + + out + + 31 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tstrb + + out + + 3 + 0 + + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tlast + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m00_axis_tready + + in + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + + PACKET_WIDTH + Packet Width + 30 + + + NUM_CLASSES + Num Classes + 10 + + + FIFO_DEPTH + Fifo Depth + 16 + + + STREAM_DEPTH + Stream Depth + 8 + + + C_M00_AXIS_TDATA_WIDTH + C M00 Axis Tdata Width + 32 + + + C_M00_AXIS_START_COUNT + C M00 Axis Start Count + 32 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/sources/FIFO.v + verilogSource + + + src/sources/OutcomeCoreProcessor.v + verilogSource + + + src/sources/OutcomeCore_M00_AXIS.v + verilogSource + + + src/sources/OutcomeCore.v + verilogSource + CHECKSUM_a9266ed3 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/sources/FIFO.v + verilogSource + + + src/sources/OutcomeCoreProcessor.v + verilogSource + + + src/sources/OutcomeCore_M00_AXIS.v + verilogSource + + + src/sources/OutcomeCore.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/OutcomeCore_v1_0.tcl + tclSource + CHECKSUM_8a972436 + XGUI_VERSION_2 + + + + OutcomeCore_v1_0 + + + PACKET_WIDTH + Packet Width + 30 + + + NUM_CLASSES + Num Classes + 10 + + + FIFO_DEPTH + Fifo Depth + 16 + + + STREAM_DEPTH + Stream Depth + 8 + + + C_M00_AXIS_TDATA_WIDTH + C M00 Axis Tdata Width + 32 + + + C_M00_AXIS_START_COUNT + C M00 Axis Start Count + 32 + + + Component_Name + OutcomeCore_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + kintexuplus + kintexu + + + /UserIP + + OutcomeCore_v1_0 + package_project + 9 + 2019-02-12T00:42:22Z + + /home/edwardrichter/RCL/RANC/outcomecore + + + + 2018.2.1 + + + + + + + + diff --git a/hardware/IP/OutcomeCore/src/simulation/OutcomeCore_tb.v b/hardware/IP/OutcomeCore/src/simulation/OutcomeCore_tb.v new file mode 100644 index 0000000..884189d --- /dev/null +++ b/hardware/IP/OutcomeCore/src/simulation/OutcomeCore_tb.v @@ -0,0 +1,363 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/09/2019 09:26:34 AM +// Design Name: +// Module Name: OutcomeCore_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module OutcomeCore_tb(); + + parameter CLOCK_PERIOD_NS_tb = 20; + + parameter PACKET_WIDTH_tb = 30; + parameter CLASS_WIDTH_tb = 8; + parameter NUM_CLASSES_tb = 10; + parameter FIFO_DEPTH_tb = 16; + parameter STREAM_DEPTH_tb = 8; + parameter C_M00_AXIS_TDATA_WIDTH_tb = 32; + parameter C_M00_AXIS_START_COUNT_tb = 32; + + reg clk_tb, rst_tb, tick_tb; + wire [PACKET_WIDTH_tb-1:0] packet_tb; + reg packet_valid_tb; + + wire packet_captured_tb; + + reg m00_axis_aresetn_tb; + wire m00_axis_tvalid_tb; + wire [C_M00_AXIS_TDATA_WIDTH_tb-1:0] m00_axis_tdata_tb; + wire [(C_M00_AXIS_TDATA_WIDTH_tb/8)-1:0] m00_axis_tstrb_tb; + wire m00_axis_tlast_tb; + reg m00_axis_tready_tb; + + OutcomeCore #( + .PACKET_WIDTH(PACKET_WIDTH_tb), + .CLASS_WIDTH(CLASS_WIDTH_tb), + .NUM_CLASSES(NUM_CLASSES_tb), + .FIFO_DEPTH(FIFO_DEPTH_tb), + .STREAM_DEPTH(STREAM_DEPTH_tb), + // Parameters of Axi Master Bus Interface M00_AXIS + .C_M00_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH_tb), + .C_M00_AXIS_START_COUNT(C_M00_AXIS_START_COUNT_tb) + ) OtcomeCore_tb ( + // Inputs: + .clk(clk_tb), + .rst(rst_tb), + .tick(tick_tb), + .packet(packet_tb), + .packet_valid(packet_valid_tb), + + .packet_captured(packet_captured_tb), + + // Ports of Axi Master Bus Interface M00_AXIS + .m00_axis_aclk(clk_tb), + .m00_axis_aresetn(m00_axis_aresetn_tb), + .m00_axis_tvalid(m00_axis_tvalid_tb), + .m00_axis_tdata(m00_axis_tdata_tb), + .m00_axis_tstrb(m00_axis_tstrb_tb), + .m00_axis_tlast(m00_axis_tlast_tb), + .m00_axis_tready(m00_axis_tready_tb) + ); + + integer counter_tb = 0; + integer num_ticks_tb = 0; + + always begin + clk_tb = ~clk_tb; + #(CLOCK_PERIOD_NS_tb / 2); + end + + integer i; + + /*Packet Organization (30 bits): + [ dx ] [ dy ] [ destination axon index ] [ delivery tick ] + [ 9 bits ] [ 9 bits ] [ 8 bits ] [ 4 bits ]*/ + reg [8:0] dx_tb, dy_tb; + reg [7:0] dest_axon_index_tb; + reg [3:0] delivery_tick_tb; + + assign packet_tb = {dx_tb, dy_tb, dest_axon_index_tb, delivery_tick_tb}; + + initial begin + dx_tb = 9'd0; + dy_tb = 9'd0; + dest_axon_index_tb = 8'd0; + delivery_tick_tb = 4'd0; + clk_tb <= 0; + rst_tb <= 1; + tick_tb <= 0; + packet_valid_tb <= 0; + m00_axis_aresetn_tb <= 0; + m00_axis_tready_tb <= 0; + @(posedge clk_tb); + @(posedge clk_tb); + @(posedge clk_tb) #2; + rst_tb <= 0; + m00_axis_aresetn_tb <= 1; + m00_axis_tready_tb <= 1; + + // Send a 1 + @(posedge clk_tb) #2; + dest_axon_index_tb = 1; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 2; + @(posedge clk_tb) #2; + dest_axon_index_tb = 1; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 2 + @(posedge clk_tb) #2; + dest_axon_index_tb = 2; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 2; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + // Send a 3 + @(posedge clk_tb) #2; + dest_axon_index_tb = 3; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 3; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 4 + @(posedge clk_tb) #2; + dest_axon_index_tb = 4; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 4; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 5 + @(posedge clk_tb) #2; + dest_axon_index_tb = 5; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 5; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 6 + @(posedge clk_tb) #2; + dest_axon_index_tb = 6; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 6; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 7 + @(posedge clk_tb) #2; + dest_axon_index_tb = 7; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 7; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 8 + @(posedge clk_tb) #2; + dest_axon_index_tb = 8; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 8; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 9 + @(posedge clk_tb) #2; + dest_axon_index_tb = 9; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 9; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 1 + @(posedge clk_tb) #2; + dest_axon_index_tb = 1; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 1; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 2 + @(posedge clk_tb) #2; + dest_axon_index_tb = 2; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 2; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + // Send a 3 + @(posedge clk_tb) #2; + dest_axon_index_tb = 3; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 3; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 4 + @(posedge clk_tb) #2; + dest_axon_index_tb = 4; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 4; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 5 + @(posedge clk_tb) #2; + dest_axon_index_tb = 5; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 5; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 6 + @(posedge clk_tb) #2; + dest_axon_index_tb = 6; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 6; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + // Send a 7 + @(posedge clk_tb) #2; + dest_axon_index_tb = 7; + packet_valid_tb <= 1; + @(posedge clk_tb) #2; + dest_axon_index_tb = 7; + @(posedge clk_tb) #2; + packet_valid_tb <= 0; + @(posedge clk_tb); + tick_tb <= 1; + @(posedge clk_tb); + tick_tb <= 0; + for (i = 0; i < NUM_CLASSES_tb*2; i = i + 1) begin + @(posedge clk_tb); + end + end + +endmodule diff --git a/hardware/IP/OutcomeCore/src/sources/FIFO.v b/hardware/IP/OutcomeCore/src/sources/FIFO.v new file mode 100644 index 0000000..a84d37f --- /dev/null +++ b/hardware/IP/OutcomeCore/src/sources/FIFO.v @@ -0,0 +1,84 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// FIFO.v +// +// Created for Dr. Akoglu's Reconfigurable Computing Lab +// at the University of Arizona +// +// Stores classificaiton values so that they can be read out in batches as streams. +////////////////////////////////////////////////////////////////////////////////// + + +module FIFO #( + parameter AXIS_DEPTH = 32, + parameter DATA_WIDTH = 32, + parameter DEPTH = 512 +)( + input clk, + input rst, + input din_valid, + input [$clog2(AXIS_DEPTH):0] addr, + input [DATA_WIDTH-1:0] din, + output [DATA_WIDTH-1:0] dout, + output reg ready, + output reg fifo_full +); + + reg [$clog2(DEPTH):0] write_addr; + reg [$clog2(DEPTH):0] counter; + reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1]; + reg [$clog2(DEPTH):0] addr_offset; + reg ready_asserted; + + assign dout = fifo[addr + addr_offset - AXIS_DEPTH]; + + initial begin + write_addr <= 0; + ready <= 0; + addr_offset <= 0; + counter <= AXIS_DEPTH; + ready_asserted <= 1; + fifo_full <= 0; + end + + always@(posedge clk) begin + if (rst) begin + write_addr <= 0; + ready <= 0; + addr_offset <= 0; + ready_asserted <= 1; + counter <= AXIS_DEPTH; + fifo_full <= 0; + end + else if (write_addr == DEPTH) begin + // Send last batch if applicable + if (ready_asserted) begin + ready <= 0; + fifo_full <= 1; + end + else begin + ready_asserted <= 1; + end + end + else begin + if (din_valid) begin + fifo[write_addr] = din; + write_addr = write_addr + 1; + if (write_addr != 0 && write_addr == counter) begin + ready <= 1; + ready_asserted <= 0; + counter <= counter + AXIS_DEPTH; + addr_offset = addr_offset + AXIS_DEPTH; + end + end + // Assert ready an extra clock cycle so that AXIS can see it. + else if (ready_asserted) begin + ready <= 0; + end + else begin + ready_asserted <= 1; + end + end + end + +endmodule diff --git a/hardware/IP/OutcomeCore/src/sources/OutcomeCore.v b/hardware/IP/OutcomeCore/src/sources/OutcomeCore.v new file mode 100644 index 0000000..c1a1dc4 --- /dev/null +++ b/hardware/IP/OutcomeCore/src/sources/OutcomeCore.v @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// OutcomeCoreProcessor.v +// +// Created for Dr. Akoglu's Reconfigurable Computing Lab +// at the University of Arizona +// +// Decodes spikes out of a RANC network assuming a classification based +// network and an alternating population output coding. +////////////////////////////////////////////////////////////////////////////////// + +module OutcomeCore #( + parameter integer PACKET_WIDTH = 30, + parameter integer NUM_CLASSES = 10, + parameter integer FIFO_DEPTH = 16, + parameter integer STREAM_DEPTH = 8, + // Parameters of Axi Master Bus Interface M00_AXIS + parameter integer C_M00_AXIS_TDATA_WIDTH = 32, + parameter integer C_M00_AXIS_START_COUNT = 32 +)( + // Inputs: + input clk, + input rst, + input tick, + input [PACKET_WIDTH-1:0] packet, + input packet_valid, + + output packet_captured, + output fifo_full, + output [1:0] outcome_error, + + // Ports of Axi Master Bus Interface M00_AXIS + input wire m00_axis_aclk, + input wire m00_axis_aresetn, + output wire m00_axis_tvalid, + output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata, + output wire [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb, + output wire m00_axis_tlast, + input wire m00_axis_tready +); + + wire [C_M00_AXIS_TDATA_WIDTH-1:0] outcome; + wire [C_M00_AXIS_TDATA_WIDTH-1:0] fifo_out; + wire outcome_valid; + wire fifo_ready; + wire [$clog2(STREAM_DEPTH):0] read_addr; + + OutcomeCoreProcessor #( + .PACKET_WIDTH(PACKET_WIDTH), + .NUM_CLASSES(NUM_CLASSES), + .OUTCOME_WIDTH(C_M00_AXIS_TDATA_WIDTH) + ) OutcomeCoreProcessor_inst ( + .clk(clk), + .rst(rst), + .tick(tick), + .packet(packet), + .packet_valid(packet_valid), + .packet_captured(packet_captured), + .winner(outcome), + .valid(outcome_valid), + .outcome_error(outcome_error) + ); + + FIFO #( + .AXIS_DEPTH(STREAM_DEPTH), + .DATA_WIDTH(C_M00_AXIS_TDATA_WIDTH), + .DEPTH(FIFO_DEPTH) + ) FIFO_inst ( + .clk(clk), + .rst(rst), + .din_valid(outcome_valid), + .addr(read_addr), + .din(outcome), + .dout(fifo_out), + .ready(fifo_ready), + .fifo_full(fifo_full) + ); + + OutcomeCore_M00_AXIS #( + .STREAM_DEPTH(STREAM_DEPTH), + .C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH), + .C_M_START_COUNT(C_M00_AXIS_START_COUNT) + ) OutcomeCore_M00_AXIS_inst ( + .fifo_ready(fifo_ready), + .data(fifo_out), + .read_addr(read_addr), + .M_AXIS_ACLK(m00_axis_aclk), + .M_AXIS_ARESETN(m00_axis_aresetn), + .M_AXIS_TVALID(m00_axis_tvalid), + .M_AXIS_TDATA(m00_axis_tdata), + .M_AXIS_TSTRB(m00_axis_tstrb), + .M_AXIS_TLAST(m00_axis_tlast), + .M_AXIS_TREADY(m00_axis_tready) + ); + +endmodule diff --git a/hardware/IP/OutcomeCore/src/sources/OutcomeCoreProcessor.v b/hardware/IP/OutcomeCore/src/sources/OutcomeCoreProcessor.v new file mode 100644 index 0000000..f7bc9d5 --- /dev/null +++ b/hardware/IP/OutcomeCore/src/sources/OutcomeCoreProcessor.v @@ -0,0 +1,162 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// OutcomeCoreProcessor.v +// +// Created for Dr. Akoglu's Reconfigurable Computing Lab +// at the University of Arizona +// +// Decodes spikes out of a RANC network assuming a classification based +// network and an alternating population output coding. +////////////////////////////////////////////////////////////////////////////////// + + +module OutcomeCoreProcessor #( + parameter integer PACKET_WIDTH = 30, + parameter integer NUM_CLASSES = 10, + parameter integer OUTCOME_WIDTH = 32 +)( + // Inputs: + input clk, + input rst, + input tick, + input [PACKET_WIDTH-1:0] packet, + input packet_valid, + + output packet_captured, + output reg [OUTCOME_WIDTH-1:0] winner, + output reg valid, + // If the tick is raised before the outcome core was done resetting + // 01 => tick occured during RESET + // 10 => tick occured during TRANSFER_BUFFER + // 11 => tick occured during COUNT_PACKETS + output reg [1:0] outcome_error +); + + reg [$clog2(NUM_CLASSES)-1:0] curr_class; + reg [OUTCOME_WIDTH-1:0] class [NUM_CLASSES-1:0]; + reg [$clog2(NUM_CLASSES)-1:0] curr_max; + reg [OUTCOME_WIDTH-1:0] curr_max_val; + // Buffer to collect packets while class accumulator is being reset + reg [OUTCOME_WIDTH-1:0] class_buffer [NUM_CLASSES-1:0]; + + // FIXME: Why is this a thing? + assign packet_captured = packet_valid ? 1'b1 : 1'b0; + + // State machine + localparam [1:0] RESET = 2'b00, // Resets all class counts + TRANSFER_BUFFER = 2'b01, // Transfers data from buffer to class + IDLE = 2'b10, // Waits for tick + COUNT_PACKETS = 2'b11; // Counts packets recieved for each class + + reg [1:0] mst_exec_state; + + initial begin + winner <= 0; + curr_class <= 0; + curr_max_val <= 0; + curr_max <= 0; + mst_exec_state <= RESET; + end + + // Main state machine + always@(negedge clk) begin + if (rst) begin + winner <= 0; + curr_class <= 0; + curr_max <= 0; + curr_max_val <= 0; + outcome_error <= 0; + mst_exec_state <= RESET; + end + else begin + case (mst_exec_state) + RESET: begin + valid <= 0; + winner <= 0; + // A tick occurred during the resetting of the outcome core + if (tick) + outcome_error <= 2'b01; + // Buffer packets while resetting + if (packet_valid) begin + if (class_buffer[packet[11:4]] > 0) + class_buffer[packet[11:4]] <= class_buffer[packet[11:4]] + 1; + else + class_buffer[packet[11:4]] <= 1; + end + // Reset + if (curr_class < NUM_CLASSES) begin + class[curr_class] = 0; + curr_class = curr_class + 1; + end + // Reset done, go to idle + else begin + curr_class <= 0; + mst_exec_state <= TRANSFER_BUFFER; + end + end + TRANSFER_BUFFER: begin + valid <= 0; + winner <= 0; + // A tick occured while transferring buffer + if (tick) + outcome_error <= 2'b10; + // This logic assumes that we'll be in TRANSFER_BUFFER for at least NUM_CLASSES worth of clock cycles. + // Transfer packets from buffer + if (curr_class < NUM_CLASSES) begin + if (class_buffer[curr_class] > 0) + class[curr_class] = class[curr_class] + class_buffer[curr_class]; + class_buffer[curr_class] = 0; + curr_class = curr_class + 1; + end + // Packets transfered, go to idle + else begin + curr_class <= 0; + mst_exec_state <= IDLE; + end + // Watch for packets + if (packet_valid) begin + class[packet[11:4]] = class[packet[11:4]] + 1; + end + end + IDLE: begin + // If tick, begin counting classes + if (tick) begin + mst_exec_state <= COUNT_PACKETS; + end + // Otherwise, keep track of packets + else if (packet_valid) begin + class[packet[11:4]] <= class[packet[11:4]] + 1; + end + end + COUNT_PACKETS: begin + // A tick occured while counting packets + if (tick) + outcome_error <= 2'b11; + // Buffer packets while determining winner + if (packet_valid) begin + class_buffer[packet[11:4]] <= class_buffer[packet[11:4]] + 1; + end + // Determine winner + if (curr_class < NUM_CLASSES) begin + if (curr_max_val < class[curr_class]) begin + curr_max = curr_class; + curr_max_val = class[curr_class]; + end + class[curr_class] = 0; + curr_class = curr_class + 1; + end + // Winner found, go to reset + else begin + winner = curr_max; + curr_max = 0; + curr_max_val <= 0; + valid <= 1; + curr_class <= 0; + mst_exec_state <= TRANSFER_BUFFER; + end + end + endcase + end + end + +endmodule diff --git a/hardware/IP/OutcomeCore/src/sources/OutcomeCore_M00_AXIS.v b/hardware/IP/OutcomeCore/src/sources/OutcomeCore_M00_AXIS.v new file mode 100644 index 0000000..79ea6b4 --- /dev/null +++ b/hardware/IP/OutcomeCore/src/sources/OutcomeCore_M00_AXIS.v @@ -0,0 +1,242 @@ + +`timescale 1 ns / 1 ps + + module OutcomeCore_M00_AXIS # + ( + // Users to add parameters here + parameter integer STREAM_DEPTH = 32, + // User parameters ends + // Do not modify the parameters beyond this line + + // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + parameter integer C_M_AXIS_TDATA_WIDTH = 32, + // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction. + parameter integer C_M_START_COUNT = 32 + ) + ( + // Users to add ports here + input wire fifo_ready, + input wire [C_M_AXIS_TDATA_WIDTH-1:0] data, + output wire [clogb2(STREAM_DEPTH)-1:0] read_addr, + // User ports ends + // Do not modify the ports beyond this line + + // Global ports + input wire M_AXIS_ACLK, + // + input wire M_AXIS_ARESETN, + // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. + output wire M_AXIS_TVALID, + // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master. + output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA, + // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. + output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB, + // TLAST indicates the boundary of a packet. + output wire M_AXIS_TLAST, + // TREADY indicates that the slave can accept a transfer in the current cycle. + input wire M_AXIS_TREADY + ); + // Total number of output data + localparam NUMBER_OF_OUTPUT_WORDS = STREAM_DEPTH; + + function integer clogb2 (input integer bit_depth); + begin + for(clogb2=0; bit_depth>0; clogb2=clogb2+1) + bit_depth = bit_depth >> 1; + end + endfunction + + // WAIT_COUNT_BITS is the width of the wait counter. + localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1); + + // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO. + localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS); + + // Define the states of state machine + // The control state machine oversees the writing of input streaming data to the FIFO, + // and outputs the streaming data from the FIFO + localparam [1:0] IDLE = 2'b00, // This is the initial/idle state + + INIT_COUNTER = 2'b01, // This state initializes the counter, once + // the counter reaches C_M_START_COUNT count, + // the state machine changes state to SEND_STREAM + SEND_STREAM = 2'b10; // In this state the + // stream data is output through M_AXIS_TDATA + // State variable + reg [1:0] mst_exec_state; + // Example design FIFO read pointer + reg [bit_num-1:0] read_pointer; + + // AXI Stream internal signals + //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer. + reg [WAIT_COUNT_BITS-1 : 0] count; + //streaming data valid + wire axis_tvalid; + //streaming data valid delayed by one clock cycle + reg axis_tvalid_delay; + //Last of the streaming data + wire axis_tlast; + //Last of the streaming data delayed by one clock cycle + reg axis_tlast_delay; + //FIFO implementation signals + reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out; + wire tx_en; + //The master has issued all the streaming data stored in FIFO + reg tx_done; + // Indicates whether to clear the read pointer + reg clear_read_pointer; + + + // I/O Connections assignments + + assign M_AXIS_TVALID = axis_tvalid_delay; + assign M_AXIS_TDATA = stream_data_out; + assign M_AXIS_TLAST = axis_tlast_delay; + assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}}; + assign read_addr = read_pointer; + + + // Control state machine implementation + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + // Synchronous reset (active low) + begin + mst_exec_state <= IDLE; + count <= 0; + end + else + case (mst_exec_state) + IDLE: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( fifo_ready == 1 ) + begin + mst_exec_state <= INIT_COUNTER; + end + //else + // begin + // mst_exec_state <= IDLE; + // end + + INIT_COUNTER: + // The slave starts accepting tdata when + // there tvalid is asserted to mark the + // presence of valid streaming data + if ( count == C_M_START_COUNT - 1 ) + begin + mst_exec_state <= SEND_STREAM; + count <= 0; + end + else + begin + count <= count + 1; + mst_exec_state <= INIT_COUNTER; + end + + SEND_STREAM: + // The example design streaming master functionality starts + // when the master drives output tdata from the FIFO and the slave + // has finished storing the S_AXIS_TDATA + if (tx_done) + begin + mst_exec_state <= IDLE; + end + else + begin + mst_exec_state <= SEND_STREAM; + end + endcase + end + + + //tvalid generation + //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and + //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS. + assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS)); + + // AXI tlast generation + // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1 + // (0 to NUMBER_OF_OUTPUT_WORDS-1) + assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1); + + + // Delay the axis_tvalid and axis_tlast signal by one clock cycle + // to match the latency of M_AXIS_TDATA + always @(posedge M_AXIS_ACLK) + begin + if (!M_AXIS_ARESETN) + begin + axis_tvalid_delay <= 1'b0; + axis_tlast_delay <= 1'b0; + end + else + begin + axis_tvalid_delay <= axis_tvalid; + axis_tlast_delay <= axis_tlast; + end + end + + + //read_pointer pointer + + always@(posedge M_AXIS_ACLK) + begin + if(!M_AXIS_ARESETN) + begin + read_pointer <= 0; + tx_done <= 1'b0; + clear_read_pointer <= 0; + end + else + if (mst_exec_state == IDLE) + tx_done <= 1'b0; + else if (mst_exec_state == SEND_STREAM && tx_done) + clear_read_pointer <= 1; + // Delay clearing of read pointer + else if (clear_read_pointer) begin + clear_read_pointer <= 0; + read_pointer <= 0; + end + else if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1) + begin + if (tx_en) + // read pointer is incremented after every read from the FIFO + // when FIFO read signal is enabled. + begin + read_pointer <= read_pointer + 1; + tx_done <= 1'b0; + end + end + else if (read_pointer == NUMBER_OF_OUTPUT_WORDS) + begin + // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data + // has been out. + tx_done <= 1'b1; + end + end + + + //FIFO read enable generation + + assign tx_en = M_AXIS_TREADY && axis_tvalid; + + // Streaming output data is read from FIFO + always @( posedge M_AXIS_ACLK ) + begin + if(!M_AXIS_ARESETN) + begin + stream_data_out <= 0; + end + else if (tx_en)// && M_AXIS_TSTRB[byte_index] + begin + stream_data_out <= data; + end + end + + // Add user logic here + + // User logic ends + + endmodule diff --git a/hardware/IP/OutcomeCore/xgui/OutcomeCore_v1_0.tcl b/hardware/IP/OutcomeCore/xgui/OutcomeCore_v1_0.tcl new file mode 100644 index 0000000..7708170 --- /dev/null +++ b/hardware/IP/OutcomeCore/xgui/OutcomeCore_v1_0.tcl @@ -0,0 +1,100 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_M00_AXIS_START_COUNT" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_M00_AXIS_TDATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "FIFO_DEPTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_CLASSES" -parent ${Page_0} + ipgui::add_param $IPINST -name "PACKET_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "STREAM_DEPTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_M00_AXIS_START_COUNT { PARAM_VALUE.C_M00_AXIS_START_COUNT } { + # Procedure called to update C_M00_AXIS_START_COUNT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXIS_START_COUNT { PARAM_VALUE.C_M00_AXIS_START_COUNT } { + # Procedure called to validate C_M00_AXIS_START_COUNT + return true +} + +proc update_PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH } { + # Procedure called to update C_M00_AXIS_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH } { + # Procedure called to validate C_M00_AXIS_TDATA_WIDTH + return true +} + +proc update_PARAM_VALUE.FIFO_DEPTH { PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to update FIFO_DEPTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FIFO_DEPTH { PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to validate FIFO_DEPTH + return true +} + +proc update_PARAM_VALUE.NUM_CLASSES { PARAM_VALUE.NUM_CLASSES } { + # Procedure called to update NUM_CLASSES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_CLASSES { PARAM_VALUE.NUM_CLASSES } { + # Procedure called to validate NUM_CLASSES + return true +} + +proc update_PARAM_VALUE.PACKET_WIDTH { PARAM_VALUE.PACKET_WIDTH } { + # Procedure called to update PACKET_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PACKET_WIDTH { PARAM_VALUE.PACKET_WIDTH } { + # Procedure called to validate PACKET_WIDTH + return true +} + +proc update_PARAM_VALUE.STREAM_DEPTH { PARAM_VALUE.STREAM_DEPTH } { + # Procedure called to update STREAM_DEPTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.STREAM_DEPTH { PARAM_VALUE.STREAM_DEPTH } { + # Procedure called to validate STREAM_DEPTH + return true +} + + +proc update_MODELPARAM_VALUE.PACKET_WIDTH { MODELPARAM_VALUE.PACKET_WIDTH PARAM_VALUE.PACKET_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PACKET_WIDTH}] ${MODELPARAM_VALUE.PACKET_WIDTH} +} + +proc update_MODELPARAM_VALUE.NUM_CLASSES { MODELPARAM_VALUE.NUM_CLASSES PARAM_VALUE.NUM_CLASSES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_CLASSES}] ${MODELPARAM_VALUE.NUM_CLASSES} +} + +proc update_MODELPARAM_VALUE.FIFO_DEPTH { MODELPARAM_VALUE.FIFO_DEPTH PARAM_VALUE.FIFO_DEPTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FIFO_DEPTH}] ${MODELPARAM_VALUE.FIFO_DEPTH} +} + +proc update_MODELPARAM_VALUE.STREAM_DEPTH { MODELPARAM_VALUE.STREAM_DEPTH PARAM_VALUE.STREAM_DEPTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.STREAM_DEPTH}] ${MODELPARAM_VALUE.STREAM_DEPTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXIS_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_TDATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_M00_AXIS_START_COUNT { MODELPARAM_VALUE.C_M00_AXIS_START_COUNT PARAM_VALUE.C_M00_AXIS_START_COUNT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_START_COUNT}] ${MODELPARAM_VALUE.C_M00_AXIS_START_COUNT} +} + diff --git a/hardware/Makefile b/hardware/IP/RANCNetwork/Makefile similarity index 100% rename from hardware/Makefile rename to hardware/IP/RANCNetwork/Makefile diff --git a/hardware/README.md b/hardware/IP/RANCNetwork/README.md similarity index 100% rename from hardware/README.md rename to hardware/IP/RANCNetwork/README.md diff --git a/hardware/component.xml b/hardware/IP/RANCNetwork/component.xml similarity index 100% rename from hardware/component.xml rename to hardware/IP/RANCNetwork/component.xml diff --git a/hardware/rancnetwork.tcl b/hardware/IP/RANCNetwork/rancnetwork.tcl similarity index 100% rename from hardware/rancnetwork.tcl rename to hardware/IP/RANCNetwork/rancnetwork.tcl diff --git a/hardware/src/simulations/.gitignore b/hardware/IP/RANCNetwork/src/simulations/.gitignore similarity index 100% rename from hardware/src/simulations/.gitignore rename to hardware/IP/RANCNetwork/src/simulations/.gitignore diff --git a/hardware/src/simulations/__init__.py b/hardware/IP/RANCNetwork/src/simulations/__init__.py similarity index 100% rename from hardware/src/simulations/__init__.py rename to hardware/IP/RANCNetwork/src/simulations/__init__.py diff --git a/hardware/src/simulations/iverilog/Makefile b/hardware/IP/RANCNetwork/src/simulations/iverilog/Makefile similarity index 100% rename from hardware/src/simulations/iverilog/Makefile rename to hardware/IP/RANCNetwork/src/simulations/iverilog/Makefile diff --git a/hardware/src/simulations/iverilog/myhdl.c b/hardware/IP/RANCNetwork/src/simulations/iverilog/myhdl.c similarity index 100% rename from hardware/src/simulations/iverilog/myhdl.c rename to hardware/IP/RANCNetwork/src/simulations/iverilog/myhdl.c diff --git a/hardware/src/simulations/iverilog/myhdl_20030518.c b/hardware/IP/RANCNetwork/src/simulations/iverilog/myhdl_20030518.c similarity index 100% rename from hardware/src/simulations/iverilog/myhdl_20030518.c rename to hardware/IP/RANCNetwork/src/simulations/iverilog/myhdl_20030518.c diff --git a/hardware/src/simulations/iverilog/myhdl_table.c b/hardware/IP/RANCNetwork/src/simulations/iverilog/myhdl_table.c similarity index 100% rename from hardware/src/simulations/iverilog/myhdl_table.c rename to hardware/IP/RANCNetwork/src/simulations/iverilog/myhdl_table.c diff --git a/hardware/src/simulations/memory_files/tea/128/csram_000.mem b/hardware/IP/RANCNetwork/src/simulations/memory_files/tea/128/csram_000.mem similarity index 100% rename from hardware/src/simulations/memory_files/tea/128/csram_000.mem rename to hardware/IP/RANCNetwork/src/simulations/memory_files/tea/128/csram_000.mem diff --git a/hardware/src/simulations/memory_files/tea/128/csram_001.mem b/hardware/IP/RANCNetwork/src/simulations/memory_files/tea/128/csram_001.mem similarity index 100% rename from hardware/src/simulations/memory_files/tea/128/csram_001.mem rename to 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b/hardware/IP/RANCNetwork/src/simulations/tests/test_NeuronBlock.py similarity index 100% rename from hardware/src/simulations/tests/test_NeuronBlock.py rename to hardware/IP/RANCNetwork/src/simulations/tests/test_NeuronBlock.py diff --git a/hardware/src/simulations/tests/test_NeuronBlock.v b/hardware/IP/RANCNetwork/src/simulations/tests/test_NeuronBlock.v similarity index 100% rename from hardware/src/simulations/tests/test_NeuronBlock.v rename to hardware/IP/RANCNetwork/src/simulations/tests/test_NeuronBlock.v diff --git a/hardware/src/simulations/tests/test_RANCNetwork.py b/hardware/IP/RANCNetwork/src/simulations/tests/test_RANCNetwork.py similarity index 100% rename from hardware/src/simulations/tests/test_RANCNetwork.py rename to hardware/IP/RANCNetwork/src/simulations/tests/test_RANCNetwork.py diff --git a/hardware/src/simulations/tests/test_RANCNetwork.v b/hardware/IP/RANCNetwork/src/simulations/tests/test_RANCNetwork.v similarity index 100% rename from hardware/src/simulations/tests/test_RANCNetwork.v rename to hardware/IP/RANCNetwork/src/simulations/tests/test_RANCNetwork.v diff --git a/hardware/src/simulations/tests/test_TokenController.py b/hardware/IP/RANCNetwork/src/simulations/tests/test_TokenController.py similarity index 100% rename from hardware/src/simulations/tests/test_TokenController.py rename to hardware/IP/RANCNetwork/src/simulations/tests/test_TokenController.py diff --git a/hardware/src/simulations/tests/test_TokenController.v b/hardware/IP/RANCNetwork/src/simulations/tests/test_TokenController.v similarity index 100% rename from hardware/src/simulations/tests/test_TokenController.v rename to hardware/IP/RANCNetwork/src/simulations/tests/test_TokenController.v diff --git a/hardware/src/simulations/tests/test_buffer.py b/hardware/IP/RANCNetwork/src/simulations/tests/test_buffer.py similarity index 100% rename from hardware/src/simulations/tests/test_buffer.py rename to hardware/IP/RANCNetwork/src/simulations/tests/test_buffer.py diff --git a/hardware/src/simulations/tests/test_buffer.v b/hardware/IP/RANCNetwork/src/simulations/tests/test_buffer.v similarity index 100% rename from hardware/src/simulations/tests/test_buffer.v rename to hardware/IP/RANCNetwork/src/simulations/tests/test_buffer.v diff --git a/hardware/src/sources/Adder.v b/hardware/IP/RANCNetwork/src/sources/Adder.v similarity index 100% rename from hardware/src/sources/Adder.v rename to hardware/IP/RANCNetwork/src/sources/Adder.v diff --git a/hardware/src/sources/Buffer.v b/hardware/IP/RANCNetwork/src/sources/Buffer.v similarity index 100% rename from hardware/src/sources/Buffer.v rename to hardware/IP/RANCNetwork/src/sources/Buffer.v diff --git a/hardware/src/sources/CSRAM.v b/hardware/IP/RANCNetwork/src/sources/CSRAM.v similarity index 100% rename from hardware/src/sources/CSRAM.v rename to hardware/IP/RANCNetwork/src/sources/CSRAM.v diff --git a/hardware/src/sources/Comp.v b/hardware/IP/RANCNetwork/src/sources/Comp.v similarity index 100% rename from hardware/src/sources/Comp.v rename to hardware/IP/RANCNetwork/src/sources/Comp.v diff --git a/hardware/src/sources/Core.v b/hardware/IP/RANCNetwork/src/sources/Core.v similarity index 100% rename from hardware/src/sources/Core.v rename to hardware/IP/RANCNetwork/src/sources/Core.v diff --git a/hardware/src/sources/Counter.v b/hardware/IP/RANCNetwork/src/sources/Counter.v similarity index 100% rename from hardware/src/sources/Counter.v rename to hardware/IP/RANCNetwork/src/sources/Counter.v diff --git a/hardware/src/sources/EnReg.v b/hardware/IP/RANCNetwork/src/sources/EnReg.v similarity index 100% rename from hardware/src/sources/EnReg.v rename to hardware/IP/RANCNetwork/src/sources/EnReg.v diff --git a/hardware/src/sources/ForwardEastWest.v b/hardware/IP/RANCNetwork/src/sources/ForwardEastWest.v similarity index 100% rename from hardware/src/sources/ForwardEastWest.v rename to hardware/IP/RANCNetwork/src/sources/ForwardEastWest.v diff --git a/hardware/src/sources/ForwardNorthSouth.v b/hardware/IP/RANCNetwork/src/sources/ForwardNorthSouth.v similarity index 100% rename from hardware/src/sources/ForwardNorthSouth.v rename to hardware/IP/RANCNetwork/src/sources/ForwardNorthSouth.v diff --git a/hardware/src/sources/FromLocal.v b/hardware/IP/RANCNetwork/src/sources/FromLocal.v similarity index 100% rename from hardware/src/sources/FromLocal.v rename to hardware/IP/RANCNetwork/src/sources/FromLocal.v diff --git a/hardware/src/sources/IntegratorUnit.v b/hardware/IP/RANCNetwork/src/sources/IntegratorUnit.v similarity index 100% rename from hardware/src/sources/IntegratorUnit.v rename to hardware/IP/RANCNetwork/src/sources/IntegratorUnit.v diff --git a/hardware/src/sources/LocalIn.v b/hardware/IP/RANCNetwork/src/sources/LocalIn.v similarity index 100% rename from hardware/src/sources/LocalIn.v rename to hardware/IP/RANCNetwork/src/sources/LocalIn.v diff --git a/hardware/src/sources/Merge2.v b/hardware/IP/RANCNetwork/src/sources/Merge2.v similarity index 100% rename from hardware/src/sources/Merge2.v rename to hardware/IP/RANCNetwork/src/sources/Merge2.v diff --git a/hardware/src/sources/Merge3.v b/hardware/IP/RANCNetwork/src/sources/Merge3.v similarity index 100% rename from hardware/src/sources/Merge3.v rename to hardware/IP/RANCNetwork/src/sources/Merge3.v diff --git a/hardware/src/sources/Mux2to1.v b/hardware/IP/RANCNetwork/src/sources/Mux2to1.v similarity index 100% rename from hardware/src/sources/Mux2to1.v rename to hardware/IP/RANCNetwork/src/sources/Mux2to1.v diff --git a/hardware/src/sources/NeuronBlock.v b/hardware/IP/RANCNetwork/src/sources/NeuronBlock.v similarity index 100% rename from hardware/src/sources/NeuronBlock.v rename to hardware/IP/RANCNetwork/src/sources/NeuronBlock.v diff --git a/hardware/src/sources/OutputBus.v b/hardware/IP/RANCNetwork/src/sources/OutputBus.v similarity index 100% rename from hardware/src/sources/OutputBus.v rename to hardware/IP/RANCNetwork/src/sources/OutputBus.v diff --git a/hardware/src/sources/PacketFetch.v b/hardware/IP/RANCNetwork/src/sources/PacketFetch.v similarity index 100% rename from hardware/src/sources/PacketFetch.v rename to hardware/IP/RANCNetwork/src/sources/PacketFetch.v diff --git a/hardware/src/sources/PathDecoder2Way.v b/hardware/IP/RANCNetwork/src/sources/PathDecoder2Way.v similarity index 100% rename from hardware/src/sources/PathDecoder2Way.v rename to hardware/IP/RANCNetwork/src/sources/PathDecoder2Way.v diff --git a/hardware/src/sources/PathDecoder3Way.v b/hardware/IP/RANCNetwork/src/sources/PathDecoder3Way.v similarity index 100% rename from hardware/src/sources/PathDecoder3Way.v rename to hardware/IP/RANCNetwork/src/sources/PathDecoder3Way.v diff --git a/hardware/src/sources/RANCNetwork.v b/hardware/IP/RANCNetwork/src/sources/RANCNetwork.v similarity index 100% rename from hardware/src/sources/RANCNetwork.v rename to hardware/IP/RANCNetwork/src/sources/RANCNetwork.v diff --git a/hardware/src/sources/RANCNetworkGrid.v b/hardware/IP/RANCNetwork/src/sources/RANCNetworkGrid.v similarity index 100% rename from hardware/src/sources/RANCNetworkGrid.v rename to hardware/IP/RANCNetwork/src/sources/RANCNetworkGrid.v diff --git a/hardware/src/sources/RANCNetwork_S00_AXIS.v b/hardware/IP/RANCNetwork/src/sources/RANCNetwork_S00_AXIS.v similarity index 100% rename from hardware/src/sources/RANCNetwork_S00_AXIS.v rename to hardware/IP/RANCNetwork/src/sources/RANCNetwork_S00_AXIS.v diff --git a/hardware/src/sources/Router.v b/hardware/IP/RANCNetwork/src/sources/Router.v similarity index 100% rename from hardware/src/sources/Router.v rename to hardware/IP/RANCNetwork/src/sources/Router.v diff --git a/hardware/src/sources/Scheduler.v b/hardware/IP/RANCNetwork/src/sources/Scheduler.v similarity index 100% rename from hardware/src/sources/Scheduler.v rename to hardware/IP/RANCNetwork/src/sources/Scheduler.v diff --git a/hardware/src/sources/SchedulerSRAM.v b/hardware/IP/RANCNetwork/src/sources/SchedulerSRAM.v similarity index 100% rename from hardware/src/sources/SchedulerSRAM.v rename to hardware/IP/RANCNetwork/src/sources/SchedulerSRAM.v diff --git a/hardware/src/sources/ThresholdResetUnit.v b/hardware/IP/RANCNetwork/src/sources/ThresholdResetUnit.v similarity index 100% rename from hardware/src/sources/ThresholdResetUnit.v rename to hardware/IP/RANCNetwork/src/sources/ThresholdResetUnit.v diff --git a/hardware/src/sources/TokenController.v b/hardware/IP/RANCNetwork/src/sources/TokenController.v similarity index 100% rename from hardware/src/sources/TokenController.v rename to hardware/IP/RANCNetwork/src/sources/TokenController.v diff --git a/hardware/xgui/RANCNetwork_v1_0.tcl b/hardware/IP/RANCNetwork/xgui/RANCNetwork_v1_0.tcl similarity index 100% rename from hardware/xgui/RANCNetwork_v1_0.tcl rename to hardware/IP/RANCNetwork/xgui/RANCNetwork_v1_0.tcl diff --git a/hardware/IP/TickGenerator/.gitignore b/hardware/IP/TickGenerator/.gitignore new file mode 100644 index 0000000..1127409 --- /dev/null +++ b/hardware/IP/TickGenerator/.gitignore @@ -0,0 +1 @@ +vivado_project/* diff --git a/hardware/IP/TickGenerator/TickGenerator.tcl b/hardware/IP/TickGenerator/TickGenerator.tcl new file mode 100644 index 0000000..22764bf --- /dev/null +++ b/hardware/IP/TickGenerator/TickGenerator.tcl @@ -0,0 +1,422 @@ +#***************************************************************************************** +# Vivado (TM) v2018.2 (64-bit) +# +# TickGenerator.tcl: Tcl script for re-creating project 'TickGenerator' +# +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir [file dirname [info script]] + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "TickGenerator" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "TickGenerator.tcl" + +# Help information for this script +proc help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/vivado_project"]" + +# Create project +create_project ${_xil_proj_name_} $origin_dir/vivado_project -part xczu9eg-ffvb1156-2-e -quiet -force + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Reconstruct message rules +# None + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "xilinx.com:zcu102:part0:3.2" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "zcu102" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.uses_pr" -value "1" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/"] [file normalize "$origin_dir/ip"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/src/design/TickGenerator.v"] \ + [file normalize "${origin_dir}/component.xml"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/component.xml" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "IP-XACT" -objects $file_obj + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "TickGenerator" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Empty (no sources present) + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +set files [list \ + [file normalize "${origin_dir}/src/testbench/TickGenerator_tb.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "TickGenerator_tb" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2018" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2018" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +# Change current directory to project folder +cd [file dirname [info script]] + +puts "INFO: Project created:${_xil_proj_name_}" diff --git a/hardware/IP/TickGenerator/component.xml b/hardware/IP/TickGenerator/component.xml new file mode 100644 index 0000000..c5bc505 --- /dev/null +++ b/hardware/IP/TickGenerator/component.xml @@ -0,0 +1,299 @@ + + + rcl.arizona.edu + RANC + TickGenerator + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + intr + + + + + + + INTERRUPT + + + intr + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + TickGenerator + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 262f1205 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + TickGenerator + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 262f1205 + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + TickGenerator_tb + + xilinx_testbench_view_fileset + + + + viewChecksum + 712a7dfa + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 6db10dff + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tick + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + intr + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + INPUT_FREQUENCY + Input Frequency + 100000000 + + + TICK_FREQUENCY + Tick Frequency + 50 + + + ASSERT_INTR_CYCLES + Assert Intr Cycles + 5 + + + + + + choice_list_9ca20931 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + + + xilinx_anylanguagesynthesis_view_fileset + + ./src/design/TickGenerator.v + verilogSource + CHECKSUM_262f1205 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ./src/design/TickGenerator.v + verilogSource + + + + xilinx_testbench_view_fileset + + ./src/testbench/TickGenerator_tb.v + verilogSource + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + + xilinx_xpgui_view_fileset + + xgui/TickGenerator_v1_0.tcl + tclSource + CHECKSUM_6db10dff + XGUI_VERSION_2 + + + + TickGenerator_v1_0 + + + INPUT_FREQUENCY + Input Frequency + 100000000 + + + TICK_FREQUENCY + Tick Frequency + 50 + + + ASSERT_INTR_CYCLES + Assert Intr Cycles + 5 + + + Component_Name + TickGenerator_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + kintexuplus + kintexu + + + /RANC + /UserIP + + TickGenerator_v1_0 + package_project + University of Arizona Reconfigurable Computing Lab + http://www2.engr.arizona.edu/~rcl/ + 2 + 2019-05-22T21:21:23Z + + c:/users/rubenpurdy/developer/ranc/emulation/ip/tickgenerator + c:/users/rubenpurdy/developer/ranc/emulation/ip/tickgenerator + c:/users/rubenpurdy/developer/ranc/emulation/ip/tickgenerator + + + + 2018.2 + + + + + + + + diff --git a/hardware/IP/TickGenerator/src/design/TickGenerator.v b/hardware/IP/TickGenerator/src/design/TickGenerator.v new file mode 100644 index 0000000..bdbd50d --- /dev/null +++ b/hardware/IP/TickGenerator/src/design/TickGenerator.v @@ -0,0 +1,53 @@ +`timescale 1ns / 1ns +////////////////////////////////////////////////////////////////////////////////// +// TickGenerator.v +// +// Created for Dr. Akoglu's Reconfigurable Computing Lab +// at the University of Arizona +// +// Generates a tick signal which goes high on the negative edge of the input clk +// and is high for one clk cycle. +////////////////////////////////////////////////////////////////////////////////// + +module TickGenerator( + input clk, + input en, + output reg tick, + output reg intr +); + + parameter INPUT_FREQUENCY = 100000000; + parameter TICK_FREQUENCY = 50; + parameter ASSERT_INTR_CYCLES = 5; + + // The count that the counter needs to count to. + localparam COUNT = INPUT_FREQUENCY / TICK_FREQUENCY; + + reg [$clog2(COUNT):0] counter; + + initial begin + tick <= 0; + counter <= 0; + end + + always @(negedge clk) begin + if (en) begin + if (counter == COUNT) begin + tick <= 1; + intr <= 1; + counter <= 0; + end + else begin + tick <= 0; + counter <= counter + 1; + if (counter == ASSERT_INTR_CYCLES) + intr <= 0; + end + end + else begin + tick <= 0; + counter <= 0; + end + end + +endmodule diff --git a/hardware/IP/TickGenerator/src/testbench/TickGenerator_tb.v b/hardware/IP/TickGenerator/src/testbench/TickGenerator_tb.v new file mode 100644 index 0000000..3a2950a --- /dev/null +++ b/hardware/IP/TickGenerator/src/testbench/TickGenerator_tb.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/17/2019 11:34:33 PM +// Design Name: +// Module Name: TickGenerator_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module TickGenerator_tb(); + + reg clk; + reg en; + wire tick; + + TickGenerator TickGenerator_inst( + .clk(clk), + .en(en), + .tick(tick), + .result_ready() + ); + + always begin + clk <= ~clk; + #20; + end + + initial begin + clk <= 0; + en <= 1; + end + +endmodule diff --git a/hardware/IP/TickGenerator/xgui/TickGenerator_v1_0.tcl b/hardware/IP/TickGenerator/xgui/TickGenerator_v1_0.tcl new file mode 100644 index 0000000..5aae03c --- /dev/null +++ b/hardware/IP/TickGenerator/xgui/TickGenerator_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ASSERT_INTR_CYCLES" -parent ${Page_0} + ipgui::add_param $IPINST -name "INPUT_FREQUENCY" -parent ${Page_0} + ipgui::add_param $IPINST -name "TICK_FREQUENCY" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ASSERT_INTR_CYCLES { PARAM_VALUE.ASSERT_INTR_CYCLES } { + # Procedure called to update ASSERT_INTR_CYCLES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASSERT_INTR_CYCLES { PARAM_VALUE.ASSERT_INTR_CYCLES } { + # Procedure called to validate ASSERT_INTR_CYCLES + return true +} + +proc update_PARAM_VALUE.INPUT_FREQUENCY { PARAM_VALUE.INPUT_FREQUENCY } { + # Procedure called to update INPUT_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INPUT_FREQUENCY { PARAM_VALUE.INPUT_FREQUENCY } { + # Procedure called to validate INPUT_FREQUENCY + return true +} + +proc update_PARAM_VALUE.TICK_FREQUENCY { PARAM_VALUE.TICK_FREQUENCY } { + # Procedure called to update TICK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TICK_FREQUENCY { PARAM_VALUE.TICK_FREQUENCY } { + # Procedure called to validate TICK_FREQUENCY + return true +} + + +proc update_MODELPARAM_VALUE.INPUT_FREQUENCY { MODELPARAM_VALUE.INPUT_FREQUENCY PARAM_VALUE.INPUT_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INPUT_FREQUENCY}] ${MODELPARAM_VALUE.INPUT_FREQUENCY} +} + +proc update_MODELPARAM_VALUE.TICK_FREQUENCY { MODELPARAM_VALUE.TICK_FREQUENCY PARAM_VALUE.TICK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TICK_FREQUENCY}] ${MODELPARAM_VALUE.TICK_FREQUENCY} +} + +proc update_MODELPARAM_VALUE.ASSERT_INTR_CYCLES { MODELPARAM_VALUE.ASSERT_INTR_CYCLES PARAM_VALUE.ASSERT_INTR_CYCLES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASSERT_INTR_CYCLES}] ${MODELPARAM_VALUE.ASSERT_INTR_CYCLES} +} +