Replies: 2 comments 1 reply
-
Reading isn't implemented because Sizif does not have enough cells inside CPLD to fit all ULA+ registers and instead use SRAM to store em. Reading would make things a much more complex. |
Beta Was this translation helpful? Give feedback.
1 reply
-
Implemented with commit 8e09254 |
Beta Was this translation helpful? Give feedback.
0 replies
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
-
According to the ULA+ specification, port 65339 is read/write. In sizif512 it looks like the port for registers (0-63) is write-only, it can only read from register 64 and only bit0.
I also have Just Speccy 128k with SLAM+128 and it matches the specifications there.
Beta Was this translation helpful? Give feedback.
All reactions