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Issues in modification of the Hazard3 ALU code for addition #29

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Arghyajoy27 opened this issue Dec 23, 2024 · 8 comments
Open

Issues in modification of the Hazard3 ALU code for addition #29

Arghyajoy27 opened this issue Dec 23, 2024 · 8 comments
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@Arghyajoy27
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Hi,

I am quite new to this RISC-V space and trying to understand how the architecture is working. To obtain it, I am attempting to change the ALU addition operation so that it reads op_a + op_b + 5 rather than op_a + op_b. I have tried so many ways to see the effect on the terminal. But it's not displying anything and displaying max cycles reached. Any idea how to modify the existing ALU addition code will be really helpful as the kickstart.

@Wren6991 Wren6991 added the question Further information is requested label Dec 23, 2024
@Wren6991
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What are you trying to achieve? If you just modify the result of all add instructions then any compiled software which relies on the add instruction operating normally will fail to run.

@Arghyajoy27
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Arghyajoy27 commented Dec 24, 2024

Hi @Wren6991 , Thanks for replying back.

Our objective is to modify the ALU such that I can get the effect of the change in the terminal. And that could be anything, like changing the LSB bit of op_a to 0 or the addition operation or any modification inside the ALU code. The reason I am doing this is because of two reasons:

  1. In the future, we may explore the effects of approximate computing on the existing applications to get the performance numbers on the Hazard3 processor.
  2. And along with this, we were trying to build a simulator to predict the performance metrics for any RISC architecture along with its extensions.

@Arghyajoy27
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Any pointers on where to start if I want to change the LSB bit of op_a to 0. Will be really helpful.

@Wren6991
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Our objective is to modify the ALU such that I can get the effect of the change in the terminal

You mean you would like to print from software on the processor to stdout? This requires you to run a substantial amount of compiled code, which is not going to tolerate any deviation between the calculation specified in the ISA manual and the actual ALU result. Addition is not just used for + operators in your program, it's also used for address generation behind the scenes.

If 2 + 3 does not equal 5 then the core is not a RISC-V core.

@Wren6991
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If you would like to add new operations with different results, you should add these as custom instructions so that they can be used alongside the standard instructions required by the compiler. Take a look at the code controlled by the EXTENSION_XH3BEXTM parameter for an example of this.

You mentioned approximate computing, but as the ALU will still have to implement both the precise and approximate versions of the calculation, I don't expect this would improve your energy per instruction.

@Arghyajoy27
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If you would like to add new operations with different results, you should add these as custom instructions so that they can be used alongside the standard instructions required by the compiler. Take a look at the code controlled by the EXTENSION_XH3BEXTM parameter for an example of this.

You mentioned approximate computing, but as the ALU will still have to implement both the precise and approximate versions of the calculation, I don't expect this would improve your energy per instruction.

Thanks for the amazing and brief explanation @Wren6991 . One last question: could you please suggest a way so that I can add my own custom instruction in such a way that I won't violate the existing logic? Is there any documentation available? And from a FPGA developer who is quite comfortable with the Verilog, how much time do you think it would take to implement on top of the existing Hazard3 processor modules?

@Wren6991
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Wren6991 commented Jan 2, 2025

One last question: could you please suggest a way so that I can add my own custom instruction in such a way that I won't violate the existing logic?

Yes, you will need to:

  • Allocate your own custom opcode e.g. under the custom1 space described in the ISA manual, and add it to rv_opcodes.vh
  • Add a decode listing for it in hazard3_decode.v
  • Add an ALU operation encoding for it in hazard3_ops.vh
  • Implement the ALU function in hazard3_alu.v

You can see an example of all of these if you search for EXTENSION_XH3BEXTM in the source code and the documentation.

@Arghyajoy27
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@Wren6991 , Thanks alot for the valuable suggestions and comments. This is really helpful for the initial kickstart.

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