From 5dc31ae156ce38034b6aaf960f08c94670821c4e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 5 May 2023 16:49:52 +0200 Subject: [PATCH 1/4] Fix CIB_EBR location --- fuzzers/machxo3/020-center-mux/6900/fuzzer.py | 4 ++-- libtrellis/src/Tile.cpp | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fuzzers/machxo3/020-center-mux/6900/fuzzer.py b/fuzzers/machxo3/020-center-mux/6900/fuzzer.py index a2bc9256..50a64a4a 100644 --- a/fuzzers/machxo3/020-center-mux/6900/fuzzer.py +++ b/fuzzers/machxo3/020-center-mux/6900/fuzzer.py @@ -72,8 +72,8 @@ def fc_filter_dcc(a, n): # Thanks to fc_filter_dcc, make sure to manually connect DCC outputs to # entrance to global network! { - "netnames" : ["R13C19_VPRX0000", "R13C19_VPRX0100", "R13C19_VPRX0200", "R13C19_VPRX0300", - "R13C19_VPRX0400", "R13C19_VPRX0500", "R13C19_VPRX0600", "R13C19_VPRX0700"], + "netnames" : ["R17C19_VPRX0000", "R17C19_VPRX0100", "R17C19_VPRX0200", "R17C19_VPRX0300", + "R17C19_VPRX0400", "R17C19_VPRX0500", "R17C19_VPRX0600", "R17C19_VPRX0700"], "cfg" : FuzzConfig(job="GLOBAL_DCC_OUT", family="MachXO3", device="LCMXO3LF-6900C", ncl="center-mux.ncl", tiles=["CENTER13:CENTER_EBR_CIB_4K", "CENTER_EBR29:CENTER_EBR", "CENTER16:CENTER8", "CENTER15:CENTER7", "CENTER14:CENTER6", diff --git a/libtrellis/src/Tile.cpp b/libtrellis/src/Tile.cpp index c9d92490..750f2a89 100644 --- a/libtrellis/src/Tile.cpp +++ b/libtrellis/src/Tile.cpp @@ -41,7 +41,7 @@ map, pair> center_map = { // LCMXO2-4000, LCMXO3-4300 {make_pair(22, 31), make_pair(11, 15)}, // LCMXO2-7000, LCMXO3-6900 - {make_pair(27, 40), make_pair(13, 18)}, + {make_pair(27, 40), make_pair(17, 18)}, // LCMXO3-9400 {make_pair(31, 48), make_pair(15, 24)}, }; From 7ab9295da9010669b3ae65e57bc4063ff9def57b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 5 May 2023 16:50:16 +0200 Subject: [PATCH 2/4] handle L_/R_ wires on spines --- libtrellis/include/RoutingGraph.hpp | 1 + libtrellis/src/RoutingGraph.cpp | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/libtrellis/include/RoutingGraph.hpp b/libtrellis/include/RoutingGraph.hpp index 811ba26e..09015b3d 100644 --- a/libtrellis/include/RoutingGraph.hpp +++ b/libtrellis/include/RoutingGraph.hpp @@ -178,6 +178,7 @@ class RoutingGraph : public IdStore const MachXO2GlobalsInfo *global_data_machxo2; enum GlobalType { CENTER, + SPINE_LEFT_RIGHT, LEFT_RIGHT, UP_DOWN, BRANCH, diff --git a/libtrellis/src/RoutingGraph.cpp b/libtrellis/src/RoutingGraph.cpp index 4c58a6e6..af0d1fdc 100644 --- a/libtrellis/src/RoutingGraph.cpp +++ b/libtrellis/src/RoutingGraph.cpp @@ -378,6 +378,12 @@ RoutingId RoutingGraph::find_machxo2_global_position(int row, int col, const std curr_global.loc.y = center.first; return curr_global; + } else if(strategy == GlobalType::SPINE_LEFT_RIGHT) { + assert(row == spine_1.row || row == spine_2.row); + curr_global.id = ident(db_name); + curr_global.loc.x = center.second; + curr_global.loc.y = row; + return curr_global; // If we found a global emanating from the CENTER MUX, return a L_/R_ // global net in the center tile based upon the current tile position // (specifically column). @@ -582,11 +588,12 @@ RoutingGraph::GlobalType RoutingGraph::get_global_type_from_name(const std::stri // static const std::regex qsw90(R"(G_DQSW90)", std::regex::optimize); if(regex_match(db_name, match, global_entry) || - regex_match(db_name, match, global_left_right) || regex_match(db_name, match, center_mux_glb_out) || regex_match(db_name, match, cib_out_to_glb) || regex_match(db_name, match, dcm_sig)) { return GlobalType::CENTER; + } else if(regex_match(db_name, match, global_left_right)) { + return GlobalType::SPINE_LEFT_RIGHT; } else if(regex_match(db_name, match, global_left_right_g)) { return GlobalType::LEFT_RIGHT; } else if(regex_match(db_name, match, global_up_down) || From 0389e87dca272606514c48b0a1f49956fe2fbdcb Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 7 May 2023 15:38:18 +0200 Subject: [PATCH 3/4] Fix that adds VPTX HPSX missing connections --- fuzzers/machxo3/022-glb-cib_ebr/2100/fuzzer.py | 4 +++- fuzzers/machxo3/022-glb-cib_ebr/4300/fuzzer.py | 6 ++++-- fuzzers/machxo3/022-glb-cib_ebr/6900/fuzzer.py | 5 +++-- fuzzers/machxo3/022-glb-cib_ebr/9400/fuzzer.py | 2 +- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/fuzzers/machxo3/022-glb-cib_ebr/2100/fuzzer.py b/fuzzers/machxo3/022-glb-cib_ebr/2100/fuzzer.py index 3d4cb06f..a772db84 100644 --- a/fuzzers/machxo3/022-glb-cib_ebr/2100/fuzzer.py +++ b/fuzzers/machxo3/022-glb-cib_ebr/2100/fuzzer.py @@ -10,7 +10,7 @@ def mk_nets(tilepos, glb_ids): # Up/Down conns ud_nets.extend(net_product( - net_product(["R6C{}_VPTX0{{}}00", "R11C{}_VPTX0{{}}00"], [tilepos[1]]), + net_product(["R5C{}_VPTX0{{}}00", "R11C{}_VPTX0{{}}00"], [tilepos[1]]), glb_ids)) # Phantom DCCs- First fill in "T"/"B", and then global id @@ -28,6 +28,8 @@ def flatten_nets(tilepos): jobs = [ (FuzzConfig(job="CIB0_EBR0_END0_UPDOWN", family="MachXO3", device="LCMXO3LF-2100C", ncl="tap.ncl", tiles=["CIB_R8C1:CIB_EBR_DUMMY_END3"]), flatten_nets((8,1))), + (FuzzConfig(job="CIB0_EBR2_END1_UPDOWN", family="MachXO3", device="LCMXO3LF-2100C", ncl="tap.ncl", + tiles=["CIB_R8C26:CIB_EBR2_END0"]), flatten_nets((8,26))) ] def main(args): diff --git a/fuzzers/machxo3/022-glb-cib_ebr/4300/fuzzer.py b/fuzzers/machxo3/022-glb-cib_ebr/4300/fuzzer.py index 67dcc171..bffb3685 100644 --- a/fuzzers/machxo3/022-glb-cib_ebr/4300/fuzzer.py +++ b/fuzzers/machxo3/022-glb-cib_ebr/4300/fuzzer.py @@ -10,7 +10,7 @@ def mk_nets(tilepos, glb_ids): # Up/Down conns ud_nets.extend(net_product( - net_product(["R11C{}_VPTX0{{}}00", "R15C{}_VPTX0{{}}00"], [tilepos[1]]), + net_product(["R6C{}_VPTX0{{}}00", "R16C{}_VPTX0{{}}00"], [tilepos[1]]), glb_ids)) # Phantom DCCs- First fill in "T"/"B", and then global id @@ -27,7 +27,9 @@ def flatten_nets(tilepos): jobs = [ (FuzzConfig(job="CIB_EBR0_END1_UPDOWN", family="MachXO3", device="LCMXO3LF-4300C", ncl="tap.ncl", - tiles=["CIB_R11C1:CIB_EBR0_END1"]), flatten_nets((11,1))) + tiles=["CIB_R11C1:CIB_EBR0_END1"]), flatten_nets((11,1))), + (FuzzConfig(job="CIB0_EBR2_END1_UPDOWN", family="MachXO3", device="LCMXO3LF-4300C", ncl="tap.ncl", + tiles=["CIB_R11C32:CIB_EBR2_END1"]), flatten_nets((11,32))) ] diff --git a/fuzzers/machxo3/022-glb-cib_ebr/6900/fuzzer.py b/fuzzers/machxo3/022-glb-cib_ebr/6900/fuzzer.py index fe6b47a7..0b3361ac 100644 --- a/fuzzers/machxo3/022-glb-cib_ebr/6900/fuzzer.py +++ b/fuzzers/machxo3/022-glb-cib_ebr/6900/fuzzer.py @@ -10,7 +10,7 @@ def mk_nets(tilepos, glb_ids): # Up/Down conns ud_nets.extend(net_product( - net_product(["R11C{}_VPTX0{{}}00", "R15C{}_VPTX0{{}}00"], [tilepos[1]]), + net_product(["R7C{}_VPTX0{{}}00", "R17C{}_VPTX0{{}}00", "R23C{}_VPTX0{{}}00"], [tilepos[1]]), glb_ids)) # Phantom DCCs- First fill in "T"/"B", and then global id @@ -26,6 +26,7 @@ def flatten_nets(tilepos): return [nets for netpair in [(0, 4), (1, 5), (2, 6), (3, 7)] for nets in mk_nets(tilepos, netpair)] jobs = [ + #0 (FuzzConfig(job="GLB_UPDOWN26", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl", tiles=["CIB_R13C10:CIB_EBR0"]), mk_nets((13, 10), (2, 6))), @@ -38,11 +39,11 @@ def flatten_nets(tilepos): (FuzzConfig(job="GLB_UPDOWN37", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl", tiles=["CIB_R13C7:CIB_EBR0"]), mk_nets((13, 7), (3, 7))), + #4 (FuzzConfig(job="CIB_EBR0_END2_DLL45_UPDOWN", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl", tiles=["CIB_R13C1:CIB_EBR0_END2_DLL45"]), flatten_nets((13,1))), (FuzzConfig(job="CIB_EBR2_END1_UPDOWN", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl", tiles=["CIB_R13C41:CIB_EBR2_END1"]), flatten_nets((13,41))), - (FuzzConfig(job="CIB_EBR0_END2_DLL3_UPDOWN", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl", tiles=["CIB_R20C1:CIB_EBR0_END2_DLL3"]), flatten_nets((20,1))), (FuzzConfig(job="CIB_EBR2_END1_SP_UPDOWN", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl", diff --git a/fuzzers/machxo3/022-glb-cib_ebr/9400/fuzzer.py b/fuzzers/machxo3/022-glb-cib_ebr/9400/fuzzer.py index 2f0bd1bb..87f441eb 100644 --- a/fuzzers/machxo3/022-glb-cib_ebr/9400/fuzzer.py +++ b/fuzzers/machxo3/022-glb-cib_ebr/9400/fuzzer.py @@ -10,7 +10,7 @@ def mk_nets(tilepos, glb_ids): # Up/Down conns ud_nets.extend(net_product( - net_product(["R13C{}_VPTX0{{}}00", "R17C{}_VPTX0{{}}00"], [tilepos[1]]), + net_product(["R5C{}_VPTX0{{}}00", "R12C{}_VPTX0{{}}00", "R19C{}_VPTX0{{}}00", "R26C{}_VPTX0{{}}00"], [tilepos[1]]), glb_ids)) # Phantom DCCs- First fill in "T"/"B", and then global id From a53754ab1c71e35e21b92774a9c0ac720a6da4db Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 8 May 2023 09:54:13 +0200 Subject: [PATCH 4/4] update database --- database | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/database b/database index 9e1585f8..ce8cdafe 160000 --- a/database +++ b/database @@ -1 +1 @@ -Subproject commit 9e1585f87319e0a7dcf38c0755fa95bfd67852be +Subproject commit ce8cdafe7a8c718f0ec43895894b668a479ba33f