Lab4.gise

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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <!--                                                          -->

  <!--             For tool use only. Do not edit.              -->

  <!--                                                          -->

  <!-- ProjectNavigator created generated project file.         -->

  <!-- For use in tracking generated file and other information -->

  <!-- allowing preservation of process status.                 -->

  <!--                                                          -->

  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->

  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="Lab4.xise"/>

  <files xmlns="http://www.xilinx.com/XMLSchema">
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="ipcore_dir/Clock50.v" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_VEO" xil_pn:name="ipcore_dir/Clock50.veo" xil_pn:origination="imported"/>
    <file xil_pn:fileType="FILE_NCD" xil_pn:name="nexys3_guide.ncd" xil_pn:origination="imported"/>
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>

</generated_project>