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alexforencich/verilog-ethernet
error_invalid_checksum asserted when receiving broadcast UDP packets

When receiving broadcast UDP packets, error_invalid_checksum is asserted every time. In this case the mac addr is all xF, so maybe there is an overflow in the accumulator? The problem is observed in this ...
  • jdeffenb
  • Opened 
    3 days ago
  • #254

alexforencich/verilog-ethernet
ARP packet not working on KC705-rgmii

hello I built the project and the .bit is built correctly but when I test on the board unfortunately the ARP packets are not responded to correctly. As shown in the image below Image
  • saman-coder
  • Opened 
    6 days ago
  • #253

alexforencich/verilog-ethernet
Does the Project Code Support Optical Module Hot-Swapping During Data Transmission?

Hello! I am currently testing the stability of the project, especially the compatibility with hardware operations during device runtime. I noticed that in real-world scenarios, it is possible that optical ...
  • Unicorn619
  • 1
  • Opened 
    9 days ago
  • #252

alexforencich/verilog-ethernet
RTL Linting with Verilator -Wall

https://github.com/chili-chips-ba/wireguard-fpga/issues/14#issue-2879563883
  • chili-chips-ba
  • 1
  • Opened 
    12 days ago
  • #251

alexforencich/verilog-ethernet
GMII output DDR and input SDR

In this line, if not XILINX and not ALTERA then DDR is automatically activated... oddr.v:135 Called from ssio_sdr_out.v with parameter IODDR_STYLE = IODDR2 ssio_sdr_out.v:54 Called from gmii_phy_if.v ...
  • jalcim
  • 5
  • Opened 
    12 days ago
  • #250

alexforencich/verilog-ethernet
Sending back to back packets - how to tell when 2nd can be sent.

I have been doing some testing (currently under simulation - but have tested and verified single packet transmittion) of an application where I might want to quickly send packets back to back. I wait for ...
  • cube1us
  • 1
  • Opened 
    28 days ago
  • #247

alexforencich/verilog-ethernet
Does this Ethernet project include Auto-Negotiation?

Thanks for this super nice project! Does this Ethernet project include Auto-Negotiation? I looked at the RTL file name and there seems to be no such module.
  • myqlee
  • 2
  • Opened 
    on Jan 23
  • #245

alexforencich/verilog-ethernet
Can this design be targeted to Alveo X3522 ?

I had earlier targeted the verilog-ethernet design on Alveo u50 and it worked as expected during testing. I would now want to understand and explore the Alveo X3522 card and can this design be targeted ...
  • lizajoseph
  • Opened 
    on Jan 16
  • #244

alexforencich/verilog-ethernet
Can you add a module to support SPI to MII conversion, like the chip DM9051

Many SPI to MII conversions are used on microcontrollers, but there is a lack of FPGA implementation on the entire GitHub. The difficulty of implementation mainly lies in compatibility with existing Linux ...
  • woodyuni
  • 1
  • Opened 
    on Dec 20, 2024
  • #239

alexforencich/verilog-ethernet
PTP_CLOCK

Hello, I hope this message finds you well. I have noticed that the ptp_clock module does not support negative increments (using two s complement) when adjusting the clock with input_adj_ related signals. ...
  • Unicorn619
  • Opened 
    on Dec 12, 2024
  • #235
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