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copy_sm100.hpp
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/***************************************************************************************************
* Copyright (c) 2023 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************************************/
//
//
#pragma once
#include <cute/arch/config.hpp>
#include <cute/arch/mma_sm100.hpp>
#include <cute/arch/copy.hpp>
////////////////////////////////////////////////////////////////////////////////////////////////////
namespace cute {
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
//
// LDSM PTX definitions
//
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_U8x8_LDSM_T
{
using SRegisters = uint128_t[1];
using DRegisters = uint32_t[2];
CUTE_HOST_DEVICE static void
copy(uint128_t const& smem_src,
uint32_t& dst0, uint32_t& dst1)
{
#if defined(CUTE_ARCH_LDSM_SM100A_ENABLED)
uint32_t tmp0, tmp1;
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_src);
asm volatile ("ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {%0, %1}, [%2];\n"
: "=r"(reinterpret_cast<uint32_t &>(tmp0)), "=r"(reinterpret_cast<uint32_t &>(tmp1))
: "r"(smem_int_ptr));
// RefLayout of ldmatrix.m16n16.x1.trans won't match stmatrix.m16n8.x2.trans without additional transformations
// Do this here so we don't need to add an additional reg to reg copy at the collective layer
uchar4& tmp0_ = reinterpret_cast<uchar4&>(tmp0);
uchar4& tmp1_ = reinterpret_cast<uchar4&>(tmp1);
uchar4 dst0_{tmp0_.x, tmp0_.y, tmp1_.x, tmp1_.y};
uchar4 dst1_{tmp0_.z, tmp0_.w, tmp1_.z, tmp1_.w};
dst0 = reinterpret_cast<uint32_t&>(dst0_);
dst1 = reinterpret_cast<uint32_t&>(dst1_);
#else
CUTE_INVALID_CONTROL_PATH("Trying to use ldmatrix without CUTE_ARCH_LDSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_U8x16_LDSM_T
{
using SRegisters = uint128_t[1];
using DRegisters = uint32_t[4];
CUTE_HOST_DEVICE static void
copy(uint128_t const& smem_src,
uint32_t& dst0, uint32_t& dst1, uint32_t& dst2, uint32_t& dst3)
{
#if defined(CUTE_ARCH_LDSM_SM100A_ENABLED)
uint32_t tmp0, tmp1, tmp2, tmp3;
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_src);
asm volatile ("ldmatrix.sync.aligned.m16n16.x2.trans.shared.b8 {%0, %1, %2, %3}, [%4];\n"
: "=r"(reinterpret_cast<uint32_t &>(tmp0)), "=r"(reinterpret_cast<uint32_t &>(tmp1)),
"=r"(reinterpret_cast<uint32_t &>(tmp2)), "=r"(reinterpret_cast<uint32_t &>(tmp3))
: "r"(smem_int_ptr));
uchar4& tmp0_ = reinterpret_cast<uchar4&>(tmp0);
uchar4& tmp1_ = reinterpret_cast<uchar4&>(tmp1);
uchar4& tmp2_ = reinterpret_cast<uchar4&>(tmp2);
uchar4& tmp3_ = reinterpret_cast<uchar4&>(tmp3);
uchar4 dst0_{tmp0_.x, tmp0_.y, tmp1_.x, tmp1_.y};
uchar4 dst1_{tmp0_.z, tmp0_.w, tmp1_.z, tmp1_.w};
uchar4 dst2_{tmp2_.x, tmp2_.y, tmp3_.x, tmp3_.y};
uchar4 dst3_{tmp2_.z, tmp2_.w, tmp3_.z, tmp3_.w};
dst0 = reinterpret_cast<uint32_t&>(dst0_);
dst1 = reinterpret_cast<uint32_t&>(dst1_);
dst2 = reinterpret_cast<uint32_t&>(dst2_);
dst3 = reinterpret_cast<uint32_t&>(dst3_);
#else
CUTE_INVALID_CONTROL_PATH("Trying to use ldmatrix without CUTE_ARCH_LDSM_SM100A_ENABLED.");
#endif
}
};
struct SM100_SU4_DU8x16_x1_LDSM_N
{
using SRegisters = uint128_t[1];
using DRegisters = uint32_t[1];
CUTE_DEVICE static void
copy(uint128_t const& smem_src,
uint32_t& dst0)
{
#if defined(CUTE_ARCH_LDSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_src);
asm volatile ("ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b4x16_p64 {%0}, [%1];\n"
: "=r"(dst0)
: "r"(smem_int_ptr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use ldmatrix without CUTE_ARCH_LDSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_SU6_DU8x16_x1_LDSM_N
{
using SRegisters = uint128_t[1];
using DRegisters = uint32_t[1];
CUTE_DEVICE static void
copy(uint128_t const& smem_src,
uint32_t& dst0)
{
#if defined(CUTE_ARCH_LDSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_src);
asm volatile ("ldmatrix.sync.aligned.m8n16.x1.shared.b8x16.b6x16_p32 {%0}, [%1];\n"
: "=r"(dst0)
: "r"(smem_int_ptr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use ldmatrix without CUTE_ARCH_LDSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_SU4_DU8x16_x2_LDSM_N
{
using SRegisters = uint128_t[1];
using DRegisters = uint32_t[2];
CUTE_DEVICE static void
copy(uint128_t const& smem_src,
uint32_t& dst0, uint32_t& dst1)
{
#if defined(CUTE_ARCH_LDSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_src);
asm volatile ("ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b4x16_p64 {%0, %1}, [%2];\n"
: "=r"(dst0), "=r"(dst1)
: "r"(smem_int_ptr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use ldmatrix without CUTE_ARCH_LDSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_SU6_DU8x16_x2_LDSM_N
{
using SRegisters = uint128_t[1];
using DRegisters = uint32_t[2];
CUTE_DEVICE static void
copy(uint128_t const& smem_src,
uint32_t& dst0, uint32_t& dst1)
{
#if defined(CUTE_ARCH_LDSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_src);
asm volatile ("ldmatrix.sync.aligned.m8n16.x2.shared.b8x16.b6x16_p32 {%0, %1}, [%2];\n"
: "=r"(dst0), "=r"(dst1)
: "r"(smem_int_ptr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use ldmatrix without CUTE_ARCH_LDSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_SU4_DU8x16_x4_LDSM_N
{
using SRegisters = uint128_t[1];
using DRegisters = uint32_t[4];
CUTE_DEVICE static void
copy(uint128_t const& smem_src,
uint32_t& dst0, uint32_t& dst1, uint32_t& dst2, uint32_t& dst3)
{
#if defined(CUTE_ARCH_LDSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_src);
asm volatile ("ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b4x16_p64 {%0, %1, %2, %3}, [%4];\n"
: "=r"(dst0), "=r"(dst1), "=r"(dst2), "=r"(dst3)
: "r"(smem_int_ptr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use ldmatrix without CUTE_ARCH_LDSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_SU6_DU8x16_x4_LDSM_N
{
using SRegisters = uint128_t[1];
using DRegisters = uint32_t[4];
CUTE_DEVICE static void
copy(uint128_t const& smem_src,
uint32_t& dst0, uint32_t& dst1, uint32_t& dst2, uint32_t& dst3)
{
#if defined(CUTE_ARCH_LDSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_src);
asm volatile ("ldmatrix.sync.aligned.m8n16.x4.shared.b8x16.b6x16_p32 {%0, %1, %2, %3}, [%4];\n"
: "=r"(dst0), "=r"(dst1), "=r"(dst2), "=r"(dst3)
: "r"(smem_int_ptr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use ldmatrix without CUTE_ARCH_LDSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
//
// STSM PTX definitions
//
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_U8x4_STSM_T
{
using SRegisters = uint32_t[1];
using DRegisters = uint128_t[1];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src,
uint128_t& smem_dst)
{
#if defined(CUTE_ARCH_STSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_dst);
asm volatile ("stmatrix.sync.aligned.m16n8.x1.trans.shared.b8 [%0], {%1};\n"
:: "r"(smem_int_ptr),
"r"(src));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use stmatrix without CUTE_ARCH_STSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_U8x8_STSM_T
{
using SRegisters = uint32_t[2];
using DRegisters = uint128_t[1];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src0, uint32_t const& src1,
uint128_t& smem_dst)
{
#if defined(CUTE_ARCH_STSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_dst);
asm volatile ("stmatrix.sync.aligned.m16n8.x2.trans.shared.b8 [%0], {%1, %2};\n"
:: "r"(smem_int_ptr),
"r"(src0), "r"(src1));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use stmatrix without CUTE_ARCH_STSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
struct SM100_U8x16_STSM_T
{
using SRegisters = uint32_t[4];
using DRegisters = uint128_t[1];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src0, uint32_t const& src1, uint32_t const& src2, uint32_t const& src3,
uint128_t& smem_dst)
{
#if defined(CUTE_ARCH_STSM_SM100A_ENABLED)
uint32_t smem_int_ptr = cast_smem_ptr_to_uint(&smem_dst);
asm volatile ("stmatrix.sync.aligned.m16n8.x4.trans.shared.b8 [%0], {%1, %2, %3, %4};\n"
:: "r"(smem_int_ptr),
"r"(src0), "r"(src1), "r"(src2), "r"(src3));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use stmatrix without CUTE_ARCH_STSM_SM100A_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
} // namespace cute
////////////////////////////////////////////////////////////////////////////////////////////////////
//
// UTCCP PTX definitions
//
////////////////////////////////////////////////////////////////////////////////////////////////////
namespace cute {
// 128 data path lanes, 256-bit pattern, 1cta mode
struct SM100_UTCCP_128dp256bit_1cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::1.128x256b [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 128 data path lanes, 256-bit pattern, 2cta mode
struct SM100_UTCCP_128dp256bit_2cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::2.128x256b [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
struct SM100_UTCCP_128dp128bit_1cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::1.128x128b [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
struct SM100_UTCCP_128dp128bit_2cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::2.128x128b [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 4 data path lanes, 256-bit pattern, 1cta mode
struct SM100_UTCCP_4dp256bit_1cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::1.4x256b [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 4 data path lanes, 256-bit pattern, 2cta mode
struct SM100_UTCCP_4dp256bit_2cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::2.4x256b [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 4x32 data path lanes (broadcast), 128-bit pattern, 1cta mode
struct SM100_UTCCP_4x32dp128bit_1cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::1.32x128b.warpx4 [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 4x32 data path lanes (broadcast), 128-bit pattern, 2cta mode
struct SM100_UTCCP_4x32dp128bit_2cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::2.32x128b.warpx4 [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 2x64 data path lanes (broadcast like 4x32dp), 128-bit pattern, 1cta mode
struct SM100_UTCCP_2x64dp128bitlw0213_1cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 2x64 data path lanes (broadcast like 4x32dp), 128-bit pattern, 2cta mode
struct SM100_UTCCP_2x64dp128bitlw0213_2cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 2x64 data path lanes (broadcast seperately in upper and lower 64dp), 128-bit pattern, 1cta mode
// data_row[0:31] -> DP[0:63]
// data_row[32:63] -> DP[64:127]
struct SM100_UTCCP_2x64dp128bitlw0123_1cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
// 2x64 data path lanes (broadcast seperately in upper and lower 64dp), 128-bit pattern, 2cta mode
// data_row[0:31] -> DP[0:63]
// data_row[32:63] -> DP[64:127]
struct SM100_UTCCP_2x64dp128bitlw0123_2cta
{
using SRegisters = uint64_t[1];
using DRegisters = uint32_t[1];
CUTE_HOST_DEVICE static void
copy(uint64_t const& src_addr, uint32_t const& dst_addr)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 [%0], %1;"
:
: "r"(dst_addr) "l"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use UTCCP without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
} // namespace cute
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
namespace cute {
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
//
// TMEM_LOAD PTX definitions
//
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 1 times
struct SM100_TMEM_LOAD_16dp256b1x
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[4];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst0, uint32_t& dst1, uint32_t& dst2, uint32_t& dst3)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x1.b32"
"{%0, %1, %2, %3},"
"[%4];\n"
: "=r"(dst0), "=r"(dst1), "=r"(dst2), "=r"(dst3)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 1 times, packed 16b read
struct SM100_TMEM_LOAD_16dp256b1x_16b
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[4];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst0, uint32_t& dst1, uint32_t& dst2, uint32_t& dst3)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32"
"{%0, %1, %2, %3},"
"[%4];\n"
: "=r"(dst0), "=r"(dst1), "=r"(dst2), "=r"(dst3)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 2 times
struct SM100_TMEM_LOAD_16dp256b2x
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[8];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst0, uint32_t& dst1, uint32_t& dst2, uint32_t& dst3,
uint32_t& dst4, uint32_t& dst5, uint32_t& dst6, uint32_t& dst7)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x2.b32"
"{%0, %1, %2, %3,"
"%4, %5, %6, %7},"
"[%8];\n"
: "=r"(dst0), "=r"(dst1), "=r"(dst2), "=r"(dst3),
"=r"(dst4), "=r"(dst5), "=r"(dst6), "=r"(dst7)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 2 times, packed 16b read
struct SM100_TMEM_LOAD_16dp256b2x_16b
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[8];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst0, uint32_t& dst1, uint32_t& dst2, uint32_t& dst3,
uint32_t& dst4, uint32_t& dst5, uint32_t& dst6, uint32_t& dst7)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32"
"{%0, %1, %2, %3,"
"%4, %5, %6, %7},"
"[%8];\n"
: "=r"(dst0), "=r"(dst1), "=r"(dst2), "=r"(dst3),
"=r"(dst4), "=r"(dst5), "=r"(dst6), "=r"(dst7)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 4 times
struct SM100_TMEM_LOAD_16dp256b4x
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[16];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst00, uint32_t& dst01, uint32_t& dst02, uint32_t& dst03,
uint32_t& dst04, uint32_t& dst05, uint32_t& dst06, uint32_t& dst07,
uint32_t& dst08, uint32_t& dst09, uint32_t& dst10, uint32_t& dst11,
uint32_t& dst12, uint32_t& dst13, uint32_t& dst14, uint32_t& dst15)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x4.b32"
"{%0, %1, %2, %3,"
"%4, %5, %6, %7,"
"%8, %9, %10, %11,"
"%12, %13, %14, %15},"
"[%16];\n"
: "=r"(dst00), "=r"(dst01), "=r"(dst02), "=r"(dst03),
"=r"(dst04), "=r"(dst05), "=r"(dst06), "=r"(dst07),
"=r"(dst08), "=r"(dst09), "=r"(dst10), "=r"(dst11),
"=r"(dst12), "=r"(dst13), "=r"(dst14), "=r"(dst15)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 4 times, packed 16b read
struct SM100_TMEM_LOAD_16dp256b4x_16b
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[16];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst00, uint32_t& dst01, uint32_t& dst02, uint32_t& dst03,
uint32_t& dst04, uint32_t& dst05, uint32_t& dst06, uint32_t& dst07,
uint32_t& dst08, uint32_t& dst09, uint32_t& dst10, uint32_t& dst11,
uint32_t& dst12, uint32_t& dst13, uint32_t& dst14, uint32_t& dst15)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32"
"{%0, %1, %2, %3,"
"%4, %5, %6, %7,"
"%8, %9, %10, %11,"
"%12, %13, %14, %15},"
"[%16];\n"
: "=r"(dst00), "=r"(dst01), "=r"(dst02), "=r"(dst03),
"=r"(dst04), "=r"(dst05), "=r"(dst06), "=r"(dst07),
"=r"(dst08), "=r"(dst09), "=r"(dst10), "=r"(dst11),
"=r"(dst12), "=r"(dst13), "=r"(dst14), "=r"(dst15)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 8 times
struct SM100_TMEM_LOAD_16dp256b8x
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[32];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst00, uint32_t& dst01, uint32_t& dst02, uint32_t& dst03,
uint32_t& dst04, uint32_t& dst05, uint32_t& dst06, uint32_t& dst07,
uint32_t& dst08, uint32_t& dst09, uint32_t& dst10, uint32_t& dst11,
uint32_t& dst12, uint32_t& dst13, uint32_t& dst14, uint32_t& dst15,
uint32_t& dst16, uint32_t& dst17, uint32_t& dst18, uint32_t& dst19,
uint32_t& dst20, uint32_t& dst21, uint32_t& dst22, uint32_t& dst23,
uint32_t& dst24, uint32_t& dst25, uint32_t& dst26, uint32_t& dst27,
uint32_t& dst28, uint32_t& dst29, uint32_t& dst30, uint32_t& dst31)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x8.b32"
"{%0, %1, %2, %3,"
"%4, %5, %6, %7,"
"%8, %9, %10, %11,"
"%12, %13, %14, %15,"
"%16, %17, %18, %19,"
"%20, %21, %22, %23,"
"%24, %25, %26, %27,"
"%28, %29, %30, %31},"
"[%32];\n"
: "=r"(dst00), "=r"(dst01), "=r"(dst02), "=r"(dst03),
"=r"(dst04), "=r"(dst05), "=r"(dst06), "=r"(dst07),
"=r"(dst08), "=r"(dst09), "=r"(dst10), "=r"(dst11),
"=r"(dst12), "=r"(dst13), "=r"(dst14), "=r"(dst15),
"=r"(dst16), "=r"(dst17), "=r"(dst18), "=r"(dst19),
"=r"(dst20), "=r"(dst21), "=r"(dst22), "=r"(dst23),
"=r"(dst24), "=r"(dst25), "=r"(dst26), "=r"(dst27),
"=r"(dst28), "=r"(dst29), "=r"(dst30), "=r"(dst31)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 8 times, packed 16b read
struct SM100_TMEM_LOAD_16dp256b8x_16b
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[32];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst00, uint32_t& dst01, uint32_t& dst02, uint32_t& dst03,
uint32_t& dst04, uint32_t& dst05, uint32_t& dst06, uint32_t& dst07,
uint32_t& dst08, uint32_t& dst09, uint32_t& dst10, uint32_t& dst11,
uint32_t& dst12, uint32_t& dst13, uint32_t& dst14, uint32_t& dst15,
uint32_t& dst16, uint32_t& dst17, uint32_t& dst18, uint32_t& dst19,
uint32_t& dst20, uint32_t& dst21, uint32_t& dst22, uint32_t& dst23,
uint32_t& dst24, uint32_t& dst25, uint32_t& dst26, uint32_t& dst27,
uint32_t& dst28, uint32_t& dst29, uint32_t& dst30, uint32_t& dst31)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x8.pack::16b.b32"
"{%0, %1, %2, %3,"
"%4, %5, %6, %7,"
"%8, %9, %10, %11,"
"%12, %13, %14, %15,"
"%16, %17, %18, %19,"
"%20, %21, %22, %23,"
"%24, %25, %26, %27,"
"%28, %29, %30, %31},"
"[%32];\n"
: "=r"(dst00), "=r"(dst01), "=r"(dst02), "=r"(dst03),
"=r"(dst04), "=r"(dst05), "=r"(dst06), "=r"(dst07),
"=r"(dst08), "=r"(dst09), "=r"(dst10), "=r"(dst11),
"=r"(dst12), "=r"(dst13), "=r"(dst14), "=r"(dst15),
"=r"(dst16), "=r"(dst17), "=r"(dst18), "=r"(dst19),
"=r"(dst20), "=r"(dst21), "=r"(dst22), "=r"(dst23),
"=r"(dst24), "=r"(dst25), "=r"(dst26), "=r"(dst27),
"=r"(dst28), "=r"(dst29), "=r"(dst30), "=r"(dst31)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 16 times
struct SM100_TMEM_LOAD_16dp256b16x
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[64];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst00, uint32_t& dst01, uint32_t& dst02, uint32_t& dst03,
uint32_t& dst04, uint32_t& dst05, uint32_t& dst06, uint32_t& dst07,
uint32_t& dst08, uint32_t& dst09, uint32_t& dst10, uint32_t& dst11,
uint32_t& dst12, uint32_t& dst13, uint32_t& dst14, uint32_t& dst15,
uint32_t& dst16, uint32_t& dst17, uint32_t& dst18, uint32_t& dst19,
uint32_t& dst20, uint32_t& dst21, uint32_t& dst22, uint32_t& dst23,
uint32_t& dst24, uint32_t& dst25, uint32_t& dst26, uint32_t& dst27,
uint32_t& dst28, uint32_t& dst29, uint32_t& dst30, uint32_t& dst31,
uint32_t& dst32, uint32_t& dst33, uint32_t& dst34, uint32_t& dst35,
uint32_t& dst36, uint32_t& dst37, uint32_t& dst38, uint32_t& dst39,
uint32_t& dst40, uint32_t& dst41, uint32_t& dst42, uint32_t& dst43,
uint32_t& dst44, uint32_t& dst45, uint32_t& dst46, uint32_t& dst47,
uint32_t& dst48, uint32_t& dst49, uint32_t& dst50, uint32_t& dst51,
uint32_t& dst52, uint32_t& dst53, uint32_t& dst54, uint32_t& dst55,
uint32_t& dst56, uint32_t& dst57, uint32_t& dst58, uint32_t& dst59,
uint32_t& dst60, uint32_t& dst61, uint32_t& dst62, uint32_t& dst63)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x16.b32"
"{%0, %1, %2, %3,"
"%4, %5, %6, %7,"
"%8, %9, %10, %11,"
"%12, %13, %14, %15,"
"%16, %17, %18, %19,"
"%20, %21, %22, %23,"
"%24, %25, %26, %27,"
"%28, %29, %30, %31,"
"%32, %33, %34, %35,"
"%36, %37, %38, %39,"
"%40, %41, %42, %43,"
"%44, %45, %46, %47,"
"%48, %49, %50, %51,"
"%52, %53, %54, %55,"
"%56, %57, %58, %59,"
"%60, %61, %62, %63},"
"[%64];\n"
: "=r"(dst00), "=r"(dst01), "=r"(dst02), "=r"(dst03),
"=r"(dst04), "=r"(dst05), "=r"(dst06), "=r"(dst07),
"=r"(dst08), "=r"(dst09), "=r"(dst10), "=r"(dst11),
"=r"(dst12), "=r"(dst13), "=r"(dst14), "=r"(dst15),
"=r"(dst16), "=r"(dst17), "=r"(dst18), "=r"(dst19),
"=r"(dst20), "=r"(dst21), "=r"(dst22), "=r"(dst23),
"=r"(dst24), "=r"(dst25), "=r"(dst26), "=r"(dst27),
"=r"(dst28), "=r"(dst29), "=r"(dst30), "=r"(dst31),
"=r"(dst32), "=r"(dst33), "=r"(dst34), "=r"(dst35),
"=r"(dst36), "=r"(dst37), "=r"(dst38), "=r"(dst39),
"=r"(dst40), "=r"(dst41), "=r"(dst42), "=r"(dst43),
"=r"(dst44), "=r"(dst45), "=r"(dst46), "=r"(dst47),
"=r"(dst48), "=r"(dst49), "=r"(dst50), "=r"(dst51),
"=r"(dst52), "=r"(dst53), "=r"(dst54), "=r"(dst55),
"=r"(dst56), "=r"(dst57), "=r"(dst58), "=r"(dst59),
"=r"(dst60), "=r"(dst61), "=r"(dst62), "=r"(dst63)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 16 times, packed 16b read
struct SM100_TMEM_LOAD_16dp256b16x_16b
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[64];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst00, uint32_t& dst01, uint32_t& dst02, uint32_t& dst03,
uint32_t& dst04, uint32_t& dst05, uint32_t& dst06, uint32_t& dst07,
uint32_t& dst08, uint32_t& dst09, uint32_t& dst10, uint32_t& dst11,
uint32_t& dst12, uint32_t& dst13, uint32_t& dst14, uint32_t& dst15,
uint32_t& dst16, uint32_t& dst17, uint32_t& dst18, uint32_t& dst19,
uint32_t& dst20, uint32_t& dst21, uint32_t& dst22, uint32_t& dst23,
uint32_t& dst24, uint32_t& dst25, uint32_t& dst26, uint32_t& dst27,
uint32_t& dst28, uint32_t& dst29, uint32_t& dst30, uint32_t& dst31,
uint32_t& dst32, uint32_t& dst33, uint32_t& dst34, uint32_t& dst35,
uint32_t& dst36, uint32_t& dst37, uint32_t& dst38, uint32_t& dst39,
uint32_t& dst40, uint32_t& dst41, uint32_t& dst42, uint32_t& dst43,
uint32_t& dst44, uint32_t& dst45, uint32_t& dst46, uint32_t& dst47,
uint32_t& dst48, uint32_t& dst49, uint32_t& dst50, uint32_t& dst51,
uint32_t& dst52, uint32_t& dst53, uint32_t& dst54, uint32_t& dst55,
uint32_t& dst56, uint32_t& dst57, uint32_t& dst58, uint32_t& dst59,
uint32_t& dst60, uint32_t& dst61, uint32_t& dst62, uint32_t& dst63)
{
#if defined(CUTE_ARCH_TCGEN05_TMEM_ENABLED)
asm volatile ("tcgen05.ld.sync.aligned.16x256b.x16.pack::16b.b32"
"{%0, %1, %2, %3,"
"%4, %5, %6, %7,"
"%8, %9, %10, %11,"
"%12, %13, %14, %15,"
"%16, %17, %18, %19,"
"%20, %21, %22, %23,"
"%24, %25, %26, %27,"
"%28, %29, %30, %31,"
"%32, %33, %34, %35,"
"%36, %37, %38, %39,"
"%40, %41, %42, %43,"
"%44, %45, %46, %47,"
"%48, %49, %50, %51,"
"%52, %53, %54, %55,"
"%56, %57, %58, %59,"
"%60, %61, %62, %63},"
"[%64];\n"
: "=r"(dst00), "=r"(dst01), "=r"(dst02), "=r"(dst03),
"=r"(dst04), "=r"(dst05), "=r"(dst06), "=r"(dst07),
"=r"(dst08), "=r"(dst09), "=r"(dst10), "=r"(dst11),
"=r"(dst12), "=r"(dst13), "=r"(dst14), "=r"(dst15),
"=r"(dst16), "=r"(dst17), "=r"(dst18), "=r"(dst19),
"=r"(dst20), "=r"(dst21), "=r"(dst22), "=r"(dst23),
"=r"(dst24), "=r"(dst25), "=r"(dst26), "=r"(dst27),
"=r"(dst28), "=r"(dst29), "=r"(dst30), "=r"(dst31),
"=r"(dst32), "=r"(dst33), "=r"(dst34), "=r"(dst35),
"=r"(dst36), "=r"(dst37), "=r"(dst38), "=r"(dst39),
"=r"(dst40), "=r"(dst41), "=r"(dst42), "=r"(dst43),
"=r"(dst44), "=r"(dst45), "=r"(dst46), "=r"(dst47),
"=r"(dst48), "=r"(dst49), "=r"(dst50), "=r"(dst51),
"=r"(dst52), "=r"(dst53), "=r"(dst54), "=r"(dst55),
"=r"(dst56), "=r"(dst57), "=r"(dst58), "=r"(dst59),
"=r"(dst60), "=r"(dst61), "=r"(dst62), "=r"(dst63)
: "r"(src_addr));
#else
CUTE_INVALID_CONTROL_PATH("Trying to use TMEM_LOAD without CUTE_ARCH_TCGEN05_TMEM_ENABLED.");
#endif
}
};
////////////////////////////////////////////////////////////////////////////////////////////////////
// 16 data path lanes, 256-bit pattern, repeated 32 times
struct SM100_TMEM_LOAD_16dp256b32x
{
using SRegisters = uint32_t[1];
using DRegisters = uint32_t[128];
CUTE_HOST_DEVICE static void
copy(uint32_t const& src_addr,
uint32_t& dst000, uint32_t& dst001, uint32_t& dst002, uint32_t& dst003,
uint32_t& dst004, uint32_t& dst005, uint32_t& dst006, uint32_t& dst007,
uint32_t& dst008, uint32_t& dst009, uint32_t& dst010, uint32_t& dst011,
uint32_t& dst012, uint32_t& dst013, uint32_t& dst014, uint32_t& dst015,
uint32_t& dst016, uint32_t& dst017, uint32_t& dst018, uint32_t& dst019,
uint32_t& dst020, uint32_t& dst021, uint32_t& dst022, uint32_t& dst023,
uint32_t& dst024, uint32_t& dst025, uint32_t& dst026, uint32_t& dst027,
uint32_t& dst028, uint32_t& dst029, uint32_t& dst030, uint32_t& dst031,
uint32_t& dst032, uint32_t& dst033, uint32_t& dst034, uint32_t& dst035,
uint32_t& dst036, uint32_t& dst037, uint32_t& dst038, uint32_t& dst039,
uint32_t& dst040, uint32_t& dst041, uint32_t& dst042, uint32_t& dst043,
uint32_t& dst044, uint32_t& dst045, uint32_t& dst046, uint32_t& dst047,
uint32_t& dst048, uint32_t& dst049, uint32_t& dst050, uint32_t& dst051,
uint32_t& dst052, uint32_t& dst053, uint32_t& dst054, uint32_t& dst055,
uint32_t& dst056, uint32_t& dst057, uint32_t& dst058, uint32_t& dst059,
uint32_t& dst060, uint32_t& dst061, uint32_t& dst062, uint32_t& dst063,