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np6532_poc

A proof-of-concept demonstration of the np65 CPU/RAM core. This design uses the np6532 version which has 32 bit CPU RAM ports and a 64 bit DMA RAM port which can be clocked at integer multiples of the CPU clock rate.

The core is connected to a minimal set of registers and memory is initialised with the test code, which signals success or failure by entering an infinite loop. The CPU program counter is used to track down the details.

The proof-of-concent design wrapped around the CPU detects infinite loops and resets the CPU when these occur, as well as toggling LED 0. LED 1 is driven on if the program counter matches the "success" address in the test code - otherwise it is driven off.

Supported boards:

  • Digilent Nexys Video

  • QMTECH Wukong

  • Altera Cyclone V E Development Kit

  • Terasic DE10-Nano

For all these, the memory clock is 96MHz and the CPU clock is 32MHz. The Xilinx targets can run at 48MHz.

Building and Programming

Build the Vivado or Quartus project by running make in the relevant build directory, and program your board from the command line by running make prog. Once the project is built, you may open it in the relevant IDE (Vivado or Quartus).

Simulation

For Xilinx FPGA boards, a simulation testbench is included in the Vivado project and the Vivado simulator may be used via the IDE.

For Intel FPGA boards, the steps to set up Quartus to simulate in Questa are…​

  1. Open the Settings dialog by choosing Settings from the Assigments menu.

  2. Select the Simulation category under EDA Tool Settings.

  3. Set the Tool name to Questa Intel FPGA.

  4. Open the More EDA Netlist Writer Settings dialog by clicking the button.

  5. Set Maintain hierarchy to On and click OK.

  6. Click the Compile test bench: radio button under NativeLink settings.

  7. Open the Test Benches dialog by clicking the Test Benches…​ button.

  8. Open the New Test Bench Settings dialog by clicking New…​.

  9. Open the Select File dialog clicking the …​ under Test bench and simulation files.

  10. Navigate to the src/designs/np6532_poc/altera_c5e_devkit directory of this repo, then select the file tb_np6532_poc_Xk_altera_c5e_dev.vhd (X is the RAM size: 64, 128 or 256).

  11. Close the Select File dialog by clicking Open.

  12. Click Add to add the selected file to the list.

  13. Type tb_np6532_poc_Xk_altera_c5e_dev in the Test bench name: box (X is the RAM size: 64, 128 or 256). The Top level module in test bench box will automatically populate with the same name.

  14. Click OK to close the New Test Bench Settings dialog.

  15. Click OK to close the Test Benches dialog.

  16. Click OK to close the Settings dialog.

You may now run Questa by choosing Run Simulation Tool > RTL Simulation from the Tools menu.

Note: Questa will initially fail because the success_addr generic has not been set:

Fatal: (vsim-3350) Generic "success_addr" has not been given a value.

To resolve this, copy and paste the vsim command in the Transcript window, adding a generic declaration to the end. For example:

vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev -L cyclonev_hssi -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" tb_np6532_poc_256k_altera_c5e_dev -gsuccess_addr=13417

To get the correct value of success_addr for your build, check your make transcript, or open the Compilation Report in Quartus - generic values are listed under Analysis & Synthesis > Parameter Settings by Entity Instance.

And oh yes, I want to automate all this. Watch this space.

Dependencies

This design depends on various submodules so make sure you initialise these when cloning this repo.

You will also need the following tools:

  • Xilinx Vivado or Intel Quartus Prime as appropriate

  • the ca65 assembler and ld65 linker from the cc65 toolchain (to build the test code)

  • Python 3 (to run scripts that build VHDL from binaries and tables)

The build process also needs make, git and assorted utilities that are (usually) part of Linux distros, and are most easily added to Windows by installing MSYS2.

Design Description

To be continued…​

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