This design combines a MicroBlaze CPU with a standard definition text display, similar to the text modes of a PC VGA adapter.
Supported boards: Digilent Nexys Video and QMTECH Wukong.
Two display modes are supported:
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720x480i60 - 80 x 25 characters
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720x576i50 - 80 x 32 characters
The text is held in a character buffer RAM, with 16 bits per character. The lower 8 bits hold the character code, and the upper 8 bits hold the background and foreground colour attributes. The 16 colour CGA palette is used. The border colour may also be specified.
8 x 16 pixel character patterns are used, and the character set is the well known code page 437.
A demonstration MicroBlaze application is provided. This includes a minimal printf implementation (credit to Kustaa Nyholm / SpareTimeLabs), and character attribute control.
The following instructions apply to Windows 10, and require Xilinx Vivado and Vitis version 2020.1 or later to be installed.
To create the Vivado and Vitis projects, and build the FPGA bitstream:
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Open a Windows command prompt, and change directory to the location of the repository files.
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Run the
settings64batch file from the Xilinx Vitis installation - if required - to set up your path for the Xilinx command line tools. For example:C:\> C:\Xilinx\Vitis\2020.1\settings64.bat
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Run the
xbuildbatch file, specifying the design name (mb_display_sd) and board name (nexys_videoorqmtech_wukong) as arguments, to create Vivado and Vitis projects in thexprojdirectory, and to build an FPGA bitstream. The number of parallel jobs to be used during compilation by Vivado may also be specified on the command line; this defaults to 1 if not specified. For example:C:\> cd \work\tyto_project C:\work\tyto_project> xbuild.bat mb_display_sd nexys_video 8
After the build process has completed, the Vivado and Vitis projects may be opened in their respective IDEs.
First, ensure that the FPGA board is correctly connected to the host PC and the display monitor as follows:
- Digilent Nexys Video
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Connect the PROG port to the host PC and the HDMI OUT port to the monitor.
- QMTECH Wukong
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Connect J1 to a suitable JTAG programmer (e.g. Digilent JTAG-HS2) and P3 to the monitor.
To program the bitstream into the board, run the xprog batch file, specifying the design name and board name as arguments. For example:
C:\work\tyto_project> xprog.bat hdmi_tpg nexys_video
When the programming process has completed, the monitor should display the image shown in Figure 1 above.
The diagram below shows the main design blocks:
The modules shown are described below:
- top
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A board specific wrapper around the main design.
- MAIN
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The main design.
- SYSTEM_CLOCK
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An MMCM configured to generate a 100MHz system clock from a 100MHz reference.
- CPU
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Automatically generated wrapper for a Xilinx Block Diagram that contains the MicroBlaze CPU subsystem. Refer to the MicroBlaze CPU Subsystem section below for further details.
- DISPLAY
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Top level of the display related portion of the design. Includes logic to convert the active pixel X/Y provided by the
dvi_outmodule into addresses for the character buffer and character ROM, and a shift register to serialise the character ROM data. - VIDEO_CLOCK
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Fixed frequency pixel (27MHz) and serialiser (135MHz) clock synthesiser (MMCM).
- CHAR_BUF
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Character buffer: a dual port RAM with independant 16-bit video and 32-bit CPU ports.
- CHAR_ROM
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Synchronous character ROM. The VHDL for this is automatically generated from a BMP file by the
char_rom.pyPython script. - DVI_OUT
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Top level of the DVI output module; refer to the DVI Output Subsystem section below for further details.
The dvi_out module comprises the following:
- TIMING
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Counters and logic to synthesise basic video timing.
- ENCODER
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Uses the DVI specification’s recipe to convert control signals and pixel data into 10-bit TMDS symbols.
- SERIALISER
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Converts the TMDS symbol stream from parallel to serial for each DVI output channel, and is also used to generate a DVI (pixel) clock. Drives out via SelectIO (TMDS differential) buffers.
The MicroBlaze CPU is instantiated within a Xilinx Block Diagram file:
The blocks are described below:
- cpu
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MicroBlaze CPU, 32 bit, microcontroller preset, no caches.
- ram
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64kBytes for CPU instructions and data.
- interconnect
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AXI interconnect to allow the CPU AXI master to connect to 3 AXI slaves.
- gpio
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AXI GPIO IP core, configured for 2 channels: 8 outputs on the first channel, 8 inputs on the second.
- uart
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"Lite" UART IP core, fixed at 115200N81, to provide console I/O (not used in this design).
- bram
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Bridges from an AXI Slave to an external block RAM port.
- rstctrl
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Reset controller IP core.
- debug
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CPU debug controller IP core.
If you alter the block diagram in Vivado, you will need to export a TCL script to recreate by entering the following command in the TCL Console:
write_bd_tcl -force -include_layout ../../../src/fpga/dsn/mb_display_sd/microblaze.tcl
To update the documentation, export an SVG image by entering the following command in the TCL Console:
write_bd_layout ‑force ‑format svg ../../../doc/mb_display_sd/microblaze.svg
The application initialises the display, prints a banner, and then fills the rest of the screen with coloured messages.
main.c-
The top level of the application.
printf.c,printf.h-
Small memory footprint
printf()implementation. vdu.c,vdu.h-
Text display (Video Display Unit) driver.
peekpoke.h-
Macros to access memory and registers.
The Vitis software project builds ELF files to run on the CPU. There are two configurations: Debug and Release. In the Debug configuration, the BUILD_CONFIG_DEBUG symbol is defined and may be used for conditional compilation. The Release ELF file is used to build the FPGA bitstream and runs on the hardware. The Debug ELF file is used for simulation.
In this design, the Debug and Release configurations are identical.