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np65_poc

A proof-of-concept demonstration of the np65 6502 compatible CPU core.

The core is connected to a minimal set of registers and memory is initialised with a build of Klaus Dormann’s 6502 functional test. The test is executed repeatedly, with the LED pattern incrementing each it completes successfully.

Supported boards: Digilent Nexys Video and QMTECH Wukong.

Build Procedure

The following instructions apply to Windows 10, and require Xilinx Vivado and Vitis version 2020.x to be installed.

To create the Vivado project, and build the FPGA bitstream:

  1. Open a Windows command prompt, and change directory to the location of the repository files.

  2. Run the settings64 batch file from the Xilinx Vivado installation - if required - to set up your path for the Xilinx command line tools. For example:

    C:\> C:\Xilinx\Vivado\2020.1\settings64.bat

  3. Run the xbuild batch file, specifying the design name (np65_poc_Xk where X is the memory size of the np65 core - 64, 128 or 256) and board name (nexys_video or qmtech_wukong) as arguments, to create the Vivado project in the xproj directory, and to build an FPGA bitstream. The number of parallel jobs to be used during compilation by Vivado may also be specified on the command line; this defaults to 1 if not specified. For example:

    C:\> cd \work\tyto_project
C:\work\tyto_project> xbuild.bat np65_poc_128k nexys_video 8

After the build process has completed, the Vivado project may be opened in the Vivado IDE.

Programming Procedure

First, ensure that the FPGA board is correctly connected to the host PC as follows:

Digilent Nexys Video

Connect the PROG port to the host PC.

QMTECH Wukong

Connect J1 to a suitable JTAG programmer (e.g. Digilent JTAG-HS2).

To program the bitstream into the board, run the xprog batch file, specifying the design name and board name as arguments. For example:

C:\work\tyto_project> xprog.bat np65_poc_128k nexys_video

When the programming process has completed, the board LEDs should display a pattern incrementing at approximately 1.5Hz, corresponding to a 640ms execution time for the functional test. This contrasts with ~96 seconds for a classic NMOS 6502 running at 1MHz.

Design Description

To be continued…​

Simulation

A simulation of the top level is provided as part of the Vivado project.

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