From 7800758ed771f98f3c984ae666f4c061b15aee06 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 27 Jan 2025 17:15:22 +0200 Subject: [PATCH] General updates: - Added/Updated licensce headers - Updated testbench depndencies - Updated class hierarchy Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/scoreboard.sv | 35 ++++++ library/drivers/common/scoreboard_pack.sv | 79 ++++++-------- library/drivers/common/watchdog.sv | 5 +- .../drivers/data_offload/data_offload_api.sv | 15 +-- library/drivers/dmac/dma_trans.sv | 4 +- library/drivers/dmac/dmac_api.sv | 15 +-- library/drivers/jesd/adi_jesd204_pkg.sv | 18 +-- library/drivers/xcvr/adi_xcvr_pkg.sv | 15 +-- library/includes/Makeinclude_axi.mk | 3 +- library/includes/Makeinclude_axis.mk | 2 +- library/includes/Makeinclude_common.mk | 4 +- library/includes/Makeinclude_data_offload.mk | 2 +- library/includes/Makeinclude_dmac.mk | 2 +- library/includes/Makeinclude_jesd.mk | 2 +- library/includes/Makeinclude_regmap.mk | 6 +- library/includes/Makeinclude_scoreboard.mk | 2 +- library/includes/Makeinclude_spi_engine.mk | 2 +- library/includes/Makeinclude_tdd.mk | 2 +- library/includes/Makeinclude_xcvr.mk | 2 +- library/includes/sp_include_axi.tcl | 5 +- library/includes/sp_include_axis.tcl | 4 +- library/includes/sp_include_common.tcl | 6 +- library/includes/sp_include_data_offload.tcl | 4 +- library/includes/sp_include_dmac.tcl | 4 +- library/includes/sp_include_jesd.tcl | 4 +- library/includes/sp_include_regmap.tcl | 8 +- library/includes/sp_include_scoreboard.tcl | 4 +- library/includes/sp_include_spi_engine.tcl | 4 +- library/includes/sp_include_tdd.tcl | 4 +- library/includes/sp_include_xcvr.tcl | 4 +- library/regmaps/adi_regmap_adc_pkg.sv | 2 +- library/regmaps/adi_regmap_axi_ad7616_pkg.sv | 2 +- library/regmaps/adi_regmap_clkgen_pkg.sv | 2 +- .../regmaps/adi_regmap_clock_monitor_pkg.sv | 2 +- library/regmaps/adi_regmap_common_pkg.sv | 2 +- library/regmaps/adi_regmap_dac_pkg.sv | 2 +- .../regmaps/adi_regmap_data_offload_pkg.sv | 4 +- library/regmaps/adi_regmap_dmac_pkg.sv | 2 +- library/regmaps/adi_regmap_fan_control_pkg.sv | 2 +- library/regmaps/adi_regmap_gpreg_pkg.sv | 2 +- library/regmaps/adi_regmap_hdmi_pkg.sv | 2 +- .../regmaps/adi_regmap_i3c_controller_pkg.sv | 2 +- library/regmaps/adi_regmap_iodelay_pkg.sv | 2 +- library/regmaps/adi_regmap_jesd_rx_pkg.sv | 2 +- library/regmaps/adi_regmap_jesd_tpl_pkg.sv | 2 +- library/regmaps/adi_regmap_jesd_tx_pkg.sv | 2 +- library/regmaps/adi_regmap_pkg.sv | 4 +- library/regmaps/adi_regmap_pwm_gen_pkg.sv | 2 +- library/regmaps/adi_regmap_spi_engine_pkg.sv | 2 +- library/regmaps/adi_regmap_system_id_pkg.sv | 2 +- library/regmaps/adi_regmap_tdd_gen_pkg.sv | 2 +- library/regmaps/adi_regmap_tdd_trans_pkg.sv | 2 +- library/regmaps/adi_regmap_xcvr_pkg.sv | 2 +- .../adi_api_pkg.sv} | 59 +++++----- library/utilities/adi_common_pkg.sv | 76 +------------ library/utilities/adi_datatypes.sv | 4 +- .../adi_environment_pkg.sv} | 34 +++--- .../adi_vip_pkg.sv} | 57 ++++++---- library/utilities/logger_pkg.sv | 4 +- library/utilities/pub_sub_pkg.sv | 4 +- library/utilities/test_harness_env.sv | 6 +- library/utilities/utils.svh | 4 +- library/vip/adi/io_vip/Makefile | 2 +- library/vip/adi/io_vip/io_vip.sv | 2 +- library/vip/adi/io_vip/io_vip_if.sv | 2 +- library/vip/adi/spi_vip/Makefile | 2 +- library/vip/adi/spi_vip/s_spi_sequencer.sv | 4 +- library/vip/amd/axi/adi_axi_agent.sv | 9 +- library/vip/amd/axi/adi_axi_monitor.sv | 41 ++++++- library/vip/amd/axi/axi_definitions.svh | 5 +- library/vip/amd/axi/m_axi_sequencer.sv | 103 ++++++++++++------ library/vip/amd/axi/s_axi_sequencer.sv | 72 +++++++++--- library/vip/amd/axis/adi_axis_agent.sv | 9 +- library/vip/amd/axis/adi_axis_monitor.sv | 43 +++++++- library/vip/amd/axis/axis_definitions.svh | 5 +- library/vip/amd/axis/m_axis_sequencer.sv | 42 +++---- library/vip/amd/axis/s_axis_sequencer.sv | 40 +++---- scripts/make_tb_path.mk | 2 +- scripts/project-sim.mk | 2 +- testbenches/ip/axi_tdd/Makefile | 2 +- testbenches/ip/axi_tdd/system_bd.tcl | 4 +- testbenches/ip/axi_tdd/system_tb.sv | 4 +- testbenches/ip/axi_tdd/tests/test_program.sv | 8 +- testbenches/ip/axi_tdd/waves/cfg1.wcfg | 1 - testbenches/ip/axis_sequencers/Makefile | 2 +- testbenches/ip/axis_sequencers/environment.sv | 37 ++++++- testbenches/ip/axis_sequencers/system_bd.tcl | 4 +- testbenches/ip/axis_sequencers/system_tb.sv | 4 +- .../ip/axis_sequencers/tests/test_program.sv | 16 ++- .../ip/axis_sequencers/waves/cfg1.wcfg | 1 - testbenches/ip/base/Makefile | 2 +- testbenches/ip/base/system_bd.tcl | 4 +- testbenches/ip/base/system_tb.sv | 4 +- testbenches/ip/base/tests/test_program.sv | 4 +- testbenches/ip/base/waves/cfg1.wcfg | 1 - testbenches/ip/data_offload/Makefile | 2 +- .../ip/data_offload/tests/test_program.sv | 37 ++++++- testbenches/ip/data_offload_2/Makefile | 2 +- .../ip/data_offload_2/data_offload_pkg.sv | 10 +- .../ip/data_offload_2/do_scoreboard.sv | 4 +- testbenches/ip/data_offload_2/environment.sv | 4 +- testbenches/ip/data_offload_2/system_tb.sv | 4 +- .../ip/data_offload_2/tests/test_program.sv | 8 +- .../data_offload_2/tests/test_program_sync.sv | 8 +- testbenches/ip/data_offload_2/waves/cfg1.wcfg | 1 - testbenches/ip/data_offload_2/waves/cfg2.wcfg | 1 - testbenches/ip/data_offload_2/waves/cfg3.wcfg | 2 +- testbenches/ip/data_offload_2/waves/cfg4.wcfg | 2 +- testbenches/ip/dma_flock/environment.sv | 4 +- testbenches/ip/dma_flock/scoreboard.sv | 2 +- testbenches/ip/dma_flock/system_tb.sv | 2 +- .../ip/dma_flock/tests/test_program.sv | 4 +- .../tests/test_program_frame_delay.sv | 4 +- testbenches/ip/dma_flock/waves/cfg1.wcfg | 4 +- .../ip/dma_flock/waves/cfg2_fsync.wcfg | 4 +- .../dma_flock/waves/cfg3_fsync_autorun.wcfg | 4 +- testbenches/ip/dma_loopback/Makefile | 2 +- testbenches/ip/dma_loopback/system_bd.tcl | 4 +- testbenches/ip/dma_loopback/system_tb.sv | 4 +- .../ip/dma_loopback/tests/test_program.sv | 8 +- testbenches/ip/dma_sg/system_bd.tcl | 2 +- testbenches/ip/dma_sg/system_tb.sv | 2 +- .../ip/dma_sg/tests/test_program_1d.sv | 6 +- .../ip/dma_sg/tests/test_program_2d.sv | 6 +- .../ip/dma_sg/tests/test_program_tr_queue.sv | 6 +- testbenches/ip/dma_sg/waves/cfg1.wcfg | 4 +- testbenches/ip/dma_sg/waves/cfg2.wcfg | 4 +- testbenches/ip/hbm/Makefile | 2 +- testbenches/ip/hbm/system_bd.tcl | 4 +- testbenches/ip/hbm/system_tb.sv | 4 +- testbenches/ip/hbm/tests/test_program.sv | 8 +- .../ip/i3c_controller/tests/test_program.sv | 4 +- testbenches/ip/i3c_controller/waves/cfg1.wcfg | 2 +- testbenches/ip/jesd_loopback/Makefile | 2 +- testbenches/ip/jesd_loopback/system_bd.tcl | 4 +- testbenches/ip/jesd_loopback/system_tb.sv | 4 +- .../ip/jesd_loopback/tests/test_program.sv | 8 +- testbenches/ip/jesd_loopback/waves/cfg1.wcfg | 4 +- testbenches/ip/jesd_loopback_64b/Makefile | 2 +- .../ip/jesd_loopback_64b/system_bd.tcl | 4 +- testbenches/ip/jesd_loopback_64b/system_tb.sv | 4 +- .../jesd_loopback_64b/tests/test_program.sv | 8 +- testbenches/ip/scoreboard/Makefile | 2 +- testbenches/ip/scoreboard/environment.sv | 39 ++++++- testbenches/ip/scoreboard/system_bd.tcl | 4 +- testbenches/ip/scoreboard/system_tb.sv | 4 +- .../ip/scoreboard/tests/test_program.sv | 8 +- testbenches/ip/scoreboard/waves/cfg1.wcfg | 4 +- testbenches/ip/spi_engine/Makefile | 4 +- testbenches/ip/spi_engine/spi_environment.sv | 2 +- testbenches/ip/spi_engine/system_tb.sv | 4 +- .../ip/spi_engine/tests/test_program.sv | 4 +- testbenches/ip/spi_engine/waves/cfg1.wcfg | 2 +- .../ip/spi_engine/waves/cfg_inv_cs.wcfg | 2 +- .../spi_engine/waves/cfg_sdo_streaming.wcfg | 2 +- testbenches/ip/util_axis_fifo/Makefile | 2 +- testbenches/ip/util_axis_fifo/environment.sv | 37 ++++++- testbenches/ip/util_axis_fifo/system_bd.tcl | 4 +- testbenches/ip/util_axis_fifo/system_tb.sv | 4 +- .../ip/util_axis_fifo/tests/test_program.sv | 12 +- .../ip/util_axis_fifo/waves/cfg_rand.wcfg | 2 +- testbenches/ip/util_axis_fifo_asym/Makefile | 2 +- .../ip/util_axis_fifo_asym/environment.sv | 37 ++++++- .../ip/util_axis_fifo_asym/system_bd.tcl | 4 +- .../ip/util_axis_fifo_asym/system_tb.sv | 4 +- .../util_axis_fifo_asym/tests/test_program.sv | 12 +- .../util_axis_fifo_asym/waves/cfg_rand.wcfg | 2 +- testbenches/ip/util_pack/Makefile | 2 +- testbenches/ip/util_pack/environment.sv | 41 ++++++- testbenches/ip/util_pack/system_bd.tcl | 4 +- testbenches/ip/util_pack/system_tb.sv | 4 +- .../ip/util_pack/tests/test_program.sv | 8 +- testbenches/ip/util_pack/waves/cfg1.wcfg | 4 +- testbenches/ip/util_pack/waves/cfg_rand.wcfg | 4 +- testbenches/project/ad463x/Makefile | 5 +- testbenches/project/ad463x/system_bd.tcl | 4 +- testbenches/project/ad463x/system_tb.sv | 4 +- .../project/ad463x/tests/test_program.sv | 4 +- testbenches/project/ad57xx/Makefile | 4 +- .../project/ad57xx/ad57xx_environment.sv | 4 +- testbenches/project/ad57xx/system_bd.tcl | 2 +- testbenches/project/ad57xx/waves/cfg1.wcfg | 2 +- testbenches/project/ad738x/Makefile | 4 +- testbenches/project/ad738x/system_bd.tcl | 4 +- testbenches/project/ad738x/system_tb.sv | 4 +- .../project/ad738x/tests/test_program.sv | 4 +- testbenches/project/ad7606x/Makefile | 4 +- testbenches/project/ad7606x/system_bd.tcl | 4 +- testbenches/project/ad7606x/system_tb.sv | 4 +- .../project/ad7606x/tests/test_program_4ch.sv | 4 +- .../project/ad7606x/tests/test_program_6ch.sv | 4 +- .../project/ad7606x/tests/test_program_8ch.sv | 4 +- .../project/ad7606x/tests/test_program_si.sv | 4 +- .../ad7606x/waves/system_tb_behav.wcfg | 2 +- testbenches/project/ad7616/Makefile | 4 +- testbenches/project/ad7616/system_bd.tcl | 4 +- testbenches/project/ad7616/system_tb.sv | 4 +- .../project/ad7616/tests/test_program_pi.sv | 4 +- .../project/ad7616/tests/test_program_si.sv | 4 +- testbenches/project/ad7616/waves/cfg_pi.wcfg | 2 +- testbenches/project/ad7616/waves/cfg_si.wcfg | 2 +- testbenches/project/ad9083/Makefile | 4 +- testbenches/project/ad9083/system_bd.tcl | 4 +- testbenches/project/ad9083/system_tb.sv | 4 +- .../project/ad9083/tests/test_program.sv | 8 +- testbenches/project/ad_quadmxfe1_ebz/Makefile | 4 +- .../project/ad_quadmxfe1_ebz/system_bd.tcl | 4 +- .../project/ad_quadmxfe1_ebz/system_tb.sv | 4 +- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 8 +- .../ad_quadmxfe1_ebz/tests/test_program.sv | 8 +- .../tests/test_program_64b66b.sv | 8 +- testbenches/project/adrv9001/Makefile | 4 +- testbenches/project/adrv9001/system_bd.tcl | 4 +- testbenches/project/adrv9001/system_tb.sv | 4 +- .../project/adrv9001/tests/test_program.sv | 8 +- testbenches/project/adrv9009/Makefile | 4 +- testbenches/project/adrv9009/system_bd.tcl | 2 +- testbenches/project/adrv9009/system_tb.sv | 2 +- .../project/adrv9009/tests/test_program.sv | 6 +- testbenches/project/adrv9009/waves/cfg1.wcfg | 4 +- testbenches/project/fmcomms2/Makefile | 4 +- testbenches/project/fmcomms2/system_bd.tcl | 4 +- testbenches/project/fmcomms2/system_tb.sv | 4 +- .../project/fmcomms2/tests/test_program.sv | 8 +- testbenches/project/mxfe/Makefile | 4 +- testbenches/project/mxfe/system_bd.tcl | 4 +- testbenches/project/mxfe/system_tb.sv | 4 +- .../project/mxfe/tests/test_program.sv | 8 +- testbenches/project/mxfe/waves/cfg1.wcfg | 4 +- testbenches/project/pluto/system_bd.tcl | 2 +- testbenches/project/pluto/system_tb.sv | 2 +- .../project/pluto/tests/test_program.sv | 6 +- testbenches/project/pluto/waves/cfg1.wcfg | 2 +- testbenches/project/pulsar_adc_pmdz/Makefile | 4 +- .../project/pulsar_adc_pmdz/spi_engine.svh | 4 +- .../project/pulsar_adc_pmdz/system_bd.tcl | 4 +- .../project/pulsar_adc_pmdz/system_tb.sv | 4 +- .../pulsar_adc_pmdz/tests/test_program.sv | 4 +- .../project/pulsar_adc_pmdz/waves/cfg1.wcfg | 2 +- 239 files changed, 1033 insertions(+), 780 deletions(-) rename library/{regmaps/adi_peripheral_pkg.sv => utilities/adi_api_pkg.sv} (76%) rename library/{drivers/common/interfaces.svh => utilities/adi_environment_pkg.sv} (76%) rename library/{regmaps/reg_accessor.sv => utilities/adi_vip_pkg.sv} (63%) diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index 7c1ccc0d..b2d54f43 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package scoreboard_pkg; diff --git a/library/drivers/common/scoreboard_pack.sv b/library/drivers/common/scoreboard_pack.sv index cd6020b1..25b3c15c 100644 --- a/library/drivers/common/scoreboard_pack.sv +++ b/library/drivers/common/scoreboard_pack.sv @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package scoreboard_pack_pkg; @@ -49,50 +84,6 @@ package scoreboard_pack_pkg; if (this.enabled == 0) return; - - // forever begin : tx_path - // if (this.enabled == 0) - // break; - // if ((this.source_byte_stream_size > 0) && - // (this.sink_byte_stream_size >= this.channels*this.samples*this.width/8)) begin - // byte_streams_empty_sig = 0; - // for (int i=0; i>byte_streams_empty; - // end - // fork begin - // fork - // @source_transaction_event; - // @sink_transaction_event; - // @stop_scoreboard; - // join_any - // byte_streams_empty_sig = 0; - // disable fork; - // end join - // end - // end while ((this.subscriber_source.get_size() > 0) && (this.subscriber_sink.get_size() >= this.channels*this.samples*this.width/8)) begin diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv index 5d377358..94f270cb 100644 --- a/library/drivers/common/watchdog.sv +++ b/library/drivers/common/watchdog.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,12 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** + `include "utils.svh" package watchdog_pkg; diff --git a/library/drivers/data_offload/data_offload_api.sv b/library/drivers/data_offload/data_offload_api.sv index c36ef999..4a036f7f 100644 --- a/library/drivers/data_offload/data_offload_api.sv +++ b/library/drivers/data_offload/data_offload_api.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -38,19 +38,20 @@ package data_offload_api_pkg; import logger_pkg::*; - import adi_peripheral_pkg::*; - import adi_regmap_data_offload_pkg::*; + import adi_common_pkg::*; + import adi_api_pkg::*; import adi_regmap_pkg::*; - import reg_accessor_pkg::*; + import adi_regmap_data_offload_pkg::*; + import m_axi_sequencer_pkg::*; - class data_offload_api extends adi_peripheral; + class data_offload_api extends adi_api; // ----------------- // // ----------------- function new( input string name, - input reg_accessor bus, + input m_axi_sequencer_base bus, input bit [31:0] base_address, input adi_component parent = null); diff --git a/library/drivers/dmac/dma_trans.sv b/library/drivers/dmac/dma_trans.sv index 23cebbe2..e66b26b6 100644 --- a/library/drivers/dmac/dma_trans.sv +++ b/library/drivers/dmac/dma_trans.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018, 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/drivers/dmac/dmac_api.sv b/library/drivers/dmac/dmac_api.sv index 1f676e9a..fe28abd6 100644 --- a/library/drivers/dmac/dmac_api.sv +++ b/library/drivers/dmac/dmac_api.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018, 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -38,13 +38,14 @@ package dmac_api_pkg; import logger_pkg::*; - import adi_peripheral_pkg::*; - import adi_regmap_dmac_pkg::*; + import adi_common_pkg::*; + import adi_api_pkg::*; import adi_regmap_pkg::*; - import reg_accessor_pkg::*; + import adi_regmap_dmac_pkg::*; + import m_axi_sequencer_pkg::*; import dma_trans_pkg::*; - class dmac_api extends adi_peripheral; + class dmac_api extends adi_api; // DMAC parameters axi_dmac_params_t p; @@ -54,7 +55,7 @@ package dmac_api_pkg; // ----------------- function new( input string name, - input reg_accessor bus, + input m_axi_sequencer_base bus, input bit [31:0] base_address, input adi_component parent = null); diff --git a/library/drivers/jesd/adi_jesd204_pkg.sv b/library/drivers/jesd/adi_jesd204_pkg.sv index bea6f505..457aab58 100644 --- a/library/drivers/jesd/adi_jesd204_pkg.sv +++ b/library/drivers/jesd/adi_jesd204_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,19 +26,21 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** + `include "utils.svh" package adi_jesd204_pkg; import logger_pkg::*; - import adi_peripheral_pkg::*; - import reg_accessor_pkg::*; + import adi_common_pkg::*; + import adi_api_pkg::*; + import m_axi_sequencer_pkg::*; import adi_regmap_pkg::*; import adi_regmap_jesd_tx_pkg::*; import adi_regmap_jesd_rx_pkg::*; @@ -181,7 +183,7 @@ package adi_jesd204_pkg; //============================================================================ // Base Link layer class //============================================================================ - class link_layer extends adi_peripheral; + class link_layer extends adi_api; jesd_link link; int dp_width = 4; // Data width towards Phy @@ -196,7 +198,7 @@ package adi_jesd204_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link); + function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link); super.new(name, bus, base_address); this.link = link; @@ -273,7 +275,7 @@ package adi_jesd204_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link); + function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link); super.new(name, bus, base_address, link); endfunction @@ -433,7 +435,7 @@ package adi_jesd204_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link); + function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link); super.new(name, bus, base_address, link); endfunction diff --git a/library/drivers/xcvr/adi_xcvr_pkg.sv b/library/drivers/xcvr/adi_xcvr_pkg.sv index e31576c0..6dfed2fe 100644 --- a/library/drivers/xcvr/adi_xcvr_pkg.sv +++ b/library/drivers/xcvr/adi_xcvr_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,22 +26,23 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on_line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** + `include "utils.svh" package adi_xcvr_pkg; import logger_pkg::*; - import adi_peripheral_pkg::*; - import reg_accessor_pkg::*; + import adi_common_pkg::*; + import adi_api_pkg::*; + import m_axi_sequencer_pkg::*; import adi_regmap_pkg::*; import adi_regmap_xcvr_pkg::*; - import adi_jesd204_pkg::*; typedef enum bit [2:0] { OUTCLKPCS = 1, @@ -285,7 +286,7 @@ package adi_xcvr_pkg; //============================================================================ // Xilinx XCVR class //============================================================================ - class xcvr extends adi_peripheral; + class xcvr extends adi_api; // Capabilities bit qpll_enable; @@ -299,7 +300,7 @@ package adi_xcvr_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address); + function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address); super.new(name, bus, base_address); endfunction diff --git a/library/includes/Makeinclude_axi.mk b/library/includes/Makeinclude_axi.mk index 8a1b27c8..5db1b2d8 100644 --- a/library/includes/Makeinclude_axi.mk +++ b/library/includes/Makeinclude_axi.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 - 2025 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -9,4 +9,3 @@ SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/s_axi_sequencer.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_monitor.sv SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/axi_definitions.svh SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv -SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv diff --git a/library/includes/Makeinclude_axis.mk b/library/includes/Makeinclude_axis.mk index 5810ebd7..2ecbf0d1 100644 --- a/library/includes/Makeinclude_axis.mk +++ b/library/includes/Makeinclude_axis.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_common.mk b/library/includes/Makeinclude_common.mk index 8a0ea7eb..10ae4c67 100644 --- a/library/includes/Makeinclude_common.mk +++ b/library/includes/Makeinclude_common.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 - 2025 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -9,6 +9,8 @@ include $(TB_LIBRARY_PATH)/includes/Makeinclude_axi.mk SV_DEPS += $(TB_LIBRARY_PATH)/utilities/utils.svh SV_DEPS += $(TB_LIBRARY_PATH)/utilities/logger_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_common_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_vip_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_environment_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/utilities/test_harness_env.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/watchdog.sv diff --git a/library/includes/Makeinclude_data_offload.mk b/library/includes/Makeinclude_data_offload.mk index bec4f316..fb2c6111 100644 --- a/library/includes/Makeinclude_data_offload.mk +++ b/library/includes/Makeinclude_data_offload.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_dmac.mk b/library/includes/Makeinclude_dmac.mk index 5c43ce10..291e67d5 100644 --- a/library/includes/Makeinclude_dmac.mk +++ b/library/includes/Makeinclude_dmac.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_jesd.mk b/library/includes/Makeinclude_jesd.mk index 3f8889e2..e1af70d9 100644 --- a/library/includes/Makeinclude_jesd.mk +++ b/library/includes/Makeinclude_jesd.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_regmap.mk b/library/includes/Makeinclude_regmap.mk index 30977cc9..8ad04899 100644 --- a/library/includes/Makeinclude_regmap.mk +++ b/library/includes/Makeinclude_regmap.mk @@ -1,8 +1,8 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 - 2025 Analog Devices, Inc. #################################################################################### #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv -SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_peripheral_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_common_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/adi_api_pkg.sv diff --git a/library/includes/Makeinclude_scoreboard.mk b/library/includes/Makeinclude_scoreboard.mk index 3fd4e67a..76c8c8b0 100644 --- a/library/includes/Makeinclude_scoreboard.mk +++ b/library/includes/Makeinclude_scoreboard.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_spi_engine.mk b/library/includes/Makeinclude_spi_engine.mk index 1c0af3b0..543c325f 100644 --- a/library/includes/Makeinclude_spi_engine.mk +++ b/library/includes/Makeinclude_spi_engine.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_tdd.mk b/library/includes/Makeinclude_tdd.mk index 0d078b04..60f6a7d3 100644 --- a/library/includes/Makeinclude_tdd.mk +++ b/library/includes/Makeinclude_tdd.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/Makeinclude_xcvr.mk b/library/includes/Makeinclude_xcvr.mk index 23dc8402..b041e70c 100644 --- a/library/includes/Makeinclude_xcvr.mk +++ b/library/includes/Makeinclude_xcvr.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/library/includes/sp_include_axi.tcl b/library/includes/sp_include_axi.tcl index 89aaa064..50885ff7 100644 --- a/library/includes/sp_include_axi.tcl +++ b/library/includes/sp_include_axi.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # @@ -41,5 +41,4 @@ adi_sim_project_files [list \ "$ad_tb_dir/library/vip/amd/axi/adi_axi_monitor.sv" \ "$ad_tb_dir/library/vip/amd/axi/axi_definitions.svh" \ "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ - "$ad_tb_dir/library/regmaps/reg_accessor.sv" \ ] diff --git a/library/includes/sp_include_axis.tcl b/library/includes/sp_include_axis.tcl index 50532616..28a261dd 100644 --- a/library/includes/sp_include_axis.tcl +++ b/library/includes/sp_include_axis.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_common.tcl b/library/includes/sp_include_common.tcl index ec70bb7f..d0548016 100644 --- a/library/includes/sp_include_common.tcl +++ b/library/includes/sp_include_common.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # @@ -40,6 +40,8 @@ adi_sim_project_files [list \ "$ad_tb_dir/library/utilities/utils.svh" \ "$ad_tb_dir/library/utilities/logger_pkg.sv" \ "$ad_tb_dir/library/utilities/adi_common_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_vip_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_environment_pkg.sv" \ "$ad_tb_dir/library/utilities/test_harness_env.sv" \ "$ad_tb_dir/library/drivers/common/watchdog.sv" \ "system_tb.sv" \ diff --git a/library/includes/sp_include_data_offload.tcl b/library/includes/sp_include_data_offload.tcl index e1a8c2c2..206af6b6 100644 --- a/library/includes/sp_include_data_offload.tcl +++ b/library/includes/sp_include_data_offload.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_dmac.tcl b/library/includes/sp_include_dmac.tcl index 511727c1..9d6a9038 100644 --- a/library/includes/sp_include_dmac.tcl +++ b/library/includes/sp_include_dmac.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_jesd.tcl b/library/includes/sp_include_jesd.tcl index e768ea17..f12665f6 100644 --- a/library/includes/sp_include_jesd.tcl +++ b/library/includes/sp_include_jesd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_regmap.tcl b/library/includes/sp_include_regmap.tcl index 583fbde0..7a4f27dc 100644 --- a/library/includes/sp_include_regmap.tcl +++ b/library/includes/sp_include_regmap.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # @@ -35,7 +35,7 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/regmaps/reg_accessor.sv" \ - "$ad_tb_dir/library/regmaps/adi_peripheral_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_common_pkg.sv" \ "$ad_tb_dir/library/regmaps/adi_regmap_pkg.sv" \ + "$ad_tb_dir/library/utilities/adi_api_pkg.sv" \ ] diff --git a/library/includes/sp_include_scoreboard.tcl b/library/includes/sp_include_scoreboard.tcl index 03ac1a8b..22fd1cc9 100644 --- a/library/includes/sp_include_scoreboard.tcl +++ b/library/includes/sp_include_scoreboard.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_spi_engine.tcl b/library/includes/sp_include_spi_engine.tcl index 114a5561..f090ec45 100644 --- a/library/includes/sp_include_spi_engine.tcl +++ b/library/includes/sp_include_spi_engine.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_tdd.tcl b/library/includes/sp_include_tdd.tcl index 38a8b855..08ffa379 100644 --- a/library/includes/sp_include_tdd.tcl +++ b/library/includes/sp_include_tdd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/includes/sp_include_xcvr.tcl b/library/includes/sp_include_xcvr.tcl index 6e27586a..8ca8ac85 100644 --- a/library/includes/sp_include_xcvr.tcl +++ b/library/includes/sp_include_xcvr.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/library/regmaps/adi_regmap_adc_pkg.sv b/library/regmaps/adi_regmap_adc_pkg.sv index 3a110dcc..51eb3e15 100644 --- a/library/regmaps/adi_regmap_adc_pkg.sv +++ b/library/regmaps/adi_regmap_adc_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_axi_ad7616_pkg.sv b/library/regmaps/adi_regmap_axi_ad7616_pkg.sv index 45b3c0a4..4ceaf753 100644 --- a/library/regmaps/adi_regmap_axi_ad7616_pkg.sv +++ b/library/regmaps/adi_regmap_axi_ad7616_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_clkgen_pkg.sv b/library/regmaps/adi_regmap_clkgen_pkg.sv index ad66325b..784753a7 100644 --- a/library/regmaps/adi_regmap_clkgen_pkg.sv +++ b/library/regmaps/adi_regmap_clkgen_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_clock_monitor_pkg.sv b/library/regmaps/adi_regmap_clock_monitor_pkg.sv index e5cc8fb5..74d472d2 100644 --- a/library/regmaps/adi_regmap_clock_monitor_pkg.sv +++ b/library/regmaps/adi_regmap_clock_monitor_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_common_pkg.sv b/library/regmaps/adi_regmap_common_pkg.sv index 002feb30..fe201938 100644 --- a/library/regmaps/adi_regmap_common_pkg.sv +++ b/library/regmaps/adi_regmap_common_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_dac_pkg.sv b/library/regmaps/adi_regmap_dac_pkg.sv index 912d3aa7..4fa4bad6 100644 --- a/library/regmaps/adi_regmap_dac_pkg.sv +++ b/library/regmaps/adi_regmap_dac_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_data_offload_pkg.sv b/library/regmaps/adi_regmap_data_offload_pkg.sv index 3142b6d6..e351cb61 100644 --- a/library/regmaps/adi_regmap_data_offload_pkg.sv +++ b/library/regmaps/adi_regmap_data_offload_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/regmaps/adi_regmap_dmac_pkg.sv b/library/regmaps/adi_regmap_dmac_pkg.sv index a893c0c2..973ecdde 100644 --- a/library/regmaps/adi_regmap_dmac_pkg.sv +++ b/library/regmaps/adi_regmap_dmac_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_fan_control_pkg.sv b/library/regmaps/adi_regmap_fan_control_pkg.sv index a70ef05c..e0f39185 100644 --- a/library/regmaps/adi_regmap_fan_control_pkg.sv +++ b/library/regmaps/adi_regmap_fan_control_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_gpreg_pkg.sv b/library/regmaps/adi_regmap_gpreg_pkg.sv index 95b5efdb..6ecb347a 100644 --- a/library/regmaps/adi_regmap_gpreg_pkg.sv +++ b/library/regmaps/adi_regmap_gpreg_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_hdmi_pkg.sv b/library/regmaps/adi_regmap_hdmi_pkg.sv index 38f24daa..028114b3 100644 --- a/library/regmaps/adi_regmap_hdmi_pkg.sv +++ b/library/regmaps/adi_regmap_hdmi_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_i3c_controller_pkg.sv b/library/regmaps/adi_regmap_i3c_controller_pkg.sv index f4587188..37fa8736 100644 --- a/library/regmaps/adi_regmap_i3c_controller_pkg.sv +++ b/library/regmaps/adi_regmap_i3c_controller_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_iodelay_pkg.sv b/library/regmaps/adi_regmap_iodelay_pkg.sv index 89ced2f4..26722c93 100644 --- a/library/regmaps/adi_regmap_iodelay_pkg.sv +++ b/library/regmaps/adi_regmap_iodelay_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_jesd_rx_pkg.sv b/library/regmaps/adi_regmap_jesd_rx_pkg.sv index 1c8371a3..cf1943ec 100644 --- a/library/regmaps/adi_regmap_jesd_rx_pkg.sv +++ b/library/regmaps/adi_regmap_jesd_rx_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_jesd_tpl_pkg.sv b/library/regmaps/adi_regmap_jesd_tpl_pkg.sv index fb6ccb77..07f12cd6 100644 --- a/library/regmaps/adi_regmap_jesd_tpl_pkg.sv +++ b/library/regmaps/adi_regmap_jesd_tpl_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_jesd_tx_pkg.sv b/library/regmaps/adi_regmap_jesd_tx_pkg.sv index 4e99b5ce..577b10b0 100644 --- a/library/regmaps/adi_regmap_jesd_tx_pkg.sv +++ b/library/regmaps/adi_regmap_jesd_tx_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_pkg.sv b/library/regmaps/adi_regmap_pkg.sv index c67e1cf3..048c1c1e 100644 --- a/library/regmaps/adi_regmap_pkg.sv +++ b/library/regmaps/adi_regmap_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/regmaps/adi_regmap_pwm_gen_pkg.sv b/library/regmaps/adi_regmap_pwm_gen_pkg.sv index 3ebddf50..5914ec5a 100644 --- a/library/regmaps/adi_regmap_pwm_gen_pkg.sv +++ b/library/regmaps/adi_regmap_pwm_gen_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_spi_engine_pkg.sv b/library/regmaps/adi_regmap_spi_engine_pkg.sv index 830bb3a7..9b264790 100644 --- a/library/regmaps/adi_regmap_spi_engine_pkg.sv +++ b/library/regmaps/adi_regmap_spi_engine_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_system_id_pkg.sv b/library/regmaps/adi_regmap_system_id_pkg.sv index 81d4abad..dd6f5580 100644 --- a/library/regmaps/adi_regmap_system_id_pkg.sv +++ b/library/regmaps/adi_regmap_system_id_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_tdd_gen_pkg.sv b/library/regmaps/adi_regmap_tdd_gen_pkg.sv index 018fa140..587eb02d 100644 --- a/library/regmaps/adi_regmap_tdd_gen_pkg.sv +++ b/library/regmaps/adi_regmap_tdd_gen_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_tdd_trans_pkg.sv b/library/regmaps/adi_regmap_tdd_trans_pkg.sv index 0f42437b..38f0bd33 100644 --- a/library/regmaps/adi_regmap_tdd_trans_pkg.sv +++ b/library/regmaps/adi_regmap_tdd_trans_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_regmap_xcvr_pkg.sv b/library/regmaps/adi_regmap_xcvr_pkg.sv index 8832b038..5a48c027 100644 --- a/library/regmaps/adi_regmap_xcvr_pkg.sv +++ b/library/regmaps/adi_regmap_xcvr_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/regmaps/adi_peripheral_pkg.sv b/library/utilities/adi_api_pkg.sv similarity index 76% rename from library/regmaps/adi_peripheral_pkg.sv rename to library/utilities/adi_api_pkg.sv index 26ed9a24..f3c5bde9 100644 --- a/library/regmaps/adi_peripheral_pkg.sv +++ b/library/utilities/adi_api_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,62 +26,51 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** + `include "utils.svh" -package adi_peripheral_pkg; +package adi_api_pkg; import logger_pkg::*; import adi_common_pkg::*; - import reg_accessor_pkg::*; + import m_axi_sequencer_pkg::*; - //============================================================================ - // Base peripheral class - //============================================================================ - class adi_peripheral extends adi_component; - reg_accessor bus; - bit [31:0] base_address; + class adi_api extends adi_component; + + protected m_axi_sequencer_base bus; + protected bit [31:0] base_address; // Semantic versioning bit [7:0] ver_major; bit [7:0] ver_minor; bit [7:0] ver_patch; - string name; - - // ----------------- - // - // ----------------- function new( input string name, - input reg_accessor bus, + input m_axi_sequencer_base bus, input bit [31:0] base_address, input adi_component parent = null); super.new(name, parent); - + this.bus = bus; this.base_address = base_address; - endfunction + endfunction: new + - // ----------------- - // - // ----------------- virtual task probe(); bit [31:0] val; this.bus.RegRead32(this.base_address + 'h0, val); {ver_major, ver_minor, ver_patch} = val; this.info($sformatf("Found peripheral version: %0d.%0d.%s", ver_major, ver_minor, ver_patch), ADI_VERBOSITY_HIGH); endtask - - // ----------------- - // - // ----------------- + task axi_read( input [31:0] addr, output [31:0] data); @@ -89,9 +78,6 @@ package adi_peripheral_pkg; this.bus.RegRead32(this.base_address + addr, data); endtask: axi_read - // ----------------- - // - // ----------------- task axi_write( input [31:0] addr, input [31:0] data); @@ -99,9 +85,6 @@ package adi_peripheral_pkg; this.bus.RegWrite32(this.base_address + addr, data); endtask: axi_write - // ----------------- - // - // ----------------- task axi_verify( input [31:0] addr, input [31:0] data); @@ -109,6 +92,16 @@ package adi_peripheral_pkg; this.bus.RegReadVerify32(this.base_address + addr, data); endtask: axi_verify - endclass + endclass: adi_api + + + class adi_regmap extends adi_component; + function new( + input string name, + input adi_api parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_regmap -endpackage +endpackage: adi_api_pkg diff --git a/library/utilities/adi_common_pkg.sv b/library/utilities/adi_common_pkg.sv index 5b3d2464..6edf6bc7 100644 --- a/library/utilities/adi_common_pkg.sv +++ b/library/utilities/adi_common_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -88,74 +88,4 @@ package adi_common_pkg; endfunction: new endclass: adi_component - - class adi_environment extends adi_component; - function new( - input string name, - input adi_environment parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_environment - - - class adi_api extends adi_component; - function new( - input string name, - input adi_component parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_api - - - class adi_regmap extends adi_component; - function new( - input string name, - input adi_api parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_regmap - - - class adi_agent extends adi_component; - function new( - input string name, - input adi_environment parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_agent - - - class adi_driver extends adi_component; - function new( - input string name, - input adi_agent parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_driver - - - class adi_sequencer extends adi_component; - function new( - input string name, - input adi_agent parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_sequencer - - - class adi_monitor extends adi_component; - function new( - input string name, - input adi_agent parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_monitor - -endpackage +endpackage: adi_common_pkg diff --git a/library/utilities/adi_datatypes.sv b/library/utilities/adi_datatypes.sv index 45219c0a..73c63dc9 100644 --- a/library/utilities/adi_datatypes.sv +++ b/library/utilities/adi_datatypes.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/drivers/common/interfaces.svh b/library/utilities/adi_environment_pkg.sv similarity index 76% rename from library/drivers/common/interfaces.svh rename to library/utilities/adi_environment_pkg.sv index a7a2d397..c57ab8e9 100644 --- a/library/drivers/common/interfaces.svh +++ b/library/utilities/adi_environment_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,28 +26,28 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -`ifndef _INTERFACES_SVH_ -`define _INTERFACES_SVH_ +`include "utils.svh" -interface clk_if (); - logic clk; +package adi_environment_pkg; - task start_clock(int clk_period); - clk = 1'b1; - fork - forever begin - #((clk_period / 2)*1ps); - clk = ~clk; - end - join_none - endtask: start_clock -endinterface: clk_if + import logger_pkg::*; + import adi_common_pkg::*; + import adi_environment_pkg::*; -`endif + class adi_environment extends adi_component; + function new( + input string name, + input adi_environment parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_environment + +endpackage: adi_environment_pkg diff --git a/library/regmaps/reg_accessor.sv b/library/utilities/adi_vip_pkg.sv similarity index 63% rename from library/regmaps/reg_accessor.sv rename to library/utilities/adi_vip_pkg.sv index ab6ad68f..b33cca46 100644 --- a/library/regmaps/reg_accessor.sv +++ b/library/utilities/adi_vip_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,39 +26,58 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -package reg_accessor_pkg; +`include "utils.svh" - import axi_vip_pkg::*; +package adi_vip_pkg; + + import logger_pkg::*; import adi_common_pkg::*; + import adi_environment_pkg::*; + + class adi_agent extends adi_component; + function new( + input string name, + input adi_environment parent = null); - class reg_accessor extends adi_component; + super.new(name, parent); + endfunction: new + endclass: adi_agent + + class adi_driver extends adi_component; function new( input string name, - input adi_component parent = null); - + input adi_agent parent = null); + super.new(name, parent); - endfunction + endfunction: new + endclass: adi_driver + + + class adi_sequencer extends adi_component; + function new( + input string name, + input adi_agent parent = null); - virtual task automatic RegWrite32(input xil_axi_ulong addr =0, - input bit [31:0] data); - endtask: RegWrite32 + super.new(name, parent); + endfunction: new + endclass: adi_sequencer - virtual task automatic RegRead32(input xil_axi_ulong addr =0, - output bit [31:0] data); - endtask: RegRead32 - virtual task automatic RegReadVerify32(input xil_axi_ulong addr =0, - input bit [31:0] data); - endtask: RegReadVerify32 + class adi_monitor extends adi_component; + function new( + input string name, + input adi_agent parent = null); - endclass + super.new(name, parent); + endfunction: new + endclass: adi_monitor -endpackage +endpackage: adi_vip_pkg diff --git a/library/utilities/logger_pkg.sv b/library/utilities/logger_pkg.sv index 6db5d3cb..0f610791 100644 --- a/library/utilities/logger_pkg.sv +++ b/library/utilities/logger_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/utilities/pub_sub_pkg.sv b/library/utilities/pub_sub_pkg.sv index 570395a6..96044b7f 100644 --- a/library/utilities/pub_sub_pkg.sv +++ b/library/utilities/pub_sub_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 50c2566f..17545cbe 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,7 +39,7 @@ package test_harness_env_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import adi_axi_agent_pkg::*; diff --git a/library/utilities/utils.svh b/library/utilities/utils.svh index 03a240df..804a60d8 100644 --- a/library/utilities/utils.svh +++ b/library/utilities/utils.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/vip/adi/io_vip/Makefile b/library/vip/adi/io_vip/Makefile index 8e61c693..99cf89e5 100644 --- a/library/vip/adi/io_vip/Makefile +++ b/library/vip/adi/io_vip/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2024 Analog Devices, Inc. +## Copyright (C) 2018 - 2024 Analog Devices, Inc. ## Auto-generated, do not modify! #################################################################################### diff --git a/library/vip/adi/io_vip/io_vip.sv b/library/vip/adi/io_vip/io_vip.sv index 62eb8f65..70c491c2 100644 --- a/library/vip/adi/io_vip/io_vip.sv +++ b/library/vip/adi/io_vip/io_vip.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/vip/adi/io_vip/io_vip_if.sv b/library/vip/adi/io_vip/io_vip_if.sv index c9fb7dac..7ec2fa9e 100644 --- a/library/vip/adi/io_vip/io_vip_if.sv +++ b/library/vip/adi/io_vip/io_vip_if.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/vip/adi/spi_vip/Makefile b/library/vip/adi/spi_vip/Makefile index 890ed530..4be1d86f 100644 --- a/library/vip/adi/spi_vip/Makefile +++ b/library/vip/adi/spi_vip/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2024 Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### diff --git a/library/vip/adi/spi_vip/s_spi_sequencer.sv b/library/vip/adi/spi_vip/s_spi_sequencer.sv index 79112770..bb0a2d73 100644 --- a/library/vip/adi/spi_vip/s_spi_sequencer.sv +++ b/library/vip/adi/spi_vip/s_spi_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/library/vip/amd/axi/adi_axi_agent.sv b/library/vip/amd/axi/adi_axi_agent.sv index ea969ff8..90b77e56 100644 --- a/library/vip/amd/axi/adi_axi_agent.sv +++ b/library/vip/amd/axi/adi_axi_agent.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,7 +39,8 @@ package adi_axi_agent_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; + import adi_environment_pkg::*; import axi_vip_pkg::*; import m_axi_sequencer_pkg::*; import s_axi_sequencer_pkg::*; @@ -150,4 +151,4 @@ package adi_axi_agent_pkg; endclass: adi_axi_passthrough_mem_agent -endpackage +endpackage: adi_axi_agent_pkg diff --git a/library/vip/amd/axi/adi_axi_monitor.sv b/library/vip/amd/axi/adi_axi_monitor.sv index 3603af7f..8c440d22 100644 --- a/library/vip/amd/axi/adi_axi_monitor.sv +++ b/library/vip/amd/axi/adi_axi_monitor.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package adi_axi_monitor_pkg; import axi_vip_pkg::*; import logger_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import pub_sub_pkg::*; class adi_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends adi_monitor; @@ -97,6 +132,6 @@ package adi_axi_monitor_pkg; end endtask: get_transaction - endclass + endclass: adi_axi_monitor -endpackage +endpackage: adi_axi_monitor_pkg diff --git a/library/vip/amd/axi/axi_definitions.svh b/library/vip/amd/axi/axi_definitions.svh index 93f026e5..bc8a2372 100644 --- a/library/vip/amd/axi/axi_definitions.svh +++ b/library/vip/amd/axi/axi_definitions.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,14 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** - `timescale 1ns/1ps `ifndef _AXI_DEFINITIONS_SVH_ diff --git a/library/vip/amd/axi/m_axi_sequencer.sv b/library/vip/amd/axi/m_axi_sequencer.sv index b339e2af..c271d9ea 100644 --- a/library/vip/amd/axi/m_axi_sequencer.sv +++ b/library/vip/amd/axi/m_axi_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -40,10 +40,43 @@ package m_axi_sequencer_pkg; import axi_vip_pkg::*; import logger_pkg::*; - import adi_common_pkg::*; - import reg_accessor_pkg::*; + import adi_vip_pkg::*; - class m_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends reg_accessor; + + class m_axi_sequencer_base extends adi_sequencer; + + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + + virtual task automatic RegWrite32( + input xil_axi_ulong addr =0, + input bit [31:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: RegWrite32 + + virtual task automatic RegRead32( + input xil_axi_ulong addr =0, + output bit [31:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: RegRead32 + + virtual task automatic RegReadVerify32( + input xil_axi_ulong addr =0, + input bit [31:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: RegReadVerify32 + + endclass: m_axi_sequencer_base + + + class m_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends m_axi_sequencer_base; axi_mst_wr_driver #(`AXI_VIP_PARAM_ORDER(AXI)) wr_driver; axi_mst_rd_driver #(`AXI_VIP_PARAM_ORDER(AXI)) rd_driver; @@ -64,13 +97,14 @@ package m_axi_sequencer_pkg; reader_s = new(1); writer_s = new(1); - endfunction + endfunction: new // --------------------------------------------------------------------------- // Generic tasks // --------------------------------------------------------------------------- - virtual task automatic RegWrite32(input xil_axi_ulong addr =0, - input bit [31:0] data); + virtual task automatic RegWrite32( + input xil_axi_ulong addr =0, + input bit [31:0] data); static xil_axi_uint id =0; @@ -85,11 +119,11 @@ package m_axi_sequencer_pkg; .data(data)); id++; writer_s.put(1); - endtask : RegWrite32 - virtual task automatic RegRead32(input xil_axi_ulong addr =0, - output bit [31:0] data); + virtual task automatic RegRead32( + input xil_axi_ulong addr =0, + output bit [31:0] data); xil_axi_data_beat DataBeat_for_read[]; static xil_axi_uint id =0; @@ -107,37 +141,37 @@ package m_axi_sequencer_pkg; this.info($sformatf(" Reading data : %h @ 0x%h", data, addr), ADI_VERBOSITY_HIGH); reader_s.put(1); - endtask : RegRead32 - virtual task automatic RegReadVerify32(input xil_axi_ulong addr =0, - input bit [31:0] data); + virtual task automatic RegReadVerify32( + input xil_axi_ulong addr =0, + input bit [31:0] data); + bit [31:0] data_out; RegRead32(.addr(addr), .data(data_out)); if (data !== data_out) begin this.error($sformatf(" Address : %h; Data mismatch. Read data is : %h; expected is %h", addr, data_out, data)); end - endtask : RegReadVerify32 // --------------------------------------------------------------------------- // BFM specific tasks // --------------------------------------------------------------------------- - task automatic single_write_transaction_api ( - input string name ="single_write", - input xil_axi_uint id =0, - input xil_axi_ulong addr =0, - input xil_axi_len_t len =0, - input xil_axi_size_t size =xil_axi_size_t'(xil_clog2((32)/8)), - input xil_axi_burst_t burst =XIL_AXI_BURST_TYPE_INCR, - input xil_axi_lock_t lock = XIL_AXI_ALOCK_NOLOCK, - input xil_axi_cache_t cache =3, - input xil_axi_prot_t prot =0, - input xil_axi_region_t region =0, - input xil_axi_qos_t qos =0, - input bit [63:0] data =0); + protected task automatic single_write_transaction_api ( + input string name ="single_write", + input xil_axi_uint id =0, + input xil_axi_ulong addr =0, + input xil_axi_len_t len =0, + input xil_axi_size_t size =xil_axi_size_t'(xil_clog2((32)/8)), + input xil_axi_burst_t burst =XIL_AXI_BURST_TYPE_INCR, + input xil_axi_lock_t lock = XIL_AXI_ALOCK_NOLOCK, + input xil_axi_cache_t cache =3, + input xil_axi_prot_t prot =0, + input xil_axi_region_t region =0, + input xil_axi_qos_t qos =0, + input bit [63:0] data =0); axi_transaction wr_trans; wr_trans = wr_driver.create_transaction(name); @@ -149,10 +183,9 @@ package m_axi_sequencer_pkg; wr_trans.set_qos(qos); wr_trans.set_data_block(data); wr_driver.send(wr_trans); - endtask : single_write_transaction_api - task automatic single_write_transaction_readback_api ( + protected task automatic single_write_transaction_readback_api ( input string name ="single_write", input xil_axi_uint id =0, input xil_axi_ulong addr =0, @@ -178,10 +211,9 @@ package m_axi_sequencer_pkg; wr_trans.set_driver_return_item_policy(XIL_AXI_PAYLOAD_RETURN); wr_driver.send(wr_trans); wr_driver.wait_rsp(wr_trans); - endtask : single_write_transaction_readback_api - task automatic single_read_transaction_api ( + protected task automatic single_read_transaction_api ( input string name ="single_read", input xil_axi_uint id =0, input xil_axi_ulong addr =0, @@ -206,7 +238,7 @@ package m_axi_sequencer_pkg; rd_driver.send(rd_trans); endtask : single_read_transaction_api - task automatic single_read_transaction_readback_api ( + protected task automatic single_read_transaction_readback_api ( input string name ="single_read", input xil_axi_uint id =0, input xil_axi_ulong addr =0, @@ -237,9 +269,8 @@ package m_axi_sequencer_pkg; Rdatabeat[beat] = rd_trans.get_data_beat(beat); //$display("Read data from Driver: beat index %d, Data beat %h ", beat, Rdatabeat[beat]); end - endtask : single_read_transaction_readback_api - endclass + endclass: m_axi_sequencer -endpackage +endpackage: m_axi_sequencer_pkg diff --git a/library/vip/amd/axi/s_axi_sequencer.sv b/library/vip/amd/axi/s_axi_sequencer.sv index 1e1ab9e3..90786f96 100644 --- a/library/vip/amd/axi/s_axi_sequencer.sv +++ b/library/vip/amd/axi/s_axi_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,10 +39,44 @@ package s_axi_sequencer_pkg; import axi_vip_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import logger_pkg::*; - class s_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends adi_component; + + class s_axi_sequencer_base extends adi_sequencer; + + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + + virtual task get_byte_from_mem( + input xil_axi_ulong addr, + output bit [7:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: get_byte_from_mem + + virtual task set_byte_in_mem( + input xil_axi_ulong addr, + input bit [7:0] data); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: set_byte_in_mem + + virtual task verify_byte( + input xil_axi_ulong addr, + input bit [7:0] refdata); + + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: verify_byte + + endclass: s_axi_sequencer_base + + + class s_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends s_axi_sequencer_base; xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(AXI)) mem_model; @@ -54,10 +88,12 @@ package s_axi_sequencer_pkg; super.new(name, parent); this.mem_model = mem_model; - endfunction + endfunction: new + + task get_byte_from_mem( + input xil_axi_ulong addr, + output bit [7:0] data); - task get_byte_from_mem(input xil_axi_ulong addr, - output bit [7:0] data); bit [31:0] four_bytes; four_bytes = this.mem_model.backdoor_memory_read_4byte(addr); case (addr[1:0]) @@ -66,10 +102,12 @@ package s_axi_sequencer_pkg; 2'b10: data = four_bytes[16+:8]; 2'b11: data = four_bytes[24+:8]; endcase - endtask + endtask: get_byte_from_mem + + task set_byte_in_mem( + input xil_axi_ulong addr, + input bit [7:0] data); - task set_byte_in_mem(input xil_axi_ulong addr, - input bit [7:0] data); bit [3:0] strb; case (addr[1:0]) 2'b00: strb = 'b0001; @@ -80,18 +118,20 @@ package s_axi_sequencer_pkg; this.mem_model.backdoor_memory_write_4byte(.addr(addr), .payload({4{data}}), .strb(strb)); - endtask + endtask: set_byte_in_mem - task verify_byte(input xil_axi_ulong addr, - input bit [7:0] refdata); + task verify_byte( + input xil_axi_ulong addr, + input bit [7:0] refdata); + bit [7:0] data; get_byte_from_mem (addr, data); if (data !== refdata) begin this.error($sformatf("Unexpected value at address %0h . Expected: %0h Found: %0h", addr, refdata, data)); end - endtask + endtask: verify_byte - endclass + endclass: s_axi_sequencer -endpackage +endpackage: s_axi_sequencer_pkg diff --git a/library/vip/amd/axis/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv index b40e4611..96ce1b25 100644 --- a/library/vip/amd/axis/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,7 +39,8 @@ package adi_axis_agent_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; @@ -156,4 +157,4 @@ package adi_axis_agent_pkg; endclass: adi_axis_passthrough_mem_agent -endpackage +endpackage: adi_axis_agent_pkg diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv index 77b5d3a5..c038ce62 100644 --- a/library/vip/amd/axis/adi_axis_monitor.sv +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package adi_axis_monitor_pkg; import axi4stream_vip_pkg::*; import logger_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import pub_sub_pkg::*; class adi_axis_monitor #(`AXIS_VIP_PARAM_DECL(AXIS)) extends adi_monitor; @@ -30,7 +65,7 @@ package adi_axis_monitor_pkg; this.publisher = new("Publisher", this); this.enabled = 0; - endfunction + endfunction: new task run(); if (this.enabled) begin @@ -86,6 +121,6 @@ package adi_axis_monitor_pkg; end endtask: get_transaction - endclass + endclass: adi_axis_monitor -endpackage +endpackage: adi_axis_monitor_pkg diff --git a/library/vip/amd/axis/axis_definitions.svh b/library/vip/amd/axis/axis_definitions.svh index ed98435c..1588109c 100644 --- a/library/vip/amd/axis/axis_definitions.svh +++ b/library/vip/amd/axis/axis_definitions.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,14 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** - `timescale 1ns/1ps `ifndef _AXIS_DEFINITIONS_SVH_ diff --git a/library/vip/amd/axis/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv index 3cc86628..fa3e39b5 100644 --- a/library/vip/amd/axis/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,7 +39,7 @@ package m_axis_sequencer_pkg; import axi4stream_vip_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import logger_pkg::*; typedef enum { @@ -55,7 +55,7 @@ package m_axis_sequencer_pkg; } stop_policy_t; - class m_axis_sequencer_base extends adi_component; + class m_axis_sequencer_base extends adi_sequencer; protected bit enabled; protected bit queue_empty_sig; @@ -116,45 +116,45 @@ package m_axis_sequencer_pkg; // set vif proxy to drive outputs with 0 when inactive virtual task set_inactive_drive_output_0(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: set_inactive_drive_output_0 // check if ready is asserted virtual function bit check_ready_asserted(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endfunction: check_ready_asserted // wait for set amount of clock cycles virtual task wait_clk_count(input int wait_clocks); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: wait_clk_count // pack the byte stream into transfers(beats) then in packets by setting the tlast virtual protected task packetize(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: packetize virtual protected task sender(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: sender // create transfer based on data beats per packet - virtual function void add_xfer_descriptor_packet_size( + virtual function void add_xfer_descriptor_sample_count( input int data_beats_per_packet, input int gen_tlast = 1, input int gen_sync = 1); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); - endfunction: add_xfer_descriptor_packet_size + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endfunction: add_xfer_descriptor_sample_count // wait until data beat is sent virtual task beat_sent(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: beat_sent // wait until packet is sent virtual task packet_sent(); - this.fatal($sformatf("Base class was instantiated instead of the inherited class!")); + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); endtask: packet_sent @@ -209,7 +209,7 @@ package m_axis_sequencer_pkg; endfunction: set_keep_some // create transfer descriptor - function void add_xfer_descriptor( + function void add_xfer_descriptor_byte_count( input int bytes_to_generate, input int gen_last = 1, input int gen_sync = 1); @@ -224,7 +224,7 @@ package m_axis_sequencer_pkg; descriptor_q.push_back(descriptor); this.queue_empty_sig = 0; ->>queue_ev; - endfunction: add_xfer_descriptor + endfunction: add_xfer_descriptor_byte_count // descriptor delay subroutine // - can be overridden in inherited classes for more specific delay generation @@ -351,13 +351,13 @@ package m_axis_sequencer_pkg; endtask: packet_sent // create transfer based on data beats per packet - virtual function void add_xfer_descriptor_packet_size( + virtual function void add_xfer_descriptor_sample_count( input int data_beats_per_packet, input int gen_tlast = 1, input int gen_sync = 1); - add_xfer_descriptor(data_beats_per_packet*AXIS_VIP_DATA_WIDTH/8, gen_tlast, gen_sync); - endfunction: add_xfer_descriptor_packet_size + add_xfer_descriptor_byte_count(data_beats_per_packet*AXIS_VIP_DATA_WIDTH/8, gen_tlast, gen_sync); + endfunction: add_xfer_descriptor_sample_count // set vif proxy to drive outputs with 0 when inactive virtual task set_inactive_drive_output_0(); @@ -497,6 +497,6 @@ package m_axis_sequencer_pkg; end endtask: sender - endclass + endclass: m_axis_sequencer -endpackage +endpackage: m_axis_sequencer_pkg diff --git a/library/vip/amd/axis/s_axis_sequencer.sv b/library/vip/amd/axis/s_axis_sequencer.sv index 6f566641..6745caa2 100644 --- a/library/vip/amd/axis/s_axis_sequencer.sv +++ b/library/vip/amd/axis/s_axis_sequencer.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -39,10 +39,10 @@ package s_axis_sequencer_pkg; import axi4stream_vip_pkg::*; - import adi_common_pkg::*; + import adi_vip_pkg::*; import logger_pkg::*; - class s_axis_sequencer_base extends adi_component; + class s_axis_sequencer_base extends adi_sequencer; protected xil_axi4stream_data_byte byte_stream [$]; protected xil_axi4stream_ready_gen_policy_t mode; @@ -89,20 +89,20 @@ package s_axis_sequencer_pkg; // ready generation policy functions function void set_mode(input xil_axi4stream_ready_gen_policy_t mode); this.mode = mode; - endfunction + endfunction: set_mode function xil_axi4stream_ready_gen_policy_t get_mode(); return this.mode; - endfunction + endfunction: get_mode // high time functions function void set_high_time(input xil_axi4stream_uint high_time); this.high_time = high_time; - endfunction + endfunction: set_high_time function xil_axi4stream_uint get_high_time(); return this.high_time; - endfunction + endfunction: get_high_time function void set_high_time_range( input xil_axi4stream_uint high_time_min, @@ -110,12 +110,12 @@ package s_axis_sequencer_pkg; this.high_time_min = high_time_min; this.high_time_max = high_time_max; - endfunction + endfunction: set_high_time_range // low time functions function void set_low_time(input xil_axi4stream_uint low_time); this.low_time = low_time; - endfunction + endfunction: set_low_time function xil_axi4stream_uint get_low_time(); return this.low_time; @@ -127,7 +127,7 @@ package s_axis_sequencer_pkg; this.low_time_min = low_time_min; this.low_time_max = low_time_max; - endfunction + endfunction: set_low_time_range // function for verifying bytes task verify_byte(input bit [7:0] refdata); @@ -140,20 +140,22 @@ package s_axis_sequencer_pkg; this.error($sformatf("Unexpected data received. Expected: %0h Found: %0h Left : %0d", refdata, data, byte_stream.size())); end end - endtask + endtask: verify_byte // call ready generation function task run(); user_gen_tready(); - endtask + endtask: run // virtual tasks to be implemented virtual task user_gen_tready(); - endtask + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: user_gen_tready virtual task get_transfer(); - endtask + this.fatal($sformatf("Base class was instantiated instead of the parameterized class!")); + endtask: get_transfer endclass: s_axis_sequencer_base @@ -171,7 +173,7 @@ package s_axis_sequencer_pkg; super.new(name, parent); this.driver = driver; - endfunction + endfunction: new virtual task user_gen_tready(); @@ -194,8 +196,8 @@ package s_axis_sequencer_pkg; tready_gen.set_high_time_range(this.high_time_min, this.high_time_max); end this.driver.send_tready(tready_gen); - endtask + endtask: user_gen_tready - endclass + endclass: s_axis_sequencer -endpackage +endpackage: s_axis_sequencer_pkg diff --git a/scripts/make_tb_path.mk b/scripts/make_tb_path.mk index c1d3707b..f0c6d921 100644 --- a/scripts/make_tb_path.mk +++ b/scripts/make_tb_path.mk @@ -1,4 +1,4 @@ -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/scripts/project-sim.mk b/scripts/project-sim.mk index 228a3710..dc6b13e6 100644 --- a/scripts/project-sim.mk +++ b/scripts/project-sim.mk @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018-2024 (c) Analog Devices, Inc. +## Copyright (C) 2018-2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/axi_tdd/Makefile b/testbenches/ip/axi_tdd/Makefile index 074e4aa1..95b799c2 100644 --- a/testbenches/ip/axi_tdd/Makefile +++ b/testbenches/ip/axi_tdd/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/axi_tdd/system_bd.tcl b/testbenches/ip/axi_tdd/system_bd.tcl index 88e6ba6b..9511a29b 100644 --- a/testbenches/ip/axi_tdd/system_bd.tcl +++ b/testbenches/ip/axi_tdd/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/axi_tdd/system_tb.sv b/testbenches/ip/axi_tdd/system_tb.sv index abf189ed..5d95605a 100644 --- a/testbenches/ip/axi_tdd/system_tb.sv +++ b/testbenches/ip/axi_tdd/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/axi_tdd/tests/test_program.sv b/testbenches/ip/axi_tdd/tests/test_program.sv index 0819bacd..a27562f4 100644 --- a/testbenches/ip/axi_tdd/tests/test_program.sv +++ b/testbenches/ip/axi_tdd/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/axi_tdd/waves/cfg1.wcfg b/testbenches/ip/axi_tdd/waves/cfg1.wcfg index 54504f63..ae7e3945 100644 --- a/testbenches/ip/axi_tdd/waves/cfg1.wcfg +++ b/testbenches/ip/axi_tdd/waves/cfg1.wcfg @@ -14,7 +14,6 @@ - diff --git a/testbenches/ip/axis_sequencers/Makefile b/testbenches/ip/axis_sequencers/Makefile index 0319e0db..095446af 100644 --- a/testbenches/ip/axis_sequencers/Makefile +++ b/testbenches/ip/axis_sequencers/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/axis_sequencers/environment.sv b/testbenches/ip/axis_sequencers/environment.sv index 4007dcc4..20198af9 100644 --- a/testbenches/ip/axis_sequencers/environment.sv +++ b/testbenches/ip/axis_sequencers/environment.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" `include "axis_definitions.svh" package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; diff --git a/testbenches/ip/axis_sequencers/system_bd.tcl b/testbenches/ip/axis_sequencers/system_bd.tcl index b05934de..783cc71c 100644 --- a/testbenches/ip/axis_sequencers/system_bd.tcl +++ b/testbenches/ip/axis_sequencers/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/axis_sequencers/system_tb.sv b/testbenches/ip/axis_sequencers/system_tb.sv index 36eff4db..2723b531 100644 --- a/testbenches/ip/axis_sequencers/system_tb.sv +++ b/testbenches/ip/axis_sequencers/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/axis_sequencers/tests/test_program.sv b/testbenches/ip/axis_sequencers/tests/test_program.sv index 1e513528..08600126 100644 --- a/testbenches/ip/axis_sequencers/tests/test_program.sv +++ b/testbenches/ip/axis_sequencers/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; @@ -101,22 +99,22 @@ program test_program; 1: begin axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(0); axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_DATA_BEAT); - // axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); - axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_packet_size(32'd10, 1, 0); + // axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_sample_count(32'd10, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 1000, "Send data"); end 2: begin axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(0); axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_DESCRIPTOR_QUEUE); - repeat (10) axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); + repeat (10) axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(32'h600, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 30000, "Send data"); end 3: begin axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(1); axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); - axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(32'h600, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 20000, "Send data"); end diff --git a/testbenches/ip/axis_sequencers/waves/cfg1.wcfg b/testbenches/ip/axis_sequencers/waves/cfg1.wcfg index 4a417396..a320c7a1 100644 --- a/testbenches/ip/axis_sequencers/waves/cfg1.wcfg +++ b/testbenches/ip/axis_sequencers/waves/cfg1.wcfg @@ -14,7 +14,6 @@ - diff --git a/testbenches/ip/base/Makefile b/testbenches/ip/base/Makefile index 845120e2..74545915 100644 --- a/testbenches/ip/base/Makefile +++ b/testbenches/ip/base/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/base/system_bd.tcl b/testbenches/ip/base/system_bd.tcl index 7e456b0a..c0eabdcb 100644 --- a/testbenches/ip/base/system_bd.tcl +++ b/testbenches/ip/base/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/base/system_tb.sv b/testbenches/ip/base/system_tb.sv index b2e0c285..0ad34c87 100644 --- a/testbenches/ip/base/system_tb.sv +++ b/testbenches/ip/base/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/base/tests/test_program.sv b/testbenches/ip/base/tests/test_program.sv index d002e04a..cfd43413 100644 --- a/testbenches/ip/base/tests/test_program.sv +++ b/testbenches/ip/base/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/base/waves/cfg1.wcfg b/testbenches/ip/base/waves/cfg1.wcfg index 2fe219f8..4469603f 100644 --- a/testbenches/ip/base/waves/cfg1.wcfg +++ b/testbenches/ip/base/waves/cfg1.wcfg @@ -13,7 +13,6 @@ - diff --git a/testbenches/ip/data_offload/Makefile b/testbenches/ip/data_offload/Makefile index 7770fc41..136eaf46 100644 --- a/testbenches/ip/data_offload/Makefile +++ b/testbenches/ip/data_offload/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/data_offload/tests/test_program.sv b/testbenches/ip/data_offload/tests/test_program.sv index 3268193e..152fb9f1 100644 --- a/testbenches/ip/data_offload/tests/test_program.sv +++ b/testbenches/ip/data_offload/tests/test_program.sv @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" import axi_vip_pkg::*; @@ -82,7 +117,7 @@ module test_program(); // ADC stub env.adc_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - env.adc_src_axis_seq.add_xfer_descriptor(`ADC_TRANSFER_LENGTH, 0, 0); + env.adc_src_axis_seq.add_xfer_descriptor_byte_count(`ADC_TRANSFER_LENGTH, 0, 0); // DAC stub dac_mode = XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE; diff --git a/testbenches/ip/data_offload_2/Makefile b/testbenches/ip/data_offload_2/Makefile index 08279063..6e4dc321 100644 --- a/testbenches/ip/data_offload_2/Makefile +++ b/testbenches/ip/data_offload_2/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2021(c) Analog Devices, Inc. +## Copyright (C) 2021 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/data_offload_2/data_offload_pkg.sv b/testbenches/ip/data_offload_2/data_offload_pkg.sv index 9b79fdb9..ee5b2d77 100644 --- a/testbenches/ip/data_offload_2/data_offload_pkg.sv +++ b/testbenches/ip/data_offload_2/data_offload_pkg.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -59,16 +59,16 @@ package data_offload_pkg; import axi_vip_pkg::*; - import reg_accessor_pkg::*; + import m_axi_sequencer_pkg::*; import logger_pkg::*; class data_offload; - reg_accessor bus; + m_axi_sequencer_base bus; xil_axi_ulong base_address; bit [1:0] reg_control; - function new (reg_accessor bus, xil_axi_ulong base_address); + function new (m_axi_sequencer_base bus, xil_axi_ulong base_address); this.bus = bus; this.base_address = base_address; endfunction diff --git a/testbenches/ip/data_offload_2/do_scoreboard.sv b/testbenches/ip/data_offload_2/do_scoreboard.sv index 8a4f56a3..0f1b1a00 100644 --- a/testbenches/ip/data_offload_2/do_scoreboard.sv +++ b/testbenches/ip/data_offload_2/do_scoreboard.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/data_offload_2/environment.sv b/testbenches/ip/data_offload_2/environment.sv index f204d1fb..5da43a2c 100644 --- a/testbenches/ip/data_offload_2/environment.sv +++ b/testbenches/ip/data_offload_2/environment.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/data_offload_2/system_tb.sv b/testbenches/ip/data_offload_2/system_tb.sv index f468237e..536ac1a3 100644 --- a/testbenches/ip/data_offload_2/system_tb.sv +++ b/testbenches/ip/data_offload_2/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/data_offload_2/tests/test_program.sv b/testbenches/ip/data_offload_2/tests/test_program.sv index a58d67f2..29ea8db1 100644 --- a/testbenches/ip/data_offload_2/tests/test_program.sv +++ b/testbenches/ip/data_offload_2/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -82,7 +82,7 @@ module test_program( env.src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); for (int i = 0; i < `SRC_TRANSFERS_INITIAL_COUNT; i++) - env.src_axis_seq.add_xfer_descriptor(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); // Only gen TLAST in TX path + env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); // Only gen TLAST in TX path env.dst_axis_seq.set_mode(`DST_READY_MODE); env.dst_axis_seq.set_high_time(`DST_READY_HIGH); @@ -132,7 +132,7 @@ module test_program( #100 for (int i = 0; i < `SRC_TRANSFERS_DELAYED_COUNT; i++) - env.src_axis_seq.add_xfer_descriptor(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); + env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, `PATH_TYPE, 0); if (!`OFFLOAD_ONESHOT) begin env.src_axis_seq.wait_empty_descriptor_queue(); diff --git a/testbenches/ip/data_offload_2/tests/test_program_sync.sv b/testbenches/ip/data_offload_2/tests/test_program_sync.sv index 4955b720..4ce9c4f9 100644 --- a/testbenches/ip/data_offload_2/tests/test_program_sync.sv +++ b/testbenches/ip/data_offload_2/tests/test_program_sync.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -73,7 +73,7 @@ module test_program_sync ( //========================================================================= env.src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - env.src_axis_seq.add_xfer_descriptor(`SRC_TRANSFERS_LENGTH, 1, 0); + env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, 1, 0); env.dst_axis_seq.set_mode(`DST_READY_MODE); env.dst_axis_seq.set_high_time(`DST_READY_HIGH); @@ -140,7 +140,7 @@ module test_program_sync ( //init_req <= 1'b1; #100 - // env.src_axis_seq.add_xfer_descriptor(`SRC_TRANSFERS_LENGTH, 1, 0); + // env.src_axis_seq.add_xfer_descriptor_byte_count(`SRC_TRANSFERS_LENGTH, 1, 0); // @env.src_axis_seq.queue_empty; // init_req <= 1'b0; diff --git a/testbenches/ip/data_offload_2/waves/cfg1.wcfg b/testbenches/ip/data_offload_2/waves/cfg1.wcfg index 8c32df33..fe3763c0 100644 --- a/testbenches/ip/data_offload_2/waves/cfg1.wcfg +++ b/testbenches/ip/data_offload_2/waves/cfg1.wcfg @@ -14,7 +14,6 @@ - diff --git a/testbenches/ip/data_offload_2/waves/cfg2.wcfg b/testbenches/ip/data_offload_2/waves/cfg2.wcfg index 9fa04440..10d70433 100644 --- a/testbenches/ip/data_offload_2/waves/cfg2.wcfg +++ b/testbenches/ip/data_offload_2/waves/cfg2.wcfg @@ -14,7 +14,6 @@ - diff --git a/testbenches/ip/data_offload_2/waves/cfg3.wcfg b/testbenches/ip/data_offload_2/waves/cfg3.wcfg index fd2b5b57..c4434594 100644 --- a/testbenches/ip/data_offload_2/waves/cfg3.wcfg +++ b/testbenches/ip/data_offload_2/waves/cfg3.wcfg @@ -14,7 +14,7 @@ - + diff --git a/testbenches/ip/data_offload_2/waves/cfg4.wcfg b/testbenches/ip/data_offload_2/waves/cfg4.wcfg index 96af8b88..6ce229cf 100644 --- a/testbenches/ip/data_offload_2/waves/cfg4.wcfg +++ b/testbenches/ip/data_offload_2/waves/cfg4.wcfg @@ -14,7 +14,7 @@ - + diff --git a/testbenches/ip/dma_flock/environment.sv b/testbenches/ip/dma_flock/environment.sv index 6305c7c4..864938b5 100644 --- a/testbenches/ip/dma_flock/environment.sv +++ b/testbenches/ip/dma_flock/environment.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -39,7 +39,7 @@ package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import scoreboard_pkg::*; import axi4stream_vip_pkg::*; diff --git a/testbenches/ip/dma_flock/scoreboard.sv b/testbenches/ip/dma_flock/scoreboard.sv index 7d532bd2..2e5f1828 100644 --- a/testbenches/ip/dma_flock/scoreboard.sv +++ b/testbenches/ip/dma_flock/scoreboard.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/testbenches/ip/dma_flock/system_tb.sv b/testbenches/ip/dma_flock/system_tb.sv index 8fb9ed2f..f76d6dd6 100644 --- a/testbenches/ip/dma_flock/system_tb.sv +++ b/testbenches/ip/dma_flock/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/testbenches/ip/dma_flock/tests/test_program.sv b/testbenches/ip/dma_flock/tests/test_program.sv index 9d34f74e..a0a7b268 100644 --- a/testbenches/ip/dma_flock/tests/test_program.sv +++ b/testbenches/ip/dma_flock/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -205,7 +205,7 @@ program test_program; begin for (int l = 0; l < m_seg.ylength; l++) begin // update the AXIS generator command - dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor(.bytes_to_generate(m_seg.length), + dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(.bytes_to_generate(m_seg.length), .gen_last(1), .gen_sync(l==0)); end diff --git a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv index e0508432..d25cf0cd 100644 --- a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv +++ b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -253,7 +253,7 @@ program test_program_frame_delay; begin for (int l = 0; l < m_seg.ylength; l++) begin // update the AXIS generator command - dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor(.bytes_to_generate(m_seg.length), + dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor_byte_count(.bytes_to_generate(m_seg.length), .gen_last(1), .gen_sync(l==0)); end diff --git a/testbenches/ip/dma_flock/waves/cfg1.wcfg b/testbenches/ip/dma_flock/waves/cfg1.wcfg index f099716c..2e3129b7 100644 --- a/testbenches/ip/dma_flock/waves/cfg1.wcfg +++ b/testbenches/ip/dma_flock/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/testbenches/ip/dma_flock/waves/cfg2_fsync.wcfg b/testbenches/ip/dma_flock/waves/cfg2_fsync.wcfg index f099716c..2e3129b7 100644 --- a/testbenches/ip/dma_flock/waves/cfg2_fsync.wcfg +++ b/testbenches/ip/dma_flock/waves/cfg2_fsync.wcfg @@ -6,7 +6,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/testbenches/ip/dma_flock/waves/cfg3_fsync_autorun.wcfg b/testbenches/ip/dma_flock/waves/cfg3_fsync_autorun.wcfg index f099716c..2e3129b7 100644 --- a/testbenches/ip/dma_flock/waves/cfg3_fsync_autorun.wcfg +++ b/testbenches/ip/dma_flock/waves/cfg3_fsync_autorun.wcfg @@ -6,7 +6,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/testbenches/ip/dma_loopback/Makefile b/testbenches/ip/dma_loopback/Makefile index 3b461f72..aabd7597 100644 --- a/testbenches/ip/dma_loopback/Makefile +++ b/testbenches/ip/dma_loopback/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/dma_loopback/system_bd.tcl b/testbenches/ip/dma_loopback/system_bd.tcl index a2fa7b7c..f190aee1 100644 --- a/testbenches/ip/dma_loopback/system_bd.tcl +++ b/testbenches/ip/dma_loopback/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/dma_loopback/system_tb.sv b/testbenches/ip/dma_loopback/system_tb.sv index 3aa095c4..5c718309 100644 --- a/testbenches/ip/dma_loopback/system_tb.sv +++ b/testbenches/ip/dma_loopback/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 0c1c93b3..3201e808 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axi_definitions.svh" diff --git a/testbenches/ip/dma_sg/system_bd.tcl b/testbenches/ip/dma_sg/system_bd.tcl index a7259071..41b9c641 100644 --- a/testbenches/ip/dma_sg/system_bd.tcl +++ b/testbenches/ip/dma_sg/system_bd.tcl @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/dma_sg/system_tb.sv b/testbenches/ip/dma_sg/system_tb.sv index 7ecc8a20..9c4dea57 100644 --- a/testbenches/ip/dma_sg/system_tb.sv +++ b/testbenches/ip/dma_sg/system_tb.sv @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/dma_sg/tests/test_program_1d.sv b/testbenches/ip/dma_sg/tests/test_program_1d.sv index e8ef4624..b3d7bbf7 100644 --- a/testbenches/ip/dma_sg/tests/test_program_1d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_1d.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/dma_sg/tests/test_program_2d.sv b/testbenches/ip/dma_sg/tests/test_program_2d.sv index 957db4d3..f225caf6 100644 --- a/testbenches/ip/dma_sg/tests/test_program_2d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_2d.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv index ed74898c..ba5c8c34 100644 --- a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv +++ b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/dma_sg/waves/cfg1.wcfg b/testbenches/ip/dma_sg/waves/cfg1.wcfg index b928ce3d..e93a4032 100644 --- a/testbenches/ip/dma_sg/waves/cfg1.wcfg +++ b/testbenches/ip/dma_sg/waves/cfg1.wcfg @@ -5,7 +5,7 @@ - + @@ -17,7 +17,7 @@ - + diff --git a/testbenches/ip/dma_sg/waves/cfg2.wcfg b/testbenches/ip/dma_sg/waves/cfg2.wcfg index a4a4c9df..a187b39f 100644 --- a/testbenches/ip/dma_sg/waves/cfg2.wcfg +++ b/testbenches/ip/dma_sg/waves/cfg2.wcfg @@ -5,7 +5,7 @@ - + @@ -17,7 +17,7 @@ - + diff --git a/testbenches/ip/hbm/Makefile b/testbenches/ip/hbm/Makefile index 956fb144..f6e420b5 100644 --- a/testbenches/ip/hbm/Makefile +++ b/testbenches/ip/hbm/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/hbm/system_bd.tcl b/testbenches/ip/hbm/system_bd.tcl index 71be57d5..33153841 100644 --- a/testbenches/ip/hbm/system_bd.tcl +++ b/testbenches/ip/hbm/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/hbm/system_tb.sv b/testbenches/ip/hbm/system_tb.sv index 3aa095c4..5c718309 100644 --- a/testbenches/ip/hbm/system_tb.sv +++ b/testbenches/ip/hbm/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/hbm/tests/test_program.sv b/testbenches/ip/hbm/tests/test_program.sv index 69abbfe0..1314ab12 100644 --- a/testbenches/ip/hbm/tests/test_program.sv +++ b/testbenches/ip/hbm/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/ip/i3c_controller/tests/test_program.sv b/testbenches/ip/i3c_controller/tests/test_program.sv index fa196f8e..21d7a395 100755 --- a/testbenches/ip/i3c_controller/tests/test_program.sv +++ b/testbenches/ip/i3c_controller/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/i3c_controller/waves/cfg1.wcfg b/testbenches/ip/i3c_controller/waves/cfg1.wcfg index 7649a5c6..090e3cba 100755 --- a/testbenches/ip/i3c_controller/waves/cfg1.wcfg +++ b/testbenches/ip/i3c_controller/waves/cfg1.wcfg @@ -13,7 +13,7 @@ - + diff --git a/testbenches/ip/jesd_loopback/Makefile b/testbenches/ip/jesd_loopback/Makefile index 197b3f07..9b805f0a 100644 --- a/testbenches/ip/jesd_loopback/Makefile +++ b/testbenches/ip/jesd_loopback/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/jesd_loopback/system_bd.tcl b/testbenches/ip/jesd_loopback/system_bd.tcl index 7b71ed7a..31d59778 100644 --- a/testbenches/ip/jesd_loopback/system_bd.tcl +++ b/testbenches/ip/jesd_loopback/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/jesd_loopback/system_tb.sv b/testbenches/ip/jesd_loopback/system_tb.sv index 2abe0526..6394fb3f 100644 --- a/testbenches/ip/jesd_loopback/system_tb.sv +++ b/testbenches/ip/jesd_loopback/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/jesd_loopback/tests/test_program.sv b/testbenches/ip/jesd_loopback/tests/test_program.sv index e37fe6f1..fcec78de 100644 --- a/testbenches/ip/jesd_loopback/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/jesd_loopback/waves/cfg1.wcfg b/testbenches/ip/jesd_loopback/waves/cfg1.wcfg index 571dd15b..56454f25 100644 --- a/testbenches/ip/jesd_loopback/waves/cfg1.wcfg +++ b/testbenches/ip/jesd_loopback/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/jesd_loopback_64b/Makefile b/testbenches/ip/jesd_loopback_64b/Makefile index 197b3f07..9b805f0a 100644 --- a/testbenches/ip/jesd_loopback_64b/Makefile +++ b/testbenches/ip/jesd_loopback_64b/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/jesd_loopback_64b/system_bd.tcl b/testbenches/ip/jesd_loopback_64b/system_bd.tcl index 33387a9a..e032ad70 100644 --- a/testbenches/ip/jesd_loopback_64b/system_bd.tcl +++ b/testbenches/ip/jesd_loopback_64b/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/jesd_loopback_64b/system_tb.sv b/testbenches/ip/jesd_loopback_64b/system_tb.sv index 656b5063..8e1f73d4 100644 --- a/testbenches/ip/jesd_loopback_64b/system_tb.sv +++ b/testbenches/ip/jesd_loopback_64b/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv index 365fa399..c93f33ce 100644 --- a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import logger_pkg::*; diff --git a/testbenches/ip/scoreboard/Makefile b/testbenches/ip/scoreboard/Makefile index b8505a2d..b39c6e04 100644 --- a/testbenches/ip/scoreboard/Makefile +++ b/testbenches/ip/scoreboard/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 36a298c1..cd4405ad 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -1,3 +1,38 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" `include "axi_definitions.svh" `include "axis_definitions.svh" @@ -5,7 +40,7 @@ package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; @@ -59,7 +94,7 @@ package environment_pkg; task configure(int bytes_to_generate); // ADC stub this.adc_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.adc_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.adc_src_axis_agent.sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); // DAC stub this.dac_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); diff --git a/testbenches/ip/scoreboard/system_bd.tcl b/testbenches/ip/scoreboard/system_bd.tcl index ccf48bfd..a0d7856a 100644 --- a/testbenches/ip/scoreboard/system_bd.tcl +++ b/testbenches/ip/scoreboard/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/scoreboard/system_tb.sv b/testbenches/ip/scoreboard/system_tb.sv index 36eff4db..2723b531 100644 --- a/testbenches/ip/scoreboard/system_tb.sv +++ b/testbenches/ip/scoreboard/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index dc821f98..48f580e6 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axi_definitions.svh" `include "axis_definitions.svh" diff --git a/testbenches/ip/scoreboard/waves/cfg1.wcfg b/testbenches/ip/scoreboard/waves/cfg1.wcfg index d74bb02b..4e1d4cb4 100644 --- a/testbenches/ip/scoreboard/waves/cfg1.wcfg +++ b/testbenches/ip/scoreboard/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -22,7 +22,7 @@ - + diff --git a/testbenches/ip/spi_engine/Makefile b/testbenches/ip/spi_engine/Makefile index 629aab2d..c256e5a8 100644 --- a/testbenches/ip/spi_engine/Makefile +++ b/testbenches/ip/spi_engine/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -22,12 +22,10 @@ ENV_DEPS += $(HDL_LIBRARY_PATH)/common/ad_edge_detect.v LIB_DEPS += axi_clkgen LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom # default test programs # Format is: diff --git a/testbenches/ip/spi_engine/spi_environment.sv b/testbenches/ip/spi_engine/spi_environment.sv index 76f17bd3..27bea6bf 100644 --- a/testbenches/ip/spi_engine/spi_environment.sv +++ b/testbenches/ip/spi_engine/spi_environment.sv @@ -38,7 +38,7 @@ package spi_environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; diff --git a/testbenches/ip/spi_engine/system_tb.sv b/testbenches/ip/spi_engine/system_tb.sv index 71a5a321..d002884d 100644 --- a/testbenches/ip/spi_engine/system_tb.sv +++ b/testbenches/ip/spi_engine/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/spi_engine/tests/test_program.sv b/testbenches/ip/spi_engine/tests/test_program.sv index 85089de1..6fc209ad 100644 --- a/testbenches/ip/spi_engine/tests/test_program.sv +++ b/testbenches/ip/spi_engine/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -224,7 +224,7 @@ task sdo_stream_gen( data[i] = (tx_data & (8'hFF << 8*i)) >> 8*i; spi_env.sdo_src_seq.push_byte_for_stream(data[i]); end - spi_env.sdo_src_seq.add_xfer_descriptor((`DATA_WIDTH/8),0,0); + spi_env.sdo_src_seq.add_xfer_descriptor_byte_count((`DATA_WIDTH/8),0,0); `endif endtask diff --git a/testbenches/ip/spi_engine/waves/cfg1.wcfg b/testbenches/ip/spi_engine/waves/cfg1.wcfg index 274ebdb8..c8dac025 100644 --- a/testbenches/ip/spi_engine/waves/cfg1.wcfg +++ b/testbenches/ip/spi_engine/waves/cfg1.wcfg @@ -12,7 +12,7 @@ - + diff --git a/testbenches/ip/spi_engine/waves/cfg_inv_cs.wcfg b/testbenches/ip/spi_engine/waves/cfg_inv_cs.wcfg index 9ae838f3..3bb16eb9 100644 --- a/testbenches/ip/spi_engine/waves/cfg_inv_cs.wcfg +++ b/testbenches/ip/spi_engine/waves/cfg_inv_cs.wcfg @@ -12,7 +12,7 @@ - + diff --git a/testbenches/ip/spi_engine/waves/cfg_sdo_streaming.wcfg b/testbenches/ip/spi_engine/waves/cfg_sdo_streaming.wcfg index 6d15b161..e7262c34 100644 --- a/testbenches/ip/spi_engine/waves/cfg_sdo_streaming.wcfg +++ b/testbenches/ip/spi_engine/waves/cfg_sdo_streaming.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/util_axis_fifo/Makefile b/testbenches/ip/util_axis_fifo/Makefile index a1d6b38a..55ee4501 100644 --- a/testbenches/ip/util_axis_fifo/Makefile +++ b/testbenches/ip/util_axis_fifo/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/util_axis_fifo/environment.sv b/testbenches/ip/util_axis_fifo/environment.sv index 3c5d6372..be53ef02 100644 --- a/testbenches/ip/util_axis_fifo/environment.sv +++ b/testbenches/ip/util_axis_fifo/environment.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" `include "axis_definitions.svh" package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; diff --git a/testbenches/ip/util_axis_fifo/system_bd.tcl b/testbenches/ip/util_axis_fifo/system_bd.tcl index 79aeedc3..32bbcb7a 100644 --- a/testbenches/ip/util_axis_fifo/system_bd.tcl +++ b/testbenches/ip/util_axis_fifo/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/util_axis_fifo/system_tb.sv b/testbenches/ip/util_axis_fifo/system_tb.sv index e92f32ea..57d8c109 100644 --- a/testbenches/ip/util_axis_fifo/system_tb.sv +++ b/testbenches/ip/util_axis_fifo/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/util_axis_fifo/tests/test_program.sv b/testbenches/ip/util_axis_fifo/tests/test_program.sv index 98696ca4..3f124c2d 100644 --- a/testbenches/ip/util_axis_fifo/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axis_definitions.svh" @@ -103,11 +101,11 @@ program test_program (); if (!`TKEEP_EN) begin repeat($urandom_range(1,5)) begin - uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_packet_size($urandom_range(1,128), `TLAST_EN, 0); + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_sample_count($urandom_range(1,128), `TLAST_EN, 0); end end else begin repeat($urandom_range(1,5)) begin - uaf_env.input_axis_agent.sequencer.add_xfer_descriptor($urandom_range(1,1024), `TLAST_EN, 0); + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_byte_count($urandom_range(1,1024), `TLAST_EN, 0); end end diff --git a/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg b/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg index 2346364e..9b1d7fa9 100644 --- a/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg +++ b/testbenches/ip/util_axis_fifo/waves/cfg_rand.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/util_axis_fifo_asym/Makefile b/testbenches/ip/util_axis_fifo_asym/Makefile index 72f90010..b5bf4cd6 100644 --- a/testbenches/ip/util_axis_fifo_asym/Makefile +++ b/testbenches/ip/util_axis_fifo_asym/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022(c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/util_axis_fifo_asym/environment.sv b/testbenches/ip/util_axis_fifo_asym/environment.sv index 3c5d6372..9da1f018 100644 --- a/testbenches/ip/util_axis_fifo_asym/environment.sv +++ b/testbenches/ip/util_axis_fifo_asym/environment.sv @@ -1,10 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" `include "axis_definitions.svh" package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; diff --git a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl index 66fd1740..5352fb0d 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl +++ b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/util_axis_fifo_asym/system_tb.sv b/testbenches/ip/util_axis_fifo_asym/system_tb.sv index e92f32ea..57d8c109 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_tb.sv +++ b/testbenches/ip/util_axis_fifo_asym/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv index a2fc7226..9caafd9b 100644 --- a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axis_definitions.svh" @@ -98,11 +96,11 @@ program test_program (); if ((!`TKEEP_EN || !`TLAST_EN) && `INPUT_WIDTH < `OUTPUT_WIDTH) begin repeat($urandom_range(1,5)) begin - uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_packet_size($urandom_range(1,128)*`OUTPUT_WIDTH/`INPUT_WIDTH, `TLAST_EN, 0); + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_sample_count($urandom_range(1,128)*`OUTPUT_WIDTH/`INPUT_WIDTH, `TLAST_EN, 0); end end else begin repeat($urandom_range(1,5)) begin - uaf_env.input_axis_agent.sequencer.add_xfer_descriptor($urandom_range(1,1024), `TLAST_EN, 0); + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_byte_count($urandom_range(1,1024), `TLAST_EN, 0); end end diff --git a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg index d556dd92..f762d66c 100644 --- a/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg +++ b/testbenches/ip/util_axis_fifo_asym/waves/cfg_rand.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/util_pack/Makefile b/testbenches/ip/util_pack/Makefile index 34d6d9ed..4a5d1227 100644 --- a/testbenches/ip/util_pack/Makefile +++ b/testbenches/ip/util_pack/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### diff --git a/testbenches/ip/util_pack/environment.sv b/testbenches/ip/util_pack/environment.sv index 41cdd55e..2be4feae 100644 --- a/testbenches/ip/util_pack/environment.sv +++ b/testbenches/ip/util_pack/environment.sv @@ -1,9 +1,44 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + `include "utils.svh" package environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; @@ -52,13 +87,13 @@ package environment_pkg; task configure(int bytes_to_generate); // TX stubs this.tx_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.tx_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.tx_src_axis_agent.sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); this.tx_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); // RX stub this.rx_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.rx_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.rx_src_axis_agent.sequencer.add_xfer_descriptor_byte_count(bytes_to_generate, 0, 0); this.rx_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); endtask diff --git a/testbenches/ip/util_pack/system_bd.tcl b/testbenches/ip/util_pack/system_bd.tcl index e1bd41d9..f0f0e29d 100644 --- a/testbenches/ip/util_pack/system_bd.tcl +++ b/testbenches/ip/util_pack/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/ip/util_pack/system_tb.sv b/testbenches/ip/util_pack/system_tb.sv index b2e0c285..0ad34c87 100644 --- a/testbenches/ip/util_pack/system_tb.sv +++ b/testbenches/ip/util_pack/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/ip/util_pack/tests/test_program.sv b/testbenches/ip/util_pack/tests/test_program.sv index 9e2ae2af..83e520d6 100644 --- a/testbenches/ip/util_pack/tests/test_program.sv +++ b/testbenches/ip/util_pack/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" `include "axi_definitions.svh" `include "axis_definitions.svh" diff --git a/testbenches/ip/util_pack/waves/cfg1.wcfg b/testbenches/ip/util_pack/waves/cfg1.wcfg index 6319d37f..2ef4b934 100644 --- a/testbenches/ip/util_pack/waves/cfg1.wcfg +++ b/testbenches/ip/util_pack/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -20,7 +20,7 @@ - + diff --git a/testbenches/ip/util_pack/waves/cfg_rand.wcfg b/testbenches/ip/util_pack/waves/cfg_rand.wcfg index 6319d37f..2ef4b934 100644 --- a/testbenches/ip/util_pack/waves/cfg_rand.wcfg +++ b/testbenches/ip/util_pack/waves/cfg_rand.wcfg @@ -6,7 +6,7 @@ - + @@ -20,7 +20,7 @@ - + diff --git a/testbenches/project/ad463x/Makefile b/testbenches/project/ad463x/Makefile index ba422b1e..a76023b9 100644 --- a/testbenches/project/ad463x/Makefile +++ b/testbenches/project/ad463x/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -21,12 +21,9 @@ LIB_DEPS += ad463x_data_capture LIB_DEPS += axi_dmac LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom LIB_DEPS += axi_clkgen LIB_DEPS += axi_i2s_adi LIB_DEPS += axi_pwm_gen -LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_axis_reorder LIB_DEPS += spi_engine/spi_engine_execution diff --git a/testbenches/project/ad463x/system_bd.tcl b/testbenches/project/ad463x/system_bd.tcl index 68071e82..9d43872f 100644 --- a/testbenches/project/ad463x/system_bd.tcl +++ b/testbenches/project/ad463x/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad463x/system_tb.sv b/testbenches/project/ad463x/system_tb.sv index 81a65aaf..b36523b1 100644 --- a/testbenches/project/ad463x/system_tb.sv +++ b/testbenches/project/ad463x/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad463x/tests/test_program.sv b/testbenches/project/ad463x/tests/test_program.sv index bb8c049a..0b19dd4d 100644 --- a/testbenches/project/ad463x/tests/test_program.sv +++ b/testbenches/project/ad463x/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad57xx/Makefile b/testbenches/project/ad57xx/Makefile index 45db572c..15fd8b7e 100644 --- a/testbenches/project/ad57xx/Makefile +++ b/testbenches/project/ad57xx/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2024(c) Analog Devices, Inc. +## Copyright (C) 2024 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -19,13 +19,11 @@ SV_DEPS += ad57xx_environment.sv LIB_DEPS += axi_clkgen LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += util_axis_fifo LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom SIM_LIB_DEPS += spi_vip diff --git a/testbenches/project/ad57xx/ad57xx_environment.sv b/testbenches/project/ad57xx/ad57xx_environment.sv index 51e4c0cb..42c91778 100644 --- a/testbenches/project/ad57xx/ad57xx_environment.sv +++ b/testbenches/project/ad57xx/ad57xx_environment.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,7 +38,7 @@ package ad57xx_environment_pkg; import logger_pkg::*; - import adi_common_pkg::*; + import adi_environment_pkg::*; import s_spi_sequencer_pkg::*; import adi_spi_vip_pkg::*; diff --git a/testbenches/project/ad57xx/system_bd.tcl b/testbenches/project/ad57xx/system_bd.tcl index 0fc21b31..20ec4742 100644 --- a/testbenches/project/ad57xx/system_bd.tcl +++ b/testbenches/project/ad57xx/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/testbenches/project/ad57xx/waves/cfg1.wcfg b/testbenches/project/ad57xx/waves/cfg1.wcfg index ac78db12..7b6f8893 100644 --- a/testbenches/project/ad57xx/waves/cfg1.wcfg +++ b/testbenches/project/ad57xx/waves/cfg1.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/project/ad738x/Makefile b/testbenches/project/ad738x/Makefile index a15dd306..8946fadb 100644 --- a/testbenches/project/ad738x/Makefile +++ b/testbenches/project/ad738x/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2021(c) Analog Devices, Inc. +## Copyright (C) 2021 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -18,12 +18,10 @@ LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac LIB_DEPS += axi_i2s_adi LIB_DEPS += axi_pwm_gen -LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom LIB_DEPS += util_axis_upscale LIB_DEPS += util_pulse_gen diff --git a/testbenches/project/ad738x/system_bd.tcl b/testbenches/project/ad738x/system_bd.tcl index bdab458f..bb842441 100644 --- a/testbenches/project/ad738x/system_bd.tcl +++ b/testbenches/project/ad738x/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad738x/system_tb.sv b/testbenches/project/ad738x/system_tb.sv index b63b2f1b..667e6827 100644 --- a/testbenches/project/ad738x/system_tb.sv +++ b/testbenches/project/ad738x/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad738x/tests/test_program.sv b/testbenches/project/ad738x/tests/test_program.sv index dd77f5f5..4f4ea8e8 100644 --- a/testbenches/project/ad738x/tests/test_program.sv +++ b/testbenches/project/ad738x/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/Makefile b/testbenches/project/ad7606x/Makefile index 879ba8d2..3ee06a16 100755 --- a/testbenches/project/ad7606x/Makefile +++ b/testbenches/project/ad7606x/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022 (c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -26,8 +26,6 @@ LIB_DEPS += axi_hdmi_tx LIB_DEPS += axi_i2s_adi LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_spdif_tx -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom LIB_DEPS += util_i2c_mixer LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_cdc diff --git a/testbenches/project/ad7606x/system_bd.tcl b/testbenches/project/ad7606x/system_bd.tcl index 46d20621..c0f8b635 100755 --- a/testbenches/project/ad7606x/system_bd.tcl +++ b/testbenches/project/ad7606x/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad7606x/system_tb.sv b/testbenches/project/ad7606x/system_tb.sv index db6083ae..bfbb0f8b 100755 --- a/testbenches/project/ad7606x/system_tb.sv +++ b/testbenches/project/ad7606x/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/tests/test_program_4ch.sv b/testbenches/project/ad7606x/tests/test_program_4ch.sv index e33a02d2..b259a2bc 100755 --- a/testbenches/project/ad7606x/tests/test_program_4ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_4ch.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/tests/test_program_6ch.sv b/testbenches/project/ad7606x/tests/test_program_6ch.sv index f9fe57e9..140783da 100755 --- a/testbenches/project/ad7606x/tests/test_program_6ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_6ch.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/tests/test_program_8ch.sv b/testbenches/project/ad7606x/tests/test_program_8ch.sv index 38cd7d80..a3eec321 100755 --- a/testbenches/project/ad7606x/tests/test_program_8ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_8ch.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/tests/test_program_si.sv b/testbenches/project/ad7606x/tests/test_program_si.sv index 3ab60eed..341c6a0f 100755 --- a/testbenches/project/ad7606x/tests/test_program_si.sv +++ b/testbenches/project/ad7606x/tests/test_program_si.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7606x/waves/system_tb_behav.wcfg b/testbenches/project/ad7606x/waves/system_tb_behav.wcfg index b675d7af..5461ca48 100644 --- a/testbenches/project/ad7606x/waves/system_tb_behav.wcfg +++ b/testbenches/project/ad7606x/waves/system_tb_behav.wcfg @@ -17,7 +17,7 @@ - + diff --git a/testbenches/project/ad7616/Makefile b/testbenches/project/ad7616/Makefile index f9e4de96..2d6e09c4 100755 --- a/testbenches/project/ad7616/Makefile +++ b/testbenches/project/ad7616/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2022 (c) Analog Devices, Inc. +## Copyright (C) 2022 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -22,12 +22,10 @@ LIB_DEPS += axi_clkgen LIB_DEPS += axi_ad7616 LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom # default test program TP := test_program_si diff --git a/testbenches/project/ad7616/system_bd.tcl b/testbenches/project/ad7616/system_bd.tcl index 7fd76333..26c8695d 100755 --- a/testbenches/project/ad7616/system_bd.tcl +++ b/testbenches/project/ad7616/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2022 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad7616/system_tb.sv b/testbenches/project/ad7616/system_tb.sv index 73480c91..21f79533 100755 --- a/testbenches/project/ad7616/system_tb.sv +++ b/testbenches/project/ad7616/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7616/tests/test_program_pi.sv b/testbenches/project/ad7616/tests/test_program_pi.sv index 6f302f47..1d9c557d 100755 --- a/testbenches/project/ad7616/tests/test_program_pi.sv +++ b/testbenches/project/ad7616/tests/test_program_pi.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7616/tests/test_program_si.sv b/testbenches/project/ad7616/tests/test_program_si.sv index 54407e77..bb2544d9 100755 --- a/testbenches/project/ad7616/tests/test_program_si.sv +++ b/testbenches/project/ad7616/tests/test_program_si.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad7616/waves/cfg_pi.wcfg b/testbenches/project/ad7616/waves/cfg_pi.wcfg index 74cfc7aa..9e48c1fc 100644 --- a/testbenches/project/ad7616/waves/cfg_pi.wcfg +++ b/testbenches/project/ad7616/waves/cfg_pi.wcfg @@ -12,7 +12,7 @@ - + diff --git a/testbenches/project/ad7616/waves/cfg_si.wcfg b/testbenches/project/ad7616/waves/cfg_si.wcfg index 31026027..22e7c6b7 100644 --- a/testbenches/project/ad7616/waves/cfg_si.wcfg +++ b/testbenches/project/ad7616/waves/cfg_si.wcfg @@ -12,7 +12,7 @@ - + diff --git a/testbenches/project/ad9083/Makefile b/testbenches/project/ad9083/Makefile index 79078678..8d54f115 100644 --- a/testbenches/project/ad9083/Makefile +++ b/testbenches/project/ad9083/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -29,8 +29,6 @@ LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/util_adxcvr -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom # default test program TP := test_program diff --git a/testbenches/project/ad9083/system_bd.tcl b/testbenches/project/ad9083/system_bd.tcl index 7b199bb6..c978ab69 100644 --- a/testbenches/project/ad9083/system_bd.tcl +++ b/testbenches/project/ad9083/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad9083/system_tb.sv b/testbenches/project/ad9083/system_tb.sv index 29d4246f..e95c19ab 100644 --- a/testbenches/project/ad9083/system_tb.sv +++ b/testbenches/project/ad9083/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad9083/tests/test_program.sv b/testbenches/project/ad9083/tests/test_program.sv index 6adfa373..530dce4d 100644 --- a/testbenches/project/ad9083/tests/test_program.sv +++ b/testbenches/project/ad9083/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/ad_quadmxfe1_ebz/Makefile b/testbenches/project/ad_quadmxfe1_ebz/Makefile index 9e9d4915..04c19b42 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/Makefile +++ b/testbenches/project/ad_quadmxfe1_ebz/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -32,8 +32,6 @@ LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pad LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/util_adxcvr -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom # default test program diff --git a/testbenches/project/ad_quadmxfe1_ebz/system_bd.tcl b/testbenches/project/ad_quadmxfe1_ebz/system_bd.tcl index ea5538cb..b7886d0c 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/system_bd.tcl +++ b/testbenches/project/ad_quadmxfe1_ebz/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/ad_quadmxfe1_ebz/system_tb.sv b/testbenches/project/ad_quadmxfe1_ebz/system_tb.sv index 9638c3dd..92b8445f 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/system_tb.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv index 26d80231..d7a66cc2 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_dma.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv index ac31f492..ba9ffd3c 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv index 85233c61..661b9c70 100644 --- a/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv +++ b/testbenches/project/ad_quadmxfe1_ebz/tests/test_program_64b66b.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/adrv9001/Makefile b/testbenches/project/adrv9001/Makefile index c17fe47d..efb482a5 100644 --- a/testbenches/project/adrv9001/Makefile +++ b/testbenches/project/adrv9001/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -19,8 +19,6 @@ LIB_DEPS += axi_dmac LIB_DEPS += axi_adrv9001 LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom # default test program TP := test_program diff --git a/testbenches/project/adrv9001/system_bd.tcl b/testbenches/project/adrv9001/system_bd.tcl index d177cbb2..accace89 100644 --- a/testbenches/project/adrv9001/system_bd.tcl +++ b/testbenches/project/adrv9001/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/adrv9001/system_tb.sv b/testbenches/project/adrv9001/system_tb.sv index df6e59ca..5ae474dd 100644 --- a/testbenches/project/adrv9001/system_tb.sv +++ b/testbenches/project/adrv9001/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/adrv9001/tests/test_program.sv b/testbenches/project/adrv9001/tests/test_program.sv index f4608377..296d9629 100644 --- a/testbenches/project/adrv9001/tests/test_program.sv +++ b/testbenches/project/adrv9001/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import axi_vip_pkg::*; diff --git a/testbenches/project/adrv9009/Makefile b/testbenches/project/adrv9009/Makefile index f11e8b86..44b5c1b4 100755 --- a/testbenches/project/adrv9009/Makefile +++ b/testbenches/project/adrv9009/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -18,14 +18,12 @@ SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_adc_pkg.sv LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac LIB_DEPS += jesd204/axi_jesd204_tx LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc LIB_DEPS += jesd204/axi_jesd204_rx LIB_DEPS += jesd204/jesd204_rx -LIB_DEPS += sysid_rom LIB_DEPS += util_dacfifo LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 diff --git a/testbenches/project/adrv9009/system_bd.tcl b/testbenches/project/adrv9009/system_bd.tcl index 58dc58ac..9ee413bb 100755 --- a/testbenches/project/adrv9009/system_bd.tcl +++ b/testbenches/project/adrv9009/system_bd.tcl @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/adrv9009/system_tb.sv b/testbenches/project/adrv9009/system_tb.sv index 869e982d..1cbfa1a1 100755 --- a/testbenches/project/adrv9009/system_tb.sv +++ b/testbenches/project/adrv9009/system_tb.sv @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/adrv9009/tests/test_program.sv b/testbenches/project/adrv9009/tests/test_program.sv index 7ffd9494..6804367b 100755 --- a/testbenches/project/adrv9009/tests/test_program.sv +++ b/testbenches/project/adrv9009/tests/test_program.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/adrv9009/waves/cfg1.wcfg b/testbenches/project/adrv9009/waves/cfg1.wcfg index f12b0f16..d974f8f9 100755 --- a/testbenches/project/adrv9009/waves/cfg1.wcfg +++ b/testbenches/project/adrv9009/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/testbenches/project/fmcomms2/Makefile b/testbenches/project/fmcomms2/Makefile index 7e64b79b..e3dd8868 100644 --- a/testbenches/project/fmcomms2/Makefile +++ b/testbenches/project/fmcomms2/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -16,8 +16,6 @@ SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_common_pkg.sv LIB_DEPS += axi_ad9361 LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_rfifo diff --git a/testbenches/project/fmcomms2/system_bd.tcl b/testbenches/project/fmcomms2/system_bd.tcl index 1fdd39b0..07429f7d 100644 --- a/testbenches/project/fmcomms2/system_bd.tcl +++ b/testbenches/project/fmcomms2/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/fmcomms2/system_tb.sv b/testbenches/project/fmcomms2/system_tb.sv index 1d23bbed..af75692e 100644 --- a/testbenches/project/fmcomms2/system_tb.sv +++ b/testbenches/project/fmcomms2/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/fmcomms2/tests/test_program.sv b/testbenches/project/fmcomms2/tests/test_program.sv index f87f626b..ead8416b 100644 --- a/testbenches/project/fmcomms2/tests/test_program.sv +++ b/testbenches/project/fmcomms2/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/mxfe/Makefile b/testbenches/project/mxfe/Makefile index 1af65b08..e1cb4ac0 100644 --- a/testbenches/project/mxfe/Makefile +++ b/testbenches/project/mxfe/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2018(c) Analog Devices, Inc. +## Copyright (C) 2018 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -35,8 +35,6 @@ LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/util_adxcvr -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom # default test program TP := test_program diff --git a/testbenches/project/mxfe/system_bd.tcl b/testbenches/project/mxfe/system_bd.tcl index 31c05a74..8ace956d 100644 --- a/testbenches/project/mxfe/system_bd.tcl +++ b/testbenches/project/mxfe/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2018 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2018 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/mxfe/system_tb.sv b/testbenches/project/mxfe/system_tb.sv index 4d06b4a0..80bb03c2 100644 --- a/testbenches/project/mxfe/system_tb.sv +++ b/testbenches/project/mxfe/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/mxfe/tests/test_program.sv b/testbenches/project/mxfe/tests/test_program.sv index ec65fea1..cbfa6728 100644 --- a/testbenches/project/mxfe/tests/test_program.sv +++ b/testbenches/project/mxfe/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014 - 2018 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/mxfe/waves/cfg1.wcfg b/testbenches/project/mxfe/waves/cfg1.wcfg index e2aea726..bda64c90 100644 --- a/testbenches/project/mxfe/waves/cfg1.wcfg +++ b/testbenches/project/mxfe/waves/cfg1.wcfg @@ -6,7 +6,7 @@ - + @@ -21,7 +21,7 @@ - + diff --git a/testbenches/project/pluto/system_bd.tcl b/testbenches/project/pluto/system_bd.tcl index 89a966c9..f2b1add1 100644 --- a/testbenches/project/pluto/system_bd.tcl +++ b/testbenches/project/pluto/system_bd.tcl @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/pluto/system_tb.sv b/testbenches/project/pluto/system_tb.sv index 9d80b90f..653a1155 100644 --- a/testbenches/project/pluto/system_tb.sv +++ b/testbenches/project/pluto/system_tb.sv @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/pluto/tests/test_program.sv b/testbenches/project/pluto/tests/test_program.sv index fe35cb2e..8dd72e0a 100644 --- a/testbenches/project/pluto/tests/test_program.sv +++ b/testbenches/project/pluto/tests/test_program.sv @@ -26,15 +26,13 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** -// -// -// + `include "utils.svh" import test_harness_env_pkg::*; diff --git a/testbenches/project/pluto/waves/cfg1.wcfg b/testbenches/project/pluto/waves/cfg1.wcfg index 0ac0b6eb..a10fec27 100644 --- a/testbenches/project/pluto/waves/cfg1.wcfg +++ b/testbenches/project/pluto/waves/cfg1.wcfg @@ -20,7 +20,7 @@ - + diff --git a/testbenches/project/pulsar_adc_pmdz/Makefile b/testbenches/project/pulsar_adc_pmdz/Makefile index ffaeb4e1..3dfa2edf 100755 --- a/testbenches/project/pulsar_adc_pmdz/Makefile +++ b/testbenches/project/pulsar_adc_pmdz/Makefile @@ -1,6 +1,6 @@ #################################################################################### #################################################################################### -## Copyright 2021(c) Analog Devices, Inc. +## Copyright (C) 2021 Analog Devices, Inc. #################################################################################### #################################################################################### @@ -20,7 +20,6 @@ ENV_DEPS += $(HDL_LIBRARY_PATH)/common/ad_edge_detect.v LIB_DEPS += axi_clkgen LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid LIB_DEPS += util_cdc LIB_DEPS += util_axis_fifo LIB_DEPS += axi_pulsar_lvds @@ -28,7 +27,6 @@ LIB_DEPS += spi_engine/axi_spi_engine LIB_DEPS += spi_engine/spi_engine_execution LIB_DEPS += spi_engine/spi_engine_interconnect LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += sysid_rom # default test programs # Format is: diff --git a/testbenches/project/pulsar_adc_pmdz/spi_engine.svh b/testbenches/project/pulsar_adc_pmdz/spi_engine.svh index 5d6096e0..beb517bc 100644 --- a/testbenches/project/pulsar_adc_pmdz/spi_engine.svh +++ b/testbenches/project/pulsar_adc_pmdz/spi_engine.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/pulsar_adc_pmdz/system_bd.tcl b/testbenches/project/pulsar_adc_pmdz/system_bd.tcl index 64517339..40e64e4d 100755 --- a/testbenches/project/pulsar_adc_pmdz/system_bd.tcl +++ b/testbenches/project/pulsar_adc_pmdz/system_bd.tcl @@ -1,6 +1,6 @@ # *************************************************************************** # *************************************************************************** -# Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +# Copyright (C) 2021 Analog Devices, Inc. All rights reserved. # # In this HDL repository, there are many different and unique modules, consisting # of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ # # 2. An ADI specific BSD license, which can be found in the top level directory # of this repository (LICENSE_ADIBSD), and also on-line at: -# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD # This will allow to generate bit files and not release the source code, # as long as it attaches to an ADI device. # diff --git a/testbenches/project/pulsar_adc_pmdz/system_tb.sv b/testbenches/project/pulsar_adc_pmdz/system_tb.sv index 3b05f965..646f19d2 100755 --- a/testbenches/project/pulsar_adc_pmdz/system_tb.sv +++ b/testbenches/project/pulsar_adc_pmdz/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv index e46538c4..de822a73 100755 --- a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv +++ b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 - 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2021 - 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/testbenches/project/pulsar_adc_pmdz/waves/cfg1.wcfg b/testbenches/project/pulsar_adc_pmdz/waves/cfg1.wcfg index c17b4aeb..f36391be 100755 --- a/testbenches/project/pulsar_adc_pmdz/waves/cfg1.wcfg +++ b/testbenches/project/pulsar_adc_pmdz/waves/cfg1.wcfg @@ -12,7 +12,7 @@ - +