From 7a02cd801c4d6a54df13299d1c45379b70792b7f Mon Sep 17 00:00:00 2001 From: Lucas Steuernagel Date: Tue, 16 Jan 2024 17:36:16 -0300 Subject: [PATCH 1/2] Create PQR instruction class --- .../SBF/Disassembler/SBFDisassembler.cpp | 1 + llvm/lib/Target/SBF/SBFISelLowering.cpp | 10 +- llvm/lib/Target/SBF/SBFInstrFormats.td | 9 + llvm/lib/Target/SBF/SBFInstrInfo.td | 115 ++++++---- llvm/lib/Target/SBF/SBFSubtarget.cpp | 2 +- llvm/lib/Target/SBF/SBFSubtarget.h | 8 +- llvm/lib/Target/SBF/SBFTargetFeatures.td | 11 +- llvm/test/CodeGen/SBF/pqr-class.ll | 196 ++++++++++++++++++ llvm/test/MC/Disassembler/SBF/sbf-alu.txt | 19 -- llvm/test/MC/Disassembler/SBF/sbf-pqr.txt | 75 +++++++ llvm/test/MC/SBF/sbf-alu.s | 24 --- llvm/test/MC/SBF/sbf-pqr.s | 102 +++++++++ llvm/test/MC/SBF/sbf-sdiv.s | 15 -- 13 files changed, 477 insertions(+), 110 deletions(-) create mode 100644 llvm/test/CodeGen/SBF/pqr-class.ll create mode 100644 llvm/test/MC/Disassembler/SBF/sbf-pqr.txt create mode 100644 llvm/test/MC/SBF/sbf-pqr.s delete mode 100644 llvm/test/MC/SBF/sbf-sdiv.s diff --git a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp index 49a63e02eb3ea6..73c9feb1e4754f 100644 --- a/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp +++ b/llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp @@ -40,6 +40,7 @@ class SBFDisassembler : public MCDisassembler { SBF_STX = 0x3, SBF_ALU = 0x4, SBF_JMP = 0x5, + SBF_PQR = 0x6, SBF_ALU64 = 0x7 }; diff --git a/llvm/lib/Target/SBF/SBFISelLowering.cpp b/llvm/lib/Target/SBF/SBFISelLowering.cpp index 51b85d8cb66efd..32420b735469d8 100644 --- a/llvm/lib/Target/SBF/SBFISelLowering.cpp +++ b/llvm/lib/Target/SBF/SBFISelLowering.cpp @@ -124,16 +124,16 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM, if (VT == MVT::i32 && !STI.getHasAlu32()) continue; - if (Subtarget->isSolana() && !STI.getHasSdiv()) { + if (Subtarget->isSolana() && !STI.getHasPqrClass()) { setOperationAction(ISD::SDIV, VT, Expand); + setOperationAction(ISD::SREM, VT, Expand); + setOperationAction(ISD::UREM, VT, Expand); + setOperationAction(ISD::MULHU, VT, Expand); + setOperationAction(ISD::MULHS, VT, Expand); } setOperationAction(ISD::SDIVREM, VT, Expand); setOperationAction(ISD::UDIVREM, VT, Expand); - setOperationAction(ISD::SREM, VT, Expand); - setOperationAction(ISD::UREM, VT, Expand); - setOperationAction(ISD::MULHU, VT, Expand); - setOperationAction(ISD::MULHS, VT, Expand); setOperationAction(ISD::UMUL_LOHI, VT, Expand); setOperationAction(ISD::SMUL_LOHI, VT, Expand); setOperationAction(ISD::ROTR, VT, Expand); diff --git a/llvm/lib/Target/SBF/SBFInstrFormats.td b/llvm/lib/Target/SBF/SBFInstrFormats.td index de8b36da7af79b..2bc92f939dde42 100644 --- a/llvm/lib/Target/SBF/SBFInstrFormats.td +++ b/llvm/lib/Target/SBF/SBFInstrFormats.td @@ -16,6 +16,7 @@ def SBF_ST : SBFOpClass<0x2>; def SBF_STX : SBFOpClass<0x3>; def SBF_ALU : SBFOpClass<0x4>; def SBF_JMP : SBFOpClass<0x5>; +def SBF_PQR : SBFOpClass<0x6>; def SBF_ALU64 : SBFOpClass<0x7>; class SBFSrcType val> { @@ -45,6 +46,14 @@ def SBF_END : SBFArithOp<0xd>; def SBF_SDIV : SBFArithOp<0xe>; def SBF_HOR : SBFArithOp<0xf>; +def PQR_UHMUL : SBFArithOp<0x2>; +def PQR_UDIV : SBFArithOp<0x4>; +def PQR_UREM : SBFArithOp<0x6>; +def PQR_LMUL : SBFArithOp<0x8>; +def PQR_SHMUL : SBFArithOp<0xa>; +def PQR_SDIV : SBFArithOp<0xc>; +def PQR_SREM : SBFArithOp<0xe>; + def SBF_XCHG : SBFArithOp<0xe>; def SBF_CMPXCHG : SBFArithOp<0xf>; diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td index 381a0fbc27bb24..bbd238ee0cc681 100644 --- a/llvm/lib/Target/SBF/SBFInstrInfo.td +++ b/llvm/lib/Target/SBF/SBFInstrInfo.td @@ -63,6 +63,8 @@ def SBFRevSub : Predicate<"Subtarget->getReverseSubImm()">; def SBFNoRevSub : Predicate<"!Subtarget->getReverseSubImm()">; def SBFCallxSrc : Predicate<"Subtarget->getCallXRegSrc()">, AssemblerPredicate<(all_of FeatureCallxRegSrc)>; def NoSBFCallxSrc : Predicate<"!Subtarget->getCallXRegSrc()">; +def SBFPqrInstr : Predicate<"Subtarget->getHasPqrClass()">; +def SBFNoPqrInstr : Predicate<"!Subtarget->getHasPqrClass()">; def brtarget : Operand { let PrintMethod = "printBrTargetOperand"; @@ -136,10 +138,13 @@ def SBF_CC_LEU : PatLeaf<(i64 imm), // +----------------+--------+--------------------+ // (MSB) (LSB) class TYPE_ALU_JMP op, bits<1> srctype, - dag outs, dag ins, string asmstr, list pattern> + dag outs, dag ins, string asmstr, list pattern, + bit IsPqr64 = 0> : InstSBF { - let Inst{63-60} = op; + // In the PQR class, instructions that deal with 64-bit registers have a difference OpCode. + // To obtain it, we add one to its base value. + let Inst{63-60} = !if(IsPqr64, !add(op, 1), op); let Inst{59} = srctype; } @@ -211,9 +216,11 @@ defm JSLE : J; } // ALU instructions -class ALU_RI pattern> - : TYPE_ALU_JMP { +class MATH_RI pattern, bit isPqr64 = 0> + : TYPE_ALU_JMP { bits<4> dst; bits<32> imm; @@ -222,9 +229,11 @@ class ALU_RI pattern> - : TYPE_ALU_JMP { +class MATH_RR pattern, bit isPqr64 = 0> + : TYPE_ALU_JMP { bits<4> dst; bits<4> src; @@ -233,25 +242,14 @@ class ALU_RR { - def _rr : ALU_RR; - def _ri : ALU_RI; - def _rr_32 : ALU_RR { + def _rr_32 : MATH_RR; - def _ri_32 : ALU_RI; } +multiclass MATH_64 { + + defvar isPqr64 = !if(!eq(Class, SBF_PQR), 1, 0); + + def _rr : MATH_RR; + + def _ri : MATH_RI; +} + +multiclass ALU { + defm "" : MATH_64; + + defm "" : MATH_32; +} + +multiclass PQR { + defm "" : MATH_64; + defm "" : MATH_32; +} + let Constraints = "$dst = $src2" in { let isAsCheapAsAMove = 1 in { defm ADD : ALU; @@ -272,13 +304,13 @@ let Constraints = "$dst = $src2" in { defm SRA : ALU; let Predicates = [SBFNoLddw] in { - def HOR : ALU_RI; let DecoderNamespace = "SBFv2" in { - def HOR_addr : ALU_RI; - defm DIV : ALU; - let Predicates = [SBFSubtargetSolana] in { - defm SDIV : ALU; + let Predicates = [SBFNoPqrInstr] in { + defm MUL : ALU; + defm DIV : ALU; + } + + let Predicates = [SBFPqrInstr] in { + defm UHMUL : MATH_64; + defm UDIV : PQR; + defm UREM : PQR; + defm LMUL : PQR; + defm SHMUL : MATH_64; + defm SDIV_pqr : PQR; + defm SREM : PQR; } } @@ -355,22 +396,22 @@ class LD_IMM64 Pseudo, string Mnemonic> let isReMaterializable = 1, isAsCheapAsAMove = 1 in { def LD_imm64 : LD_IMM64<0, "lddw">, Requires<[SBFHasLddw]>; -def MOV_rr : ALU_RR; -def MOV_ri : ALU_RI; -def MOV_rr_32 : ALU_RR; -def MOV_ri_32 : ALU_RI; let Constraints = "$dst = $src" in { - def CORE_SHIFT : ALU_RR; - def MOV_32_64_addr : ALU_RI, Requires<[SBFNoLddw]>; } let DecoderNamespace = "SBFv2", Predicates = [SBFNoLddw] in { - def MOV_32_64_imm : ALU_RI; } diff --git a/llvm/lib/Target/SBF/SBFSubtarget.cpp b/llvm/lib/Target/SBF/SBFSubtarget.cpp index c820d3b13eca8d..2ea2804eb94b7b 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.cpp +++ b/llvm/lib/Target/SBF/SBFSubtarget.cpp @@ -38,7 +38,6 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) { IsSolana = true; HasJmpExt = false; HasAlu32 = false; - HasSdiv = false; UseDwarfRIS = false; // SBFv2 features @@ -47,6 +46,7 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) { ReverseSubImm = false; NoLddw = false; CallxRegSrc = false; + HasPqrClass = false; } void SBFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { diff --git a/llvm/lib/Target/SBF/SBFSubtarget.h b/llvm/lib/Target/SBF/SBFSubtarget.h index 07ad4a8f1b225d..1b07852f0d98ca 100644 --- a/llvm/lib/Target/SBF/SBFSubtarget.h +++ b/llvm/lib/Target/SBF/SBFSubtarget.h @@ -59,9 +59,6 @@ class SBFSubtarget : public SBFGenSubtargetInfo { // Relocate FK_Data_8 fixups as R_SBF_64_ABS64 bool UseRelocAbs64; - // whether the cpu supports native SBF_SDIV - bool HasSdiv; - // Not used for anything, just set by the static-syscalls marker feature. bool HasStaticSyscalls; @@ -81,6 +78,9 @@ class SBFSubtarget : public SBFGenSubtargetInfo { // Whether to encode destination register in Callx's src field bool CallxRegSrc; + // Whether we have the PQR instruction class + bool HasPqrClass; + public: // This constructor initializes the data members to match that // of the specified triple. @@ -97,12 +97,12 @@ class SBFSubtarget : public SBFGenSubtargetInfo { bool getHasJmpExt() const { return HasJmpExt; } bool getHasAlu32() const { return HasAlu32; } bool getHasDynamicFrames() const { return HasDynamicFrames; } - bool getHasSdiv() const { return HasSdiv; } bool getUseDwarfRIS() const { return UseDwarfRIS; } bool getDisableNeg() const { return DisableNeg; } bool getReverseSubImm() const { return ReverseSubImm; } bool getNoLddw() const { return NoLddw; } bool getCallXRegSrc() const { return CallxRegSrc; } + bool getHasPqrClass() const { return HasPqrClass; } const SBFInstrInfo *getInstrInfo() const override { return &InstrInfo; } const SBFFrameLowering *getFrameLowering() const override { diff --git a/llvm/lib/Target/SBF/SBFTargetFeatures.td b/llvm/lib/Target/SBF/SBFTargetFeatures.td index 75115bf36eb290..bc2e83ef973372 100644 --- a/llvm/lib/Target/SBF/SBFTargetFeatures.td +++ b/llvm/lib/Target/SBF/SBFTargetFeatures.td @@ -25,9 +25,6 @@ def FeatureSolana : SubtargetFeature<"solana", "IsSolana", "true", def FeatureDynamicFrames : SubtargetFeature<"dynamic-frames", "HasDynamicFrames", "true", "Enable dynamic frames">; -def FeatureSdiv : SubtargetFeature<"sdiv", "HasSdiv", "true", - "Enable native SBF_SDIV support">; - def FeatureRelocAbs64 : SubtargetFeature<"reloc-abs64", "UseRelocAbs64", "true", "Fix 64bit data relocations">; @@ -46,6 +43,9 @@ def FeatureDisableLddw : SubtargetFeature<"no-lddw", "NoLddw", "true", def FeatureCallxRegSrc : SubtargetFeature<"callx-reg-src", "CallxRegSrc", "true", "Encode Callx destination register in the src field">; +def FeaturePqrInstr : SubtargetFeature<"pqr-instr", "HasPqrClass", "true", + "Enable the PQR instruction class">; + class Proc Features> : Processor; @@ -54,5 +54,6 @@ def : Proc<"v1", []>; def : Proc<"v2", []>; def : Proc<"v3", []>; def : Proc<"probe", []>; -def : Proc<"sbfv2", [FeatureSolana, FeatureDynamicFrames, FeatureSdiv, FeatureRelocAbs64, FeatureStaticSyscalls, - FeatureDisableNeg, FeatureReverseSubImm, FeatureDisableLddw, FeatureCallxRegSrc]>; \ No newline at end of file +def : Proc<"sbfv2", [FeatureSolana, FeatureDynamicFrames, FeatureRelocAbs64, FeatureStaticSyscalls, + FeatureDisableNeg, FeatureReverseSubImm, FeatureDisableLddw, FeatureCallxRegSrc, + FeaturePqrInstr]>; \ No newline at end of file diff --git a/llvm/test/CodeGen/SBF/pqr-class.ll b/llvm/test/CodeGen/SBF/pqr-class.ll new file mode 100644 index 00000000000000..7c8e01093a4ed4 --- /dev/null +++ b/llvm/test/CodeGen/SBF/pqr-class.ll @@ -0,0 +1,196 @@ +; RUN: llc -march=sbf -mcpu=sbfv2 -mattr=+alu32 < %s | FileCheck --check-prefix=CHECK-v2 %s +; RUN: llc -march=sbf -mattr=+alu32 < %s | FileCheck --check-prefix=CHECK-v1 %s + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i64 @test_pqr_unsigned(i64 noundef %a, i64 noundef %b) local_unnamed_addr #0 { +entry: + %div1 = udiv i64 %a, %b + %div2 = udiv i64 %b, 7 + %rem1 = urem i64 %a, %b + %rem2 = urem i64 %b, 17 + +; CHECK-v2: urem64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v2: udiv64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v2: urem64 r{{[0-9]+}}, 17 +; CHECK-v2: udiv64 r{{[0-9]+}}, 7 +; CHECK-v2: lmul64 r{{[0-9]+}}, r2 +; CHECK-V2: lmul64 r{{[0-9]+}}, 7 + +; CHECK-v1: div64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v1: mul64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v1: sub64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v1: add64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v1: div64 r{{[0-9]+}}, 17 +; CHECK-v1: mul64 r{{[0-9]+}}, 17 +; CHECK-v1: mov64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v1: sub64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v1: div64 r{{[0-9]+}}, 7 +; CHECK-v1: mul64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v1: mul64 r{{[0-9]+}}, 7 + + %add1 = add i64 %div1, %rem1 + %add2 = add i64 %div2, %rem2 + + %mul1 = mul i64 %add1, %add2 + %mul2 = mul i64 %mul1, 7 + ret i64 %mul2 +} + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i64 @test_pqr_signed(i64 noundef %a, i64 noundef %b) local_unnamed_addr #0 { +entry: + %div1 = sdiv i64 %a, %b + %div2 = sdiv i64 %b, 7 + %rem1 = srem i64 %a, %b + %rem2 = srem i64 %b, 17 + +; CHECK-v2: srem64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v2: sdiv64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v2: srem64 r{{[0-9]+}}, 17 +; CHECK-v2: sdiv64 r{{[0-9]+}}, 7 +; CHECK-v2: lmul64 r{{[0-9]+}}, r2 +; CHECK-v2: lmul64 r{{[0-9]+}}, 7 + +; CHECK-v1: call __divdi3 +; CHECK-v1: call __moddi3 +; CHECK-v1: call __divdi3 +; CHECK-v1: call __moddi3 + + %add1 = add i64 %div1, %rem1 + %add2 = add i64 %div2, %rem2 + + %mul1 = mul i64 %add1, %add2 + %mul2 = mul i64 %mul1, 7 + ret i64 %mul2 +} + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_pqr_unsigned_32(i32 noundef %a, i32 noundef %b) local_unnamed_addr #0 { +entry: + %div1 = udiv i32 %a, %b + %div2 = udiv i32 %b, 7 + %rem1 = urem i32 %a, %b + %rem2 = urem i32 %b, 17 + +; CHECK-v2: urem32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v2: udiv32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v2: urem32 w{{[0-9]+}}, 17 +; CHECK-v2: udiv32 w{{[0-9]+}}, 7 +; CHECK-v2: lmul32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v2: lmul32 w{{[0-9]+}}, 7 + +; CHECK-v1: div32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v1: mul32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v1: sub32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v1: add32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v1: div32 w{{[0-9]+}}, 17 +; CHECK-v1: mul32 w{{[0-9]+}}, 17 +; CHECK-v1: mov32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v1: sub32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v1: div32 w{{[0-9]+}}, 7 +; CHECK-v1: add32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v1: mul32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v1: mul32 w{{[0-9]+}}, 7 + + %add1 = add i32 %div1, %rem1 + %add2 = add i32 %div2, %rem2 + + %mul1 = mul i32 %add1, %add2 + %mul2 = mul i32 %mul1, 7 + ret i32 %mul2 +} + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_pqr_signed_32(i32 noundef %a, i32 noundef %b) local_unnamed_addr #0 { +entry: + %div1 = sdiv i32 %a, %b + %div2 = sdiv i32 %b, 7 + %rem1 = srem i32 %a, %b + %rem2 = srem i32 %b, 17 + +; CHECK-v2: srem32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v2: sdiv32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v2: srem32 w{{[0-9]+}}, 17 +; CHECK-v2: sdiv32 w{{[0-9]+}}, 7 +; CHECK-v2: lmul32 w{{[0-9]+}}, w{{[0-9]+}} +; CHECK-v2: lmul32 w{{[0-9]+}}, 7 + +; CHECK-v1: call __divsi3 +; CHECK-v1: call __modsi3 +; CHECK-v1: call __divsi3 +; CHECK-v1: call __modsi3 + + %add1 = add i32 %div1, %rem1 + %add2 = add i32 %div2, %rem2 + + %mul1 = mul i32 %add1, %add2 + %mul2 = mul i32 %mul1, 7 + ret i32 %mul2 +} + + +; int64_t try_mul(int64_t a, int64_t b) { +; int64_t c = (a * (unsigned __int128)b) >> 64; +; int64_t d = (73 * (unsigned __int128)b) >> 64; +; return c+d; +; } + +; Function Attrs: mustprogress nofree norecurse nosync nounwind ssp willreturn memory(none) uwtable(sync) +define i64 @uhmul(i64 noundef %a, i64 noundef %b) local_unnamed_addr #0 { +entry: + %conv = zext i64 %a to i128 + %conv1 = zext i64 %b to i128 + %mul = mul nuw i128 %conv1, %conv + %shr = lshr i128 %mul, 64 + %conv2 = trunc i128 %shr to i64 + %mul4 = mul nuw nsw i128 %conv1, 73 + %shr5 = lshr i128 %mul4, 64 + %conv6 = trunc i128 %shr5 to i64 + %add = add i64 %conv2, %conv6 + ret i64 %add + +; CHECK-v2: uhmul64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v2: uhmul64 r{{[0-9]+}}, 73 + +; CHECK-v1: call __multi3 +; CHECK-v1: call __multi3 + +} + +; uint64_t try_mul(int64_t a, int64_t b) { +; uint64_t c = (a * (unsigned __int128)b) >> 64; +; uint64_t d = (73 * (unsigned __int128)b) >> 64; +; return c+d; +; } + +; Function Attrs: mustprogress nofree norecurse nosync nounwind ssp willreturn memory(none) uwtable(sync) +define i64 @shmul(i64 noundef %a, i64 noundef %b) local_unnamed_addr #0 { +entry: + %conv = sext i64 %a to i128 + %conv1 = sext i64 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %shr = lshr i128 %mul, 64 + %conv2 = trunc i128 %shr to i64 + %mul4 = mul nsw i128 %conv1, 73 + %shr5 = lshr i128 %mul4, 64 + %conv6 = trunc i128 %shr5 to i64 + %add = add nsw i64 %conv2, %conv6 + ret i64 %add + +; CHECK-v2: shmul64 r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-v2: shmul64 r{{[0-9]+}}, 73 + +; CHECK-v1: call __multi3 +; CHECK-v1: call __multi3 + +} + + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+solana" } + +!llvm.module.flags = !{!0, !1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"frame-pointer", i32 2} +!2 = !{!"clang version 16.0.5 (https://github.com/solana-labs/llvm-project.git abdbb6e4ef63f7b5b4ee40d2770ed0fca909c2dc)"} diff --git a/llvm/test/MC/Disassembler/SBF/sbf-alu.txt b/llvm/test/MC/Disassembler/SBF/sbf-alu.txt index 38b3f10efe04e5..20e3f701c0d8f6 100644 --- a/llvm/test/MC/Disassembler/SBF/sbf-alu.txt +++ b/llvm/test/MC/Disassembler/SBF/sbf-alu.txt @@ -83,25 +83,6 @@ -# CHECK-NEW: sdiv64 r0, r9 -0xef,0x90,0x00,0x00,0x00,0x00,0x00,0x00 - -# CHECK-NEW: sdiv64 r3, r2 -0xef,0x23,0x00,0x00,0x00,0x00,0x00,0x00 - -# CHECK-NEW: sdiv64 r3, 123 -0xe7,0x03,0x00,0x00,0x7b,0x00,0x00,0x00 - -# CHECK-NEW: sdiv64 r5, -123 -0xe7,0x05,0x00,0x00,0x85,0xff,0xff,0xff - -# CHECK-NEW: sdiv32 w6, w2 -0xec,0x26,0x00,0x00,0x00,0x00,0x00,0x00 - -# CHECK-NEW: sdiv32 w5, -123 -0xe4,0x05,0x00,0x00,0x85,0xff,0xff,0xff - - # CHECK-NEW: hor64 r0, 129 0xf7,0x90,0x00,0x00,0x81,0x00,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/SBF/sbf-pqr.txt b/llvm/test/MC/Disassembler/SBF/sbf-pqr.txt new file mode 100644 index 00000000000000..d941711b1987fe --- /dev/null +++ b/llvm/test/MC/Disassembler/SBF/sbf-pqr.txt @@ -0,0 +1,75 @@ +# RUN: llvm-mc --disassemble %s -triple=sbf-solana-solana \ +# RUN: | FileCheck %s --check-prefix=CHECK + + +# CHECK: uhmul64 r1, 65226 +0x36,0x01,0x00,0x00,0xca,0xfe,0x00,0x00 + +# CHECK: uhmul64 r5, r4 +0x3e,0x45,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: udiv32 w9, 4185 +0x46,0x09,0x00,0x00,0x59,0x10,0x00,0x00 + +# CHECK: udiv32 w3, w2 +0x4e,0x23,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: udiv64 r5, 120 +0x56,0x05,0x00,0x00,0x78,0x00,0x00,0x00 + +# CHECK: udiv64 r7, r6 +0x5e,0x67,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: urem32 w5, 27 +0x66,0x05,0x00,0x00,0x1b,0x00,0x00,0x00 + +# CHECK: urem32 w8, w2 +0x6e,0x28,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: urem64 r2, 125 +0x76,0x02,0x00,0x00,0x7d,0x00,0x00,0x00 + +# CHECK: urem64 r4, r3 +0x7e,0x34,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: lmul32 w3, 29819 +0x86,0x03,0x00,0x00,0x7b,0x74,0x00,0x00 + +# CHECK: lmul32 w9, w10 +0x8e,0xa9,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: lmul64 r7, 903 +0x96,0x07,0x00,0x00,0x87,0x03,0x00,0x00 + +# CHECK: lmul64 r8, r2 +0x9e,0x28,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: shmul64 r7, 629 +0xb6,0x07,0x00,0x00,0x75,0x02,0x00,0x00 + +# CHECK: shmul64 r10, r9 +0xbe,0x9a,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: sdiv32 w10, 14912 +0xc6,0x0a,0x00,0x00,0x40,0x3a,0x00,0x00 + +# CHECK: sdiv32 w1, w10 +0xce,0xa1,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: sdiv64 r10, 15804061 +0xd6,0x0a,0x00,0x00,0x9d,0x26,0xf1,0x00 + +# CHECK: sdiv64 r9, r10 +0xde,0xa9,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: srem32 w3, -98 +0xe6,0x03,0x00,0x00,0x9e,0xff,0xff,0xff + +# CHECK: srem32 w11, w10 +0xee,0xab,0x00,0x00,0x00,0x00,0x00,0x00 + +# CHECK: srem64 r7, -987 +0xf6,0x07,0x00,0x00,0x25,0xfc,0xff,0xff + +# CHECK: srem64 r6, r5 +0xfe,0x56,0x00,0x00,0x00,0x00,0x00,0x00 \ No newline at end of file diff --git a/llvm/test/MC/SBF/sbf-alu.s b/llvm/test/MC/SBF/sbf-alu.s index 7cc5ce6d2a3464..eb0d5da9de0411 100644 --- a/llvm/test/MC/SBF/sbf-alu.s +++ b/llvm/test/MC/SBF/sbf-alu.s @@ -111,30 +111,6 @@ div32 w5, -123 -# CHECK-OBJ-NEW: sdiv64 r0, r9 -# CHECK-ASM-NEW: encoding: [0xef,0x90,0x00,0x00,0x00,0x00,0x00,0x00] -sdiv64 r0, r9 - -# CHECK-OBJ-NEW: sdiv64 r3, r2 -# CHECK-ASM-NEW: encoding: [0xef,0x23,0x00,0x00,0x00,0x00,0x00,0x00] -sdiv64 r3, r2 - -# CHECK-OBJ-NEW: sdiv64 r3, 0x7b -# CHECK-ASM-NEW: encoding: [0xe7,0x03,0x00,0x00,0x7b,0x00,0x00,0x00] -sdiv64 r3, 123 - -# CHECK-OBJ-NEW: sdiv64 r5, -0x7b -# CHECK-ASM-NEW: encoding: [0xe7,0x05,0x00,0x00,0x85,0xff,0xff,0xff] -sdiv64 r5, -123 - -# CHECK-OBJ-NEW: sdiv32 w6, w2 -# CHECK-ASM-NEW: encoding: [0xec,0x26,0x00,0x00,0x00,0x00,0x00,0x00] -sdiv32 w6, w2 - -# CHECK-OBJ-NEW: sdiv32 w5, -0x7b -# CHECK-ASM-NEW: encoding: [0xe4,0x05,0x00,0x00,0x85,0xff,0xff,0xff] -sdiv32 w5, -123 - # CHECK-OBJ-NEW: hor64 r0, 0x2c4 # CHECK-ASM-NEW: encoding: [0xf7,0x00,0x00,0x00,0xc4,0x02,0x00,0x00] hor64 r0, 708 diff --git a/llvm/test/MC/SBF/sbf-pqr.s b/llvm/test/MC/SBF/sbf-pqr.s new file mode 100644 index 00000000000000..d2d1a65a25f8b7 --- /dev/null +++ b/llvm/test/MC/SBF/sbf-pqr.s @@ -0,0 +1,102 @@ +# RUN: llvm-mc %s -triple=sbf-solana-solana --mcpu=sbfv2 --show-encoding \ +# RUN: | FileCheck %s --check-prefix=CHECK-ASM-NEW +# RUN: llvm-mc %s -triple=sbf-solana-solana --mcpu=sbfv2 -filetype=obj \ +# RUN: | llvm-objdump -d -r --mattr=+alu32 - \ +# RUN: | FileCheck --check-prefix=CHECK-OBJ-NEW %s + + +# CHECK-OBJ-NEW: uhmul64 r1, 0x1b +# CHECK-ASM-NEW: encoding: [0x36,0x01,0x00,0x00,0x1b,0x00,0x00,0x00] +uhmul64 r1, 27 + +# CHECK-OBJ-NEW: uhmul64 r2, r3 +# CHECK-ASM-NEW: encoding: [0x3e,0x32,0x00,0x00,0x00,0x00,0x00,0x00] +uhmul64 r2, r3 + +# CHECK-OBJ-NEW: udiv32 w4, 0x59 +# CHECK-ASM-NEW: encoding: [0x46,0x04,0x00,0x00,0x59,0x00,0x00,0x00] +udiv32 w4, 89 + +# CHECK-OBJ-NEW: udiv32 w4, w5 +# CHECK-ASM-NEW: encoding: [0x4e,0x54,0x00,0x00,0x00,0x00,0x00,0x00] +udiv32 w4, w5 + +# CHECK-OBJ-NEW: udiv64 r5, 0x63 +# CHECK-ASM-NEW: encoding: [0x56,0x05,0x00,0x00,0x63,0x00,0x00,0x00] +udiv64 r5, 99 + +# CHECK-OBJ-NEW: udiv64 r6, r7 +# CHECK-ASM-NEW: encoding: [0x5e,0x76,0x00,0x00,0x00,0x00,0x00,0x00] +udiv64 r6, r7 + +# CHECK-OBJ-NEW: urem32 w9, 0xb +# CHECK-ASM-NEW: encoding: [0x66,0x09,0x00,0x00,0x0b,0x00,0x00,0x00] +urem32 w9, 11 + +# CHECK-OBJ-NEW: urem32 w2, w1 +# CHECK-ASM-NEW: encoding: [0x6e,0x12,0x00,0x00,0x00,0x00,0x00,0x00] +urem32 w2, w1 + +# CHECK-OBJ-NEW: urem64 r4, 0x4d +# CHECK-ASM-NEW: encoding: [0x76,0x04,0x00,0x00,0x4d,0x00,0x00,0x00] +urem64 r4, 77 + +# CHECK-OBJ-NEW: urem64 r4, r3 +# CHECK-ASM-NEW: encoding: [0x7e,0x34,0x00,0x00,0x00,0x00,0x00,0x00] +urem64 r4, r3 + +# CHECK-OBJ-NEW: lmul32 w4, 0x7b +# CHECK-ASM-NEW: encoding: [0x86,0x04,0x00,0x00,0x7b,0x00,0x00,0x00] +lmul32 w4, 123 + +# CHECK-OBJ-NEW: lmul32 w5, w4 +# CHECK-ASM-NEW: encoding: [0x8e,0x45,0x00,0x00,0x00,0x00,0x00,0x00] +lmul32 w5, w4 + +# CHECK-OBJ-NEW: lmul64 r6, 0x387 +# CHECK-ASM-NEW: encoding: [0x96,0x06,0x00,0x00,0x87,0x03,0x00,0x00] +lmul64 r6, 903 + +# CHECK-OBJ-NEW: lmul64 r8, r7 +# CHECK-ASM-NEW: encoding: [0x9e,0x78,0x00,0x00,0x00,0x00,0x00,0x00] +lmul64 r8, r7 + +# CHECK-OBJ-NEW: shmul64 r8, 0x275 +# CHECK-ASM-NEW: encoding: [0xb6,0x08,0x00,0x00,0x75,0x02,0x00,0x00] +shmul64 r8, 629 + +# CHECK-OBJ-NEW: shmul64 r9, r8 +# CHECK-ASM-NEW: encoding: [0xbe,0x89,0x00,0x00,0x00,0x00,0x00,0x00] +shmul64 r9, r8 + +# CHECK-OBJ-NEW: sdiv32 w10, 0x3a40 +# CHECK-ASM-NEW: encoding: [0xc6,0x0a,0x00,0x00,0x40,0x3a,0x00,0x00] +sdiv32 w10, 14912 + +# CHECK-OBJ-NEW: sdiv32 w10, w9 +# CHECK-ASM-NEW: encoding: [0xce,0x9a,0x00,0x00,0x00,0x00,0x00,0x00] +sdiv32 w10, w9 + +# CHECK-OBJ-NEW: sdiv64 r10, 0x1269d +# CHECK-ASM-NEW: encoding: [0xd6,0x0a,0x00,0x00,0x9d,0x26,0x01,0x00] +sdiv64 r10, 75421 + +# CHECK-OBJ-NEW: sdiv64 r9, r10 +# CHECK-ASM-NEW: encoding: [0xde,0xa9,0x00,0x00,0x00,0x00,0x00,0x00] +sdiv64 r9, r10 + +# CHECK-OBJ-NEW: srem32 w3, -0x62 +# CHECK-ASM-NEW: encoding: [0xe6,0x03,0x00,0x00,0x9e,0xff,0xff,0xff] +srem32 w3, -98 + +# CHECK-OBJ-NEW: srem32 w4, w3 +# CHECK-ASM-NEW: encoding: [0xee,0x34,0x00,0x00,0x00,0x00,0x00,0x00] +srem32 w4, w3 + +# CHECK-OBJ-NEW: srem64 r7, -0x3db +# CHECK-ASM-NEW: encoding: [0xf6,0x07,0x00,0x00,0x25,0xfc,0xff,0xff] +srem64 r7, -987 + +# CHECK-OBJ-NEW: srem64 r10, r5 +# CHECK-ASM-NEW: encoding: [0xfe,0x5a,0x00,0x00,0x00,0x00,0x00,0x00] +srem64 r10, r5 diff --git a/llvm/test/MC/SBF/sbf-sdiv.s b/llvm/test/MC/SBF/sbf-sdiv.s deleted file mode 100644 index 81c002d0712e88..00000000000000 --- a/llvm/test/MC/SBF/sbf-sdiv.s +++ /dev/null @@ -1,15 +0,0 @@ -# RUN: llvm-mc -triple sbf --mcpu=sbfv2 -filetype=obj -o %t %s -# RUN: llvm-objdump -d -r %t | FileCheck %s - -sdiv32 w1, w2 // BPF_SDIV | BPF_X -// CHECK: ec 21 00 00 00 00 00 00 sdiv32 w1, w2 - -sdiv32 w3, 6 // BPF_SDIV | BPF_K -// CHECK: e4 03 00 00 06 00 00 00 sdiv32 w3, 0x6 - - -sdiv64 r4, r5 // BPF_SDIV | BPF_X -// CHECK: ef 54 00 00 00 00 00 00 sdiv64 r4, r5 - -sdiv64 r5, 6 // BPF_SDIV | BPF_K -// CHECK: e7 05 00 00 06 00 00 00 sdiv64 r5, 0x6 From aa4788d7c5d5e3bac74bf452f570524dadf25c2d Mon Sep 17 00:00:00 2001 From: Lucas Steuernagel <38472950+LucasSte@users.noreply.github.com> Date: Wed, 17 Jan 2024 09:39:29 -0300 Subject: [PATCH 2/2] Update llvm/lib/Target/SBF/SBFInstrInfo.td --- llvm/lib/Target/SBF/SBFInstrInfo.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td index bbd238ee0cc681..95ce0ec412c035 100644 --- a/llvm/lib/Target/SBF/SBFInstrInfo.td +++ b/llvm/lib/Target/SBF/SBFInstrInfo.td @@ -142,7 +142,7 @@ class TYPE_ALU_JMP op, bits<1> srctype, bit IsPqr64 = 0> : InstSBF { - // In the PQR class, instructions that deal with 64-bit registers have a difference OpCode. + // In the PQR class, instructions that deal with 64-bit registers have a different OpCode. // To obtain it, we add one to its base value. let Inst{63-60} = !if(IsPqr64, !add(op, 1), op); let Inst{59} = srctype;