buildroot.patch

diff --git a/board/ciaa/acc/busybox_defconfig b/board/ciaa/acc/busybox_defconfig
new file mode 100644
index 0000000..2cdb8c9
--- /dev/null
+++ b/board/ciaa/acc/busybox_defconfig
@@ -0,0 +1,1135 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Thu Nov 16 11:22:34 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+# CONFIG_FEATURE_COMPRESS_USAGE is not set
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+# CONFIG_FEATURE_PIDFILE is not set
+CONFIG_PID_FILE_PATH=""
+CONFIG_FEATURE_SUID=y
+# CONFIG_FEATURE_SUID_CONFIG is not set
+# CONFIG_FEATURE_SUID_CONFIG_QUIET is not set
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_STATIC is not set
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS=""
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+CONFIG_FEATURE_EDITING_VI=y
+CONFIG_FEATURE_EDITING_HISTORY=999
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+# CONFIG_FEATURE_USERNAME_COMPLETION is not set
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+# CONFIG_UNICODE_SUPPORT is not set
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=0
+CONFIG_LAST_SUPPORTED_WCHAR=0
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+CONFIG_FEATURE_SEAMLESS_Z=y
+CONFIG_AR=y
+CONFIG_FEATURE_AR_LONG_FILENAMES=y
+CONFIG_FEATURE_AR_CREATE=y
+CONFIG_UNCOMPRESS=y
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+CONFIG_FEATURE_LZMA_FAST=y
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+# CONFIG_DPKG is not set
+# CONFIG_DPKG_DEB is not set
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+CONFIG_FEATURE_GZIP_LEVELS=y
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+CONFIG_UNLZOP=y
+CONFIG_LZOPCAT=y
+CONFIG_LZOP_COMPR_HIGH=y
+# CONFIG_RPM is not set
+# CONFIG_RPM2CPIO is not set
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+# CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY is not set
+# CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY is not set
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+# CONFIG_FEATURE_CHOWN_LONG_OPTIONS is not set
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+# CONFIG_COMM is not set
+CONFIG_CP=y
+# CONFIG_FEATURE_CP_LONG_OPTIONS is not set
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+# CONFIG_FEATURE_DD_THIRD_STATUS_LINE is not set
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+# CONFIG_FEATURE_DF_FANCY is not set
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+# CONFIG_FEATURE_ENV_LONG_OPTIONS is not set
+# CONFIG_EXPAND is not set
+# CONFIG_FEATURE_EXPAND_LONG_OPTIONS is not set
+# CONFIG_UNEXPAND is not set
+# CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS is not set
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+# CONFIG_FSYNC is not set
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+# CONFIG_GROUPS is not set
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+CONFIG_FEATURE_LS_COLOR=y
+CONFIG_FEATURE_LS_COLOR_IS_DEFAULT=y
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+# CONFIG_FEATURE_RMDIR_LONG_OPTIONS is not set
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+# CONFIG_SHUF is not set
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+# CONFIG_SPLIT is not set
+# CONFIG_FEATURE_SPLIT_FANCY is not set
+# CONFIG_STAT is not set
+# CONFIG_FEATURE_STAT_FORMAT is not set
+# CONFIG_FEATURE_STAT_FILESYSTEM is not set
+CONFIG_STTY=y
+# CONFIG_SUM is not set
+CONFIG_SYNC=y
+# CONFIG_FEATURE_SYNC_FANCY is not set
+# CONFIG_TAC is not set
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+# CONFIG_TIMEOUT is not set
+CONFIG_TOUCH=y
+# CONFIG_FEATURE_TOUCH_NODEREF is not set
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+# CONFIG_BASE64 is not set
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+# CONFIG_FEATURE_WC_LARGE is not set
+CONFIG_WHO=y
+CONFIG_W=y
+# CONFIG_USERS is not set
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+# CONFIG_FGCONSOLE is not set
+# CONFIG_KBD_MODE is not set
+CONFIG_LOADFONT=y
+# CONFIG_SETFONT is not set
+# CONFIG_FEATURE_SETFONT_TEXTUAL_MAP is not set
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+# CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS is not set
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+# CONFIG_SHOWKEY is not set
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+# CONFIG_FEATURE_RUN_PARTS_FANCY is not set
+CONFIG_START_STOP_DAEMON=y
+CONFIG_FEATURE_START_STOP_DAEMON_LONG_OPTIONS=y
+CONFIG_FEATURE_START_STOP_DAEMON_FANCY=y
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+# CONFIG_FEATURE_AWK_LIBM is not set
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+# CONFIG_FEATURE_DIFF_LONG_OPTIONS is not set
+CONFIG_FEATURE_DIFF_DIR=y
+# CONFIG_ED is not set
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+CONFIG_FEATURE_VI_8BIT=y
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+# CONFIG_FEATURE_FIND_INUM is not set
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+# CONFIG_FEATURE_FIND_DELETE is not set
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+# CONFIG_FEATURE_FIND_LINKS is not set
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+# CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION is not set
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+# CONFIG_BOOTCHARTD is not set
+# CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER is not set
+# CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE is not set
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+CONFIG_LINUXRC=y
+CONFIG_FEATURE_USE_INITTAB=y
+CONFIG_FEATURE_KILL_REMOVED=y
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+# CONFIG_USE_BB_PWD_GRP is not set
+# CONFIG_USE_BB_SHADOW is not set
+CONFIG_USE_BB_CRYPT=y
+# CONFIG_USE_BB_CRYPT_SHA is not set
+# CONFIG_ADD_SHELL is not set
+# CONFIG_REMOVE_SHELL is not set
+CONFIG_ADDGROUP=y
+# CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS is not set
+# CONFIG_FEATURE_ADDUSER_TO_GROUP is not set
+CONFIG_ADDUSER=y
+# CONFIG_FEATURE_ADDUSER_LONG_OPTIONS is not set
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+# CONFIG_CHPASSWD is not set
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="md5"
+# CONFIG_CRYPTPW is not set
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+# CONFIG_FEATURE_DEL_USER_FROM_GROUP is not set
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+# CONFIG_LOGIN_SCRIPTS is not set
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+# CONFIG_MODPROBE_SMALL is not set
+# CONFIG_DEPMOD is not set
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT=y
+# CONFIG_MODINFO is not set
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+# CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED is not set
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+CONFIG_FEATURE_CHECK_TAINTED_MODULE=y
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+CONFIG_FEATURE_MODUTILS_ALIAS=y
+CONFIG_FEATURE_MODUTILS_SYMBOLS=y
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+# CONFIG_ACPID is not set
+# CONFIG_FEATURE_ACPID_COMPAT is not set
+# CONFIG_BLKDISCARD is not set
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+# CONFIG_BLOCKDEV is not set
+# CONFIG_CAL is not set
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+# CONFIG_FEATURE_EJECT_SCSI is not set
+CONFIG_FALLOCATE=y
+# CONFIG_FATATTR is not set
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+# CONFIG_FINDFS is not set
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+# CONFIG_FSCK_MINIX is not set
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+# CONFIG_FEATURE_HEXDUMP_REVERSE is not set
+# CONFIG_HD is not set
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS=y
+# CONFIG_IONICE is not set
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+# CONFIG_FEATURE_LAST_FANCY is not set
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+# CONFIG_FEATURE_MDEV_RENAME_REGEXP is not set
+CONFIG_FEATURE_MDEV_EXEC=y
+# CONFIG_FEATURE_MDEV_LOAD_FIRMWARE is not set
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+# CONFIG_MKFS_EXT2 is not set
+# CONFIG_MKFS_MINIX is not set
+# CONFIG_FEATURE_MINIX2 is not set
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+# CONFIG_MKFS_VFAT is not set
+CONFIG_MKSWAP=y
+# CONFIG_FEATURE_MKSWAP_UUID is not set
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+# CONFIG_FEATURE_MOUNT_FAKE is not set
+# CONFIG_FEATURE_MOUNT_VERBOSE is not set
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+# CONFIG_FEATURE_MOUNT_LABEL is not set
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+# CONFIG_NSENTER is not set
+# CONFIG_FEATURE_NSENTER_LONG_OPTS is not set
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+# CONFIG_RDEV is not set
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+# CONFIG_REV is not set
+# CONFIG_RTCWAKE is not set
+# CONFIG_SCRIPT is not set
+# CONFIG_SCRIPTREPLAY is not set
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+# CONFIG_FEATURE_SWAPON_DISCARD is not set
+# CONFIG_FEATURE_SWAPON_PRI is not set
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+# CONFIG_TASKSET is not set
+# CONFIG_FEATURE_TASKSET_FANCY is not set
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+# CONFIG_UNSHARE is not set
+# CONFIG_WALL is not set
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+# CONFIG_FEATURE_VOLUMEID_BCACHE is not set
+# CONFIG_FEATURE_VOLUMEID_BTRFS is not set
+# CONFIG_FEATURE_VOLUMEID_CRAMFS is not set
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+# CONFIG_FEATURE_VOLUMEID_HFS is not set
+# CONFIG_FEATURE_VOLUMEID_ISO9660 is not set
+# CONFIG_FEATURE_VOLUMEID_JFS is not set
+# CONFIG_FEATURE_VOLUMEID_LINUXRAID is not set
+# CONFIG_FEATURE_VOLUMEID_LINUXSWAP is not set
+# CONFIG_FEATURE_VOLUMEID_LUKS is not set
+# CONFIG_FEATURE_VOLUMEID_NILFS is not set
+# CONFIG_FEATURE_VOLUMEID_NTFS is not set
+# CONFIG_FEATURE_VOLUMEID_OCFS2 is not set
+# CONFIG_FEATURE_VOLUMEID_REISERFS is not set
+# CONFIG_FEATURE_VOLUMEID_ROMFS is not set
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+# CONFIG_FEATURE_VOLUMEID_SYSV is not set
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+# CONFIG_FEATURE_VOLUMEID_UDF is not set
+# CONFIG_FEATURE_VOLUMEID_XFS is not set
+
+#
+# Miscellaneous Utilities
+#
+# CONFIG_ADJTIMEX is not set
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+# CONFIG_BEEP is not set
+CONFIG_FEATURE_BEEP_FREQ=0
+CONFIG_FEATURE_BEEP_LENGTH_MS=0
+# CONFIG_CHAT is not set
+# CONFIG_FEATURE_CHAT_NOFAIL is not set
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+# CONFIG_FEATURE_CHAT_IMPLICIT_CR is not set
+# CONFIG_FEATURE_CHAT_SWALLOW_OPTS is not set
+# CONFIG_FEATURE_CHAT_SEND_ESCAPES is not set
+# CONFIG_FEATURE_CHAT_VAR_ABORT_LEN is not set
+# CONFIG_FEATURE_CHAT_CLR_ABORT is not set
+# CONFIG_CONSPY is not set
+CONFIG_CROND=y
+# CONFIG_FEATURE_CROND_D is not set
+# CONFIG_FEATURE_CROND_CALL_SENDMAIL is not set
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+# CONFIG_FEATURE_DC_LIBM is not set
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+# CONFIG_FBSPLASH is not set
+CONFIG_FLASH_ERASEALL=y
+CONFIG_FLASH_LOCK=y
+CONFIG_FLASH_UNLOCK=y
+CONFIG_FLASHCP=y
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+# CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF is not set
+# CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF is not set
+# CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET is not set
+# CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF is not set
+# CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA is not set
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+# CONFIG_FEATURE_LESS_MARKS is not set
+CONFIG_FEATURE_LESS_REGEXP=y
+# CONFIG_FEATURE_LESS_WINCH is not set
+# CONFIG_FEATURE_LESS_ASK_TERMINAL is not set
+# CONFIG_FEATURE_LESS_DASHCMD is not set
+# CONFIG_FEATURE_LESS_LINENUMS is not set
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+# CONFIG_MAN is not set
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+# CONFIG_NANDWRITE is not set
+# CONFIG_NANDDUMP is not set
+CONFIG_PARTPROBE=y
+# CONFIG_RAIDAUTORUN is not set
+# CONFIG_READAHEAD is not set
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+# CONFIG_TTYSIZE is not set
+CONFIG_UBIATTACH=y
+CONFIG_UBIDETACH=y
+CONFIG_UBIMKVOL=y
+CONFIG_UBIRMVOL=y
+CONFIG_UBIRSVOL=y
+CONFIG_UBIUPDATEVOL=y
+CONFIG_UBIRENAME=y
+# CONFIG_VOLNAME is not set
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+# CONFIG_BRCTL is not set
+# CONFIG_FEATURE_BRCTL_FANCY is not set
+# CONFIG_FEATURE_BRCTL_SHOW is not set
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+# CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS is not set
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+# CONFIG_FAKEIDENTD is not set
+CONFIG_NAMEIF=y
+# CONFIG_FEATURE_NAMEIF_EXTENDED is not set
+# CONFIG_NBDCLIENT is not set
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+# CONFIG_FEATURE_NETSTAT_WIDE is not set
+# CONFIG_FEATURE_NETSTAT_PRG is not set
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+# CONFIG_PING6 is not set
+CONFIG_FEATURE_FANCY_PING=y
+# CONFIG_PSCAN is not set
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+# CONFIG_FEATURE_WGET_HTTPS is not set
+# CONFIG_FEATURE_WGET_OPENSSL is not set
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+CONFIG_UDHCPC6=y
+CONFIG_FEATURE_UDHCPC6_RFC3646=y
+CONFIG_FEATURE_UDHCPC6_RFC4704=y
+CONFIG_FEATURE_UDHCPC6_RFC4833=y
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+# CONFIG_DUMPLEASES is not set
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+CONFIG_FEATURE_UDHCP_PORT=y
+CONFIG_UDHCP_DEBUG=0
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+# CONFIG_LPD is not set
+# CONFIG_LPR is not set
+# CONFIG_LPQ is not set
+
+#
+# Mail Utilities
+#
+# CONFIG_MAKEMIME is not set
+# CONFIG_POPMAILDIR is not set
+# CONFIG_FEATURE_POPMAILDIR_DELIVERY is not set
+# CONFIG_REFORMIME is not set
+# CONFIG_FEATURE_REFORMIME_COMPAT is not set
+# CONFIG_SENDMAIL is not set
+CONFIG_FEATURE_MIME_CHARSET=""
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+# CONFIG_POWERTOP is not set
+# CONFIG_FEATURE_POWERTOP_INTERACTIVE is not set
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+# CONFIG_CHPST is not set
+# CONFIG_SETUIDGID is not set
+# CONFIG_ENVUIDGID is not set
+# CONFIG_ENVDIR is not set
+# CONFIG_SOFTLIMIT is not set
+# CONFIG_RUNSV is not set
+# CONFIG_RUNSVDIR is not set
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+# CONFIG_SV is not set
+CONFIG_SV_DEFAULT_SERVICE_DIR=""
+CONFIG_SVC=y
+# CONFIG_SVLOGD is not set
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+# CONFIG_BASH_IS_ASH is not set
+# CONFIG_BASH_IS_HUSH is not set
+CONFIG_BASH_IS_NONE=y
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+# CONFIG_ASH_MAIL is not set
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+# CONFIG_CTTYHACK is not set
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+# CONFIG_FEATURE_SH_HISTFILESIZE is not set
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+# CONFIG_LOGREAD is not set
+# CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING is not set
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+# CONFIG_FEATURE_SYSLOGD_DUP is not set
+# CONFIG_FEATURE_SYSLOGD_CFG is not set
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+# CONFIG_FEATURE_IPC_SYSLOG is not set
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=0
+# CONFIG_FEATURE_KMSG_SYSLOG is not set
diff --git a/board/ciaa/acc/ciaa_acc_defconfig b/board/ciaa/acc/ciaa_acc_defconfig
new file mode 100644
index 0000000..fdb5418
--- /dev/null
+++ b/board/ciaa/acc/ciaa_acc_defconfig
@@ -0,0 +1,966 @@
+CONFIG_ARM=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-xilinx"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_FHANDLE=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_SRCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_BUILD_BIN2C=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_NMI_LOG_BUF_SHIFT=13
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_HAVE_UID16=y
+CONFIG_BPF=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_MULTIUSER=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_PRINTK=y
+CONFIG_PRINTK_NMI=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_MEMBARRIER=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PERF_EVENTS=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_NMI=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_GCC_PLUGINS=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_CC_STACKPROTECTOR_NONE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_HAVE_EXIT_THREAD=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_BITS=8
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_CFQ=y
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+CONFIG_MMU=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_XILINX_PREFETCH=y
+CONFIG_PLAT_VERSATILE=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_SWP_EMULATE=y
+CONFIG_KUSER_HELPERS=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_CACHE_L2X0=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+CONFIG_DEBUG_RODATA=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ICST=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCIE_XILINX=y
+CONFIG_HAVE_SMP=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+CONFIG_ARCH_NR_GPIO=1024
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_100=y
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_AEABI=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_CPU_SW_DOMAIN_PAN=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+CONFIG_BOUNCE=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CMA=y
+CONFIG_CMA_AREAS=7
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_FRAME_VECTOR=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_SWIOTLB=y
+CONFIG_IOMMU_HELPER=y
+CONFIG_USE_OF=y
+CONFIG_ATAGS=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CMDLINE=""
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_ARM_ZYNQ_CPUIDLE=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+CONFIG_BINFMT_ELF=y
+CONFIG_ELFCORE=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_COREDUMP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_VLAN_8021Q=m
+CONFIG_LLC=m
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_GW=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_CAN_XILINXCAN=y
+CONFIG_WIRELESS=y
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_DST_CACHE=y
+CONFIG_MAY_USE_DEVLINK=y
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_ARM_AMBA=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_SOC_BUS=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=16
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_PL35X=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_DTC=y
+CONFIG_OF=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_NET=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_CONFIGFS=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SRAM=y
+CONFIG_VEXPRESS_SYSCFG=y
+CONFIG_XILINX_TRAFGEN=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_HAVE_IDE=y
+CONFIG_SCSI_MOD=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_PROC_FS=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_HAVE_PATA_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_3COM=y
+CONFIG_NET_VENDOR_ADAPTEC=y
+CONFIG_NET_VENDOR_AGERE=y
+CONFIG_NET_VENDOR_ALTEON=y
+CONFIG_NET_VENDOR_AMAZON=y
+CONFIG_NET_VENDOR_AMD=y
+CONFIG_NET_VENDOR_ARC=y
+CONFIG_NET_VENDOR_ATHEROS=y
+CONFIG_NET_CADENCE=y
+CONFIG_MACB=y
+CONFIG_NET_VENDOR_BROADCOM=y
+CONFIG_NET_VENDOR_BROCADE=y
+CONFIG_NET_VENDOR_CAVIUM=y
+CONFIG_NET_VENDOR_CHELSIO=y
+CONFIG_NET_VENDOR_CISCO=y
+CONFIG_NET_VENDOR_DEC=y
+CONFIG_NET_VENDOR_DLINK=y
+CONFIG_NET_VENDOR_EMULEX=y
+CONFIG_NET_VENDOR_EZCHIP=y
+CONFIG_NET_VENDOR_EXAR=y
+CONFIG_NET_VENDOR_HISILICON=y
+CONFIG_NET_VENDOR_HP=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_E1000E=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_MELLANOX=y
+CONFIG_NET_VENDOR_MYRI=y
+CONFIG_NET_VENDOR_NETRONOME=y
+CONFIG_NET_VENDOR_NVIDIA=y
+CONFIG_NET_VENDOR_OKI=y
+CONFIG_NET_PACKET_ENGINE=y
+CONFIG_NET_VENDOR_QLOGIC=y
+CONFIG_NET_VENDOR_QUALCOMM=y
+CONFIG_NET_VENDOR_REALTEK=y
+CONFIG_R8169=y
+CONFIG_NET_VENDOR_RENESAS=y
+CONFIG_NET_VENDOR_RDC=y
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_NET_VENDOR_SAMSUNG=y
+CONFIG_NET_VENDOR_SILAN=y
+CONFIG_NET_VENDOR_SIS=y
+CONFIG_NET_VENDOR_SUN=y
+CONFIG_NET_VENDOR_SYNOPSYS=y
+CONFIG_NET_VENDOR_TEHUTI=y
+CONFIG_NET_VENDOR_TI=y
+CONFIG_NET_VENDOR_XILINX=y
+CONFIG_XILINX_EMACLITE=y
+CONFIG_XILINX_AXI_EMAC=y
+CONFIG_XILINX_PS_EMAC=y
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_FIXED_PHY=y
+CONFIG_MARVELL_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_WLAN=y
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_WLAN_VENDOR_ATH=y
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_WLAN_VENDOR_INTERSIL=y
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WLAN_VENDOR_ZYDAS=y
+CONFIG_INPUT=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_POLLDEV=y
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_DEVMEM=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_XILINX_NR_UARTS=2
+CONFIG_XILINX_DEVCFG=y
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_CADENCE=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CADENCE=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPI_ZYNQ_QSPI=y
+CONFIG_PPS=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PINCTRL=y
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_PINCTRL_ZYNQ=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_GPIOLIB=y
+CONFIG_OF_GPIO=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_XILINX=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_HWMON=y
+CONFIG_PMBUS=y
+CONFIG_SENSORS_PMBUS=y
+CONFIG_SENSORS_UCD9000=y
+CONFIG_SENSORS_UCD9200=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_CADENCE_WATCHDOG=y
+CONFIG_SSB_POSSIBLE=y
+CONFIG_BCMA_POSSIBLE=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CEC_EDID=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEOBUF2_MEMOPS=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_XILINX=y
+CONFIG_VIDEO_XILINX_CFA=y
+CONFIG_VIDEO_XILINX_CRESAMPLE=y
+CONFIG_VIDEO_XILINX_REMAPPER=y
+CONFIG_VIDEO_XILINX_RGB2YUV=y
+CONFIG_VIDEO_XILINX_SCALER=y
+CONFIG_VIDEO_XILINX_SWITCH=y
+CONFIG_VIDEO_XILINX_TPG=y
+CONFIG_VIDEO_XILINX_VTC=y
+CONFIG_VIDEO_ADV7604=y
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_DRM=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_GEM_CMA_HELPER=y
+CONFIG_DRM_KMS_CMA_HELPER=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_XILINX=y
+CONFIG_DRM_XILINX_DP=y
+CONFIG_DRM_XILINX_DP_SUB=y
+CONFIG_FB=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_HDMI=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_PCI=y
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_ADI=y
+CONFIG_SND_SOC_ADI_AXI_I2S=y
+CONFIG_SND_SOC_ADI_AXI_SPDIF=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_USB_HID=y
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_DEFAULT_PERSIST=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_OF=y
+CONFIG_USB_CHIPIDEA_PCI=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_USB_GADGET_XILINX=y
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_F_SS_LB=m
+CONFIG_USB_F_MASS_STORAGE=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_ZERO=m
+CONFIG_MMC=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_SYNOPSYS=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_PL330_DMA=y
+CONFIG_XILINX_DMA_ENGINES=y
+CONFIG_XILINX_FRMBUF=y
+CONFIG_XILINX_DMA=y
+CONFIG_UIO=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_XILINX_APM=m
+CONFIG_VIRTIO=m
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_VERSATILE=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_COMMON_CLK_SI570=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CADENCE_TTC_TIMER=y
+CONFIG_ARM_GLOBAL_TIMER=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
+CONFIG_CLKSRC_VERSATILE=y
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_REMOTEPROC=m
+CONFIG_ZYNQ_REMOTEPROC=m
+CONFIG_RPMSG=m
+CONFIG_RPMSG_VIRTIO=m
+CONFIG_EXTCON=y
+CONFIG_MEMORY=y
+CONFIG_PL35X_SMC=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+CONFIG_XILINX_XADC=y
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_MAX_NR=1
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_ZYNQ=y
+CONFIG_ARM_PMU=y
+CONFIG_RAS=y
+CONFIG_NVMEM=y
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_GRACE_PERIOD=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_TIMER_STATS=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=m
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_DRBG_MENU=m
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG=m
+CONFIG_CRYPTO_JITTERENTROPY=m
+CONFIG_CRYPTO_HW=y
+CONFIG_BITREVERSE=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_CRC16=y
+CONFIG_CRC32=y
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_LIBFDT=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_SG_POOL=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_SBITMAP=y
+CONFIG_VIRTUALIZATION=y
diff --git a/board/ciaa/acc/device_table.txt b/board/ciaa/acc/device_table.txt
new file mode 100644
index 0000000..7767478
--- /dev/null
+++ b/board/ciaa/acc/device_table.txt
@@ -0,0 +1,2 @@
+/etc/init.d/S35mount    f 755 0 0 - - - - -
+/etc/init.d/S50dropbear f 755 0 0 - - - - -
diff --git a/board/ciaa/acc/overlay_fs/etc/default/dropbear b/board/ciaa/acc/overlay_fs/etc/default/dropbear
new file mode 100644
index 0000000..91fc032
--- /dev/null
+++ b/board/ciaa/acc/overlay_fs/etc/default/dropbear
@@ -0,0 +1,3 @@
+# Allow blank password on dropbear ssh server
+DROPBEAR_ARGS=-B
+
diff --git a/board/ciaa/acc/overlay_fs/etc/init.d/S35mount b/board/ciaa/acc/overlay_fs/etc/init.d/S35mount
new file mode 100644
index 0000000..0801bbe
--- /dev/null
+++ b/board/ciaa/acc/overlay_fs/etc/init.d/S35mount
@@ -0,0 +1,39 @@
+#!/bin/sh
+#
+# Mount SD persistents points
+#
+
+case "$1" in
+  start)
+        echo "Starting SD binds: "
+        [ -r /etc/default/dropbear ] && . /etc/default/dropbear
+        mount /dev/mmcblk0p1 /mnt &&
+        mkdir -p /mnt/dropbear && rm -fr /etc/dropbear &&  mkdir -p /etc/dropbear &&
+        mount --bind /mnt/dropbear /etc/dropbear
+        if [ ! -e /etc/dropbear/dropbear_rsa_host_key ]; then
+                dropbearkey -t rsa -f /var/rsa_key && mv /var/rsa_key /etc/dropbear/dropbear_rsa_host_key
+        fi
+        if [ ! -e /etc/dropbear/dropbear_dss_host_key ]; then
+                dropbearkey -t dss -f /var/dss_key && mv /var/dss_key /etc/dropbear/dropbear_dss_host_key
+        fi
+        test -f /mnt/network/interfaces &&
+        echo "Update network interfaces from SD" &&
+        cp /mnt/network/interfaces /etc/network/interfaces
+        [ $? = 0 ] && echo "OK" || echo "FAIL"
+        ;;
+  stop)
+        printf "Stopping SD binds: "
+        umount /etc/dropbear
+        umount /mnt
+        [ $? = 0 ] && echo "OK" || echo "FAIL"
+        ;;
+  restart|reload)
+        "$0" stop
+        "$0" start
+        ;;
+  *)
+        echo "Usage: $0 {start|stop|restart}"
+        exit 1
+esac
+
+exit $?
diff --git a/board/ciaa/acc/overlay_fs/etc/init.d/S50dropbear b/board/ciaa/acc/overlay_fs/etc/init.d/S50dropbear
new file mode 100644
index 0000000..bd92d46
--- /dev/null
+++ b/board/ciaa/acc/overlay_fs/etc/init.d/S50dropbear
@@ -0,0 +1,59 @@
+#!/bin/sh
+#
+# Starts dropbear sshd.
+#
+
+# Allow a few customizations from a config file
+test -r /etc/default/dropbear && . /etc/default/dropbear
+
+start() {
+	# If /etc/dropbear is a symlink to /var/run/dropbear, and
+	#   - the filesystem is RO (i.e. we can not rm the symlink),
+	#     create the directory pointed to by the symlink.
+	#   - the filesystem is RW (i.e. we can rm the symlink),
+	#     replace the symlink with an actual directory
+	if [ -L /etc/dropbear \
+	     -a "$(readlink /etc/dropbear)" = "/var/run/dropbear" ]
+	then
+		if rm -f /etc/dropbear >/dev/null 2>&1; then
+			mkdir -p /etc/dropbear
+		else
+			echo "No persistent location to store SSH host keys. New keys will be"
+			echo "generated at each boot. Are you sure this is what you want to do?"
+			mkdir -p "$(readlink /etc/dropbear)"
+		fi
+	fi
+
+	printf "Starting dropbear sshd: "
+	umask 077
+
+	start-stop-daemon -S -q -p /var/run/dropbear.pid \
+		--exec /usr/sbin/dropbear -- $DROPBEAR_ARGS
+	[ $? = 0 ] && echo "OK" || echo "FAIL"
+}
+stop() {
+	printf "Stopping dropbear sshd: "
+	start-stop-daemon -K -q -p /var/run/dropbear.pid
+	[ $? = 0 ] && echo "OK" || echo "FAIL"
+}
+restart() {
+	stop
+	start
+}
+
+case "$1" in
+  start)
+  	start
+	;;
+  stop)
+  	stop
+	;;
+  restart|reload)
+  	restart
+	;;
+  *)
+	echo "Usage: $0 {start|stop|restart}"
+	exit 1
+esac
+
+exit $?
diff --git a/board/ciaa/acc/overlay_fs/etc/network/interfaces b/board/ciaa/acc/overlay_fs/etc/network/interfaces
new file mode 100644
index 0000000..46cb724
--- /dev/null
+++ b/board/ciaa/acc/overlay_fs/etc/network/interfaces
@@ -0,0 +1,8 @@
+auto lo
+iface lo inet loopback
+
+auto eth0
+iface eth0 inet static
+	address 192.168.1.20
+	netmask 255.255.255.0
+	gateway 192.168.1.1
diff --git a/board/ciaa/acc/post-build.sh b/board/ciaa/acc/post-build.sh
new file mode 100644
index 0000000..3ba831c
--- /dev/null
+++ b/board/ciaa/acc/post-build.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+SD_DIR=${BINARIES_DIR}/sd
+test -d ${SD_DIR} || mkdir ${SD_DIR}
+
+cp ${BINARIES_DIR}/BOOT.BIN ${SD_DIR}/BOOT.BIN
+cp ${BINARIES_DIR}/u-boot.img ${SD_DIR}/u-boot.img
+cp ${BINARIES_DIR}/uImage ${SD_DIR}/uImage
+cp ${BINARIES_DIR}/zynq-ciaa_acc.dtb ${SD_DIR}/devicetree.dtb
+cp ${BINARIES_DIR}/rootfs.cpio.uboot ${SD_DIR}/uramdisk.image.gz
+cp ${BASE_DIR}/../board/ciaa/acc/uEnv.txt ${SD_DIR}/uEnv.txt
diff --git a/board/ciaa/acc/u-boot.dts b/board/ciaa/acc/u-boot.dts
new file mode 100644
index 0000000..176eb43
--- /dev/null
+++ b/board/ciaa/acc/u-boot.dts
@@ -0,0 +1,140 @@
+/*
+ * Device Tree Generator version: 1.1
+ *
+ *
+ * (C) Copyright 2007-2017 Xilinx, Inc.
+ * (C) Copyright      2017 Martin Ribelotta@emtech
+ * Martin Ribelotta <mribelotta@emtech.com.ar>
+ *
+ * CAUTION: This file is automatically generated by Xilinx.
+ * Version: Today is: Sat Nov 11 16:59:04 2017
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+	compatible = "xlnx,zynq-ciaa_acc", "xlnx,zynq-7000";
+	model = "Xilinx Zynq";
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &qspi;
+		spi1 = &spi1;
+		mmc0 = &sdhci0;
+	};
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+};
+
+&can0 {
+	status = "okay";
+};
+
+&gem0 {
+	enet-reset = <&gpio0 7 0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+	xlnx,ptp-enet-clock = <0x69f6bcb>;
+};
+
+&gpio0 {
+	emio-gpio-width = <2>;
+	gpio-mask-high = <0x0>;
+	gpio-mask-low = <0x5600>;
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&intc {
+	num_cpus = <2>;
+	num_interrupts = <96>;
+};
+
+&qspi {
+	is-dual = <0>;
+	num-cs = <1>;
+	status = "okay";
+        flash@0 {
+                compatible = "n25q128a11";
+                reg = <0x0>;
+                spi-tx-bus-width = <1>;
+                spi-rx-bus-width = <4>;
+                spi-max-frequency = <50000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@qspi-fsbl-uboot {
+                        label = "qspi-fsbl-uboot";
+                        reg = <0x0 0x100000>;
+                };
+                partition@qspi-linux {
+                        label = "qspi-linux";
+                        reg = <0x100000 0x500000>;
+                };
+                partition@qspi-device-tree {
+                        label = "qspi-device-tree";
+                        reg = <0x600000 0x40000>;
+                };
+                partition@qspi-rootfs {
+                        label = "qspi-rootfs";
+                        reg = <0x640000 0x500000>;
+                };
+                partition@qspi-bitstream {
+                        label = "qspi-bitstream";
+                        reg = <0xC00000 0x400000>;
+                };
+        };
+};
+
+&sdhci0 {
+        u-boot,dm-pre-reloc;
+        status = "okay";
+	xlnx,has-cd = <0x0>;
+	xlnx,has-power = <0x0>;
+	xlnx,has-wp = <0x0>;
+};
+
+&spi1 {
+	is-decoded-cs = <0>;
+	num-cs = <1>;
+	status = "okay";
+};
+
+&uart0 {
+	device_type = "serial";
+	port-number = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	device_type = "serial";
+	port-number = <1>;
+	status = "okay";
+};
+
+&usb0 {
+	phy_type = "ulpi";
+	status = "okay";
+	usb-reset = <&gpio0 0 0>;
+};
+
+&clkc {
+	fclk-enable = <0x1>;
+	ps-clk-frequency = <33333333>;
+};
diff --git a/board/ciaa/acc/u-boot.patch b/board/ciaa/acc/u-boot.patch
new file mode 100644
index 0000000..f3e28e3
--- /dev/null
+++ b/board/ciaa/acc/u-boot.patch
@@ -0,0 +1,14480 @@
+diff -Naur b/arch/arm/dts/Makefile a/arch/arm/dts/Makefile
+--- b/arch/arm/dts/Makefile	2017-09-26 09:56:19.000000000 -0300
++++ a/arch/arm/dts/Makefile	2017-11-22 17:17:11.677677090 -0300
+@@ -115,7 +115,8 @@
+ 	zynq-zc770-xm010.dtb \
+ 	zynq-zc770-xm011.dtb \
+ 	zynq-zc770-xm012.dtb \
+-	zynq-zc770-xm013.dtb
++	zynq-zc770-xm013.dtb \
++	zynq-ciaa_acc.dtb
+ dtb-$(CONFIG_ARCH_ZYNQMP) += \
+ 	zynqmp-ep108.dtb			\
+ 	zynqmp-zcu100-revC.dtb			\
+diff -Naur b/arch/arm/dts/zynq-ciaa_acc.dts a/arch/arm/dts/zynq-ciaa_acc.dts
+--- b/arch/arm/dts/zynq-ciaa_acc.dts	1969-12-31 21:00:00.000000000 -0300
++++ a/arch/arm/dts/zynq-ciaa_acc.dts	2017-11-23 11:52:31.871686577 -0300
+@@ -0,0 +1,140 @@
++/*
++ * Device Tree Generator version: 1.1
++ *
++ *
++ * (C) Copyright 2007-2017 Xilinx, Inc.
++ * (C) Copyright      2017 Martin Ribelotta@emtech
++ * Martin Ribelotta <mribelotta@emtech.com.ar>
++ *
++ * CAUTION: This file is automatically generated by Xilinx.
++ * Version: Today is: Sat Nov 11 16:59:04 2017
++ */
++
++/dts-v1/;
++/include/ "zynq-7000.dtsi"
++
++/ {
++	compatible = "xlnx,zynq-ciaa_acc", "xlnx,zynq-7000";
++	model = "Xilinx Zynq";
++
++	chosen {
++		bootargs = "earlycon";
++		stdout-path = "serial0:115200n8";
++	};
++	aliases {
++		ethernet0 = &gem0;
++		serial0 = &uart0;
++		serial1 = &uart1;
++		spi0 = &qspi;
++		spi1 = &spi1;
++		mmc0 = &sdhci0;
++	};
++        memory@0 {
++                device_type = "memory";
++                reg = <0x0 0x40000000>;
++        };
++};
++
++&can0 {
++	status = "okay";
++};
++
++&gem0 {
++	enet-reset = <&gpio0 7 0>;
++	phy-mode = "rgmii-id";
++	status = "okay";
++	xlnx,ptp-enet-clock = <0x69f6bcb>;
++};
++
++&gpio0 {
++	emio-gpio-width = <2>;
++	gpio-mask-high = <0x0>;
++	gpio-mask-low = <0x5600>;
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	status = "okay";
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	status = "okay";
++};
++
++&intc {
++	num_cpus = <2>;
++	num_interrupts = <96>;
++};
++
++&qspi {
++	is-dual = <0>;
++	num-cs = <1>;
++	status = "okay";
++        flash@0 {
++                compatible = "n25q128a11";
++                reg = <0x0>;
++                spi-tx-bus-width = <1>;
++                spi-rx-bus-width = <4>;
++                spi-max-frequency = <50000000>;
++                #address-cells = <1>;
++                #size-cells = <1>;
++                partition@qspi-fsbl-uboot {
++                        label = "qspi-fsbl-uboot";
++                        reg = <0x0 0x100000>;
++                };
++                partition@qspi-linux {
++                        label = "qspi-linux";
++                        reg = <0x100000 0x500000>;
++                };
++                partition@qspi-device-tree {
++                        label = "qspi-device-tree";
++                        reg = <0x600000 0x40000>;
++                };
++                partition@qspi-rootfs {
++                        label = "qspi-rootfs";
++                        reg = <0x640000 0x500000>;
++                };
++                partition@qspi-bitstream {
++                        label = "qspi-bitstream";
++                        reg = <0xC00000 0x400000>;
++                };
++        };
++};
++
++&sdhci0 {
++        u-boot,dm-pre-reloc;
++        status = "okay";
++	xlnx,has-cd = <0x0>;
++	xlnx,has-power = <0x0>;
++	xlnx,has-wp = <0x0>;
++};
++
++&spi1 {
++	is-decoded-cs = <0>;
++	num-cs = <1>;
++	status = "okay";
++};
++
++&uart0 {
++	device_type = "serial";
++	port-number = <0>;
++	status = "okay";
++};
++
++&uart1 {
++	device_type = "serial";
++	port-number = <1>;
++	status = "okay";
++};
++
++&usb0 {
++	phy_type = "ulpi";
++	status = "okay";
++	usb-reset = <&gpio0 0 0>;
++};
++
++&clkc {
++	fclk-enable = <0x1>;
++	ps-clk-frequency = <33333333>;
++};
+diff -Naur b/board/xilinx/zynq/zynq-ciaa_acc/ps7_init_gpl.c a/board/xilinx/zynq/zynq-ciaa_acc/ps7_init_gpl.c
+--- b/board/xilinx/zynq/zynq-ciaa_acc/ps7_init_gpl.c	1969-12-31 21:00:00.000000000 -0300
++++ a/board/xilinx/zynq/zynq-ciaa_acc/ps7_init_gpl.c	2017-11-17 15:51:06.000000000 -0300
+@@ -0,0 +1,13260 @@
++/******************************************************************************
++* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
++*
++*  This program is free software; you can redistribute it and/or modify
++*  it under the terms of the GNU General Public License as published by
++*  the Free Software Foundation; either version 2 of the License, or
++*  (at your option) any later version.
++*
++*  This program is distributed in the hope that it will be useful,
++*  but WITHOUT ANY WARRANTY; without even the implied warranty of
++*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++*  GNU General Public License for more details.
++* 
++*  You should have received a copy of the GNU General Public License along
++*  with this program; if not, see <http://www.gnu.org/licenses/>
++*
++*
++******************************************************************************/
++/****************************************************************************/
++/**
++*
++* @file ps7_init_gpl.c
++*
++* This file is automatically generated 
++*
++*****************************************************************************/
++
++#include "ps7_init_gpl.h"
++
++unsigned long ps7_pll_init_data_3_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: PLL SLCR REGISTERS
++    // .. .. START: ARM PLL INIT
++    // .. .. PLL_RES = 0x2
++    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0xfa
++    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x28
++    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. ARM_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. .. SRCSEL = 0x0
++    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. .. DIVISOR = 0x2
++    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
++    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
++    // .. .. .. CPU_6OR4XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
++    // .. .. .. CPU_3OR2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
++    // .. .. .. CPU_2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
++    // .. .. .. CPU_1XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
++    // .. .. .. CPU_PERI_CLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
++    // .. .. FINISH: ARM PLL INIT
++    // .. .. START: DDR PLL INIT
++    // .. .. PLL_RES = 0x2
++    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0x12c
++    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x20
++    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. DDR_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. .. DDR_3XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. DDR_2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
++    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
++    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
++    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
++    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
++    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
++    // .. .. FINISH: DDR PLL INIT
++    // .. .. START: IO PLL INIT
++    // .. .. PLL_RES = 0xc
++    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0x145
++    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x1e
++    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. IO_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. FINISH: IO PLL INIT
++    // .. FINISH: PLL SLCR REGISTERS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_clock_init_data_3_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: CLOCK CONTROL SLCR REGISTERS
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000128[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. DIVISOR0 = 0xf
++    // .. ==> 0XF8000128[13:8] = 0x0000000FU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
++    // .. DIVISOR1 = 0x7
++    // .. ==> 0XF8000128[25:20] = 0x00000007U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000138[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000138[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000140[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000140[6:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. DIVISOR = 0x8
++    // .. ==> 0XF8000140[13:8] = 0x00000008U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
++    // .. DIVISOR1 = 0x1
++    // .. ==> 0XF8000140[25:20] = 0x00000001U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF800014C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF800014C[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x7
++    // .. ==> 0XF800014C[13:8] = 0x00000007U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
++    // .. 
++    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000701U),
++    // .. CLKACT0 = 0x1
++    // .. ==> 0XF8000150[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. CLKACT1 = 0x0
++    // .. ==> 0XF8000150[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000150[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x14
++    // .. ==> 0XF8000150[13:8] = 0x00000014U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
++    // .. 
++    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
++    // .. CLKACT0 = 0x1
++    // .. ==> 0XF8000154[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. CLKACT1 = 0x1
++    // .. ==> 0XF8000154[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000154[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0xa
++    // .. ==> 0XF8000154[13:8] = 0x0000000AU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
++    // .. 
++    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
++    // .. CLKACT0 = 0x0
++    // .. ==> 0XF8000158[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. CLKACT1 = 0x1
++    // .. ==> 0XF8000158[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000158[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x6
++    // .. ==> 0XF8000158[13:8] = 0x00000006U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000600U
++    // .. 
++    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000602U),
++    // .. .. START: TRACE CLOCK
++    // .. .. FINISH: TRACE CLOCK
++    // .. .. CLKACT = 0x1
++    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR = 0x5
++    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR0 = 0x5
++    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. DIVISOR1 = 0x2
++    // .. .. ==> 0XF8000170[25:20] = 0x00000002U
++    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
++    // .. .. CLK_621_TRUE = 0x1
++    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
++    // .. .. DMA_CPU_2XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. USB0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. .. USB1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
++    // .. .. GEM0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
++    // .. .. GEM1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. .. SDI0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
++    // .. .. SDI1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. SPI0_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. SPI1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
++    // .. .. CAN0_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. CAN1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. I2C0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
++    // .. .. I2C1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. UART0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
++    // .. .. UART1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
++    // .. .. GPIO_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
++    // .. .. LQSPI_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
++    // .. .. SMC_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC844DU),
++    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
++    // .. START: THIS SHOULD BE BLANK
++    // .. FINISH: THIS SHOULD BE BLANK
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_ddr_init_data_3_0[] = {
++    // START: top
++    // .. START: DDR INITIALIZATION
++    // .. .. START: LOCK DDR
++    // .. .. reg_ddrc_soft_rstb = 0
++    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_powerdown_en = 0x0
++    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_data_bus_width = 0x0
++    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
++    // .. .. reg_ddrc_burst8_refresh = 0x0
++    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
++    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
++    // .. .. reg_ddrc_dis_rd_bypass = 0x0
++    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_act_bypass = 0x0
++    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_auto_refresh = 0x0
++    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
++    // .. .. FINISH: LOCK DDR
++    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x40
++    // .. .. ==> 0XF8006004[11:0] = 0x00000040U
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000040U
++    // .. .. reserved_reg_ddrc_active_ranks = 0x1
++    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
++    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
++    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001040U),
++    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
++    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
++    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
++    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
++    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
++    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
++    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
++    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
++    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
++    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
++    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
++    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
++    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
++    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
++    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
++    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
++    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
++    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
++    // .. .. reg_ddrc_w_xact_run_length = 0x8
++    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
++    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
++    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
++    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
++    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
++    // .. .. reg_ddrc_t_rc = 0x1b
++    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
++    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
++    // .. .. reg_ddrc_t_rfc_min = 0xa0
++    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
++    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
++    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
++    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
++    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU),
++    // .. .. reg_ddrc_wr2pre = 0x11
++    // .. .. ==> 0XF8006018[4:0] = 0x00000011U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000011U
++    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
++    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
++    // .. .. reg_ddrc_t_faw = 0x16
++    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
++    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
++    // .. .. reg_ddrc_t_ras_max = 0x12
++    // .. .. ==> 0XF8006018[21:16] = 0x00000012U
++    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00120000U
++    // .. .. reg_ddrc_t_ras_min = 0x13
++    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
++    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
++    // .. .. reg_ddrc_t_cke = 0x4
++    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44D258D1U),
++    // .. .. reg_ddrc_write_latency = 0x4
++    // .. .. ==> 0XF800601C[4:0] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000004U
++    // .. .. reg_ddrc_rd2wr = 0x9
++    // .. .. ==> 0XF800601C[9:5] = 0x00000009U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000120U
++    // .. .. reg_ddrc_wr2rd = 0xd
++    // .. .. ==> 0XF800601C[14:10] = 0x0000000DU
++    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003400U
++    // .. .. reg_ddrc_t_xp = 0x4
++    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
++    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
++    // .. .. reg_ddrc_pad_pd = 0x0
++    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rd2pre = 0x4
++    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
++    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
++    // .. .. reg_ddrc_t_rcd = 0x8
++    // .. .. ==> 0XF800601C[31:28] = 0x00000008U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x80000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x82023524U),
++    // .. .. reg_ddrc_t_ccd = 0x4
++    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
++    // .. .. reg_ddrc_t_rrd = 0x6
++    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
++    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
++    // .. .. reg_ddrc_refresh_margin = 0x2
++    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. reg_ddrc_t_rp = 0x8
++    // .. .. ==> 0XF8006020[15:12] = 0x00000008U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00008000U
++    // .. .. reg_ddrc_refresh_to_x32 = 0x8
++    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
++    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
++    // .. .. reg_ddrc_mobile = 0x0
++    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
++    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_read_latency = 0x8
++    // .. .. ==> 0XF8006020[28:24] = 0x00000008U
++    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x08000000U
++    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
++    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
++    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
++    // .. .. reg_ddrc_dis_pad_pd = 0x0
++    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
++    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x280882D0U),
++    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
++    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_prefer_write = 0x0
++    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_wr = 0x0
++    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_addr = 0x0
++    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_data = 0x0
++    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
++    // .. .. ddrc_reg_mr_wr_busy = 0x0
++    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_type = 0x0
++    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_rdata_valid = 0x0
++    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
++    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
++    // .. .. reg_ddrc_final_wait_x32 = 0x7
++    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
++    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
++    // .. .. reg_ddrc_t_mrd = 0x4
++    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
++    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
++    // .. .. reg_ddrc_emr2 = 0x0
++    // .. .. ==> 0XF800602C[15:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. reg_ddrc_emr3 = 0x0
++    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_ddrc_mr = 0x940
++    // .. .. ==> 0XF8006030[15:0] = 0x00000940U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000940U
++    // .. .. reg_ddrc_emr = 0x4
++    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
++    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040940U),
++    // .. .. reg_ddrc_burst_rdwr = 0x4
++    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
++    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
++    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
++    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
++    // .. .. reg_ddrc_post_cke_x1024 = 0x1
++    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
++    // .. .. reg_ddrc_burstchop = 0x0
++    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
++    // .. .. reg_ddrc_force_low_pri_n = 0x0
++    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_dq = 0x0
++    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
++    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
++    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
++    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
++    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
++    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
++    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
++    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
++    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
++    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
++    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
++    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
++    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
++    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
++    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
++    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
++    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
++    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
++    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
++    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
++    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
++    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
++    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
++    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
++    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
++    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
++    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
++    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
++    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
++    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
++    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
++    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
++    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
++    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
++    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
++    // .. .. reg_phy_rd_local_odt = 0x0
++    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_local_odt = 0x3
++    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
++    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
++    // .. .. reg_phy_idle_local_odt = 0x3
++    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
++    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
++    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
++    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
++    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
++    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
++    // .. .. reg_phy_rd_cmd_to_data = 0x0
++    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_phy_wr_cmd_to_data = 0x0
++    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
++    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
++    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
++    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_phy_use_fixed_re = 0x1
++    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
++    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
++    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_phy_clk_stall_level = 0x0
++    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
++    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
++    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
++    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
++    // .. .. reg_ddrc_dis_dll_calib = 0x0
++    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
++    // .. .. reg_ddrc_rd_odt_delay = 0x3
++    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
++    // .. .. reg_ddrc_wr_odt_delay = 0x0
++    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rd_odt_hold = 0x0
++    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
++    // .. .. reg_ddrc_wr_odt_hold = 0x5
++    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
++    // .. .. reg_ddrc_pageclose = 0x0
++    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_lpr_num_entries = 0x1f
++    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
++    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
++    // .. .. reg_ddrc_auto_pre_en = 0x0
++    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. .. reg_ddrc_refresh_update_level = 0x0
++    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_wc = 0x0
++    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
++    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_ddrc_selfref_en = 0x0
++    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
++    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
++    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
++    // .. .. reg_arb_go2critical_en = 0x1
++    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
++    // .. .. reg_ddrc_wrlvl_ww = 0x42
++    // .. .. ==> 0XF8006068[7:0] = 0x00000042U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000042U
++    // .. .. reg_ddrc_rdlvl_rr = 0x42
++    // .. .. ==> 0XF8006068[15:8] = 0x00000042U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004200U
++    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
++    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
++    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284242U),
++    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
++    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
++    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
++    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
++    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
++    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
++    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
++    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
++    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
++    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
++    // .. .. reg_ddrc_t_cksre = 0x6
++    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
++    // .. .. reg_ddrc_t_cksrx = 0x6
++    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
++    // .. .. reg_ddrc_t_ckesr = 0x4
++    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
++    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
++    // .. .. reg_ddrc_t_ckpde = 0x2
++    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
++    // .. .. reg_ddrc_t_ckpdx = 0x2
++    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
++    // .. .. reg_ddrc_t_ckdpde = 0x2
++    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. reg_ddrc_t_ckdpdx = 0x2
++    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
++    // .. .. reg_ddrc_t_ckcsx = 0x3
++    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
++    // .. .. reg_ddrc_dis_auto_zq = 0x0
++    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_ddr3 = 0x1
++    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. reg_ddrc_t_mod = 0x200
++    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
++    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
++    // .. .. reg_ddrc_t_zq_long_nop = 0x200
++    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
++    // .. .. reg_ddrc_t_zq_short_nop = 0x40
++    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
++    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
++    // .. .. t_zq_short_interval_x1024 = 0xcb73
++    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
++    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
++    // .. .. dram_rstn_x1024 = 0x69
++    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
++    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
++    // .. .. deeppowerdown_en = 0x0
++    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. deeppowerdown_to_x1024 = 0xff
++    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
++    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
++    // .. .. dfi_wrlvl_max_x1024 = 0xfff
++    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
++    // .. .. dfi_rdlvl_max_x1024 = 0xfff
++    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
++    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
++    // .. .. ddrc_reg_twrlvl_max_error = 0x0
++    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. .. ddrc_reg_trdlvl_max_error = 0x0
++    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
++    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
++    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
++    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
++    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
++    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
++    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
++    // .. .. reg_ddrc_skip_ocd = 0x1
++    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
++    // .. .. reg_ddrc_dfi_t_rddata_en = 0x7
++    // .. .. ==> 0XF80060B8[4:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
++    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
++    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
++    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
++    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
++    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200067U),
++    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
++    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
++    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
++    // .. .. CORR_ECC_LOG_VALID = 0x0
++    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
++    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
++    // .. .. UNCORR_ECC_LOG_VALID = 0x0
++    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
++    // .. .. STAT_NUM_CORR_ERR = 0x0
++    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
++    // .. .. STAT_NUM_UNCORR_ERR = 0x0
++    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
++    // .. .. reg_ddrc_ecc_mode = 0x0
++    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_scrub = 0x1
++    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
++    // .. .. reg_phy_dif_on = 0x0
++    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_phy_dif_off = 0x0
++    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x1f
++    // .. .. ==> 0XF800612C[9:0] = 0x0000001FU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001FU
++    // .. .. reg_phy_gatelvl_init_ratio = 0xa1
++    // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002841FU),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x24
++    // .. .. ==> 0XF8006130[9:0] = 0x00000024U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000024U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x98
++    // .. .. ==> 0XF8006130[19:10] = 0x00000098U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00026000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00026024U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x21
++    // .. .. ==> 0XF8006134[9:0] = 0x00000021U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x9d
++    // .. .. ==> 0XF8006134[19:10] = 0x0000009DU
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00027400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00027421U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x20
++    // .. .. ==> 0XF8006138[9:0] = 0x00000020U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000020U
++    // .. .. reg_phy_gatelvl_init_ratio = 0xa0
++    // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028020U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9f
++    // .. .. ==> 0XF8006154[9:0] = 0x0000009FU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009FU
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009FU),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa4
++    // .. .. ==> 0XF8006158[9:0] = 0x000000A4U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A4U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A4U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
++    // .. .. ==> 0XF800615C[9:0] = 0x000000A1U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x000000A1U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa0
++    // .. .. ==> 0XF8006160[9:0] = 0x000000A0U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A0U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A0U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
++    // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F6U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xed
++    // .. .. ==> 0XF800616C[10:0] = 0x000000EDU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000EDU
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000EDU),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf2
++    // .. .. ==> 0XF8006170[10:0] = 0x000000F2U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F2U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F2U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
++    // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F5U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xdf
++    // .. .. ==> 0XF800617C[9:0] = 0x000000DFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DFU
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DFU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe4
++    // .. .. ==> 0XF8006180[9:0] = 0x000000E4U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E4U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E4U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
++    // .. .. ==> 0XF8006184[9:0] = 0x000000E1U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000E1U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe0
++    // .. .. ==> 0XF8006188[9:0] = 0x000000E0U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E0U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E0U),
++    // .. .. reg_phy_bl2 = 0x0
++    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_at_spd_atpg = 0x0
++    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_enable = 0x0
++    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_force_err = 0x0
++    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_mode = 0x0
++    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. .. reg_phy_invert_clkout = 0x1
++    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. .. reg_phy_sel_logic = 0x0
++    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_ratio = 0x100
++    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
++    // .. .. reg_phy_ctrl_slave_force = 0x0
++    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_delay = 0x0
++    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
++    // .. .. reg_phy_lpddr = 0x0
++    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
++    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
++    // .. .. reg_phy_cmd_latency = 0x0
++    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
++    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
++    // .. .. reg_phy_wr_rl_delay = 0x1
++    // .. .. ==> 0XF8006194[4:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000001U
++    // .. .. reg_phy_rd_rl_delay = 0x5
++    // .. .. ==> 0XF8006194[9:5] = 0x00000005U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000A0U
++    // .. .. reg_phy_dll_lock_diff = 0xf
++    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
++    // .. .. reg_phy_use_wr_level = 0x1
++    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
++    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
++    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
++    // .. .. reg_phy_use_rd_data_eye_level = 0x1
++    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. .. reg_phy_dis_calib_rst = 0x0
++    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_delay = 0x0
++    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FCA1U),
++    // .. .. reg_arb_page_addr_mask = 0x0
++    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_ddrc_lpddr2 = 0x0
++    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_derate_enable = 0x0
++    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr4_margin = 0x0
++    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
++    // .. .. reg_ddrc_mr4_read_interval = 0x0
++    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
++    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
++    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
++    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
++    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
++    // .. .. reg_ddrc_t_mrw = 0x5
++    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
++    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
++    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
++    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
++    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
++    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
++    // .. .. START: POLL ON DCI STATUS
++    // .. .. DONE = 1
++    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
++    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
++    // .. .. 
++    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
++    // .. .. FINISH: POLL ON DCI STATUS
++    // .. .. START: UNLOCK DDR
++    // .. .. reg_ddrc_soft_rstb = 0x1
++    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_ddrc_powerdown_en = 0x0
++    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_data_bus_width = 0x0
++    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
++    // .. .. reg_ddrc_burst8_refresh = 0x0
++    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rdwr_idle_gap = 1
++    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
++    // .. .. reg_ddrc_dis_rd_bypass = 0x0
++    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_act_bypass = 0x0
++    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_auto_refresh = 0x0
++    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
++    // .. .. FINISH: UNLOCK DDR
++    // .. .. START: CHECK DDR STATUS
++    // .. .. ddrc_reg_operating_mode = 1
++    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
++    // .. .. 
++    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
++    // .. .. FINISH: CHECK DDR STATUS
++    // .. FINISH: DDR INITIALIZATION
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_mio_init_data_3_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: OCM REMAPPING
++    // .. FINISH: OCM REMAPPING
++    // .. START: DDRIOB SETTINGS
++    // .. reserved_INP_POWER = 0x0
++    // .. ==> 0XF8000B40[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B40[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE_B = 0x0
++    // .. ==> 0XF8000B40[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B40[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCI_TYPE = 0x0
++    // .. ==> 0XF8000B40[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B40[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B40[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B40[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B40[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
++    // .. reserved_INP_POWER = 0x0
++    // .. ==> 0XF8000B44[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B44[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE_B = 0x0
++    // .. ==> 0XF8000B44[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B44[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCI_TYPE = 0x0
++    // .. ==> 0XF8000B44[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B44[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B44[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B44[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B44[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
++    // .. reserved_INP_POWER = 0x0
++    // .. ==> 0XF8000B48[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x1
++    // .. ==> 0XF8000B48[2:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
++    // .. DCI_UPDATE_B = 0x0
++    // .. ==> 0XF8000B48[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B48[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCI_TYPE = 0x3
++    // .. ==> 0XF8000B48[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B48[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B48[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B48[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B48[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
++    // .. reserved_INP_POWER = 0x0
++    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x1
++    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
++    // .. DCI_UPDATE_B = 0x0
++    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCI_TYPE = 0x3
++    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
++    // .. reserved_INP_POWER = 0x0
++    // .. ==> 0XF8000B50[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x2
++    // .. ==> 0XF8000B50[2:1] = 0x00000002U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
++    // .. DCI_UPDATE_B = 0x0
++    // .. ==> 0XF8000B50[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B50[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCI_TYPE = 0x3
++    // .. ==> 0XF8000B50[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B50[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B50[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B50[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B50[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
++    // .. reserved_INP_POWER = 0x0
++    // .. ==> 0XF8000B54[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x2
++    // .. ==> 0XF8000B54[2:1] = 0x00000002U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
++    // .. DCI_UPDATE_B = 0x0
++    // .. ==> 0XF8000B54[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B54[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCI_TYPE = 0x3
++    // .. ==> 0XF8000B54[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B54[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B54[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B54[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B54[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
++    // .. reserved_INP_POWER = 0x0
++    // .. ==> 0XF8000B58[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B58[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE_B = 0x0
++    // .. ==> 0XF8000B58[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B58[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCI_TYPE = 0x0
++    // .. ==> 0XF8000B58[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B58[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B58[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B58[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B58[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
++    // .. reserved_DRIVE_P = 0x1c
++    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. reserved_DRIVE_N = 0xc
++    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. reserved_SLEW_P = 0x3
++    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
++    // .. reserved_SLEW_N = 0x3
++    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
++    // .. reserved_GTL = 0x0
++    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. reserved_RTERM = 0x0
++    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
++    // .. reserved_DRIVE_P = 0x1c
++    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. reserved_DRIVE_N = 0xc
++    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. reserved_SLEW_P = 0x6
++    // .. ==> 0XF8000B60[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. reserved_SLEW_N = 0x1f
++    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. reserved_GTL = 0x0
++    // .. ==> 0XF8000B60[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. reserved_RTERM = 0x0
++    // .. ==> 0XF8000B60[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. reserved_DRIVE_P = 0x1c
++    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. reserved_DRIVE_N = 0xc
++    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. reserved_SLEW_P = 0x6
++    // .. ==> 0XF8000B64[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. reserved_SLEW_N = 0x1f
++    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. reserved_GTL = 0x0
++    // .. ==> 0XF8000B64[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. reserved_RTERM = 0x0
++    // .. ==> 0XF8000B64[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. reserved_DRIVE_P = 0x1c
++    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. reserved_DRIVE_N = 0xc
++    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. reserved_SLEW_P = 0x6
++    // .. ==> 0XF8000B68[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. reserved_SLEW_N = 0x1f
++    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. reserved_GTL = 0x0
++    // .. ==> 0XF8000B68[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. reserved_RTERM = 0x0
++    // .. ==> 0XF8000B68[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. VREF_INT_EN = 0x0
++    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. VREF_SEL = 0x0
++    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
++    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
++    // .. VREF_EXT_EN = 0x3
++    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. reserved_VREF_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
++    // .. REFIO_EN = 0x1
++    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
++    // .. reserved_REFIO_TEST = 0x0
++    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
++    // .. reserved_REFIO_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. reserved_DRST_B_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. reserved_CKE_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
++    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
++    // .. .. START: ASSERT RESET
++    // .. .. RESET = 1
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
++    // .. .. FINISH: ASSERT RESET
++    // .. .. START: DEASSERT RESET
++    // .. .. RESET = 0
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reserved_VRN_OUT = 0x1
++    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
++    // .. .. FINISH: DEASSERT RESET
++    // .. .. RESET = 0x1
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. ENABLE = 0x1
++    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. reserved_VRP_TRI = 0x0
++    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reserved_VRN_TRI = 0x0
++    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reserved_VRP_OUT = 0x0
++    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reserved_VRN_OUT = 0x1
++    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
++    // .. .. NREF_OPT1 = 0x0
++    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. .. NREF_OPT2 = 0x0
++    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
++    // .. .. NREF_OPT4 = 0x1
++    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
++    // .. .. PREF_OPT1 = 0x0
++    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
++    // .. .. PREF_OPT2 = 0x0
++    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
++    // .. .. UPDATE_CONTROL = 0x0
++    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. .. reserved_INIT_COMPLETE = 0x0
++    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
++    // .. .. reserved_TST_CLK = 0x0
++    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. .. reserved_TST_HLN = 0x0
++    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. .. reserved_TST_HLP = 0x0
++    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. .. reserved_TST_RST = 0x0
++    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. reserved_INT_DCI_EN = 0x0
++    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
++    // .. FINISH: DDRIOB SETTINGS
++    // .. START: MIO PROGRAMMING
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000700[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000700[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000700[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000700[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000700[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000700[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000700[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000700[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000700[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000704[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000704[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000704[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000704[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000704[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000704[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000704[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000704[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000704[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000708[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000708[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000708[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000708[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000708[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000708[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000708[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000708[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000708[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800070C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800070C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800070C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800070C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800070C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800070C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800070C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800070C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800070C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000710[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000710[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000710[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000710[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000710[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000710[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000710[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000710[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000710[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000714[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000714[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000714[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000714[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000714[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000714[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000714[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000714[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000714[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000718[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000718[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000718[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000718[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000718[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000718[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000718[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000718[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000718[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800071C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800071C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800071C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800071C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800071C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800071C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800071C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800071C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800071C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000720[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000720[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000720[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000720[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000720[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000720[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000720[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000720[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000720[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000724[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000724[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000724[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000724[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000724[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000724[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000724[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000724[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000724[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000728[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000728[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000728[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000728[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000728[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000728[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000728[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000728[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000728[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000006E1U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800072C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800072C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800072C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800072C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF800072C[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF800072C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800072C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800072C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800072C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000006E0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000730[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000730[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000730[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000730[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000730[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000730[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000730[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000730[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000730[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000734[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000734[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000734[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000734[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000734[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000734[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000734[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000734[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000734[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000738[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000738[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000738[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000738[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000738[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000738[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000738[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000738[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000738[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800073C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800073C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800073C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800073C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF800073C[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF800073C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800073C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF800073C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800073C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000740[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000740[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000740[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000740[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000740[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000740[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000740[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000740[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000740[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000744[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000744[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000744[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000744[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000744[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000744[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000744[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000744[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000744[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000748[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000748[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000748[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000748[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000748[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000748[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000748[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000748[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000748[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800074C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800074C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800074C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800074C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800074C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800074C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800074C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800074C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800074C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000750[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000750[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000750[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000750[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000750[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000750[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000750[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000750[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000750[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000754[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000754[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000754[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000754[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000754[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000754[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000754[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000754[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000754[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000758[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000758[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000758[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000758[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000758[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000758[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000758[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000758[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000758[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800075C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800075C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800075C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800075C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800075C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800075C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800075C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800075C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800075C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000760[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000760[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000760[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000760[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000760[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000760[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000760[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000760[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000760[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000764[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000764[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000764[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000764[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000764[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000764[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000764[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000764[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000764[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000768[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000768[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000768[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000768[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000768[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000768[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000768[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000768[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000768[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800076C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800076C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800076C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800076C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800076C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800076C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800076C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800076C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800076C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000770[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000770[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000770[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000770[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000770[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000770[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000770[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000770[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000770[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000774[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000774[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000774[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000774[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000774[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000774[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000774[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000774[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000774[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000778[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000778[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000778[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000778[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000778[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000778[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000778[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000778[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000778[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800077C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800077C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800077C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800077C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800077C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800077C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800077C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800077C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800077C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000780[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000780[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000780[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000780[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000780[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000780[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000780[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000780[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000780[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000784[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000784[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000784[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000784[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000784[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000784[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000784[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000784[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000784[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000788[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000788[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000788[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000788[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000788[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000788[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000788[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000788[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000788[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800078C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800078C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800078C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800078C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800078C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800078C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800078C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800078C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800078C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000790[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000790[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000790[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000790[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000790[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000790[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000790[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000790[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000790[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000794[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000794[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000794[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000794[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000794[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000794[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000794[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000794[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000794[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000798[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000798[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000798[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000798[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000798[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000798[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000798[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000798[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000798[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800079C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800079C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800079C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800079C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800079C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800079C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800079C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800079C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800079C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A0[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A0[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A4[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A4[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A8[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A8[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A8[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007AC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007AC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007AC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007AC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007AC[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007AC[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007AC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007AC[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007AC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007B0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007B0[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007B0[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007B4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007B4[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007B4[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007B8[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007B8[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007B8[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007BC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007BC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007BC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007BC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007BC[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007BC[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007BC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007BC[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007BC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007C0[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007C0[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C0[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007C4[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007C4[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C4[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007C8[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF80007C8[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C8[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007CC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007CC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007CC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007CC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007CC[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF80007CC[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007CC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007CC[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007CC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007D0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007D0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007D0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007D0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007D0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 0
++    // .. ==> 0XF80007D0[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007D0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007D0[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007D0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007D4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007D4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007D4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007D4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007D4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 0
++    // .. ==> 0XF80007D4[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007D4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007D4[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007D4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
++    // .. SDIO0_WP_SEL = 55
++    // .. ==> 0XF8000830[5:0] = 0x00000037U
++    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
++    // .. SDIO0_CD_SEL = 56
++    // .. ==> 0XF8000830[21:16] = 0x00000038U
++    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
++    // .. FINISH: MIO PROGRAMMING
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_peripherals_init_data_3_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B48[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B48[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B50[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B50[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B54[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B54[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
++    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // .. START: SRAM/NOR SET OPMODE
++    // .. FINISH: SRAM/NOR SET OPMODE
++    // .. START: UART REGISTERS
++    // .. BDIV = 0x6
++    // .. ==> 0XE0001034[7:0] = 0x00000006U
++    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
++    // .. 
++    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
++    // .. CD = 0x7c
++    // .. ==> 0XE0001018[15:0] = 0x0000007CU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
++    // .. 
++    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
++    // .. STPBRK = 0x0
++    // .. ==> 0XE0001000[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. STTBRK = 0x0
++    // .. ==> 0XE0001000[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. RSTTO = 0x0
++    // .. ==> 0XE0001000[6:6] = 0x00000000U
++    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. TXDIS = 0x0
++    // .. ==> 0XE0001000[5:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. TXEN = 0x1
++    // .. ==> 0XE0001000[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. RXDIS = 0x0
++    // .. ==> 0XE0001000[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. RXEN = 0x1
++    // .. ==> 0XE0001000[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. TXRES = 0x1
++    // .. ==> 0XE0001000[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. RXRES = 0x1
++    // .. ==> 0XE0001000[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. 
++    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
++    // .. CHMODE = 0x0
++    // .. ==> 0XE0001004[9:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
++    // .. NBSTOP = 0x0
++    // .. ==> 0XE0001004[7:6] = 0x00000000U
++    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. PAR = 0x4
++    // .. ==> 0XE0001004[5:3] = 0x00000004U
++    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
++    // .. CHRL = 0x0
++    // .. ==> 0XE0001004[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. CLKS = 0x0
++    // .. ==> 0XE0001004[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
++    // .. BDIV = 0x6
++    // .. ==> 0XE0000034[7:0] = 0x00000006U
++    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
++    // .. 
++    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
++    // .. CD = 0x7c
++    // .. ==> 0XE0000018[15:0] = 0x0000007CU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
++    // .. 
++    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
++    // .. STPBRK = 0x0
++    // .. ==> 0XE0000000[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. STTBRK = 0x0
++    // .. ==> 0XE0000000[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. RSTTO = 0x0
++    // .. ==> 0XE0000000[6:6] = 0x00000000U
++    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. TXDIS = 0x0
++    // .. ==> 0XE0000000[5:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. TXEN = 0x1
++    // .. ==> 0XE0000000[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. RXDIS = 0x0
++    // .. ==> 0XE0000000[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. RXEN = 0x1
++    // .. ==> 0XE0000000[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. TXRES = 0x1
++    // .. ==> 0XE0000000[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. RXRES = 0x1
++    // .. ==> 0XE0000000[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. 
++    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
++    // .. CHMODE = 0x0
++    // .. ==> 0XE0000004[9:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
++    // .. NBSTOP = 0x0
++    // .. ==> 0XE0000004[7:6] = 0x00000000U
++    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. PAR = 0x4
++    // .. ==> 0XE0000004[5:3] = 0x00000004U
++    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
++    // .. CHRL = 0x0
++    // .. ==> 0XE0000004[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. CLKS = 0x0
++    // .. ==> 0XE0000004[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
++    // .. FINISH: UART REGISTERS
++    // .. START: QSPI REGISTERS
++    // .. Holdb_dr = 1
++    // .. ==> 0XE000D000[19:19] = 0x00000001U
++    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. 
++    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
++    // .. FINISH: QSPI REGISTERS
++    // .. START: PL POWER ON RESET REGISTERS
++    // .. PCFG_POR_CNT_4K = 0
++    // .. ==> 0XF8007000[29:29] = 0x00000000U
++    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
++    // .. FINISH: PL POWER ON RESET REGISTERS
++    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
++    // .. .. START: NAND SET CYCLE
++    // .. .. FINISH: NAND SET CYCLE
++    // .. .. START: OPMODE
++    // .. .. FINISH: OPMODE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: SRAM/NOR CS0 SET CYCLE
++    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: NOR CS0 BASE ADDRESS
++    // .. .. FINISH: NOR CS0 BASE ADDRESS
++    // .. .. START: SRAM/NOR CS1 SET CYCLE
++    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: NOR CS1 BASE ADDRESS
++    // .. .. FINISH: NOR CS1 BASE ADDRESS
++    // .. .. START: USB RESET
++    // .. .. .. START: USB0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x81
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x1
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000001U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000001U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0001U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. OP_ENABLE_0 = 0x81
++    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x0
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0000U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x1
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000001U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000001U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0001U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB0 RESET
++    // .. .. .. START: USB1 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB1 RESET
++    // .. .. FINISH: USB RESET
++    // .. .. START: ENET RESET
++    // .. .. .. START: ENET0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x81
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. OP_ENABLE_0 = 0x81
++    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x0
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET0 RESET
++    // .. .. .. START: ENET1 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET1 RESET
++    // .. .. FINISH: ENET RESET
++    // .. .. START: I2C RESET
++    // .. .. .. START: I2C0 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C0 RESET
++    // .. .. .. START: I2C1 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C1 RESET
++    // .. .. FINISH: I2C RESET
++    // .. .. START: NOR CHIP SELECT
++    // .. .. .. START: DIR MODE BANK 0
++    // .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. FINISH: NOR CHIP SELECT
++    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_post_config_3_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: ENABLING LEVEL SHIFTER
++    // .. USER_LVL_INP_EN_0 = 1
++    // .. ==> 0XF8000900[3:3] = 0x00000001U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
++    // .. USER_LVL_OUT_EN_0 = 1
++    // .. ==> 0XF8000900[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. USER_LVL_INP_EN_1 = 1
++    // .. ==> 0XF8000900[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. USER_LVL_OUT_EN_1 = 1
++    // .. ==> 0XF8000900[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. 
++    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
++    // .. FINISH: ENABLING LEVEL SHIFTER
++    // .. START: FPGA RESETS TO 0
++    // .. reserved_3 = 0
++    // .. ==> 0XF8000240[31:25] = 0x00000000U
++    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
++    // .. reserved_FPGA_ACP_RST = 0
++    // .. ==> 0XF8000240[24:24] = 0x00000000U
++    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. reserved_FPGA_AXDS3_RST = 0
++    // .. ==> 0XF8000240[23:23] = 0x00000000U
++    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. reserved_FPGA_AXDS2_RST = 0
++    // .. ==> 0XF8000240[22:22] = 0x00000000U
++    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. reserved_FPGA_AXDS1_RST = 0
++    // .. ==> 0XF8000240[21:21] = 0x00000000U
++    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
++    // .. reserved_FPGA_AXDS0_RST = 0
++    // .. ==> 0XF8000240[20:20] = 0x00000000U
++    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. reserved_2 = 0
++    // .. ==> 0XF8000240[19:18] = 0x00000000U
++    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
++    // .. reserved_FSSW1_FPGA_RST = 0
++    // .. ==> 0XF8000240[17:17] = 0x00000000U
++    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. reserved_FSSW0_FPGA_RST = 0
++    // .. ==> 0XF8000240[16:16] = 0x00000000U
++    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. reserved_1 = 0
++    // .. ==> 0XF8000240[15:14] = 0x00000000U
++    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
++    // .. reserved_FPGA_FMSW1_RST = 0
++    // .. ==> 0XF8000240[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. reserved_FPGA_FMSW0_RST = 0
++    // .. ==> 0XF8000240[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. reserved_FPGA_DMA3_RST = 0
++    // .. ==> 0XF8000240[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. reserved_FPGA_DMA2_RST = 0
++    // .. ==> 0XF8000240[10:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. reserved_FPGA_DMA1_RST = 0
++    // .. ==> 0XF8000240[9:9] = 0x00000000U
++    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. reserved_FPGA_DMA0_RST = 0
++    // .. ==> 0XF8000240[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. reserved = 0
++    // .. ==> 0XF8000240[7:4] = 0x00000000U
++    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. FPGA3_OUT_RST = 0
++    // .. ==> 0XF8000240[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. FPGA2_OUT_RST = 0
++    // .. ==> 0XF8000240[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. FPGA1_OUT_RST = 0
++    // .. ==> 0XF8000240[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. FPGA0_OUT_RST = 0
++    // .. ==> 0XF8000240[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
++    // .. FINISH: FPGA RESETS TO 0
++    // .. START: AFI REGISTERS
++    // .. .. START: AFI0 REGISTERS
++    // .. .. FINISH: AFI0 REGISTERS
++    // .. .. START: AFI1 REGISTERS
++    // .. .. FINISH: AFI1 REGISTERS
++    // .. .. START: AFI2 REGISTERS
++    // .. .. FINISH: AFI2 REGISTERS
++    // .. .. START: AFI3 REGISTERS
++    // .. .. FINISH: AFI3 REGISTERS
++    // .. .. START: AFI2 SECURE REGISTER
++    // .. .. FINISH: AFI2 SECURE REGISTER
++    // .. FINISH: AFI REGISTERS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_debug_3_0[] = {
++    // START: top
++    // .. START: CROSS TRIGGER CONFIGURATIONS
++    // .. .. START: UNLOCKING CTI REGISTERS
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
++    // .. .. FINISH: UNLOCKING CTI REGISTERS
++    // .. .. START: ENABLING CTI MODULES AND CHANNELS
++    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
++    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
++    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
++    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_pll_init_data_2_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: PLL SLCR REGISTERS
++    // .. .. START: ARM PLL INIT
++    // .. .. PLL_RES = 0x2
++    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0xfa
++    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x28
++    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. ARM_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. .. SRCSEL = 0x0
++    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. .. DIVISOR = 0x2
++    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
++    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
++    // .. .. .. CPU_6OR4XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
++    // .. .. .. CPU_3OR2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
++    // .. .. .. CPU_2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
++    // .. .. .. CPU_1XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
++    // .. .. .. CPU_PERI_CLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
++    // .. .. FINISH: ARM PLL INIT
++    // .. .. START: DDR PLL INIT
++    // .. .. PLL_RES = 0x2
++    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0x12c
++    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x20
++    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. DDR_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. .. DDR_3XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. DDR_2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
++    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
++    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
++    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
++    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
++    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
++    // .. .. FINISH: DDR PLL INIT
++    // .. .. START: IO PLL INIT
++    // .. .. PLL_RES = 0xc
++    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0x145
++    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x1e
++    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. IO_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. FINISH: IO PLL INIT
++    // .. FINISH: PLL SLCR REGISTERS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_clock_init_data_2_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: CLOCK CONTROL SLCR REGISTERS
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000128[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. DIVISOR0 = 0xf
++    // .. ==> 0XF8000128[13:8] = 0x0000000FU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
++    // .. DIVISOR1 = 0x7
++    // .. ==> 0XF8000128[25:20] = 0x00000007U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000138[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000138[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000140[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000140[6:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. DIVISOR = 0x8
++    // .. ==> 0XF8000140[13:8] = 0x00000008U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
++    // .. DIVISOR1 = 0x1
++    // .. ==> 0XF8000140[25:20] = 0x00000001U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF800014C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF800014C[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x7
++    // .. ==> 0XF800014C[13:8] = 0x00000007U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
++    // .. 
++    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000701U),
++    // .. CLKACT0 = 0x1
++    // .. ==> 0XF8000150[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. CLKACT1 = 0x0
++    // .. ==> 0XF8000150[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000150[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x14
++    // .. ==> 0XF8000150[13:8] = 0x00000014U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
++    // .. 
++    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
++    // .. CLKACT0 = 0x1
++    // .. ==> 0XF8000154[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. CLKACT1 = 0x1
++    // .. ==> 0XF8000154[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000154[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0xa
++    // .. ==> 0XF8000154[13:8] = 0x0000000AU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
++    // .. 
++    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
++    // .. CLKACT0 = 0x0
++    // .. ==> 0XF8000158[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. CLKACT1 = 0x1
++    // .. ==> 0XF8000158[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000158[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x6
++    // .. ==> 0XF8000158[13:8] = 0x00000006U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000600U
++    // .. 
++    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000602U),
++    // .. .. START: TRACE CLOCK
++    // .. .. FINISH: TRACE CLOCK
++    // .. .. CLKACT = 0x1
++    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR = 0x5
++    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR0 = 0x5
++    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. DIVISOR1 = 0x2
++    // .. .. ==> 0XF8000170[25:20] = 0x00000002U
++    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
++    // .. .. CLK_621_TRUE = 0x1
++    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
++    // .. .. DMA_CPU_2XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. USB0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. .. USB1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
++    // .. .. GEM0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
++    // .. .. GEM1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. .. SDI0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
++    // .. .. SDI1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. SPI0_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. SPI1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
++    // .. .. CAN0_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. CAN1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. I2C0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
++    // .. .. I2C1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. UART0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
++    // .. .. UART1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
++    // .. .. GPIO_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
++    // .. .. LQSPI_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
++    // .. .. SMC_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC844DU),
++    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
++    // .. START: THIS SHOULD BE BLANK
++    // .. FINISH: THIS SHOULD BE BLANK
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_ddr_init_data_2_0[] = {
++    // START: top
++    // .. START: DDR INITIALIZATION
++    // .. .. START: LOCK DDR
++    // .. .. reg_ddrc_soft_rstb = 0
++    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_powerdown_en = 0x0
++    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_data_bus_width = 0x0
++    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
++    // .. .. reg_ddrc_burst8_refresh = 0x0
++    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
++    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
++    // .. .. reg_ddrc_dis_rd_bypass = 0x0
++    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_act_bypass = 0x0
++    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_auto_refresh = 0x0
++    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
++    // .. .. FINISH: LOCK DDR
++    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x40
++    // .. .. ==> 0XF8006004[11:0] = 0x00000040U
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000040U
++    // .. .. reg_ddrc_active_ranks = 0x1
++    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
++    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
++    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_wr_odt_block = 0x1
++    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
++    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
++    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
++    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
++    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_open_bank = 0x0
++    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
++    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
++    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081040U),
++    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
++    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
++    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
++    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
++    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
++    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
++    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
++    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
++    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
++    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
++    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
++    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
++    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
++    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
++    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
++    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
++    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
++    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
++    // .. .. reg_ddrc_w_xact_run_length = 0x8
++    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
++    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
++    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
++    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
++    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
++    // .. .. reg_ddrc_t_rc = 0x1b
++    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
++    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
++    // .. .. reg_ddrc_t_rfc_min = 0xa0
++    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
++    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
++    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
++    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
++    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU),
++    // .. .. reg_ddrc_wr2pre = 0x11
++    // .. .. ==> 0XF8006018[4:0] = 0x00000011U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000011U
++    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
++    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
++    // .. .. reg_ddrc_t_faw = 0x16
++    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
++    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
++    // .. .. reg_ddrc_t_ras_max = 0x12
++    // .. .. ==> 0XF8006018[21:16] = 0x00000012U
++    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00120000U
++    // .. .. reg_ddrc_t_ras_min = 0x13
++    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
++    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
++    // .. .. reg_ddrc_t_cke = 0x4
++    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44D258D1U),
++    // .. .. reg_ddrc_write_latency = 0x4
++    // .. .. ==> 0XF800601C[4:0] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000004U
++    // .. .. reg_ddrc_rd2wr = 0x9
++    // .. .. ==> 0XF800601C[9:5] = 0x00000009U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000120U
++    // .. .. reg_ddrc_wr2rd = 0xd
++    // .. .. ==> 0XF800601C[14:10] = 0x0000000DU
++    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003400U
++    // .. .. reg_ddrc_t_xp = 0x4
++    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
++    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
++    // .. .. reg_ddrc_pad_pd = 0x0
++    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rd2pre = 0x4
++    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
++    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
++    // .. .. reg_ddrc_t_rcd = 0x8
++    // .. .. ==> 0XF800601C[31:28] = 0x00000008U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x80000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x82023524U),
++    // .. .. reg_ddrc_t_ccd = 0x4
++    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
++    // .. .. reg_ddrc_t_rrd = 0x6
++    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
++    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
++    // .. .. reg_ddrc_refresh_margin = 0x2
++    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. reg_ddrc_t_rp = 0x8
++    // .. .. ==> 0XF8006020[15:12] = 0x00000008U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00008000U
++    // .. .. reg_ddrc_refresh_to_x32 = 0x8
++    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
++    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
++    // .. .. reg_ddrc_sdram = 0x1
++    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
++    // .. .. reg_ddrc_mobile = 0x0
++    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_clock_stop_en = 0x0
++    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_read_latency = 0x8
++    // .. .. ==> 0XF8006020[28:24] = 0x00000008U
++    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x08000000U
++    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
++    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
++    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
++    // .. .. reg_ddrc_dis_pad_pd = 0x0
++    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
++    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_loopback = 0x0
++    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
++    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x282882D0U),
++    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
++    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_prefer_write = 0x0
++    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_max_rank_rd = 0xf
++    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
++    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
++    // .. .. reg_ddrc_mr_wr = 0x0
++    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_addr = 0x0
++    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_data = 0x0
++    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
++    // .. .. ddrc_reg_mr_wr_busy = 0x0
++    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_type = 0x0
++    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_rdata_valid = 0x0
++    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
++    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
++    // .. .. reg_ddrc_final_wait_x32 = 0x7
++    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
++    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
++    // .. .. reg_ddrc_t_mrd = 0x4
++    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
++    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
++    // .. .. reg_ddrc_emr2 = 0x0
++    // .. .. ==> 0XF800602C[15:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. reg_ddrc_emr3 = 0x0
++    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_ddrc_mr = 0x940
++    // .. .. ==> 0XF8006030[15:0] = 0x00000940U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000940U
++    // .. .. reg_ddrc_emr = 0x4
++    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
++    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040940U),
++    // .. .. reg_ddrc_burst_rdwr = 0x4
++    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
++    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
++    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
++    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
++    // .. .. reg_ddrc_post_cke_x1024 = 0x1
++    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
++    // .. .. reg_ddrc_burstchop = 0x0
++    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
++    // .. .. reg_ddrc_force_low_pri_n = 0x0
++    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_dq = 0x0
++    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_debug_mode = 0x0
++    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_level_start = 0x0
++    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_level_start = 0x0
++    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. .. reg_phy_dq0_wait_t = 0x0
++    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
++    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
++    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
++    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
++    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
++    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
++    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
++    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
++    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
++    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
++    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
++    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
++    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
++    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
++    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
++    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
++    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
++    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
++    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
++    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
++    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
++    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
++    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
++    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
++    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
++    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
++    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
++    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
++    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
++    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
++    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
++    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
++    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
++    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
++    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
++    // .. .. reg_ddrc_rank0_rd_odt = 0x0
++    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rank0_wr_odt = 0x1
++    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
++    // .. .. reg_ddrc_rank1_rd_odt = 0x1
++    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
++    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
++    // .. .. reg_ddrc_rank1_wr_odt = 0x1
++    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. .. reg_phy_rd_local_odt = 0x0
++    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_local_odt = 0x3
++    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
++    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
++    // .. .. reg_phy_idle_local_odt = 0x3
++    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
++    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
++    // .. .. reg_ddrc_rank2_rd_odt = 0x0
++    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rank2_wr_odt = 0x0
++    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rank3_rd_odt = 0x0
++    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
++    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rank3_wr_odt = 0x0
++    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
++    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
++    // .. .. reg_phy_rd_cmd_to_data = 0x0
++    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_phy_wr_cmd_to_data = 0x0
++    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
++    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
++    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
++    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_phy_use_fixed_re = 0x1
++    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
++    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
++    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_phy_clk_stall_level = 0x0
++    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
++    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
++    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
++    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
++    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
++    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
++    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
++    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
++    // .. .. reg_ddrc_dis_dll_calib = 0x0
++    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
++    // .. .. reg_ddrc_rd_odt_delay = 0x3
++    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
++    // .. .. reg_ddrc_wr_odt_delay = 0x0
++    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rd_odt_hold = 0x0
++    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
++    // .. .. reg_ddrc_wr_odt_hold = 0x5
++    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
++    // .. .. reg_ddrc_pageclose = 0x0
++    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_lpr_num_entries = 0x1f
++    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
++    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
++    // .. .. reg_ddrc_auto_pre_en = 0x0
++    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. .. reg_ddrc_refresh_update_level = 0x0
++    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_wc = 0x0
++    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
++    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_ddrc_selfref_en = 0x0
++    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
++    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
++    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
++    // .. .. reg_arb_go2critical_en = 0x1
++    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
++    // .. .. reg_ddrc_wrlvl_ww = 0x42
++    // .. .. ==> 0XF8006068[7:0] = 0x00000042U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000042U
++    // .. .. reg_ddrc_rdlvl_rr = 0x42
++    // .. .. ==> 0XF8006068[15:8] = 0x00000042U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004200U
++    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
++    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
++    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284242U),
++    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
++    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
++    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
++    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
++    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
++    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
++    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
++    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
++    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
++    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
++    // .. .. reg_ddrc_t_cksre = 0x6
++    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
++    // .. .. reg_ddrc_t_cksrx = 0x6
++    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
++    // .. .. reg_ddrc_t_ckesr = 0x4
++    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
++    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
++    // .. .. reg_ddrc_t_ckpde = 0x2
++    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
++    // .. .. reg_ddrc_t_ckpdx = 0x2
++    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
++    // .. .. reg_ddrc_t_ckdpde = 0x2
++    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. reg_ddrc_t_ckdpdx = 0x2
++    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
++    // .. .. reg_ddrc_t_ckcsx = 0x3
++    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
++    // .. .. refresh_timer0_start_value_x32 = 0x0
++    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
++    // .. .. refresh_timer1_start_value_x32 = 0x8
++    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
++    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
++    // .. .. reg_ddrc_dis_auto_zq = 0x0
++    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_ddr3 = 0x1
++    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. reg_ddrc_t_mod = 0x200
++    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
++    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
++    // .. .. reg_ddrc_t_zq_long_nop = 0x200
++    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
++    // .. .. reg_ddrc_t_zq_short_nop = 0x40
++    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
++    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
++    // .. .. t_zq_short_interval_x1024 = 0xcb73
++    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
++    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
++    // .. .. dram_rstn_x1024 = 0x69
++    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
++    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
++    // .. .. deeppowerdown_en = 0x0
++    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. deeppowerdown_to_x1024 = 0xff
++    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
++    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
++    // .. .. dfi_wrlvl_max_x1024 = 0xfff
++    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
++    // .. .. dfi_rdlvl_max_x1024 = 0xfff
++    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
++    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
++    // .. .. ddrc_reg_twrlvl_max_error = 0x0
++    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. .. ddrc_reg_trdlvl_max_error = 0x0
++    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
++    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
++    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
++    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
++    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
++    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
++    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
++    // .. .. reg_ddrc_2t_delay = 0x0
++    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
++    // .. .. reg_ddrc_skip_ocd = 0x1
++    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
++    // .. .. reg_ddrc_dis_pre_bypass = 0x0
++    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
++    // .. .. reg_ddrc_dfi_t_rddata_en = 0x7
++    // .. .. ==> 0XF80060B8[4:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
++    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
++    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
++    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
++    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
++    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200067U),
++    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
++    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
++    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
++    // .. .. CORR_ECC_LOG_VALID = 0x0
++    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
++    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
++    // .. .. UNCORR_ECC_LOG_VALID = 0x0
++    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
++    // .. .. STAT_NUM_CORR_ERR = 0x0
++    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
++    // .. .. STAT_NUM_UNCORR_ERR = 0x0
++    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
++    // .. .. reg_ddrc_ecc_mode = 0x0
++    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_scrub = 0x1
++    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
++    // .. .. reg_phy_dif_on = 0x0
++    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_phy_dif_off = 0x0
++    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x1f
++    // .. .. ==> 0XF800612C[9:0] = 0x0000001FU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001FU
++    // .. .. reg_phy_gatelvl_init_ratio = 0xa1
++    // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002841FU),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x24
++    // .. .. ==> 0XF8006130[9:0] = 0x00000024U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000024U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x98
++    // .. .. ==> 0XF8006130[19:10] = 0x00000098U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00026000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00026024U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x21
++    // .. .. ==> 0XF8006134[9:0] = 0x00000021U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x9d
++    // .. .. ==> 0XF8006134[19:10] = 0x0000009DU
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00027400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00027421U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x20
++    // .. .. ==> 0XF8006138[9:0] = 0x00000020U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000020U
++    // .. .. reg_phy_gatelvl_init_ratio = 0xa0
++    // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028020U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9f
++    // .. .. ==> 0XF8006154[9:0] = 0x0000009FU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009FU
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009FU),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa4
++    // .. .. ==> 0XF8006158[9:0] = 0x000000A4U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A4U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A4U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
++    // .. .. ==> 0XF800615C[9:0] = 0x000000A1U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x000000A1U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa0
++    // .. .. ==> 0XF8006160[9:0] = 0x000000A0U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A0U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A0U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
++    // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F6U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xed
++    // .. .. ==> 0XF800616C[10:0] = 0x000000EDU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000EDU
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000EDU),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf2
++    // .. .. ==> 0XF8006170[10:0] = 0x000000F2U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F2U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F2U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
++    // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F5U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xdf
++    // .. .. ==> 0XF800617C[9:0] = 0x000000DFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DFU
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DFU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe4
++    // .. .. ==> 0XF8006180[9:0] = 0x000000E4U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E4U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E4U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
++    // .. .. ==> 0XF8006184[9:0] = 0x000000E1U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000E1U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe0
++    // .. .. ==> 0XF8006188[9:0] = 0x000000E0U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E0U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E0U),
++    // .. .. reg_phy_loopback = 0x0
++    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_phy_bl2 = 0x0
++    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_at_spd_atpg = 0x0
++    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_enable = 0x0
++    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_force_err = 0x0
++    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_mode = 0x0
++    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. .. reg_phy_invert_clkout = 0x1
++    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
++    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. .. reg_phy_sel_logic = 0x0
++    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_ratio = 0x100
++    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
++    // .. .. reg_phy_ctrl_slave_force = 0x0
++    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_delay = 0x0
++    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
++    // .. .. reg_phy_use_rank0_delays = 0x1
++    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
++    // .. .. reg_phy_lpddr = 0x0
++    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
++    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
++    // .. .. reg_phy_cmd_latency = 0x0
++    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
++    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
++    // .. .. reg_phy_int_lpbk = 0x0
++    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
++    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
++    // .. .. reg_phy_wr_rl_delay = 0x1
++    // .. .. ==> 0XF8006194[4:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000001U
++    // .. .. reg_phy_rd_rl_delay = 0x5
++    // .. .. ==> 0XF8006194[9:5] = 0x00000005U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000A0U
++    // .. .. reg_phy_dll_lock_diff = 0xf
++    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
++    // .. .. reg_phy_use_wr_level = 0x1
++    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
++    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
++    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
++    // .. .. reg_phy_use_rd_data_eye_level = 0x1
++    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. .. reg_phy_dis_calib_rst = 0x0
++    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_delay = 0x0
++    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FCA1U),
++    // .. .. reg_arb_page_addr_mask = 0x0
++    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_rmw_portn = 0x1
++    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_rmw_portn = 0x1
++    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_rmw_portn = 0x1
++    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_rmw_portn = 0x1
++    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_ddrc_lpddr2 = 0x0
++    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_per_bank_refresh = 0x0
++    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_derate_enable = 0x0
++    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr4_margin = 0x0
++    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
++    // .. .. reg_ddrc_mr4_read_interval = 0x0
++    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
++    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
++    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
++    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
++    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
++    // .. .. reg_ddrc_t_mrw = 0x5
++    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
++    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
++    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
++    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
++    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
++    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
++    // .. .. START: POLL ON DCI STATUS
++    // .. .. DONE = 1
++    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
++    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
++    // .. .. 
++    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
++    // .. .. FINISH: POLL ON DCI STATUS
++    // .. .. START: UNLOCK DDR
++    // .. .. reg_ddrc_soft_rstb = 0x1
++    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_ddrc_powerdown_en = 0x0
++    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_data_bus_width = 0x0
++    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
++    // .. .. reg_ddrc_burst8_refresh = 0x0
++    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rdwr_idle_gap = 1
++    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
++    // .. .. reg_ddrc_dis_rd_bypass = 0x0
++    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_act_bypass = 0x0
++    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_auto_refresh = 0x0
++    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
++    // .. .. FINISH: UNLOCK DDR
++    // .. .. START: CHECK DDR STATUS
++    // .. .. ddrc_reg_operating_mode = 1
++    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
++    // .. .. 
++    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
++    // .. .. FINISH: CHECK DDR STATUS
++    // .. FINISH: DDR INITIALIZATION
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_mio_init_data_2_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: OCM REMAPPING
++    // .. FINISH: OCM REMAPPING
++    // .. START: DDRIOB SETTINGS
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B40[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B40[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B40[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B40[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCR_TYPE = 0x0
++    // .. ==> 0XF8000B40[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B40[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B40[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B40[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B40[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B44[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B44[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B44[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B44[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCR_TYPE = 0x0
++    // .. ==> 0XF8000B44[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B44[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B44[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B44[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B44[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B48[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x1
++    // .. ==> 0XF8000B48[2:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B48[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B48[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCR_TYPE = 0x3
++    // .. ==> 0XF8000B48[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B48[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B48[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B48[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B48[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x1
++    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCR_TYPE = 0x3
++    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B50[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x2
++    // .. ==> 0XF8000B50[2:1] = 0x00000002U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B50[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B50[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCR_TYPE = 0x3
++    // .. ==> 0XF8000B50[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B50[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B50[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B50[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B50[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B54[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x2
++    // .. ==> 0XF8000B54[2:1] = 0x00000002U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B54[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B54[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCR_TYPE = 0x3
++    // .. ==> 0XF8000B54[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B54[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B54[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B54[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B54[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B58[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B58[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B58[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B58[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCR_TYPE = 0x0
++    // .. ==> 0XF8000B58[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B58[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B58[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B58[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B58[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
++    // .. DRIVE_P = 0x1c
++    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. DRIVE_N = 0xc
++    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. SLEW_P = 0x3
++    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
++    // .. SLEW_N = 0x3
++    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
++    // .. GTL = 0x0
++    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. RTERM = 0x0
++    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
++    // .. DRIVE_P = 0x1c
++    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. DRIVE_N = 0xc
++    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. SLEW_P = 0x6
++    // .. ==> 0XF8000B60[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. SLEW_N = 0x1f
++    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. GTL = 0x0
++    // .. ==> 0XF8000B60[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. RTERM = 0x0
++    // .. ==> 0XF8000B60[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. DRIVE_P = 0x1c
++    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. DRIVE_N = 0xc
++    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. SLEW_P = 0x6
++    // .. ==> 0XF8000B64[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. SLEW_N = 0x1f
++    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. GTL = 0x0
++    // .. ==> 0XF8000B64[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. RTERM = 0x0
++    // .. ==> 0XF8000B64[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. DRIVE_P = 0x1c
++    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. DRIVE_N = 0xc
++    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. SLEW_P = 0x6
++    // .. ==> 0XF8000B68[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. SLEW_N = 0x1f
++    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. GTL = 0x0
++    // .. ==> 0XF8000B68[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. RTERM = 0x0
++    // .. ==> 0XF8000B68[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. VREF_INT_EN = 0x0
++    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. VREF_SEL = 0x0
++    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
++    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
++    // .. VREF_EXT_EN = 0x3
++    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. VREF_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
++    // .. REFIO_EN = 0x1
++    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
++    // .. REFIO_TEST = 0x0
++    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
++    // .. REFIO_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DRST_B_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. CKE_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
++    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U),
++    // .. .. START: ASSERT RESET
++    // .. .. RESET = 1
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. VRN_OUT = 0x1
++    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
++    // .. .. FINISH: ASSERT RESET
++    // .. .. START: DEASSERT RESET
++    // .. .. RESET = 0
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. VRN_OUT = 0x1
++    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
++    // .. .. FINISH: DEASSERT RESET
++    // .. .. RESET = 0x1
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. ENABLE = 0x1
++    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. VRP_TRI = 0x0
++    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. VRN_TRI = 0x0
++    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. VRP_OUT = 0x0
++    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. VRN_OUT = 0x1
++    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
++    // .. .. NREF_OPT1 = 0x0
++    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. .. NREF_OPT2 = 0x0
++    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
++    // .. .. NREF_OPT4 = 0x1
++    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
++    // .. .. PREF_OPT1 = 0x0
++    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
++    // .. .. PREF_OPT2 = 0x0
++    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
++    // .. .. UPDATE_CONTROL = 0x0
++    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. .. INIT_COMPLETE = 0x0
++    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
++    // .. .. TST_CLK = 0x0
++    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. .. TST_HLN = 0x0
++    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. .. TST_HLP = 0x0
++    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. .. TST_RST = 0x0
++    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. INT_DCI_EN = 0x0
++    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
++    // .. FINISH: DDRIOB SETTINGS
++    // .. START: MIO PROGRAMMING
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000700[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000700[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000700[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000700[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000700[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000700[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000700[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000700[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000700[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000704[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000704[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000704[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000704[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000704[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000704[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000704[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000704[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000704[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000708[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000708[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000708[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000708[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000708[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000708[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000708[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000708[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000708[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800070C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800070C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800070C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800070C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800070C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800070C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800070C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800070C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800070C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000710[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000710[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000710[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000710[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000710[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000710[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000710[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000710[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000710[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000714[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000714[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000714[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000714[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000714[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000714[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000714[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000714[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000714[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000718[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000718[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000718[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000718[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000718[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000718[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000718[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000718[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000718[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800071C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800071C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800071C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800071C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800071C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800071C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800071C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800071C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800071C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000720[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000720[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000720[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000720[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000720[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000720[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000720[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000720[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000720[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000724[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000724[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000724[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000724[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000724[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000724[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000724[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000724[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000724[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000728[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000728[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000728[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000728[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000728[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000728[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000728[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000728[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000728[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000006E1U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800072C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800072C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800072C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800072C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF800072C[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF800072C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800072C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800072C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800072C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000006E0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000730[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000730[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000730[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000730[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000730[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000730[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000730[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000730[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000730[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000734[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000734[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000734[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000734[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000734[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000734[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000734[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000734[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000734[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000738[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000738[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000738[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000738[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000738[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000738[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000738[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000738[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000738[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800073C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800073C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800073C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800073C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF800073C[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF800073C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800073C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF800073C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800073C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000740[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000740[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000740[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000740[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000740[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000740[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000740[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000740[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000740[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000744[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000744[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000744[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000744[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000744[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000744[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000744[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000744[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000744[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000748[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000748[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000748[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000748[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000748[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000748[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000748[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000748[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000748[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800074C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800074C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800074C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800074C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800074C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800074C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800074C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800074C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800074C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000750[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000750[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000750[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000750[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000750[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000750[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000750[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000750[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000750[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000754[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000754[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000754[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000754[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000754[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000754[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000754[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000754[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000754[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000758[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000758[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000758[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000758[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000758[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000758[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000758[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000758[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000758[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800075C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800075C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800075C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800075C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800075C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800075C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800075C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800075C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800075C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000760[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000760[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000760[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000760[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000760[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000760[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000760[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000760[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000760[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000764[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000764[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000764[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000764[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000764[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000764[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000764[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000764[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000764[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000768[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000768[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000768[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000768[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000768[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000768[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000768[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000768[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000768[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800076C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800076C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800076C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800076C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800076C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800076C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800076C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800076C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800076C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000770[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000770[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000770[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000770[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000770[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000770[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000770[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000770[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000770[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000774[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000774[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000774[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000774[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000774[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000774[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000774[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000774[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000774[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000778[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000778[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000778[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000778[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000778[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000778[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000778[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000778[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000778[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800077C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800077C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800077C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800077C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800077C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800077C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800077C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800077C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800077C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000780[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000780[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000780[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000780[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000780[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000780[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000780[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000780[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000780[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000784[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000784[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000784[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000784[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000784[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000784[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000784[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000784[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000784[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000788[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000788[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000788[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000788[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000788[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000788[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000788[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000788[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000788[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800078C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800078C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800078C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800078C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800078C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800078C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800078C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800078C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800078C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000790[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000790[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000790[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000790[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000790[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000790[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000790[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000790[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000790[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000794[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000794[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000794[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000794[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000794[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000794[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000794[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000794[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000794[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000798[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000798[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000798[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000798[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000798[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000798[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000798[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000798[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000798[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800079C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800079C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800079C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800079C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800079C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800079C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800079C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800079C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800079C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A0[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A0[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A4[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A4[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A8[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A8[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A8[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007AC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007AC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007AC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007AC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007AC[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007AC[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007AC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007AC[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007AC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007B0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007B0[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007B0[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007B4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007B4[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007B4[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007B8[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007B8[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007B8[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007BC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007BC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007BC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007BC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007BC[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007BC[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007BC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007BC[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007BC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007C0[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007C0[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C0[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007C4[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007C4[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C4[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007C8[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF80007C8[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C8[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007CC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007CC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007CC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007CC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007CC[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF80007CC[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007CC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007CC[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007CC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007D0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007D0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007D0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007D0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007D0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 0
++    // .. ==> 0XF80007D0[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007D0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007D0[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007D0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007D4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007D4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007D4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007D4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007D4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 0
++    // .. ==> 0XF80007D4[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007D4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007D4[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007D4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
++    // .. SDIO0_WP_SEL = 55
++    // .. ==> 0XF8000830[5:0] = 0x00000037U
++    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
++    // .. SDIO0_CD_SEL = 56
++    // .. ==> 0XF8000830[21:16] = 0x00000038U
++    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
++    // .. FINISH: MIO PROGRAMMING
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_peripherals_init_data_2_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B48[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B48[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B50[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B50[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B54[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B54[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
++    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // .. START: SRAM/NOR SET OPMODE
++    // .. FINISH: SRAM/NOR SET OPMODE
++    // .. START: UART REGISTERS
++    // .. BDIV = 0x6
++    // .. ==> 0XE0001034[7:0] = 0x00000006U
++    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
++    // .. 
++    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
++    // .. CD = 0x7c
++    // .. ==> 0XE0001018[15:0] = 0x0000007CU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
++    // .. 
++    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
++    // .. STPBRK = 0x0
++    // .. ==> 0XE0001000[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. STTBRK = 0x0
++    // .. ==> 0XE0001000[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. RSTTO = 0x0
++    // .. ==> 0XE0001000[6:6] = 0x00000000U
++    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. TXDIS = 0x0
++    // .. ==> 0XE0001000[5:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. TXEN = 0x1
++    // .. ==> 0XE0001000[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. RXDIS = 0x0
++    // .. ==> 0XE0001000[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. RXEN = 0x1
++    // .. ==> 0XE0001000[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. TXRES = 0x1
++    // .. ==> 0XE0001000[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. RXRES = 0x1
++    // .. ==> 0XE0001000[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. 
++    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
++    // .. IRMODE = 0x0
++    // .. ==> 0XE0001004[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. UCLKEN = 0x0
++    // .. ==> 0XE0001004[10:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. CHMODE = 0x0
++    // .. ==> 0XE0001004[9:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
++    // .. NBSTOP = 0x0
++    // .. ==> 0XE0001004[7:6] = 0x00000000U
++    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. PAR = 0x4
++    // .. ==> 0XE0001004[5:3] = 0x00000004U
++    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
++    // .. CHRL = 0x0
++    // .. ==> 0XE0001004[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. CLKS = 0x0
++    // .. ==> 0XE0001004[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
++    // .. BDIV = 0x6
++    // .. ==> 0XE0000034[7:0] = 0x00000006U
++    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
++    // .. 
++    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
++    // .. CD = 0x7c
++    // .. ==> 0XE0000018[15:0] = 0x0000007CU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
++    // .. 
++    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
++    // .. STPBRK = 0x0
++    // .. ==> 0XE0000000[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. STTBRK = 0x0
++    // .. ==> 0XE0000000[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. RSTTO = 0x0
++    // .. ==> 0XE0000000[6:6] = 0x00000000U
++    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. TXDIS = 0x0
++    // .. ==> 0XE0000000[5:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. TXEN = 0x1
++    // .. ==> 0XE0000000[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. RXDIS = 0x0
++    // .. ==> 0XE0000000[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. RXEN = 0x1
++    // .. ==> 0XE0000000[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. TXRES = 0x1
++    // .. ==> 0XE0000000[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. RXRES = 0x1
++    // .. ==> 0XE0000000[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. 
++    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
++    // .. IRMODE = 0x0
++    // .. ==> 0XE0000004[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. UCLKEN = 0x0
++    // .. ==> 0XE0000004[10:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. CHMODE = 0x0
++    // .. ==> 0XE0000004[9:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
++    // .. NBSTOP = 0x0
++    // .. ==> 0XE0000004[7:6] = 0x00000000U
++    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. PAR = 0x4
++    // .. ==> 0XE0000004[5:3] = 0x00000004U
++    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
++    // .. CHRL = 0x0
++    // .. ==> 0XE0000004[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. CLKS = 0x0
++    // .. ==> 0XE0000004[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
++    // .. FINISH: UART REGISTERS
++    // .. START: QSPI REGISTERS
++    // .. Holdb_dr = 1
++    // .. ==> 0XE000D000[19:19] = 0x00000001U
++    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. 
++    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
++    // .. FINISH: QSPI REGISTERS
++    // .. START: PL POWER ON RESET REGISTERS
++    // .. PCFG_POR_CNT_4K = 0
++    // .. ==> 0XF8007000[29:29] = 0x00000000U
++    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
++    // .. FINISH: PL POWER ON RESET REGISTERS
++    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
++    // .. .. START: NAND SET CYCLE
++    // .. .. FINISH: NAND SET CYCLE
++    // .. .. START: OPMODE
++    // .. .. FINISH: OPMODE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: SRAM/NOR CS0 SET CYCLE
++    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: NOR CS0 BASE ADDRESS
++    // .. .. FINISH: NOR CS0 BASE ADDRESS
++    // .. .. START: SRAM/NOR CS1 SET CYCLE
++    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: NOR CS1 BASE ADDRESS
++    // .. .. FINISH: NOR CS1 BASE ADDRESS
++    // .. .. START: USB RESET
++    // .. .. .. START: USB0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x81
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x1
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000001U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000001U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0001U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. OP_ENABLE_0 = 0x81
++    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x0
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0000U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x1
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000001U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000001U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0001U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB0 RESET
++    // .. .. .. START: USB1 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB1 RESET
++    // .. .. FINISH: USB RESET
++    // .. .. START: ENET RESET
++    // .. .. .. START: ENET0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x81
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. OP_ENABLE_0 = 0x81
++    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x0
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET0 RESET
++    // .. .. .. START: ENET1 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET1 RESET
++    // .. .. FINISH: ENET RESET
++    // .. .. START: I2C RESET
++    // .. .. .. START: I2C0 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C0 RESET
++    // .. .. .. START: I2C1 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C1 RESET
++    // .. .. FINISH: I2C RESET
++    // .. .. START: NOR CHIP SELECT
++    // .. .. .. START: DIR MODE BANK 0
++    // .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. FINISH: NOR CHIP SELECT
++    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_post_config_2_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: ENABLING LEVEL SHIFTER
++    // .. USER_INP_ICT_EN_0 = 3
++    // .. ==> 0XF8000900[1:0] = 0x00000003U
++    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
++    // .. USER_INP_ICT_EN_1 = 3
++    // .. ==> 0XF8000900[3:2] = 0x00000003U
++    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
++    // .. 
++    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
++    // .. FINISH: ENABLING LEVEL SHIFTER
++    // .. START: FPGA RESETS TO 0
++    // .. reserved_3 = 0
++    // .. ==> 0XF8000240[31:25] = 0x00000000U
++    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
++    // .. FPGA_ACP_RST = 0
++    // .. ==> 0XF8000240[24:24] = 0x00000000U
++    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. FPGA_AXDS3_RST = 0
++    // .. ==> 0XF8000240[23:23] = 0x00000000U
++    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. FPGA_AXDS2_RST = 0
++    // .. ==> 0XF8000240[22:22] = 0x00000000U
++    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. FPGA_AXDS1_RST = 0
++    // .. ==> 0XF8000240[21:21] = 0x00000000U
++    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
++    // .. FPGA_AXDS0_RST = 0
++    // .. ==> 0XF8000240[20:20] = 0x00000000U
++    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. reserved_2 = 0
++    // .. ==> 0XF8000240[19:18] = 0x00000000U
++    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
++    // .. FSSW1_FPGA_RST = 0
++    // .. ==> 0XF8000240[17:17] = 0x00000000U
++    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. FSSW0_FPGA_RST = 0
++    // .. ==> 0XF8000240[16:16] = 0x00000000U
++    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. reserved_1 = 0
++    // .. ==> 0XF8000240[15:14] = 0x00000000U
++    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
++    // .. FPGA_FMSW1_RST = 0
++    // .. ==> 0XF8000240[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. FPGA_FMSW0_RST = 0
++    // .. ==> 0XF8000240[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. FPGA_DMA3_RST = 0
++    // .. ==> 0XF8000240[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. FPGA_DMA2_RST = 0
++    // .. ==> 0XF8000240[10:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. FPGA_DMA1_RST = 0
++    // .. ==> 0XF8000240[9:9] = 0x00000000U
++    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. FPGA_DMA0_RST = 0
++    // .. ==> 0XF8000240[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. reserved = 0
++    // .. ==> 0XF8000240[7:4] = 0x00000000U
++    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. FPGA3_OUT_RST = 0
++    // .. ==> 0XF8000240[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. FPGA2_OUT_RST = 0
++    // .. ==> 0XF8000240[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. FPGA1_OUT_RST = 0
++    // .. ==> 0XF8000240[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. FPGA0_OUT_RST = 0
++    // .. ==> 0XF8000240[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
++    // .. FINISH: FPGA RESETS TO 0
++    // .. START: AFI REGISTERS
++    // .. .. START: AFI0 REGISTERS
++    // .. .. FINISH: AFI0 REGISTERS
++    // .. .. START: AFI1 REGISTERS
++    // .. .. FINISH: AFI1 REGISTERS
++    // .. .. START: AFI2 REGISTERS
++    // .. .. FINISH: AFI2 REGISTERS
++    // .. .. START: AFI3 REGISTERS
++    // .. .. FINISH: AFI3 REGISTERS
++    // .. FINISH: AFI REGISTERS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_debug_2_0[] = {
++    // START: top
++    // .. START: CROSS TRIGGER CONFIGURATIONS
++    // .. .. START: UNLOCKING CTI REGISTERS
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
++    // .. .. FINISH: UNLOCKING CTI REGISTERS
++    // .. .. START: ENABLING CTI MODULES AND CHANNELS
++    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
++    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
++    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
++    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_pll_init_data_1_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: PLL SLCR REGISTERS
++    // .. .. START: ARM PLL INIT
++    // .. .. PLL_RES = 0x2
++    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0xfa
++    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x28
++    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. ARM_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. .. SRCSEL = 0x0
++    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. .. DIVISOR = 0x2
++    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
++    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
++    // .. .. .. CPU_6OR4XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
++    // .. .. .. CPU_3OR2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
++    // .. .. .. CPU_2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
++    // .. .. .. CPU_1XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
++    // .. .. .. CPU_PERI_CLKACT = 0x1
++    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
++    // .. .. FINISH: ARM PLL INIT
++    // .. .. START: DDR PLL INIT
++    // .. .. PLL_RES = 0x2
++    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0x12c
++    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x20
++    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. DDR_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. .. DDR_3XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. DDR_2XCLKACT = 0x1
++    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
++    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
++    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
++    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
++    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
++    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
++    // .. .. FINISH: DDR PLL INIT
++    // .. .. START: IO PLL INIT
++    // .. .. PLL_RES = 0xc
++    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
++    // .. .. PLL_CP = 0x2
++    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. LOCK_CNT = 0x145
++    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
++    // .. .. .. START: UPDATE FB_DIV
++    // .. .. .. PLL_FDIV = 0x1e
++    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
++    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
++    // .. .. .. FINISH: UPDATE FB_DIV
++    // .. .. .. START: BY PASS PLL
++    // .. .. .. PLL_BYPASS_FORCE = 1
++    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
++    // .. .. .. FINISH: BY PASS PLL
++    // .. .. .. START: ASSERT RESET
++    // .. .. .. PLL_RESET = 1
++    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
++    // .. .. .. FINISH: ASSERT RESET
++    // .. .. .. START: DEASSERT RESET
++    // .. .. .. PLL_RESET = 0
++    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
++    // .. .. .. FINISH: DEASSERT RESET
++    // .. .. .. START: CHECK PLL STATUS
++    // .. .. .. IO_PLL_LOCK = 1
++    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
++    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. .. .. 
++    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
++    // .. .. .. FINISH: CHECK PLL STATUS
++    // .. .. .. START: REMOVE PLL BY PASS
++    // .. .. .. PLL_BYPASS_FORCE = 0
++    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
++    // .. .. .. FINISH: REMOVE PLL BY PASS
++    // .. .. FINISH: IO PLL INIT
++    // .. FINISH: PLL SLCR REGISTERS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_clock_init_data_1_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: CLOCK CONTROL SLCR REGISTERS
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000128[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. DIVISOR0 = 0xf
++    // .. ==> 0XF8000128[13:8] = 0x0000000FU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
++    // .. DIVISOR1 = 0x7
++    // .. ==> 0XF8000128[25:20] = 0x00000007U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000138[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000138[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF8000140[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000140[6:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. DIVISOR = 0x8
++    // .. ==> 0XF8000140[13:8] = 0x00000008U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
++    // .. DIVISOR1 = 0x1
++    // .. ==> 0XF8000140[25:20] = 0x00000001U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
++    // .. CLKACT = 0x1
++    // .. ==> 0XF800014C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF800014C[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x7
++    // .. ==> 0XF800014C[13:8] = 0x00000007U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
++    // .. 
++    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000701U),
++    // .. CLKACT0 = 0x1
++    // .. ==> 0XF8000150[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. CLKACT1 = 0x0
++    // .. ==> 0XF8000150[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000150[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x14
++    // .. ==> 0XF8000150[13:8] = 0x00000014U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
++    // .. 
++    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
++    // .. CLKACT0 = 0x1
++    // .. ==> 0XF8000154[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. CLKACT1 = 0x1
++    // .. ==> 0XF8000154[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000154[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0xa
++    // .. ==> 0XF8000154[13:8] = 0x0000000AU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
++    // .. 
++    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U),
++    // .. CLKACT0 = 0x0
++    // .. ==> 0XF8000158[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. CLKACT1 = 0x1
++    // .. ==> 0XF8000158[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. SRCSEL = 0x0
++    // .. ==> 0XF8000158[5:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. DIVISOR = 0x6
++    // .. ==> 0XF8000158[13:8] = 0x00000006U
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000600U
++    // .. 
++    EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000602U),
++    // .. .. START: TRACE CLOCK
++    // .. .. FINISH: TRACE CLOCK
++    // .. .. CLKACT = 0x1
++    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR = 0x5
++    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR0 = 0x5
++    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. DIVISOR1 = 0x2
++    // .. .. ==> 0XF8000170[25:20] = 0x00000002U
++    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
++    // .. .. CLK_621_TRUE = 0x1
++    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
++    // .. .. DMA_CPU_2XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. USB0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. .. USB1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
++    // .. .. GEM0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
++    // .. .. GEM1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. .. SDI0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[10:10] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
++    // .. .. SDI1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. SPI0_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. SPI1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[15:15] = 0x00000001U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
++    // .. .. CAN0_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. CAN1_CPU_1XCLKACT = 0x0
++    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. I2C0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
++    // .. .. I2C1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. UART0_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[20:20] = 0x00000001U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
++    // .. .. UART1_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
++    // .. .. GPIO_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
++    // .. .. LQSPI_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
++    // .. .. SMC_CPU_1XCLKACT = 0x1
++    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC844DU),
++    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
++    // .. START: THIS SHOULD BE BLANK
++    // .. FINISH: THIS SHOULD BE BLANK
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_ddr_init_data_1_0[] = {
++    // START: top
++    // .. START: DDR INITIALIZATION
++    // .. .. START: LOCK DDR
++    // .. .. reg_ddrc_soft_rstb = 0
++    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_powerdown_en = 0x0
++    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_data_bus_width = 0x0
++    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
++    // .. .. reg_ddrc_burst8_refresh = 0x0
++    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
++    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
++    // .. .. reg_ddrc_dis_rd_bypass = 0x0
++    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_act_bypass = 0x0
++    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_auto_refresh = 0x0
++    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
++    // .. .. FINISH: LOCK DDR
++    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x40
++    // .. .. ==> 0XF8006004[11:0] = 0x00000040U
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000040U
++    // .. .. reg_ddrc_active_ranks = 0x1
++    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
++    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
++    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_wr_odt_block = 0x1
++    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
++    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
++    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
++    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
++    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_open_bank = 0x0
++    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
++    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
++    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081040U),
++    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
++    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
++    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
++    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
++    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
++    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
++    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
++    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
++    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
++    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
++    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
++    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
++    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
++    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
++    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
++    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
++    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
++    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
++    // .. .. reg_ddrc_w_xact_run_length = 0x8
++    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
++    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
++    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
++    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
++    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
++    // .. .. reg_ddrc_t_rc = 0x1b
++    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
++    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
++    // .. .. reg_ddrc_t_rfc_min = 0xa0
++    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
++    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
++    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
++    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
++    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU),
++    // .. .. reg_ddrc_wr2pre = 0x11
++    // .. .. ==> 0XF8006018[4:0] = 0x00000011U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000011U
++    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
++    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
++    // .. .. reg_ddrc_t_faw = 0x16
++    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
++    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
++    // .. .. reg_ddrc_t_ras_max = 0x12
++    // .. .. ==> 0XF8006018[21:16] = 0x00000012U
++    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00120000U
++    // .. .. reg_ddrc_t_ras_min = 0x13
++    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
++    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
++    // .. .. reg_ddrc_t_cke = 0x4
++    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44D258D1U),
++    // .. .. reg_ddrc_write_latency = 0x4
++    // .. .. ==> 0XF800601C[4:0] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000004U
++    // .. .. reg_ddrc_rd2wr = 0x9
++    // .. .. ==> 0XF800601C[9:5] = 0x00000009U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000120U
++    // .. .. reg_ddrc_wr2rd = 0xd
++    // .. .. ==> 0XF800601C[14:10] = 0x0000000DU
++    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003400U
++    // .. .. reg_ddrc_t_xp = 0x4
++    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
++    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
++    // .. .. reg_ddrc_pad_pd = 0x0
++    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rd2pre = 0x4
++    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
++    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
++    // .. .. reg_ddrc_t_rcd = 0x8
++    // .. .. ==> 0XF800601C[31:28] = 0x00000008U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x80000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x82023524U),
++    // .. .. reg_ddrc_t_ccd = 0x4
++    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
++    // .. .. reg_ddrc_t_rrd = 0x6
++    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
++    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
++    // .. .. reg_ddrc_refresh_margin = 0x2
++    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
++    // .. .. reg_ddrc_t_rp = 0x8
++    // .. .. ==> 0XF8006020[15:12] = 0x00000008U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00008000U
++    // .. .. reg_ddrc_refresh_to_x32 = 0x8
++    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
++    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
++    // .. .. reg_ddrc_sdram = 0x1
++    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
++    // .. .. reg_ddrc_mobile = 0x0
++    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_clock_stop_en = 0x0
++    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_read_latency = 0x8
++    // .. .. ==> 0XF8006020[28:24] = 0x00000008U
++    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x08000000U
++    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
++    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
++    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
++    // .. .. reg_ddrc_dis_pad_pd = 0x0
++    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
++    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_loopback = 0x0
++    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
++    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x282882D0U),
++    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
++    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_prefer_write = 0x0
++    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_max_rank_rd = 0xf
++    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
++    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
++    // .. .. reg_ddrc_mr_wr = 0x0
++    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_addr = 0x0
++    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_data = 0x0
++    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
++    // .. .. ddrc_reg_mr_wr_busy = 0x0
++    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_type = 0x0
++    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr_rdata_valid = 0x0
++    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
++    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
++    // .. .. reg_ddrc_final_wait_x32 = 0x7
++    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
++    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
++    // .. .. reg_ddrc_t_mrd = 0x4
++    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
++    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
++    // .. .. reg_ddrc_emr2 = 0x0
++    // .. .. ==> 0XF800602C[15:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. reg_ddrc_emr3 = 0x0
++    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_ddrc_mr = 0x940
++    // .. .. ==> 0XF8006030[15:0] = 0x00000940U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000940U
++    // .. .. reg_ddrc_emr = 0x4
++    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
++    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040940U),
++    // .. .. reg_ddrc_burst_rdwr = 0x4
++    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
++    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
++    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
++    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
++    // .. .. reg_ddrc_post_cke_x1024 = 0x1
++    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
++    // .. .. reg_ddrc_burstchop = 0x0
++    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
++    // .. .. reg_ddrc_force_low_pri_n = 0x0
++    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_dq = 0x0
++    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_debug_mode = 0x0
++    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_level_start = 0x0
++    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_level_start = 0x0
++    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. .. reg_phy_dq0_wait_t = 0x0
++    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
++    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
++    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
++    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
++    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
++    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
++    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
++    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
++    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
++    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
++    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
++    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
++    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
++    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
++    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
++    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
++    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
++    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
++    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
++    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
++    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
++    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
++    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
++    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
++    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
++    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
++    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
++    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
++    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
++    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
++    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
++    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
++    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
++    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
++    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
++    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
++    // .. .. reg_ddrc_rank0_rd_odt = 0x0
++    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rank0_wr_odt = 0x1
++    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
++    // .. .. reg_ddrc_rank1_rd_odt = 0x1
++    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
++    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
++    // .. .. reg_ddrc_rank1_wr_odt = 0x1
++    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. .. reg_phy_rd_local_odt = 0x0
++    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_local_odt = 0x3
++    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
++    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
++    // .. .. reg_phy_idle_local_odt = 0x3
++    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
++    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
++    // .. .. reg_ddrc_rank2_rd_odt = 0x0
++    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rank2_wr_odt = 0x0
++    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rank3_rd_odt = 0x0
++    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
++    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rank3_wr_odt = 0x0
++    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
++    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
++    // .. .. reg_phy_rd_cmd_to_data = 0x0
++    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_phy_wr_cmd_to_data = 0x0
++    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
++    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
++    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
++    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_phy_use_fixed_re = 0x1
++    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
++    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
++    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_phy_clk_stall_level = 0x0
++    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
++    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
++    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
++    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
++    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
++    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
++    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
++    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
++    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
++    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
++    // .. .. reg_ddrc_dis_dll_calib = 0x0
++    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
++    // .. .. reg_ddrc_rd_odt_delay = 0x3
++    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
++    // .. .. reg_ddrc_wr_odt_delay = 0x0
++    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rd_odt_hold = 0x0
++    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
++    // .. .. reg_ddrc_wr_odt_hold = 0x5
++    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
++    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
++    // .. .. reg_ddrc_pageclose = 0x0
++    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_lpr_num_entries = 0x1f
++    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
++    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
++    // .. .. reg_ddrc_auto_pre_en = 0x0
++    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. .. reg_ddrc_refresh_update_level = 0x0
++    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_wc = 0x0
++    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
++    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_ddrc_selfref_en = 0x0
++    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
++    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
++    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
++    // .. .. reg_arb_go2critical_en = 0x1
++    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
++    // .. .. reg_ddrc_wrlvl_ww = 0x42
++    // .. .. ==> 0XF8006068[7:0] = 0x00000042U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000042U
++    // .. .. reg_ddrc_rdlvl_rr = 0x42
++    // .. .. ==> 0XF8006068[15:8] = 0x00000042U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004200U
++    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
++    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
++    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284242U),
++    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
++    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
++    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
++    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
++    // .. .. refresh_timer0_start_value_x32 = 0x0
++    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
++    // .. .. refresh_timer1_start_value_x32 = 0x8
++    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
++    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
++    // .. .. reg_ddrc_dis_auto_zq = 0x0
++    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_ddr3 = 0x1
++    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. reg_ddrc_t_mod = 0x200
++    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
++    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
++    // .. .. reg_ddrc_t_zq_long_nop = 0x200
++    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
++    // .. .. reg_ddrc_t_zq_short_nop = 0x40
++    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
++    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
++    // .. .. t_zq_short_interval_x1024 = 0xcb73
++    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
++    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
++    // .. .. dram_rstn_x1024 = 0x69
++    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
++    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
++    // .. .. deeppowerdown_en = 0x0
++    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. deeppowerdown_to_x1024 = 0xff
++    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
++    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
++    // .. .. dfi_wrlvl_max_x1024 = 0xfff
++    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
++    // .. .. dfi_rdlvl_max_x1024 = 0xfff
++    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
++    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
++    // .. .. ddrc_reg_twrlvl_max_error = 0x0
++    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. .. ddrc_reg_trdlvl_max_error = 0x0
++    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
++    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
++    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
++    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
++    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
++    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
++    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
++    // .. .. reg_ddrc_2t_delay = 0x0
++    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
++    // .. .. reg_ddrc_skip_ocd = 0x1
++    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
++    // .. .. reg_ddrc_dis_pre_bypass = 0x0
++    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
++    // .. .. reg_ddrc_dfi_t_rddata_en = 0x7
++    // .. .. ==> 0XF80060B8[4:0] = 0x00000007U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000007U
++    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
++    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
++    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
++    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
++    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
++    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200067U),
++    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
++    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
++    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
++    // .. .. CORR_ECC_LOG_VALID = 0x0
++    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
++    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
++    // .. .. UNCORR_ECC_LOG_VALID = 0x0
++    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
++    // .. .. STAT_NUM_CORR_ERR = 0x0
++    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
++    // .. .. STAT_NUM_UNCORR_ERR = 0x0
++    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
++    // .. .. reg_ddrc_ecc_mode = 0x0
++    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_scrub = 0x1
++    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
++    // .. .. reg_phy_dif_on = 0x0
++    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
++    // .. .. reg_phy_dif_off = 0x0
++    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
++    // .. .. reg_phy_data_slice_in_use = 0x1
++    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_phy_rdlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_gatelvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_wrlvl_inc_mode = 0x0
++    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_tx = 0x0
++    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_board_lpbk_rx = 0x0
++    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_shift_dq = 0x0
++    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_err_clr = 0x0
++    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
++    // .. .. reg_phy_dq_offset = 0x40
++    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
++    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x1f
++    // .. .. ==> 0XF800612C[9:0] = 0x0000001FU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001FU
++    // .. .. reg_phy_gatelvl_init_ratio = 0xa1
++    // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002841FU),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x24
++    // .. .. ==> 0XF8006130[9:0] = 0x00000024U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000024U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x98
++    // .. .. ==> 0XF8006130[19:10] = 0x00000098U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00026000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00026024U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x21
++    // .. .. ==> 0XF8006134[9:0] = 0x00000021U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x9d
++    // .. .. ==> 0XF8006134[19:10] = 0x0000009DU
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00027400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00027421U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x20
++    // .. .. ==> 0XF8006138[9:0] = 0x00000020U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000020U
++    // .. .. reg_phy_gatelvl_init_ratio = 0xa0
++    // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028020U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
++    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
++    // .. .. reg_phy_rd_dqs_slave_force = 0x0
++    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9f
++    // .. .. ==> 0XF8006154[9:0] = 0x0000009FU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009FU
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009FU),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa4
++    // .. .. ==> 0XF8006158[9:0] = 0x000000A4U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A4U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A4U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
++    // .. .. ==> 0XF800615C[9:0] = 0x000000A1U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x000000A1U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa0
++    // .. .. ==> 0XF8006160[9:0] = 0x000000A0U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A0U
++    // .. .. reg_phy_wr_dqs_slave_force = 0x0
++    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
++    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A0U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
++    // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F6U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xed
++    // .. .. ==> 0XF800616C[10:0] = 0x000000EDU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000EDU
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000EDU),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf2
++    // .. .. ==> 0XF8006170[10:0] = 0x000000F2U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F2U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F2U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
++    // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F5U
++    // .. .. reg_phy_fifo_we_in_force = 0x0
++    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. .. reg_phy_fifo_we_in_delay = 0x0
++    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
++    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xdf
++    // .. .. ==> 0XF800617C[9:0] = 0x000000DFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DFU
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DFU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe4
++    // .. .. ==> 0XF8006180[9:0] = 0x000000E4U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E4U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E4U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
++    // .. .. ==> 0XF8006184[9:0] = 0x000000E1U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000E1U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe0
++    // .. .. ==> 0XF8006188[9:0] = 0x000000E0U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E0U
++    // .. .. reg_phy_wr_data_slave_force = 0x0
++    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. .. reg_phy_wr_data_slave_delay = 0x0
++    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
++    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E0U),
++    // .. .. reg_phy_loopback = 0x0
++    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_phy_bl2 = 0x0
++    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_phy_at_spd_atpg = 0x0
++    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_enable = 0x0
++    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_force_err = 0x0
++    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. reg_phy_bist_mode = 0x0
++    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. .. reg_phy_invert_clkout = 0x1
++    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
++    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. .. reg_phy_sel_logic = 0x0
++    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_ratio = 0x100
++    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
++    // .. .. reg_phy_ctrl_slave_force = 0x0
++    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_delay = 0x0
++    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
++    // .. .. reg_phy_use_rank0_delays = 0x1
++    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
++    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
++    // .. .. reg_phy_lpddr = 0x0
++    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
++    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
++    // .. .. reg_phy_cmd_latency = 0x0
++    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
++    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
++    // .. .. reg_phy_int_lpbk = 0x0
++    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
++    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
++    // .. .. reg_phy_wr_rl_delay = 0x1
++    // .. .. ==> 0XF8006194[4:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000001U
++    // .. .. reg_phy_rd_rl_delay = 0x5
++    // .. .. ==> 0XF8006194[9:5] = 0x00000005U
++    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000A0U
++    // .. .. reg_phy_dll_lock_diff = 0xf
++    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
++    // .. .. reg_phy_use_wr_level = 0x1
++    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
++    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
++    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
++    // .. .. reg_phy_use_rd_data_eye_level = 0x1
++    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. .. reg_phy_dis_calib_rst = 0x0
++    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_phy_ctrl_slave_delay = 0x0
++    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FCA1U),
++    // .. .. reg_arb_page_addr_mask = 0x0
++    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_rmw_portn = 0x1
++    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_rmw_portn = 0x1
++    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_rmw_portn = 0x1
++    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
++    // .. .. reg_arb_pri_wr_portn = 0x3ff
++    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
++    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_rmw_portn = 0x1
++    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_arb_pri_rd_portn = 0x3ff
++    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
++    // .. .. reg_arb_disable_aging_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
++    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
++    // .. .. reg_arb_set_hpr_rd_portn = 0x0
++    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
++    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
++    // .. .. reg_ddrc_lpddr2 = 0x0
++    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. reg_ddrc_per_bank_refresh = 0x0
++    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_derate_enable = 0x0
++    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. reg_ddrc_mr4_margin = 0x0
++    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
++    // .. .. reg_ddrc_mr4_read_interval = 0x0
++    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
++    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
++    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
++    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
++    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
++    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
++    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
++    // .. .. reg_ddrc_t_mrw = 0x5
++    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
++    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
++    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
++    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
++    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
++    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
++    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
++    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
++    // .. .. 
++    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
++    // .. .. START: POLL ON DCI STATUS
++    // .. .. DONE = 1
++    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
++    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
++    // .. .. 
++    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
++    // .. .. FINISH: POLL ON DCI STATUS
++    // .. .. START: UNLOCK DDR
++    // .. .. reg_ddrc_soft_rstb = 0x1
++    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. reg_ddrc_powerdown_en = 0x0
++    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. .. reg_ddrc_data_bus_width = 0x0
++    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
++    // .. .. reg_ddrc_burst8_refresh = 0x0
++    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
++    // .. .. reg_ddrc_rdwr_idle_gap = 1
++    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
++    // .. .. reg_ddrc_dis_rd_bypass = 0x0
++    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_act_bypass = 0x0
++    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
++    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
++    // .. .. reg_ddrc_dis_auto_refresh = 0x0
++    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
++    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
++    // .. .. FINISH: UNLOCK DDR
++    // .. .. START: CHECK DDR STATUS
++    // .. .. ddrc_reg_operating_mode = 1
++    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
++    // .. .. 
++    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
++    // .. .. FINISH: CHECK DDR STATUS
++    // .. FINISH: DDR INITIALIZATION
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_mio_init_data_1_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: OCM REMAPPING
++    // .. FINISH: OCM REMAPPING
++    // .. START: DDRIOB SETTINGS
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B40[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B40[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B40[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B40[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCR_TYPE = 0x0
++    // .. ==> 0XF8000B40[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B40[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B40[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B40[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B40[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B44[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B44[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B44[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B44[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCR_TYPE = 0x0
++    // .. ==> 0XF8000B44[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B44[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B44[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B44[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B44[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B48[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x1
++    // .. ==> 0XF8000B48[2:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B48[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B48[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCR_TYPE = 0x3
++    // .. ==> 0XF8000B48[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B48[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B48[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B48[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B48[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x1
++    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCR_TYPE = 0x3
++    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B50[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x2
++    // .. ==> 0XF8000B50[2:1] = 0x00000002U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B50[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B50[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCR_TYPE = 0x3
++    // .. ==> 0XF8000B50[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B50[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B50[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B50[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B50[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B54[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x2
++    // .. ==> 0XF8000B54[2:1] = 0x00000002U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B54[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x1
++    // .. ==> 0XF8000B54[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. DCR_TYPE = 0x3
++    // .. ==> 0XF8000B54[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. IBUF_DISABLE_MODE = 0
++    // .. ==> 0XF8000B54[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0
++    // .. ==> 0XF8000B54[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B54[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B54[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
++    // .. INP_POWER = 0x0
++    // .. ==> 0XF8000B58[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. INP_TYPE = 0x0
++    // .. ==> 0XF8000B58[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. DCI_UPDATE = 0x0
++    // .. ==> 0XF8000B58[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. TERM_EN = 0x0
++    // .. ==> 0XF8000B58[4:4] = 0x00000000U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. DCR_TYPE = 0x0
++    // .. ==> 0XF8000B58[6:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
++    // .. IBUF_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B58[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. TERM_DISABLE_MODE = 0x0
++    // .. ==> 0XF8000B58[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. OUTPUT_EN = 0x3
++    // .. ==> 0XF8000B58[10:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
++    // .. PULLUP_EN = 0x0
++    // .. ==> 0XF8000B58[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
++    // .. DRIVE_P = 0x1c
++    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. DRIVE_N = 0xc
++    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. SLEW_P = 0x3
++    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
++    // .. SLEW_N = 0x3
++    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
++    // .. GTL = 0x0
++    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. RTERM = 0x0
++    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
++    // .. DRIVE_P = 0x1c
++    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. DRIVE_N = 0xc
++    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. SLEW_P = 0x6
++    // .. ==> 0XF8000B60[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. SLEW_N = 0x1f
++    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. GTL = 0x0
++    // .. ==> 0XF8000B60[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. RTERM = 0x0
++    // .. ==> 0XF8000B60[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. DRIVE_P = 0x1c
++    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. DRIVE_N = 0xc
++    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. SLEW_P = 0x6
++    // .. ==> 0XF8000B64[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. SLEW_N = 0x1f
++    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. GTL = 0x0
++    // .. ==> 0XF8000B64[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. RTERM = 0x0
++    // .. ==> 0XF8000B64[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. DRIVE_P = 0x1c
++    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
++    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
++    // .. DRIVE_N = 0xc
++    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
++    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
++    // .. SLEW_P = 0x6
++    // .. ==> 0XF8000B68[18:14] = 0x00000006U
++    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
++    // .. SLEW_N = 0x1f
++    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
++    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
++    // .. GTL = 0x0
++    // .. ==> 0XF8000B68[26:24] = 0x00000000U
++    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
++    // .. RTERM = 0x0
++    // .. ==> 0XF8000B68[31:27] = 0x00000000U
++    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
++    // .. VREF_INT_EN = 0x0
++    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. VREF_SEL = 0x0
++    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
++    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
++    // .. VREF_EXT_EN = 0x3
++    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
++    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
++    // .. VREF_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
++    // .. REFIO_EN = 0x1
++    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
++    // .. REFIO_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DRST_B_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. CKE_PULLUP_EN = 0x0
++    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
++    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
++    // .. .. START: ASSERT RESET
++    // .. .. RESET = 1
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. VRN_OUT = 0x1
++    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
++    // .. .. FINISH: ASSERT RESET
++    // .. .. START: DEASSERT RESET
++    // .. .. RESET = 0
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. .. VRN_OUT = 0x1
++    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
++    // .. .. FINISH: DEASSERT RESET
++    // .. .. RESET = 0x1
++    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. ENABLE = 0x1
++    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. .. VRP_TRI = 0x0
++    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. .. VRN_TRI = 0x0
++    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. .. VRP_OUT = 0x0
++    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
++    // .. .. VRN_OUT = 0x1
++    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
++    // .. .. NREF_OPT1 = 0x0
++    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
++    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. .. NREF_OPT2 = 0x0
++    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
++    // .. .. NREF_OPT4 = 0x1
++    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
++    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
++    // .. .. PREF_OPT1 = 0x0
++    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
++    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
++    // .. .. PREF_OPT2 = 0x0
++    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
++    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
++    // .. .. UPDATE_CONTROL = 0x0
++    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
++    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. .. INIT_COMPLETE = 0x0
++    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
++    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
++    // .. .. TST_CLK = 0x0
++    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
++    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. .. TST_HLN = 0x0
++    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
++    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. .. TST_HLP = 0x0
++    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
++    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. .. TST_RST = 0x0
++    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
++    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
++    // .. .. INT_DCI_EN = 0x0
++    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
++    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
++    // .. FINISH: DDRIOB SETTINGS
++    // .. START: MIO PROGRAMMING
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000700[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000700[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000700[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000700[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000700[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000700[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000700[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000700[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000700[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000704[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000704[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000704[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000704[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000704[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000704[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000704[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000704[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000704[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000708[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000708[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000708[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000708[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000708[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000708[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000708[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000708[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000708[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800070C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800070C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800070C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800070C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800070C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800070C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800070C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800070C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800070C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000710[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000710[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000710[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000710[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000710[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000710[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000710[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000710[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000710[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000714[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000714[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000714[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000714[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000714[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000714[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000714[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000714[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000714[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000718[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000718[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000718[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000718[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000718[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000718[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000718[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000718[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000718[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800071C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800071C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800071C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800071C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800071C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800071C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800071C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800071C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800071C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000720[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000720[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000720[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000720[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000720[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000720[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000720[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000720[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000720[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000724[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000724[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000724[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000724[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000724[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000724[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000724[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000724[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000724[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000728[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000728[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000728[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000728[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF8000728[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF8000728[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000728[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF8000728[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000728[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x000006E1U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800072C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800072C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800072C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800072C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 7
++    // .. ==> 0XF800072C[7:5] = 0x00000007U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
++    // .. Speed = 0
++    // .. ==> 0XF800072C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800072C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 0
++    // .. ==> 0XF800072C[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800072C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x000006E0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000730[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000730[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000730[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000730[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000730[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000730[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000730[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000730[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000730[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000734[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000734[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000734[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000734[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000734[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000734[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000734[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000734[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000734[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000738[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000738[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000738[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000738[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF8000738[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF8000738[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF8000738[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000738[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000738[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800073C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800073C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800073C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800073C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 2
++    // .. ==> 0XF800073C[7:5] = 0x00000002U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
++    // .. Speed = 0
++    // .. ==> 0XF800073C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 3
++    // .. ==> 0XF800073C[11:9] = 0x00000003U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
++    // .. PULLUP = 1
++    // .. ==> 0XF800073C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800073C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000740[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000740[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000740[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000740[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000740[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000740[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000740[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000740[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000740[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000744[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000744[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000744[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000744[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000744[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000744[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000744[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000744[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000744[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000748[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000748[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000748[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000748[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000748[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000748[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000748[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000748[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000748[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800074C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800074C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800074C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800074C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800074C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800074C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800074C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800074C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800074C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000750[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000750[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000750[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000750[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000750[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000750[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000750[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000750[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000750[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000754[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000754[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000754[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000754[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000754[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000754[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000754[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000754[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000754[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000758[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000758[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000758[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000758[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000758[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000758[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000758[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000758[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000758[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800075C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800075C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800075C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800075C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800075C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800075C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800075C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800075C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800075C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000760[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000760[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000760[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000760[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000760[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000760[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000760[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000760[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000760[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000764[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000764[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000764[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000764[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000764[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000764[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000764[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000764[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000764[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000768[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000768[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000768[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000768[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000768[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000768[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000768[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000768[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000768[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800076C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800076C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF800076C[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800076C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800076C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800076C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800076C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800076C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800076C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000770[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000770[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000770[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000770[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000770[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000770[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000770[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000770[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000770[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000774[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000774[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000774[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000774[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000774[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000774[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000774[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000774[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000774[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000778[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000778[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000778[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000778[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000778[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000778[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000778[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000778[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000778[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF800077C[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800077C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800077C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800077C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800077C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800077C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800077C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800077C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800077C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000780[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000780[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000780[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000780[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000780[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000780[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000780[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000780[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000780[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000784[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000784[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000784[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000784[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000784[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000784[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000784[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000784[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000784[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000788[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000788[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000788[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000788[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000788[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000788[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000788[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000788[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000788[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800078C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800078C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800078C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800078C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800078C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800078C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800078C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800078C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800078C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000790[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000790[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000790[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000790[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000790[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000790[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000790[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000790[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000790[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000794[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000794[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000794[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000794[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000794[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000794[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000794[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000794[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000794[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000798[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF8000798[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF8000798[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000798[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000798[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000798[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF8000798[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF8000798[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF8000798[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF800079C[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF800079C[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 1
++    // .. ==> 0XF800079C[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. L2_SEL = 0
++    // .. ==> 0XF800079C[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF800079C[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF800079C[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF800079C[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF800079C[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF800079C[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A0[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A0[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A4[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A4[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007A8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007A8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007A8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007A8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007A8[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007A8[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007A8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007A8[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007A8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007AC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007AC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007AC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007AC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007AC[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007AC[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007AC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007AC[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007AC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007B0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007B0[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007B0[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007B4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 1
++    // .. ==> 0XF80007B4[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 0
++    // .. ==> 0XF80007B4[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007B8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007B8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007B8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007B8[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007B8[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007B8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007B8[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007B8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007BC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007BC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007BC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007BC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007BC[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007BC[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007BC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007BC[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007BC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007C0[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007C0[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C0[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 5
++    // .. ==> 0XF80007C4[7:5] = 0x00000005U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
++    // .. Speed = 0
++    // .. ==> 0XF80007C4[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C4[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012A0U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007C8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007C8[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007C8[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007C8[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007C8[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF80007C8[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007C8[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007C8[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007C8[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007CC[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007CC[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007CC[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007CC[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007CC[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF80007CC[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007CC[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007CC[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007CC[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007D0[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007D0[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007D0[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007D0[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007D0[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 0
++    // .. ==> 0XF80007D0[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007D0[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007D0[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007D0[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U),
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007D4[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 0
++    // .. ==> 0XF80007D4[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L1_SEL = 0
++    // .. ==> 0XF80007D4[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF80007D4[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 4
++    // .. ==> 0XF80007D4[7:5] = 0x00000004U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. Speed = 0
++    // .. ==> 0XF80007D4[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. IO_Type = 1
++    // .. ==> 0XF80007D4[11:9] = 0x00000001U
++    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
++    // .. PULLUP = 1
++    // .. ==> 0XF80007D4[12:12] = 0x00000001U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
++    // .. DisableRcvr = 0
++    // .. ==> 0XF80007D4[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U),
++    // .. SDIO0_WP_SEL = 55
++    // .. ==> 0XF8000830[5:0] = 0x00000037U
++    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U
++    // .. SDIO0_CD_SEL = 56
++    // .. ==> 0XF8000830[21:16] = 0x00000038U
++    // ..     ==> MASK : 0x003F0000U    VAL : 0x00380000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U),
++    // .. FINISH: MIO PROGRAMMING
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_peripherals_init_data_1_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B48[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B48[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B50[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B50[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
++    // .. IBUF_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B54[7:7] = 0x00000001U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
++    // .. TERM_DISABLE_MODE = 0x1
++    // .. ==> 0XF8000B54[8:8] = 0x00000001U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
++    // .. 
++    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
++    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // .. START: SRAM/NOR SET OPMODE
++    // .. FINISH: SRAM/NOR SET OPMODE
++    // .. START: UART REGISTERS
++    // .. BDIV = 0x6
++    // .. ==> 0XE0001034[7:0] = 0x00000006U
++    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
++    // .. 
++    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
++    // .. CD = 0x7c
++    // .. ==> 0XE0001018[15:0] = 0x0000007CU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
++    // .. 
++    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
++    // .. STPBRK = 0x0
++    // .. ==> 0XE0001000[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. STTBRK = 0x0
++    // .. ==> 0XE0001000[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. RSTTO = 0x0
++    // .. ==> 0XE0001000[6:6] = 0x00000000U
++    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. TXDIS = 0x0
++    // .. ==> 0XE0001000[5:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. TXEN = 0x1
++    // .. ==> 0XE0001000[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. RXDIS = 0x0
++    // .. ==> 0XE0001000[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. RXEN = 0x1
++    // .. ==> 0XE0001000[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. TXRES = 0x1
++    // .. ==> 0XE0001000[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. RXRES = 0x1
++    // .. ==> 0XE0001000[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. 
++    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
++    // .. IRMODE = 0x0
++    // .. ==> 0XE0001004[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. UCLKEN = 0x0
++    // .. ==> 0XE0001004[10:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. CHMODE = 0x0
++    // .. ==> 0XE0001004[9:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
++    // .. NBSTOP = 0x0
++    // .. ==> 0XE0001004[7:6] = 0x00000000U
++    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. PAR = 0x4
++    // .. ==> 0XE0001004[5:3] = 0x00000004U
++    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
++    // .. CHRL = 0x0
++    // .. ==> 0XE0001004[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. CLKS = 0x0
++    // .. ==> 0XE0001004[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
++    // .. BDIV = 0x6
++    // .. ==> 0XE0000034[7:0] = 0x00000006U
++    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
++    // .. 
++    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
++    // .. CD = 0x7c
++    // .. ==> 0XE0000018[15:0] = 0x0000007CU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU
++    // .. 
++    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
++    // .. STPBRK = 0x0
++    // .. ==> 0XE0000000[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. STTBRK = 0x0
++    // .. ==> 0XE0000000[7:7] = 0x00000000U
++    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
++    // .. RSTTO = 0x0
++    // .. ==> 0XE0000000[6:6] = 0x00000000U
++    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
++    // .. TXDIS = 0x0
++    // .. ==> 0XE0000000[5:5] = 0x00000000U
++    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
++    // .. TXEN = 0x1
++    // .. ==> 0XE0000000[4:4] = 0x00000001U
++    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
++    // .. RXDIS = 0x0
++    // .. ==> 0XE0000000[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. RXEN = 0x1
++    // .. ==> 0XE0000000[2:2] = 0x00000001U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
++    // .. TXRES = 0x1
++    // .. ==> 0XE0000000[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. RXRES = 0x1
++    // .. ==> 0XE0000000[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. 
++    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
++    // .. IRMODE = 0x0
++    // .. ==> 0XE0000004[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. UCLKEN = 0x0
++    // .. ==> 0XE0000004[10:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. CHMODE = 0x0
++    // .. ==> 0XE0000004[9:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
++    // .. NBSTOP = 0x0
++    // .. ==> 0XE0000004[7:6] = 0x00000000U
++    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
++    // .. PAR = 0x4
++    // .. ==> 0XE0000004[5:3] = 0x00000004U
++    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
++    // .. CHRL = 0x0
++    // .. ==> 0XE0000004[2:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
++    // .. CLKS = 0x0
++    // .. ==> 0XE0000004[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
++    // .. FINISH: UART REGISTERS
++    // .. START: QSPI REGISTERS
++    // .. Holdb_dr = 1
++    // .. ==> 0XE000D000[19:19] = 0x00000001U
++    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
++    // .. 
++    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
++    // .. FINISH: QSPI REGISTERS
++    // .. START: PL POWER ON RESET REGISTERS
++    // .. PCFG_POR_CNT_4K = 0
++    // .. ==> 0XF8007000[29:29] = 0x00000000U
++    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
++    // .. FINISH: PL POWER ON RESET REGISTERS
++    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
++    // .. .. START: NAND SET CYCLE
++    // .. .. FINISH: NAND SET CYCLE
++    // .. .. START: OPMODE
++    // .. .. FINISH: OPMODE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: SRAM/NOR CS0 SET CYCLE
++    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: NOR CS0 BASE ADDRESS
++    // .. .. FINISH: NOR CS0 BASE ADDRESS
++    // .. .. START: SRAM/NOR CS1 SET CYCLE
++    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
++    // .. .. START: DIRECT COMMAND
++    // .. .. FINISH: DIRECT COMMAND
++    // .. .. START: NOR CS1 BASE ADDRESS
++    // .. .. FINISH: NOR CS1 BASE ADDRESS
++    // .. .. START: USB RESET
++    // .. .. .. START: USB0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x81
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x1
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000001U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000001U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0001U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. OP_ENABLE_0 = 0x81
++    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x0
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0000U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xfffe
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFFEU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFFFE0000U
++    // .. .. .. .. DATA_0_LSW = 0x1
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000001U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000001U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFFE0001U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB0 RESET
++    // .. .. .. START: USB1 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB1 RESET
++    // .. .. FINISH: USB RESET
++    // .. .. START: ENET RESET
++    // .. .. .. START: ENET0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x81
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. OP_ENABLE_0 = 0x81
++    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000081U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000081U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000081U),
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x0
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. .. 
++    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET0 RESET
++    // .. .. .. START: ENET1 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. FINISH: DIR MODE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET1 RESET
++    // .. .. FINISH: ENET RESET
++    // .. .. START: I2C RESET
++    // .. .. .. START: I2C0 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C0 RESET
++    // .. .. .. START: I2C1 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: OUTPUT ENABLE
++    // .. .. .. .. FINISH: OUTPUT ENABLE
++    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. .. 
++    EMIT_MASKDELAY(0XF8F00200, 1),
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C1 RESET
++    // .. .. FINISH: I2C RESET
++    // .. .. START: NOR CHIP SELECT
++    // .. .. .. START: DIR MODE BANK 0
++    // .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. FINISH: NOR CHIP SELECT
++    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_post_config_1_0[] = {
++    // START: top
++    // .. START: SLCR SETTINGS
++    // .. UNLOCK_KEY = 0XDF0D
++    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
++    // .. 
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
++    // .. FINISH: SLCR SETTINGS
++    // .. START: ENABLING LEVEL SHIFTER
++    // .. USER_INP_ICT_EN_0 = 3
++    // .. ==> 0XF8000900[1:0] = 0x00000003U
++    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
++    // .. USER_INP_ICT_EN_1 = 3
++    // .. ==> 0XF8000900[3:2] = 0x00000003U
++    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
++    // .. 
++    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
++    // .. FINISH: ENABLING LEVEL SHIFTER
++    // .. START: FPGA RESETS TO 0
++    // .. reserved_3 = 0
++    // .. ==> 0XF8000240[31:25] = 0x00000000U
++    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
++    // .. FPGA_ACP_RST = 0
++    // .. ==> 0XF8000240[24:24] = 0x00000000U
++    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
++    // .. FPGA_AXDS3_RST = 0
++    // .. ==> 0XF8000240[23:23] = 0x00000000U
++    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
++    // .. FPGA_AXDS2_RST = 0
++    // .. ==> 0XF8000240[22:22] = 0x00000000U
++    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
++    // .. FPGA_AXDS1_RST = 0
++    // .. ==> 0XF8000240[21:21] = 0x00000000U
++    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
++    // .. FPGA_AXDS0_RST = 0
++    // .. ==> 0XF8000240[20:20] = 0x00000000U
++    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
++    // .. reserved_2 = 0
++    // .. ==> 0XF8000240[19:18] = 0x00000000U
++    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
++    // .. FSSW1_FPGA_RST = 0
++    // .. ==> 0XF8000240[17:17] = 0x00000000U
++    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
++    // .. FSSW0_FPGA_RST = 0
++    // .. ==> 0XF8000240[16:16] = 0x00000000U
++    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
++    // .. reserved_1 = 0
++    // .. ==> 0XF8000240[15:14] = 0x00000000U
++    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
++    // .. FPGA_FMSW1_RST = 0
++    // .. ==> 0XF8000240[13:13] = 0x00000000U
++    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
++    // .. FPGA_FMSW0_RST = 0
++    // .. ==> 0XF8000240[12:12] = 0x00000000U
++    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
++    // .. FPGA_DMA3_RST = 0
++    // .. ==> 0XF8000240[11:11] = 0x00000000U
++    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
++    // .. FPGA_DMA2_RST = 0
++    // .. ==> 0XF8000240[10:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
++    // .. FPGA_DMA1_RST = 0
++    // .. ==> 0XF8000240[9:9] = 0x00000000U
++    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
++    // .. FPGA_DMA0_RST = 0
++    // .. ==> 0XF8000240[8:8] = 0x00000000U
++    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
++    // .. reserved = 0
++    // .. ==> 0XF8000240[7:4] = 0x00000000U
++    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
++    // .. FPGA3_OUT_RST = 0
++    // .. ==> 0XF8000240[3:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
++    // .. FPGA2_OUT_RST = 0
++    // .. ==> 0XF8000240[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. FPGA1_OUT_RST = 0
++    // .. ==> 0XF8000240[1:1] = 0x00000000U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. FPGA0_OUT_RST = 0
++    // .. ==> 0XF8000240[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. 
++    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
++    // .. FINISH: FPGA RESETS TO 0
++    // .. START: AFI REGISTERS
++    // .. .. START: AFI0 REGISTERS
++    // .. .. FINISH: AFI0 REGISTERS
++    // .. .. START: AFI1 REGISTERS
++    // .. .. FINISH: AFI1 REGISTERS
++    // .. .. START: AFI2 REGISTERS
++    // .. .. FINISH: AFI2 REGISTERS
++    // .. .. START: AFI3 REGISTERS
++    // .. .. FINISH: AFI3 REGISTERS
++    // .. FINISH: AFI REGISTERS
++    // .. START: LOCK IT BACK
++    // .. LOCK_KEY = 0X767B
++    // .. ==> 0XF8000004[15:0] = 0x0000767BU
++    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
++    // .. 
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
++    // .. FINISH: LOCK IT BACK
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++unsigned long ps7_debug_1_0[] = {
++    // START: top
++    // .. START: CROSS TRIGGER CONFIGURATIONS
++    // .. .. START: UNLOCKING CTI REGISTERS
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
++    // .. .. KEY = 0XC5ACCE55
++    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
++    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
++    // .. .. 
++    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
++    // .. .. FINISH: UNLOCKING CTI REGISTERS
++    // .. .. START: ENABLING CTI MODULES AND CHANNELS
++    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
++    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
++    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
++    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
++    // FINISH: top
++    //
++    EMIT_EXIT(),
++
++    //
++};
++
++
++#include "xil_io.h"
++#define PS7_MASK_POLL_TIME 100000000
++
++char*
++getPS7MessageInfo(unsigned key) {
++
++  char* err_msg = "";
++  switch (key) {
++    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
++    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
++    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
++    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
++    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
++    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
++    default:                                err_msg = "Undefined error status"; break;
++  }
++  
++  return err_msg;  
++}
++
++unsigned long
++ps7GetSiliconVersion () {
++  // Read PS version from MCTRL register [31:28]
++  unsigned long mask = 0xF0000000;
++  unsigned long *addr = (unsigned long*) 0XF8007080;    
++  unsigned long ps_version = (*addr & mask) >> 28;
++  return ps_version;
++}
++
++void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
++        volatile unsigned long *addr = (volatile unsigned long*) add;
++        *addr = ( val & mask ) | ( *addr & ~mask);
++        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
++}
++
++
++int mask_poll(unsigned long add , unsigned long mask ) {
++        volatile unsigned long *addr = (volatile unsigned long*) add;
++        int i = 0;
++        while (!(*addr & mask)) {
++          if (i == PS7_MASK_POLL_TIME) {
++            return -1;
++          }
++          i++;
++        }
++     return 1;   
++        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
++}
++
++unsigned long mask_read(unsigned long add , unsigned long mask ) {
++        volatile unsigned long *addr = (volatile unsigned long*) add;
++        unsigned long val = (*addr & mask);
++        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
++        return val;
++}
++
++
++
++int
++ps7_config(unsigned long * ps7_config_init) 
++{
++    unsigned long *ptr = ps7_config_init;
++
++    unsigned long  opcode;            // current instruction ..
++    unsigned long  args[16];           // no opcode has so many args ...
++    int  numargs;           // number of arguments of this instruction
++    int  j;                 // general purpose index
++
++    volatile unsigned long *addr;         // some variable to make code readable
++    unsigned long  val,mask;              // some variable to make code readable
++
++    int finish = -1 ;           // loop while this is negative !
++    int i = 0;                  // Timeout variable
++    
++    while( finish < 0 ) {
++        numargs = ptr[0] & 0xF;
++        opcode = ptr[0] >> 4;
++
++        for( j = 0 ; j < numargs ; j ++ ) 
++            args[j] = ptr[j+1];
++        ptr += numargs + 1;
++        
++        
++        switch ( opcode ) {
++            
++        case OPCODE_EXIT:
++            finish = PS7_INIT_SUCCESS;
++            break;
++            
++        case OPCODE_CLEAR:
++            addr = (unsigned long*) args[0];
++            *addr = 0;
++            break;
++
++        case OPCODE_WRITE:
++            addr = (unsigned long*) args[0];
++            val = args[1];
++            *addr = val;
++            break;
++
++        case OPCODE_MASKWRITE:
++            addr = (unsigned long*) args[0];
++            mask = args[1];
++            val = args[2];
++            *addr = ( val & mask ) | ( *addr & ~mask);
++            break;
++
++        case OPCODE_MASKPOLL:
++            addr = (unsigned long*) args[0];
++            mask = args[1];
++            i = 0;
++            while (!(*addr & mask)) {
++                if (i == PS7_MASK_POLL_TIME) {
++                    finish = PS7_INIT_TIMEOUT;
++                    break;
++                }
++                i++;
++            }
++            break;
++        case OPCODE_MASKDELAY:
++            addr = (unsigned long*) args[0];
++            mask = args[1];
++            int delay = get_number_of_cycles_for_delay(mask);
++            perf_reset_and_start_timer(); 
++            while ((*addr < delay)) {
++            }
++            break;
++        default:
++            finish = PS7_INIT_CORRUPT;
++            break;
++        }
++    }
++    return finish;
++}
++
++unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
++unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
++unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
++unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
++unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
++
++int
++ps7_post_config() 
++{
++  // Get the PS_VERSION on run time
++  unsigned long si_ver = ps7GetSiliconVersion ();
++  int ret = -1;
++  if (si_ver == PCW_SILICON_VERSION_1) {
++      ret = ps7_config (ps7_post_config_1_0);   
++      if (ret != PS7_INIT_SUCCESS) return ret;
++  } else if (si_ver == PCW_SILICON_VERSION_2) {
++      ret = ps7_config (ps7_post_config_2_0);   
++      if (ret != PS7_INIT_SUCCESS) return ret;
++  } else {
++      ret = ps7_config (ps7_post_config_3_0);
++      if (ret != PS7_INIT_SUCCESS) return ret;
++  }
++  return PS7_INIT_SUCCESS;
++}
++
++int
++ps7_debug() 
++{
++  // Get the PS_VERSION on run time
++  unsigned long si_ver = ps7GetSiliconVersion ();
++  int ret = -1;
++  if (si_ver == PCW_SILICON_VERSION_1) {
++      ret = ps7_config (ps7_debug_1_0);   
++      if (ret != PS7_INIT_SUCCESS) return ret;
++  } else if (si_ver == PCW_SILICON_VERSION_2) {
++      ret = ps7_config (ps7_debug_2_0);   
++      if (ret != PS7_INIT_SUCCESS) return ret;
++  } else {
++      ret = ps7_config (ps7_debug_3_0);
++      if (ret != PS7_INIT_SUCCESS) return ret;
++  }
++  return PS7_INIT_SUCCESS;
++}
++
++
++int
++ps7_init() 
++{
++  // Get the PS_VERSION on run time
++  unsigned long si_ver = ps7GetSiliconVersion ();
++  int ret;
++  //int pcw_ver = 0;
++  
++  if (si_ver == PCW_SILICON_VERSION_1) {
++    ps7_mio_init_data = ps7_mio_init_data_1_0;
++    ps7_pll_init_data = ps7_pll_init_data_1_0;
++    ps7_clock_init_data = ps7_clock_init_data_1_0;
++    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
++    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
++    //pcw_ver = 1;
++
++  } else if (si_ver == PCW_SILICON_VERSION_2) {
++    ps7_mio_init_data = ps7_mio_init_data_2_0;
++    ps7_pll_init_data = ps7_pll_init_data_2_0;
++    ps7_clock_init_data = ps7_clock_init_data_2_0;
++    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
++    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
++    //pcw_ver = 2;
++
++  } else {
++    ps7_mio_init_data = ps7_mio_init_data_3_0;
++    ps7_pll_init_data = ps7_pll_init_data_3_0;
++    ps7_clock_init_data = ps7_clock_init_data_3_0;
++    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
++    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
++    //pcw_ver = 3;
++  }
++
++  // MIO init
++  ret = ps7_config (ps7_mio_init_data);  
++  if (ret != PS7_INIT_SUCCESS) return ret;
++
++  // PLL init
++  ret = ps7_config (ps7_pll_init_data); 
++  if (ret != PS7_INIT_SUCCESS) return ret;
++
++  // Clock init
++  ret = ps7_config (ps7_clock_init_data);
++  if (ret != PS7_INIT_SUCCESS) return ret;
++
++  // DDR init
++  ret = ps7_config (ps7_ddr_init_data);
++  if (ret != PS7_INIT_SUCCESS) return ret;
++
++
++
++  // Peripherals init
++  ret = ps7_config (ps7_peripherals_init_data);
++  if (ret != PS7_INIT_SUCCESS) return ret;
++  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
++  return PS7_INIT_SUCCESS;
++}
++
++
++
++
++/* For delay calculation using global timer */
++
++/* start timer */
++ void perf_start_clock(void)
++{
++	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
++						      (1 << 3) | // Auto-increment
++						      (0 << 8) // Pre-scale
++	); 
++}
++
++/* stop timer and reset timer count regs */
++ void perf_reset_clock(void)
++{
++	perf_disable_clock();
++	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
++	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
++}
++
++/* Compute mask for given delay in miliseconds*/
++int get_number_of_cycles_for_delay(unsigned int delay) 
++{
++  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
++  return (APU_FREQ*delay/(2*1000));
++   
++}
++
++/* stop timer */
++ void perf_disable_clock(void)
++{
++	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
++}
++
++void perf_reset_and_start_timer() 
++{
++  	    perf_reset_clock();
++	    perf_start_clock();
++}
++
++
++
++
+diff -Naur b/board/xilinx/zynq/zynq-ciaa_acc/ps7_init_gpl.h a/board/xilinx/zynq/zynq-ciaa_acc/ps7_init_gpl.h
+--- b/board/xilinx/zynq/zynq-ciaa_acc/ps7_init_gpl.h	1969-12-31 21:00:00.000000000 -0300
++++ a/board/xilinx/zynq/zynq-ciaa_acc/ps7_init_gpl.h	2017-11-17 15:51:06.000000000 -0300
+@@ -0,0 +1,137 @@
++
++/******************************************************************************
++*
++* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
++*
++* Permission is hereby granted, free of charge, to any person obtaining a copy of this
++* software and associated documentation files (the "Software"), to deal in the Software
++* without restriction, including without limitation the rights to use, copy, modify, merge,
++* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
++* persons to whom the Software is furnished to do so, subject to the following conditions:
++* 
++* The above copyright notice and this permission notice shall be included in all copies or 
++* substantial portions of the Software.
++* 
++* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or 
++* (b) that interact with a Xilinx device through a bus or interconnect.  
++* 
++* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING 
++* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
++* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 
++* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++* 
++* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or 
++* otherwise to promote the sale, use or other dealings in this Software without prior written 
++* authorization from Xilinx.
++* 
++*******************************************************************************/
++/****************************************************************************/
++/**
++*
++* @file ps7_init.h
++*
++* This file can be included in FSBL code
++* to get prototype of ps7_init() function
++* and error codes
++*
++*****************************************************************************/
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++//typedef unsigned int  u32;
++
++
++/** do we need to make this name more unique ? **/
++//extern u32 ps7_init_data[];
++extern unsigned long  * ps7_ddr_init_data;
++extern unsigned long  * ps7_mio_init_data;
++extern unsigned long  * ps7_pll_init_data;
++extern unsigned long  * ps7_clock_init_data;
++extern unsigned long  * ps7_peripherals_init_data;
++
++
++
++#define OPCODE_EXIT       0U
++#define OPCODE_CLEAR      1U
++#define OPCODE_WRITE      2U
++#define OPCODE_MASKWRITE  3U
++#define OPCODE_MASKPOLL   4U
++#define OPCODE_MASKDELAY  5U
++#define NEW_PS7_ERR_CODE 1
++
++/* Encode number of arguments in last nibble */
++#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
++#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
++#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
++#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
++#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
++#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
++
++/* Returns codes  of PS7_Init */
++#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
++#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
++#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
++#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
++#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
++#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
++
++
++/* Silicon Versions */
++#define PCW_SILICON_VERSION_1 0
++#define PCW_SILICON_VERSION_2 1
++#define PCW_SILICON_VERSION_3 2
++
++/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
++#define PS7_POST_CONFIG
++
++/* Freq of all peripherals */
++
++#define APU_FREQ  666666687
++#define DDR_FREQ  533333374
++#define DCI_FREQ  10158730
++#define QSPI_FREQ  142857132
++#define SMC_FREQ  10000000
++#define ENET0_FREQ  125000000
++#define ENET1_FREQ  10000000
++#define USB0_FREQ  60000000
++#define USB1_FREQ  60000000
++#define SDIO_FREQ  50000000
++#define UART_FREQ  100000000
++#define SPI_FREQ  166666672
++#define I2C_FREQ  111111115
++#define WDT_FREQ  111111115
++#define TTC_FREQ  50000000
++#define CAN_FREQ  10000000
++#define PCAP_FREQ  200000000
++#define TPIU_FREQ  200000000
++#define FPGA0_FREQ  100000000
++#define FPGA1_FREQ  10000000
++#define FPGA2_FREQ  10000000
++#define FPGA3_FREQ  10000000
++
++
++/* For delay calculation using global registers*/
++#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
++#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
++#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
++#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
++
++int ps7_config( unsigned long*);
++int ps7_init();
++int ps7_post_config();
++int ps7_debug();
++char* getPS7MessageInfo(unsigned key);
++
++void perf_start_clock(void);
++void perf_disable_clock(void);
++void perf_reset_clock(void);
++void perf_reset_and_start_timer(); 
++int get_number_of_cycles_for_delay(unsigned int delay); 
++#ifdef __cplusplus
++}
++#endif
++
+diff -Naur b/configs/zynq_ciaa_acc_defconfig a/configs/zynq_ciaa_acc_defconfig
+--- b/configs/zynq_ciaa_acc_defconfig	1969-12-31 21:00:00.000000000 -0300
++++ a/configs/zynq_ciaa_acc_defconfig	2017-11-23 16:00:01.629097533 -0300
+@@ -0,0 +1,892 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# U-Boot 2017.01 Configuration
++#
++CONFIG_CREATE_ARCH_SYMLINK=y
++# CONFIG_ARC is not set
++CONFIG_ARM=y
++# CONFIG_AVR32 is not set
++# CONFIG_BLACKFIN is not set
++# CONFIG_M68K is not set
++# CONFIG_MICROBLAZE is not set
++# CONFIG_MIPS is not set
++# CONFIG_NDS32 is not set
++# CONFIG_NIOS2 is not set
++# CONFIG_OPENRISC is not set
++# CONFIG_PPC is not set
++# CONFIG_SANDBOX is not set
++# CONFIG_SH is not set
++# CONFIG_SPARC is not set
++# CONFIG_X86 is not set
++# CONFIG_XTENSA is not set
++CONFIG_SYS_ARCH="arm"
++CONFIG_SYS_CPU="armv7"
++CONFIG_SYS_SOC="zynq"
++CONFIG_SYS_VENDOR="xilinx"
++CONFIG_SYS_BOARD="zynq"
++CONFIG_SYS_CONFIG_NAME="zynq_ciaa_acc"
++
++#
++# ARM architecture
++#
++CONFIG_HAS_VBAR=y
++CONFIG_HAS_THUMB2=y
++CONFIG_CPU_V7=y
++CONFIG_SYS_ARM_ARCH=7
++CONFIG_SYS_CACHE_SHIFT_6=y
++CONFIG_SYS_CACHELINE_SIZE=64
++# CONFIG_SEMIHOSTING is not set
++# CONFIG_SYS_L2CACHE_OFF is not set
++# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
++CONFIG_USE_ARCH_MEMCPY=y
++CONFIG_USE_ARCH_MEMSET=y
++# CONFIG_ARM64_SUPPORT_AARCH32 is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_TARGET_EDB93XX is not set
++# CONFIG_TARGET_ASPENITE is not set
++# CONFIG_TARGET_GPLUGD is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_KIRKWOOD is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_TARGET_DEVKIT3250 is not set
++# CONFIG_TARGET_WORK_92105 is not set
++# CONFIG_TARGET_MX25PDK is not set
++# CONFIG_TARGET_ZMX25 is not set
++# CONFIG_TARGET_APF27 is not set
++# CONFIG_TARGET_APX4DEVKIT is not set
++# CONFIG_TARGET_XFI3 is not set
++# CONFIG_TARGET_M28EVK is not set
++# CONFIG_TARGET_MX23EVK is not set
++# CONFIG_TARGET_MX28EVK is not set
++# CONFIG_TARGET_MX23_OLINUXINO is not set
++# CONFIG_TARGET_BG0900 is not set
++# CONFIG_TARGET_SANSA_FUZE_PLUS is not set
++# CONFIG_TARGET_SC_SPS_1 is not set
++# CONFIG_ORION5X is not set
++# CONFIG_TARGET_SPEAR300 is not set
++# CONFIG_TARGET_SPEAR310 is not set
++# CONFIG_TARGET_SPEAR320 is not set
++# CONFIG_TARGET_SPEAR600 is not set
++# CONFIG_TARGET_STV0991 is not set
++# CONFIG_TARGET_X600 is not set
++# CONFIG_TARGET_IMX31_PHYCORE is not set
++# CONFIG_TARGET_MX31ADS is not set
++# CONFIG_TARGET_MX31PDK is not set
++# CONFIG_TARGET_WOODBURN is not set
++# CONFIG_TARGET_WOODBURN_SD is not set
++# CONFIG_TARGET_FLEA3 is not set
++# CONFIG_TARGET_MX35PDK is not set
++# CONFIG_ARCH_BCM283X is not set
++# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set
++# CONFIG_TARGET_VEXPRESS_CA5X2 is not set
++# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
++# CONFIG_TARGET_BRXRE1 is not set
++# CONFIG_TARGET_BRPPT1 is not set
++# CONFIG_TARGET_DRACO is not set
++# CONFIG_TARGET_THUBAN is not set
++# CONFIG_TARGET_RASTABAN is not set
++# CONFIG_TARGET_ETAMIN is not set
++# CONFIG_TARGET_PXM2 is not set
++# CONFIG_TARGET_RUT is not set
++# CONFIG_TARGET_TI814X_EVM is not set
++# CONFIG_TARGET_TI816X_EVM is not set
++# CONFIG_TARGET_BCM23550_W1D is not set
++# CONFIG_TARGET_BCM28155_AP is not set
++# CONFIG_TARGET_BCMCYGNUS is not set
++# CONFIG_TARGET_BCMNSP is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_S5PC1XX is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_MESON is not set
++# CONFIG_ARCH_MX7 is not set
++# CONFIG_ARCH_MX6 is not set
++# CONFIG_ARCH_MX5 is not set
++# CONFIG_TARGET_M53EVK is not set
++# CONFIG_TARGET_MX51EVK is not set
++# CONFIG_TARGET_MX53ARD is not set
++# CONFIG_TARGET_MX53EVK is not set
++# CONFIG_TARGET_MX53LOCO is not set
++# CONFIG_TARGET_MX53SMD is not set
++# CONFIG_OMAP34XX is not set
++# CONFIG_OMAP44XX is not set
++# CONFIG_OMAP54XX is not set
++# CONFIG_AM43XX is not set
++# CONFIG_AM33XX is not set
++# CONFIG_ARCH_RMOBILE is not set
++# CONFIG_TARGET_S32V234EVB is not set
++# CONFIG_ARCH_SNAPDRAGON is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_TARGET_CM_T43 is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_TARGET_TS4600 is not set
++# CONFIG_TARGET_TS4800 is not set
++# CONFIG_TARGET_VF610TWR is not set
++# CONFIG_TARGET_COLIBRI_VF is not set
++# CONFIG_TARGET_PCM052 is not set
++# CONFIG_TARGET_BK4R1 is not set
++CONFIG_ARCH_ZYNQ=y
++# CONFIG_ARCH_ZYNQMP is not set
++# CONFIG_TEGRA is not set
++# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set
++# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set
++# CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM is not set
++# CONFIG_TARGET_VEXPRESS64_JUNO is not set
++# CONFIG_TARGET_LS2080A_EMU is not set
++# CONFIG_TARGET_LS2080A_SIMU is not set
++# CONFIG_TARGET_LS2080AQDS is not set
++# CONFIG_TARGET_LS2080ARDB is not set
++# CONFIG_TARGET_HIKEY is not set
++# CONFIG_TARGET_LS1012AQDS is not set
++# CONFIG_TARGET_LS1012ARDB is not set
++# CONFIG_TARGET_LS1012AFRDM is not set
++# CONFIG_TARGET_LS1021AQDS is not set
++# CONFIG_TARGET_LS1021ATWR is not set
++# CONFIG_TARGET_LS1021AIOT is not set
++# CONFIG_TARGET_LS1043AQDS is not set
++# CONFIG_TARGET_LS1043ARDB is not set
++# CONFIG_TARGET_LS1046AQDS is not set
++# CONFIG_TARGET_LS1046ARDB is not set
++# CONFIG_TARGET_H2200 is not set
++# CONFIG_TARGET_ZIPITZ2 is not set
++# CONFIG_TARGET_COLIBRI_PXA270 is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_STM32 is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_TARGET_THUNDERX_88XX is not set
++# CONFIG_SPL_GPIO_SUPPORT is not set
++CONFIG_SPL_LIBCOMMON_SUPPORT=y
++CONFIG_SPL_LIBGENERIC_SUPPORT=y
++CONFIG_SYS_MALLOC_F_LEN=0x600
++# CONFIG_SPL_EXT_SUPPORT is not set
++CONFIG_SPL_FAT_SUPPORT=y
++# CONFIG_SPL_I2C_SUPPORT is not set
++CONFIG_SPL_LIBDISK_SUPPORT=y
++CONFIG_SPL_MMC_SUPPORT=y
++# CONFIG_SPL_NAND_SUPPORT is not set
++# CONFIG_SPL_POWER_SUPPORT is not set
++CONFIG_SPL_SERIAL_SUPPORT=y
++# CONFIG_SPL_DISPLAY_PRINT is not set
++# CONFIG_SPL_ENV_SUPPORT is not set
++# CONFIG_SPL_DRIVERS_MISC_SUPPORT is not set
++CONFIG_SPL_SPI_FLASH_SUPPORT=y
++CONFIG_SPL_SPI_SUPPORT=y
++# CONFIG_SPL_WATCHDOG_SUPPORT is not set
++CONFIG_ZYNQ_DDRC_INIT=y
++CONFIG_SYS_MALLOC_LEN=0x1400000
++CONFIG_BOOT_INIT_FILE=""
++# CONFIG_ZYNQ_M29EW_WB_HACK is not set
++# CONFIG_ARMV7_LPAE is not set
++CONFIG_IDENT_STRING=""
++# CONFIG_PRE_CONSOLE_BUFFER is not set
++CONFIG_MMC=y
++# CONFIG_VIDEO is not set
++# CONFIG_SPL_YMODEM_SUPPORT is not set
++
++#
++# ARM debug
++#
++# CONFIG_DEBUG_LL is not set
++CONFIG_SYS_TEXT_BASE=0x4000000
++CONFIG_DEFAULT_DEVICE_TREE="zynq-ciaa_acc"
++CONFIG_SMBIOS_PRODUCT_NAME="zynq"
++# CONFIG_AHCI is not set
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++# CONFIG_DISTRO_DEFAULTS is not set
++CONFIG_SYS_MALLOC_F=y
++CONFIG_EXPERT=y
++CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
++# CONFIG_TOOLS_DEBUG is not set
++# CONFIG_PHYS_64BIT is not set
++
++#
++# Boot images
++#
++CONFIG_FIT=y
++# CONFIG_SPL_FIT is not set
++CONFIG_FIT_VERBOSE=y
++# CONFIG_FIT_SIGNATURE is not set
++# CONFIG_FIT_BEST_MATCH is not set
++# CONFIG_OF_BOARD_SETUP is not set
++# CONFIG_OF_SYSTEM_SETUP is not set
++# CONFIG_OF_STDOUT_VIA_ALIAS is not set
++CONFIG_SYS_EXTRA_OPTIONS=""
++# CONFIG_SPL_LOAD_FIT is not set
++CONFIG_ARCH_FIXUP_FDT_MEMORY=y
++
++#
++# Boot timing
++#
++# CONFIG_BOOTSTAGE is not set
++CONFIG_BOOTSTAGE_USER_COUNT=20
++CONFIG_BOOTSTAGE_STASH_ADDR=0
++CONFIG_BOOTSTAGE_STASH_SIZE=4096
++
++#
++# Boot media
++#
++# CONFIG_NAND_BOOT is not set
++# CONFIG_ONENAND_BOOT is not set
++# CONFIG_QSPI_BOOT is not set
++# CONFIG_SATA_BOOT is not set
++# CONFIG_SD_BOOT is not set
++# CONFIG_SPI_BOOT is not set
++CONFIG_BOOTDELAY=2
++
++#
++# Console
++#
++# CONFIG_CONSOLE_RECORD is not set
++# CONFIG_SILENT_CONSOLE is not set
++# CONFIG_CONSOLE_MUX is not set
++# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set
++# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
++# CONFIG_SYS_CONSOLE_ENV_OVERWRITE is not set
++# CONFIG_SYS_CONSOLE_INFO_QUIET is not set
++# CONFIG_SYS_STDIO_DEREGISTER is not set
++CONFIG_DEFAULT_FDT_FILE=""
++CONFIG_SYS_NO_FLASH=y
++# CONFIG_VERSION_VARIABLE is not set
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO=y
++
++#
++# SPL / TPL
++#
++CONFIG_SUPPORT_SPL=y
++CONFIG_SPL=y
++# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
++# CONFIG_SPL_STACK_R is not set
++CONFIG_SPL_SEPARATE_BSS=y
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
++# CONFIG_SPL_CRYPTO_SUPPORT is not set
++# CONFIG_SPL_HASH_SUPPORT is not set
++# CONFIG_SPL_DMA_SUPPORT is not set
++# CONFIG_SPL_FPGA_SUPPORT is not set
++# CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT is not set
++# CONFIG_SPL_MTD_SUPPORT is not set
++# CONFIG_SPL_MUSB_NEW_SUPPORT is not set
++# CONFIG_SPL_NET_SUPPORT is not set
++# CONFIG_SPL_NO_CPU_SUPPORT is not set
++# CONFIG_SPL_NOR_SUPPORT is not set
++# CONFIG_SPL_ONENAND_SUPPORT is not set
++CONFIG_SPL_OS_BOOT=y
++# CONFIG_SPL_POST_MEM_SUPPORT is not set
++# CONFIG_SPL_SATA_SUPPORT is not set
++# CONFIG_SPL_USB_HOST_SUPPORT is not set
++# CONFIG_SPL_USB_GADGET_SUPPORT is not set
++
++#
++# Command line interface
++#
++CONFIG_CMDLINE=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_PROMPT="Zynq> "
++
++#
++# Autoboot options
++#
++CONFIG_AUTOBOOT=y
++# CONFIG_AUTOBOOT_KEYED is not set
++
++#
++# FASTBOOT
++#
++# CONFIG_FASTBOOT is not set
++
++#
++# Commands
++#
++
++#
++# Info commands
++#
++CONFIG_CMD_BDI=y
++CONFIG_CMD_CONSOLE=y
++# CONFIG_CMD_CPU is not set
++# CONFIG_CMD_LICENSE is not set
++
++#
++# Boot commands
++#
++CONFIG_CMD_BOOTD=y
++CONFIG_CMD_BOOTM=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_BOOTEFI=y
++CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
++# CONFIG_CMD_BOOTEFI_HELLO is not set
++# CONFIG_CMD_BOOTMENU is not set
++CONFIG_CMD_ELF=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_GO=y
++CONFIG_CMD_RUN=y
++CONFIG_CMD_IMI=y
++# CONFIG_CMD_IMLS is not set
++CONFIG_CMD_XIMG=y
++# CONFIG_CMD_POWEROFF is not set
++
++#
++# Environment commands
++#
++# CONFIG_CMD_ASKENV is not set
++CONFIG_CMD_EXPORTENV=y
++CONFIG_CMD_IMPORTENV=y
++CONFIG_CMD_EDITENV=y
++# CONFIG_CMD_GREPENV is not set
++CONFIG_CMD_SAVEENV=y
++CONFIG_CMD_ENV_EXISTS=y
++
++#
++# Memory commands
++#
++CONFIG_CMD_MEMORY=y
++CONFIG_CMD_CRC32=y
++# CONFIG_LOOPW is not set
++# CONFIG_CMD_MEMTEST is not set
++# CONFIG_CMD_MX_CYCLIC is not set
++# CONFIG_CMD_MEMINFO is not set
++
++#
++# Device access commands
++#
++CONFIG_CMD_DM=y
++# CONFIG_CMD_DEMO is not set
++CONFIG_CMD_LOADB=y
++CONFIG_CMD_LOADS=y
++# CONFIG_CMD_FLASH is not set
++# CONFIG_CMD_ARMFLASH is not set
++CONFIG_CMD_MMC=y
++# CONFIG_CMD_NAND is not set
++CONFIG_CMD_SF=y
++# CONFIG_CMD_SPI is not set
++CONFIG_CMD_I2C=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_DFU=y
++# CONFIG_CMD_USB_MASS_STORAGE is not set
++CONFIG_CMD_FPGA=y
++# CONFIG_CMD_FPGA_LOADP is not set
++# CONFIG_CMD_FPGA_LOADBP is not set
++# CONFIG_CMD_FPGA_LOAD_SECURE is not set
++CONFIG_CMD_GPIO=y
++
++#
++# Shell scripting commands
++#
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_SOURCE=y
++# CONFIG_CMD_SETEXPR is not set
++
++#
++# Network commands
++#
++CONFIG_CMD_NET=y
++CONFIG_CMD_TFTPPUT=y
++# CONFIG_CMD_TFTPSRV is not set
++# CONFIG_CMD_RARP is not set
++CONFIG_CMD_DHCP=y
++# CONFIG_CMD_PXE is not set
++CONFIG_CMD_NFS=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_PING=y
++# CONFIG_CMD_CDP is not set
++# CONFIG_CMD_SNTP is not set
++# CONFIG_CMD_DNS is not set
++# CONFIG_CMD_LINK_LOCAL is not set
++
++#
++# Misc commands
++#
++# CONFIG_CMD_AES is not set
++# CONFIG_CMD_BKOPS_ENABLE is not set
++CONFIG_CMD_CACHE=y
++# CONFIG_CMD_TIME is not set
++CONFIG_CMD_MISC=y
++# CONFIG_MP is not set
++# CONFIG_CMD_TIMER is not set
++# CONFIG_CMD_ZYNQ_RSA is not set
++# CONFIG_CMD_QFW is not set
++
++#
++# Power commands
++#
++
++#
++# Security commands
++#
++
++#
++# Firmware commands
++#
++
++#
++# Filesystem commands
++#
++CONFIG_CMD_EXT2=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_EXT4_WRITE=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FS_GENERIC=y
++# CONFIG_CMD_UBI is not set
++CONFIG_SUPPORT_OF_CONTROL=y
++
++#
++# Device Tree Control
++#
++CONFIG_OF_CONTROL=y
++CONFIG_SPL_OF_CONTROL=y
++# CONFIG_OF_SEPARATE is not set
++CONFIG_OF_EMBED=y
++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
++# CONFIG_SPL_OF_PLATDATA is not set
++CONFIG_NET=y
++CONFIG_NET_RANDOM_ETHADDR=y
++# CONFIG_NETCONSOLE is not set
++CONFIG_NET_TFTP_VARS=y
++CONFIG_BOOTP_PXE_CLIENTARCH=0x15
++CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_DM=y
++CONFIG_SPL_DM=y
++CONFIG_DM_WARN=y
++CONFIG_DM_DEVICE_REMOVE=y
++CONFIG_DM_STDIO=y
++CONFIG_DM_SEQ_ALIAS=y
++CONFIG_SPL_DM_SEQ_ALIAS=y
++# CONFIG_REGMAP is not set
++# CONFIG_SPL_REGMAP is not set
++# CONFIG_DEVRES is not set
++CONFIG_SIMPLE_BUS=y
++CONFIG_SPL_SIMPLE_BUS=y
++CONFIG_OF_TRANSLATE=y
++# CONFIG_SPL_OF_TRANSLATE is not set
++# CONFIG_ADC is not set
++# CONFIG_ADC_EXYNOS is not set
++# CONFIG_ADC_SANDBOX is not set
++CONFIG_BLK=y
++# CONFIG_DM_SCSI is not set
++# CONFIG_BLOCK_CACHE is not set
++
++#
++# SATA/SCSI device support
++#
++
++#
++# Clock
++#
++# CONFIG_CLK is not set
++# CONFIG_CPU is not set
++
++#
++# Hardware crypto devices
++#
++# CONFIG_FSL_CAAM is not set
++# CONFIG_SYS_FSL_SEC_BE is not set
++# CONFIG_SYS_FSL_SEC_LE is not set
++
++#
++# Demo for driver model
++#
++# CONFIG_DM_DEMO is not set
++
++#
++# DFU support
++#
++CONFIG_USB_FUNCTION_DFU=y
++# CONFIG_DFU_TFTP is not set
++CONFIG_DFU_MMC=y
++# CONFIG_DFU_NAND is not set
++CONFIG_DFU_RAM=y
++# CONFIG_DFU_SF is not set
++
++#
++# DMA Support
++#
++# CONFIG_DMA is not set
++# CONFIG_TI_EDMA3 is not set
++
++#
++# FPGA support
++#
++# CONFIG_FPGA_ALTERA is not set
++# CONFIG_FPGA_XILINX is not set
++
++#
++# GPIO Support
++#
++CONFIG_DM_GPIO=y
++# CONFIG_ALTERA_PIO is not set
++# CONFIG_DWAPB_GPIO is not set
++# CONFIG_ATMEL_PIO4 is not set
++# CONFIG_INTEL_BROADWELL_GPIO is not set
++# CONFIG_LPC32XX_GPIO is not set
++# CONFIG_MSM_GPIO is not set
++# CONFIG_ROCKCHIP_GPIO is not set
++# CONFIG_TEGRA_GPIO is not set
++# CONFIG_TEGRA186_GPIO is not set
++# CONFIG_VYBRID_GPIO is not set
++CONFIG_ZYNQ_GPIO=y
++# CONFIG_DM_74X164 is not set
++# CONFIG_DM_PCA953X is not set
++# CONFIG_MPC85XX_GPIO is not set
++
++#
++# I2C support
++#
++# CONFIG_DM_I2C is not set
++# CONFIG_DM_I2C_COMPAT is not set
++# CONFIG_SYS_I2C_DW is not set
++# CONFIG_DM_KEYBOARD is not set
++# CONFIG_CROS_EC_KEYB is not set
++
++#
++# LED Support
++#
++# CONFIG_LED is not set
++# CONFIG_SPL_LED is not set
++
++#
++# Mailbox Controller Support
++#
++# CONFIG_DM_MAILBOX is not set
++
++#
++# Memory Controller drivers
++#
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MISC is not set
++# CONFIG_CROS_EC is not set
++# CONFIG_FSL_SEC_MON is not set
++# CONFIG_MXC_OCOTP is not set
++# CONFIG_NUVOTON_NCT6102D is not set
++# CONFIG_PWRSEQ is not set
++# CONFIG_PCA9551_LED is not set
++# CONFIG_WINBOND_W83627 is not set
++
++#
++# MMC Host controller Support
++#
++CONFIG_DM_MMC=y
++CONFIG_DM_MMC_OPS=y
++# CONFIG_SPL_MMC_TINY is not set
++# CONFIG_MSM_SDHCI is not set
++# CONFIG_ROCKCHIP_DWMMC is not set
++CONFIG_ZYNQ_SDHCI=y
++# CONFIG_ROCKCHIP_SDHCI is not set
++CONFIG_MMC_SDHCI=y
++# CONFIG_MMC_SDHCI_SDMA is not set
++# CONFIG_MMC_SDHCI_KONA is not set
++# CONFIG_MMC_SDHCI_S5P is not set
++# CONFIG_MMC_SDHCI_SPEAR is not set
++
++#
++# MTD Support
++#
++# CONFIG_MTD is not set
++
++#
++# NAND Device Support
++#
++# CONFIG_NAND_DENALI is not set
++# CONFIG_NAND_VF610_NFC is not set
++# CONFIG_NAND_PXA3XX is not set
++# CONFIG_NAND_ARASAN is not set
++# CONFIG_NAND_ZYNQ is not set
++
++#
++# Generic NAND options
++#
++# CONFIG_SYS_NAND_U_BOOT_LOCATIONS is not set
++# CONFIG_SPL_NAND_DENALI is not set
++
++#
++# SPI Flash Support
++#
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_BAR=y
++# CONFIG_SPI_FLASH_ATMEL is not set
++# CONFIG_SPI_FLASH_EON is not set
++# CONFIG_SPI_FLASH_GIGADEVICE is not set
++# CONFIG_SPI_FLASH_ISSI is not set
++# CONFIG_SPI_FLASH_MACRONIX is not set
++CONFIG_SPI_FLASH_SPANSION=y
++# CONFIG_SPI_FLASH_STMICRO is not set
++# CONFIG_SPI_FLASH_SST is not set
++# CONFIG_SPI_FLASH_WINBOND is not set
++CONFIG_SPI_FLASH_USE_4K_SECTORS=y
++# CONFIG_SPI_FLASH_DATAFLASH is not set
++# CONFIG_SPI_FLASH_MTD is not set
++
++#
++# UBI support
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_DM_ETH=y
++CONFIG_PHYLIB=y
++# CONFIG_RTL8211X_PHY_FORCE_MASTER is not set
++CONFIG_NETDEVICES=y
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_DWC_ETH_QOS is not set
++# CONFIG_E1000 is not set
++# CONFIG_ETH_DESIGNWARE is not set
++# CONFIG_ETHOC is not set
++# CONFIG_RTL8139 is not set
++# CONFIG_RTL8169 is not set
++# CONFIG_SUN8I_EMAC is not set
++# CONFIG_XILINX_AXIEMAC is not set
++# CONFIG_XILINX_EMACLITE is not set
++CONFIG_ZYNQ_GEM=y
++# CONFIG_PCI is not set
++# CONFIG_MVEBU_COMPHY_SUPPORT is not set
++
++#
++# Pin controllers
++#
++# CONFIG_PINCTRL is not set
++# CONFIG_SPL_PINCTRL is not set
++
++#
++# Power
++#
++
++#
++# Power Domain Support
++#
++# CONFIG_POWER_DOMAIN is not set
++# CONFIG_DM_PMIC is not set
++# CONFIG_DM_REGULATOR is not set
++# CONFIG_DM_PWM is not set
++# CONFIG_RAM is not set
++
++#
++# Remote Processor drivers
++#
++
++#
++# Reset Controller Support
++#
++# CONFIG_DM_RESET is not set
++
++#
++# Real Time Clock
++#
++# CONFIG_DM_RTC is not set
++
++#
++# Serial drivers
++#
++CONFIG_REQUIRE_SERIAL_CONSOLE=y
++CONFIG_SERIAL_PRESENT=y
++CONFIG_SPL_SERIAL_PRESENT=y
++CONFIG_DM_SERIAL=y
++CONFIG_DEBUG_UART=y
++# CONFIG_DEBUG_UART_ALTERA_JTAGUART is not set
++# CONFIG_DEBUG_UART_ALTERA_UART is not set
++# CONFIG_DEBUG_UART_ATMEL is not set
++# CONFIG_DEBUG_UART_NS16550 is not set
++# CONFIG_DEBUG_UART_S5P is not set
++# CONFIG_DEBUG_UART_UARTLITE is not set
++# CONFIG_DEBUG_UART_ARM_DCC is not set
++# CONFIG_DEBUG_MVEBU_A3700_UART is not set
++CONFIG_DEBUG_UART_ZYNQ=y
++# CONFIG_DEBUG_UART_PL010 is not set
++# CONFIG_DEBUG_UART_PL011 is not set
++CONFIG_DEBUG_UART_BASE=0xe0001000
++CONFIG_DEBUG_UART_CLOCK=50000000
++CONFIG_DEBUG_UART_SHIFT=0
++# CONFIG_DEBUG_UART_BOARD_INIT is not set
++# CONFIG_DEBUG_UART_ANNOUNCE is not set
++# CONFIG_DEBUG_UART_SKIP_INIT is not set
++# CONFIG_ALTERA_JTAG_UART is not set
++# CONFIG_ALTERA_UART is not set
++# CONFIG_ATMEL_USART is not set
++# CONFIG_FSL_LPUART is not set
++# CONFIG_MVEBU_A3700_UART is not set
++# CONFIG_SYS_NS16550 is not set
++# CONFIG_XILINX_UARTLITE is not set
++# CONFIG_MSM_SERIAL is not set
++# CONFIG_PXA_SERIAL is not set
++
++#
++# Sound support
++#
++# CONFIG_SOUND is not set
++
++#
++# SPI Support
++#
++CONFIG_DM_SPI=y
++# CONFIG_ALTERA_SPI is not set
++# CONFIG_CADENCE_QSPI is not set
++# CONFIG_DESIGNWARE_SPI is not set
++# CONFIG_EXYNOS_SPI is not set
++# CONFIG_FSL_DSPI is not set
++# CONFIG_ICH_SPI is not set
++# CONFIG_MVEBU_A3700_SPI is not set
++# CONFIG_ROCKCHIP_SPI is not set
++# CONFIG_TEGRA114_SPI is not set
++# CONFIG_TEGRA20_SFLASH is not set
++# CONFIG_TEGRA20_SLINK is not set
++# CONFIG_TEGRA210_QSPI is not set
++# CONFIG_XILINX_SPI is not set
++# CONFIG_ZYNQ_SPI is not set
++CONFIG_ZYNQ_QSPI=y
++# CONFIG_OMAP3_SPI is not set
++# CONFIG_FSL_ESPI is not set
++# CONFIG_FSL_QSPI is not set
++# CONFIG_TI_QSPI is not set
++
++#
++# SPMI support
++#
++# CONFIG_SPMI is not set
++
++#
++# System reset device drivers
++#
++# CONFIG_SYSRESET is not set
++# CONFIG_DM_THERMAL is not set
++
++#
++# Timer Support
++#
++# CONFIG_TIMER is not set
++
++#
++# TPM support
++#
++CONFIG_USB=y
++CONFIG_DM_USB=y
++
++#
++# USB Host Controller Drivers
++#
++CONFIG_USB_HOST=y
++# CONFIG_USB_XHCI_HCD is not set
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI=y
++# CONFIG_USB_EHCI_MSM is not set
++CONFIG_USB_EHCI_ZYNQ=y
++# CONFIG_USB_EHCI_GENERIC is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_DWC3 is not set
++
++#
++# MUSB Controller Driver
++#
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_GADGET is not set
++# CONFIG_USB_MUSB_TI is not set
++
++#
++# ULPI drivers
++#
++CONFIG_USB_ULPI_VIEWPORT=y
++# CONFIG_USB_ULPI_VIEWPORT_OMAP is not set
++CONFIG_USB_ULPI=y
++
++#
++# USB peripherals
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_KEYBOARD is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_BCM_UDC_OTG_PHY is not set
++# CONFIG_USB_GADGET_DWC2_OTG is not set
++CONFIG_CI_UDC=y
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_DUALSPEED=y
++CONFIG_USB_GADGET_DOWNLOAD=y
++CONFIG_G_DNL_MANUFACTURER="Xilinx"
++CONFIG_G_DNL_VENDOR_NUM=0x03fd
++CONFIG_G_DNL_PRODUCT_NUM=0x0300
++CONFIG_USBNET_DEVADDR="de:ad:be:ef:00:01"
++
++#
++# Graphics support
++#
++# CONFIG_DM_VIDEO is not set
++
++#
++# TrueType Fonts
++#
++# CONFIG_VIDEO_VESA is not set
++# CONFIG_VIDEO_LCD_ANX9804 is not set
++# CONFIG_VIDEO_LCD_SSD2828 is not set
++# CONFIG_VIDEO_MVEBU is not set
++# CONFIG_DISPLAY is not set
++# CONFIG_VIDEO_TEGRA20 is not set
++# CONFIG_VIDEO_BRIDGE is not set
++# CONFIG_LCD is not set
++# CONFIG_PHYS_TO_BUS is not set
++
++#
++# File systems
++#
++
++#
++# Library routines
++#
++# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
++CONFIG_HAVE_PRIVATE_LIBGCC=y
++CONFIG_USE_PRIVATE_LIBGCC=y
++CONFIG_SYS_HZ=1000
++# CONFIG_USE_TINY_PRINTF is not set
++CONFIG_REGEX=y
++CONFIG_LIB_RAND=y
++# CONFIG_CMD_DHRYSTONE is not set
++CONFIG_RSA=y
++# CONFIG_SPL_RSA is not set
++CONFIG_RSA_SOFTWARE_EXP=y
++# CONFIG_TPM is not set
++
++#
++# Encryption Support
++#
++# CONFIG_AES is not set
++
++#
++# Hashing Support
++#
++# CONFIG_SHA1 is not set
++# CONFIG_SHA256 is not set
++# CONFIG_SHA_HW_ACCEL is not set
++
++#
++# Compression Support
++#
++# CONFIG_LZ4 is not set
++# CONFIG_ERRNO_STR is not set
++CONFIG_OF_LIBFDT=y
++# CONFIG_OF_LIBFDT_OVERLAY is not set
++CONFIG_SPL_OF_LIBFDT=y
++# CONFIG_FDT_FIXUP_PARTITIONS is not set
++
++#
++# System tables
++#
++CONFIG_GENERATE_SMBIOS_TABLE=y
++CONFIG_SMBIOS_MANUFACTURER="xilinx"
++CONFIG_EFI_LOADER=y
++# CONFIG_UNIT_TEST is not set
+diff -Naur b/include/configs/zynq_ciaa_acc.h a/include/configs/zynq_ciaa_acc.h
+--- b/include/configs/zynq_ciaa_acc.h	1969-12-31 21:00:00.000000000 -0300
++++ a/include/configs/zynq_ciaa_acc.h	2017-11-22 17:25:29.976998527 -0300
+@@ -0,0 +1,18 @@
++/*
++ * (C) Copyright 2013 Xilinx, Inc.
++ *
++ * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
++ * See zynq-common.h for Zynq common configs
++ *
++ * SPDX-License-Identifier:	GPL-2.0+
++ */
++
++#ifndef __CONFIG_ZYNQ_ZC70X_H
++#define __CONFIG_ZYNQ_ZC70X_H
++
++#define CONFIG_ZYNQ_I2C0
++#define CONFIG_ZYNQ_EEPROM
++
++#include <configs/zynq-common.h>
++
++#endif /* __CONFIG_ZYNQ_ZC70X_H */
diff --git a/board/ciaa/acc/u-boot_defconfig b/board/ciaa/acc/u-boot_defconfig
new file mode 100644
index 0000000..8e14f90
--- /dev/null
+++ b/board/ciaa/acc/u-boot_defconfig
@@ -0,0 +1,892 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# U-Boot 2017.01 Configuration
+#
+CONFIG_CREATE_ARCH_SYMLINK=y
+# CONFIG_ARC is not set
+CONFIG_ARM=y
+# CONFIG_AVR32 is not set
+# CONFIG_BLACKFIN is not set
+# CONFIG_M68K is not set
+# CONFIG_MICROBLAZE is not set
+# CONFIG_MIPS is not set
+# CONFIG_NDS32 is not set
+# CONFIG_NIOS2 is not set
+# CONFIG_OPENRISC is not set
+# CONFIG_PPC is not set
+# CONFIG_SANDBOX is not set
+# CONFIG_SH is not set
+# CONFIG_SPARC is not set
+# CONFIG_X86 is not set
+# CONFIG_XTENSA is not set
+CONFIG_SYS_ARCH="arm"
+CONFIG_SYS_CPU="armv7"
+CONFIG_SYS_SOC="zynq"
+CONFIG_SYS_VENDOR="xilinx"
+CONFIG_SYS_BOARD="zynq"
+CONFIG_SYS_CONFIG_NAME="zynq_ciaa_acc"
+
+#
+# ARM architecture
+#
+CONFIG_HAS_VBAR=y
+CONFIG_HAS_THUMB2=y
+CONFIG_CPU_V7=y
+CONFIG_SYS_ARM_ARCH=7
+CONFIG_SYS_CACHE_SHIFT_6=y
+CONFIG_SYS_CACHELINE_SIZE=64
+# CONFIG_SEMIHOSTING is not set
+# CONFIG_SYS_L2CACHE_OFF is not set
+# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
+CONFIG_USE_ARCH_MEMCPY=y
+CONFIG_USE_ARCH_MEMSET=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_TARGET_EDB93XX is not set
+# CONFIG_TARGET_ASPENITE is not set
+# CONFIG_TARGET_GPLUGD is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_KIRKWOOD is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_TARGET_DEVKIT3250 is not set
+# CONFIG_TARGET_WORK_92105 is not set
+# CONFIG_TARGET_MX25PDK is not set
+# CONFIG_TARGET_ZMX25 is not set
+# CONFIG_TARGET_APF27 is not set
+# CONFIG_TARGET_APX4DEVKIT is not set
+# CONFIG_TARGET_XFI3 is not set
+# CONFIG_TARGET_M28EVK is not set
+# CONFIG_TARGET_MX23EVK is not set
+# CONFIG_TARGET_MX28EVK is not set
+# CONFIG_TARGET_MX23_OLINUXINO is not set
+# CONFIG_TARGET_BG0900 is not set
+# CONFIG_TARGET_SANSA_FUZE_PLUS is not set
+# CONFIG_TARGET_SC_SPS_1 is not set
+# CONFIG_ORION5X is not set
+# CONFIG_TARGET_SPEAR300 is not set
+# CONFIG_TARGET_SPEAR310 is not set
+# CONFIG_TARGET_SPEAR320 is not set
+# CONFIG_TARGET_SPEAR600 is not set
+# CONFIG_TARGET_STV0991 is not set
+# CONFIG_TARGET_X600 is not set
+# CONFIG_TARGET_IMX31_PHYCORE is not set
+# CONFIG_TARGET_MX31ADS is not set
+# CONFIG_TARGET_MX31PDK is not set
+# CONFIG_TARGET_WOODBURN is not set
+# CONFIG_TARGET_WOODBURN_SD is not set
+# CONFIG_TARGET_FLEA3 is not set
+# CONFIG_TARGET_MX35PDK is not set
+# CONFIG_ARCH_BCM283X is not set
+# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set
+# CONFIG_TARGET_VEXPRESS_CA5X2 is not set
+# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
+# CONFIG_TARGET_BRXRE1 is not set
+# CONFIG_TARGET_BRPPT1 is not set
+# CONFIG_TARGET_DRACO is not set
+# CONFIG_TARGET_THUBAN is not set
+# CONFIG_TARGET_RASTABAN is not set
+# CONFIG_TARGET_ETAMIN is not set
+# CONFIG_TARGET_PXM2 is not set
+# CONFIG_TARGET_RUT is not set
+# CONFIG_TARGET_TI814X_EVM is not set
+# CONFIG_TARGET_TI816X_EVM is not set
+# CONFIG_TARGET_BCM23550_W1D is not set
+# CONFIG_TARGET_BCM28155_AP is not set
+# CONFIG_TARGET_BCMCYGNUS is not set
+# CONFIG_TARGET_BCMNSP is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_KEYSTONE is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MX7 is not set
+# CONFIG_ARCH_MX6 is not set
+# CONFIG_ARCH_MX5 is not set
+# CONFIG_TARGET_M53EVK is not set
+# CONFIG_TARGET_MX51EVK is not set
+# CONFIG_TARGET_MX53ARD is not set
+# CONFIG_TARGET_MX53EVK is not set
+# CONFIG_TARGET_MX53LOCO is not set
+# CONFIG_TARGET_MX53SMD is not set
+# CONFIG_OMAP34XX is not set
+# CONFIG_OMAP44XX is not set
+# CONFIG_OMAP54XX is not set
+# CONFIG_AM43XX is not set
+# CONFIG_AM33XX is not set
+# CONFIG_ARCH_RMOBILE is not set
+# CONFIG_TARGET_S32V234EVB is not set
+# CONFIG_ARCH_SNAPDRAGON is not set
+# CONFIG_ARCH_SOCFPGA is not set
+# CONFIG_TARGET_CM_T43 is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_TARGET_TS4600 is not set
+# CONFIG_TARGET_TS4800 is not set
+# CONFIG_TARGET_VF610TWR is not set
+# CONFIG_TARGET_COLIBRI_VF is not set
+# CONFIG_TARGET_PCM052 is not set
+# CONFIG_TARGET_BK4R1 is not set
+CONFIG_ARCH_ZYNQ=y
+# CONFIG_ARCH_ZYNQMP is not set
+# CONFIG_TEGRA is not set
+# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set
+# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set
+# CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM is not set
+# CONFIG_TARGET_VEXPRESS64_JUNO is not set
+# CONFIG_TARGET_LS2080A_EMU is not set
+# CONFIG_TARGET_LS2080A_SIMU is not set
+# CONFIG_TARGET_LS2080AQDS is not set
+# CONFIG_TARGET_LS2080ARDB is not set
+# CONFIG_TARGET_HIKEY is not set
+# CONFIG_TARGET_LS1012AQDS is not set
+# CONFIG_TARGET_LS1012ARDB is not set
+# CONFIG_TARGET_LS1012AFRDM is not set
+# CONFIG_TARGET_LS1021AQDS is not set
+# CONFIG_TARGET_LS1021ATWR is not set
+# CONFIG_TARGET_LS1021AIOT is not set
+# CONFIG_TARGET_LS1043AQDS is not set
+# CONFIG_TARGET_LS1043ARDB is not set
+# CONFIG_TARGET_LS1046AQDS is not set
+# CONFIG_TARGET_LS1046ARDB is not set
+# CONFIG_TARGET_H2200 is not set
+# CONFIG_TARGET_ZIPITZ2 is not set
+# CONFIG_TARGET_COLIBRI_PXA270 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_STM32 is not set
+# CONFIG_ARCH_ROCKCHIP is not set
+# CONFIG_TARGET_THUNDERX_88XX is not set
+# CONFIG_SPL_GPIO_SUPPORT is not set
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x600
+# CONFIG_SPL_EXT_SUPPORT is not set
+CONFIG_SPL_FAT_SUPPORT=y
+# CONFIG_SPL_I2C_SUPPORT is not set
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+# CONFIG_SPL_POWER_SUPPORT is not set
+CONFIG_SPL_SERIAL_SUPPORT=y
+# CONFIG_SPL_DISPLAY_PRINT is not set
+# CONFIG_SPL_ENV_SUPPORT is not set
+# CONFIG_SPL_DRIVERS_MISC_SUPPORT is not set
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_SPL_WATCHDOG_SUPPORT is not set
+CONFIG_ZYNQ_DDRC_INIT=y
+CONFIG_SYS_MALLOC_LEN=0x1400000
+CONFIG_BOOT_INIT_FILE=""
+# CONFIG_ZYNQ_M29EW_WB_HACK is not set
+# CONFIG_ARMV7_LPAE is not set
+CONFIG_IDENT_STRING=""
+# CONFIG_PRE_CONSOLE_BUFFER is not set
+CONFIG_MMC=y
+# CONFIG_VIDEO is not set
+# CONFIG_SPL_YMODEM_SUPPORT is not set
+
+#
+# ARM debug
+#
+# CONFIG_DEBUG_LL is not set
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-ciaa_acc"
+CONFIG_SMBIOS_PRODUCT_NAME="zynq"
+# CONFIG_AHCI is not set
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_DISTRO_DEFAULTS is not set
+CONFIG_SYS_MALLOC_F=y
+CONFIG_EXPERT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
+# CONFIG_TOOLS_DEBUG is not set
+# CONFIG_PHYS_64BIT is not set
+
+#
+# Boot images
+#
+CONFIG_FIT=y
+# CONFIG_SPL_FIT is not set
+CONFIG_FIT_VERBOSE=y
+# CONFIG_FIT_SIGNATURE is not set
+# CONFIG_FIT_BEST_MATCH is not set
+# CONFIG_OF_BOARD_SETUP is not set
+# CONFIG_OF_SYSTEM_SETUP is not set
+# CONFIG_OF_STDOUT_VIA_ALIAS is not set
+CONFIG_SYS_EXTRA_OPTIONS=""
+# CONFIG_SPL_LOAD_FIT is not set
+CONFIG_ARCH_FIXUP_FDT_MEMORY=y
+
+#
+# Boot timing
+#
+# CONFIG_BOOTSTAGE is not set
+CONFIG_BOOTSTAGE_USER_COUNT=20
+CONFIG_BOOTSTAGE_STASH_ADDR=0
+CONFIG_BOOTSTAGE_STASH_SIZE=4096
+
+#
+# Boot media
+#
+# CONFIG_NAND_BOOT is not set
+# CONFIG_ONENAND_BOOT is not set
+# CONFIG_QSPI_BOOT is not set
+# CONFIG_SATA_BOOT is not set
+# CONFIG_SD_BOOT is not set
+# CONFIG_SPI_BOOT is not set
+CONFIG_BOOTDELAY=2
+
+#
+# Console
+#
+# CONFIG_CONSOLE_RECORD is not set
+# CONFIG_SILENT_CONSOLE is not set
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set
+# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
+# CONFIG_SYS_CONSOLE_ENV_OVERWRITE is not set
+# CONFIG_SYS_CONSOLE_INFO_QUIET is not set
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+CONFIG_DEFAULT_FDT_FILE=""
+CONFIG_SYS_NO_FLASH=y
+# CONFIG_VERSION_VARIABLE is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO=y
+
+#
+# SPL / TPL
+#
+CONFIG_SUPPORT_SPL=y
+CONFIG_SPL=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+# CONFIG_SPL_STACK_R is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_CRYPTO_SUPPORT is not set
+# CONFIG_SPL_HASH_SUPPORT is not set
+# CONFIG_SPL_DMA_SUPPORT is not set
+# CONFIG_SPL_FPGA_SUPPORT is not set
+# CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT is not set
+# CONFIG_SPL_MTD_SUPPORT is not set
+# CONFIG_SPL_MUSB_NEW_SUPPORT is not set
+# CONFIG_SPL_NET_SUPPORT is not set
+# CONFIG_SPL_NO_CPU_SUPPORT is not set
+# CONFIG_SPL_NOR_SUPPORT is not set
+# CONFIG_SPL_ONENAND_SUPPORT is not set
+CONFIG_SPL_OS_BOOT=y
+# CONFIG_SPL_POST_MEM_SUPPORT is not set
+# CONFIG_SPL_SATA_SUPPORT is not set
+# CONFIG_SPL_USB_HOST_SUPPORT is not set
+# CONFIG_SPL_USB_GADGET_SUPPORT is not set
+
+#
+# Command line interface
+#
+CONFIG_CMDLINE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+
+#
+# Autoboot options
+#
+CONFIG_AUTOBOOT=y
+# CONFIG_AUTOBOOT_KEYED is not set
+
+#
+# FASTBOOT
+#
+# CONFIG_FASTBOOT is not set
+
+#
+# Commands
+#
+
+#
+# Info commands
+#
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+# CONFIG_CMD_CPU is not set
+# CONFIG_CMD_LICENSE is not set
+
+#
+# Boot commands
+#
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTEFI=y
+CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
+# CONFIG_CMD_BOOTEFI_HELLO is not set
+# CONFIG_CMD_BOOTMENU is not set
+CONFIG_CMD_ELF=y
+CONFIG_CMD_FDT=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_XIMG=y
+# CONFIG_CMD_POWEROFF is not set
+
+#
+# Environment commands
+#
+# CONFIG_CMD_ASKENV is not set
+CONFIG_CMD_EXPORTENV=y
+CONFIG_CMD_IMPORTENV=y
+CONFIG_CMD_EDITENV=y
+# CONFIG_CMD_GREPENV is not set
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_ENV_EXISTS=y
+
+#
+# Memory commands
+#
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_CRC32=y
+# CONFIG_LOOPW is not set
+# CONFIG_CMD_MEMTEST is not set
+# CONFIG_CMD_MX_CYCLIC is not set
+# CONFIG_CMD_MEMINFO is not set
+
+#
+# Device access commands
+#
+CONFIG_CMD_DM=y
+# CONFIG_CMD_DEMO is not set
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_ARMFLASH is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SPI is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_USB_MASS_STORAGE is not set
+CONFIG_CMD_FPGA=y
+# CONFIG_CMD_FPGA_LOADP is not set
+# CONFIG_CMD_FPGA_LOADBP is not set
+# CONFIG_CMD_FPGA_LOAD_SECURE is not set
+CONFIG_CMD_GPIO=y
+
+#
+# Shell scripting commands
+#
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+# CONFIG_CMD_SETEXPR is not set
+
+#
+# Network commands
+#
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+# CONFIG_CMD_TFTPSRV is not set
+# CONFIG_CMD_RARP is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_PXE is not set
+CONFIG_CMD_NFS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+# CONFIG_CMD_CDP is not set
+# CONFIG_CMD_SNTP is not set
+# CONFIG_CMD_DNS is not set
+# CONFIG_CMD_LINK_LOCAL is not set
+
+#
+# Misc commands
+#
+# CONFIG_CMD_AES is not set
+# CONFIG_CMD_BKOPS_ENABLE is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_TIME is not set
+CONFIG_CMD_MISC=y
+# CONFIG_MP is not set
+# CONFIG_CMD_TIMER is not set
+# CONFIG_CMD_ZYNQ_RSA is not set
+# CONFIG_CMD_QFW is not set
+
+#
+# Power commands
+#
+
+#
+# Security commands
+#
+
+#
+# Firmware commands
+#
+
+#
+# Filesystem commands
+#
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_CMD_UBI is not set
+CONFIG_SUPPORT_OF_CONTROL=y
+
+#
+# Device Tree Control
+#
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+# CONFIG_OF_SEPARATE is not set
+CONFIG_OF_EMBED=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
+# CONFIG_SPL_OF_PLATDATA is not set
+CONFIG_NET=y
+CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_NETCONSOLE is not set
+CONFIG_NET_TFTP_VARS=y
+CONFIG_BOOTP_PXE_CLIENTARCH=0x15
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_DM_WARN=y
+CONFIG_DM_DEVICE_REMOVE=y
+CONFIG_DM_STDIO=y
+CONFIG_DM_SEQ_ALIAS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_REGMAP is not set
+# CONFIG_SPL_REGMAP is not set
+# CONFIG_DEVRES is not set
+CONFIG_SIMPLE_BUS=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_OF_TRANSLATE=y
+# CONFIG_SPL_OF_TRANSLATE is not set
+# CONFIG_ADC is not set
+# CONFIG_ADC_EXYNOS is not set
+# CONFIG_ADC_SANDBOX is not set
+CONFIG_BLK=y
+# CONFIG_DM_SCSI is not set
+# CONFIG_BLOCK_CACHE is not set
+
+#
+# SATA/SCSI device support
+#
+
+#
+# Clock
+#
+# CONFIG_CLK is not set
+# CONFIG_CPU is not set
+
+#
+# Hardware crypto devices
+#
+# CONFIG_FSL_CAAM is not set
+# CONFIG_SYS_FSL_SEC_BE is not set
+# CONFIG_SYS_FSL_SEC_LE is not set
+
+#
+# Demo for driver model
+#
+# CONFIG_DM_DEMO is not set
+
+#
+# DFU support
+#
+CONFIG_USB_FUNCTION_DFU=y
+# CONFIG_DFU_TFTP is not set
+CONFIG_DFU_MMC=y
+# CONFIG_DFU_NAND is not set
+CONFIG_DFU_RAM=y
+# CONFIG_DFU_SF is not set
+
+#
+# DMA Support
+#
+# CONFIG_DMA is not set
+# CONFIG_TI_EDMA3 is not set
+
+#
+# FPGA support
+#
+# CONFIG_FPGA_ALTERA is not set
+# CONFIG_FPGA_XILINX is not set
+
+#
+# GPIO Support
+#
+CONFIG_DM_GPIO=y
+# CONFIG_ALTERA_PIO is not set
+# CONFIG_DWAPB_GPIO is not set
+# CONFIG_ATMEL_PIO4 is not set
+# CONFIG_INTEL_BROADWELL_GPIO is not set
+# CONFIG_LPC32XX_GPIO is not set
+# CONFIG_MSM_GPIO is not set
+# CONFIG_ROCKCHIP_GPIO is not set
+# CONFIG_TEGRA_GPIO is not set
+# CONFIG_TEGRA186_GPIO is not set
+# CONFIG_VYBRID_GPIO is not set
+CONFIG_ZYNQ_GPIO=y
+# CONFIG_DM_74X164 is not set
+# CONFIG_DM_PCA953X is not set
+# CONFIG_MPC85XX_GPIO is not set
+
+#
+# I2C support
+#
+# CONFIG_DM_I2C is not set
+# CONFIG_DM_I2C_COMPAT is not set
+# CONFIG_SYS_I2C_DW is not set
+# CONFIG_DM_KEYBOARD is not set
+# CONFIG_CROS_EC_KEYB is not set
+
+#
+# LED Support
+#
+# CONFIG_LED is not set
+# CONFIG_SPL_LED is not set
+
+#
+# Mailbox Controller Support
+#
+# CONFIG_DM_MAILBOX is not set
+
+#
+# Memory Controller drivers
+#
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MISC is not set
+# CONFIG_CROS_EC is not set
+# CONFIG_FSL_SEC_MON is not set
+# CONFIG_MXC_OCOTP is not set
+# CONFIG_NUVOTON_NCT6102D is not set
+# CONFIG_PWRSEQ is not set
+# CONFIG_PCA9551_LED is not set
+# CONFIG_WINBOND_W83627 is not set
+
+#
+# MMC Host controller Support
+#
+CONFIG_DM_MMC=y
+CONFIG_DM_MMC_OPS=y
+# CONFIG_SPL_MMC_TINY is not set
+# CONFIG_MSM_SDHCI is not set
+# CONFIG_ROCKCHIP_DWMMC is not set
+CONFIG_ZYNQ_SDHCI=y
+# CONFIG_ROCKCHIP_SDHCI is not set
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_SDMA is not set
+# CONFIG_MMC_SDHCI_KONA is not set
+# CONFIG_MMC_SDHCI_S5P is not set
+# CONFIG_MMC_SDHCI_SPEAR is not set
+
+#
+# MTD Support
+#
+# CONFIG_MTD is not set
+
+#
+# NAND Device Support
+#
+# CONFIG_NAND_DENALI is not set
+# CONFIG_NAND_VF610_NFC is not set
+# CONFIG_NAND_PXA3XX is not set
+# CONFIG_NAND_ARASAN is not set
+# CONFIG_NAND_ZYNQ is not set
+
+#
+# Generic NAND options
+#
+# CONFIG_SYS_NAND_U_BOOT_LOCATIONS is not set
+# CONFIG_SPL_NAND_DENALI is not set
+
+#
+# SPI Flash Support
+#
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+# CONFIG_SPI_FLASH_ATMEL is not set
+# CONFIG_SPI_FLASH_EON is not set
+# CONFIG_SPI_FLASH_GIGADEVICE is not set
+# CONFIG_SPI_FLASH_ISSI is not set
+# CONFIG_SPI_FLASH_MACRONIX is not set
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_STMICRO is not set
+# CONFIG_SPI_FLASH_SST is not set
+# CONFIG_SPI_FLASH_WINBOND is not set
+CONFIG_SPI_FLASH_USE_4K_SECTORS=y
+# CONFIG_SPI_FLASH_DATAFLASH is not set
+# CONFIG_SPI_FLASH_MTD is not set
+
+#
+# UBI support
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+# CONFIG_RTL8211X_PHY_FORCE_MASTER is not set
+CONFIG_NETDEVICES=y
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_DWC_ETH_QOS is not set
+# CONFIG_E1000 is not set
+# CONFIG_ETH_DESIGNWARE is not set
+# CONFIG_ETHOC is not set
+# CONFIG_RTL8139 is not set
+# CONFIG_RTL8169 is not set
+# CONFIG_SUN8I_EMAC is not set
+# CONFIG_XILINX_AXIEMAC is not set
+# CONFIG_XILINX_EMACLITE is not set
+CONFIG_ZYNQ_GEM=y
+# CONFIG_PCI is not set
+# CONFIG_MVEBU_COMPHY_SUPPORT is not set
+
+#
+# Pin controllers
+#
+# CONFIG_PINCTRL is not set
+# CONFIG_SPL_PINCTRL is not set
+
+#
+# Power
+#
+
+#
+# Power Domain Support
+#
+# CONFIG_POWER_DOMAIN is not set
+# CONFIG_DM_PMIC is not set
+# CONFIG_DM_REGULATOR is not set
+# CONFIG_DM_PWM is not set
+# CONFIG_RAM is not set
+
+#
+# Remote Processor drivers
+#
+
+#
+# Reset Controller Support
+#
+# CONFIG_DM_RESET is not set
+
+#
+# Real Time Clock
+#
+# CONFIG_DM_RTC is not set
+
+#
+# Serial drivers
+#
+CONFIG_REQUIRE_SERIAL_CONSOLE=y
+CONFIG_SERIAL_PRESENT=y
+CONFIG_SPL_SERIAL_PRESENT=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+# CONFIG_DEBUG_UART_ALTERA_JTAGUART is not set
+# CONFIG_DEBUG_UART_ALTERA_UART is not set
+# CONFIG_DEBUG_UART_ATMEL is not set
+# CONFIG_DEBUG_UART_NS16550 is not set
+# CONFIG_DEBUG_UART_S5P is not set
+# CONFIG_DEBUG_UART_UARTLITE is not set
+# CONFIG_DEBUG_UART_ARM_DCC is not set
+# CONFIG_DEBUG_MVEBU_A3700_UART is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+# CONFIG_DEBUG_UART_PL010 is not set
+# CONFIG_DEBUG_UART_PL011 is not set
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_SHIFT=0
+# CONFIG_DEBUG_UART_BOARD_INIT is not set
+# CONFIG_DEBUG_UART_ANNOUNCE is not set
+# CONFIG_DEBUG_UART_SKIP_INIT is not set
+# CONFIG_ALTERA_JTAG_UART is not set
+# CONFIG_ALTERA_UART is not set
+# CONFIG_ATMEL_USART is not set
+# CONFIG_FSL_LPUART is not set
+# CONFIG_MVEBU_A3700_UART is not set
+# CONFIG_SYS_NS16550 is not set
+# CONFIG_XILINX_UARTLITE is not set
+# CONFIG_MSM_SERIAL is not set
+# CONFIG_PXA_SERIAL is not set
+
+#
+# Sound support
+#
+# CONFIG_SOUND is not set
+
+#
+# SPI Support
+#
+CONFIG_DM_SPI=y
+# CONFIG_ALTERA_SPI is not set
+# CONFIG_CADENCE_QSPI is not set
+# CONFIG_DESIGNWARE_SPI is not set
+# CONFIG_EXYNOS_SPI is not set
+# CONFIG_FSL_DSPI is not set
+# CONFIG_ICH_SPI is not set
+# CONFIG_MVEBU_A3700_SPI is not set
+# CONFIG_ROCKCHIP_SPI is not set
+# CONFIG_TEGRA114_SPI is not set
+# CONFIG_TEGRA20_SFLASH is not set
+# CONFIG_TEGRA20_SLINK is not set
+# CONFIG_TEGRA210_QSPI is not set
+# CONFIG_XILINX_SPI is not set
+# CONFIG_ZYNQ_SPI is not set
+CONFIG_ZYNQ_QSPI=y
+# CONFIG_OMAP3_SPI is not set
+# CONFIG_FSL_ESPI is not set
+# CONFIG_FSL_QSPI is not set
+# CONFIG_TI_QSPI is not set
+
+#
+# SPMI support
+#
+# CONFIG_SPMI is not set
+
+#
+# System reset device drivers
+#
+# CONFIG_SYSRESET is not set
+# CONFIG_DM_THERMAL is not set
+
+#
+# Timer Support
+#
+# CONFIG_TIMER is not set
+
+#
+# TPM support
+#
+CONFIG_USB=y
+CONFIG_DM_USB=y
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_HOST=y
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI=y
+# CONFIG_USB_EHCI_MSM is not set
+CONFIG_USB_EHCI_ZYNQ=y
+# CONFIG_USB_EHCI_GENERIC is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_DWC3 is not set
+
+#
+# MUSB Controller Driver
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_GADGET is not set
+# CONFIG_USB_MUSB_TI is not set
+
+#
+# ULPI drivers
+#
+CONFIG_USB_ULPI_VIEWPORT=y
+# CONFIG_USB_ULPI_VIEWPORT_OMAP is not set
+CONFIG_USB_ULPI=y
+
+#
+# USB peripherals
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_KEYBOARD is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_BCM_UDC_OTG_PHY is not set
+# CONFIG_USB_GADGET_DWC2_OTG is not set
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_USBNET_DEVADDR="de:ad:be:ef:00:01"
+
+#
+# Graphics support
+#
+# CONFIG_DM_VIDEO is not set
+
+#
+# TrueType Fonts
+#
+# CONFIG_VIDEO_VESA is not set
+# CONFIG_VIDEO_LCD_ANX9804 is not set
+# CONFIG_VIDEO_LCD_SSD2828 is not set
+# CONFIG_VIDEO_MVEBU is not set
+# CONFIG_DISPLAY is not set
+# CONFIG_VIDEO_TEGRA20 is not set
+# CONFIG_VIDEO_BRIDGE is not set
+# CONFIG_LCD is not set
+# CONFIG_PHYS_TO_BUS is not set
+
+#
+# File systems
+#
+
+#
+# Library routines
+#
+# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
+CONFIG_HAVE_PRIVATE_LIBGCC=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_SYS_HZ=1000
+# CONFIG_USE_TINY_PRINTF is not set
+CONFIG_REGEX=y
+CONFIG_LIB_RAND=y
+# CONFIG_CMD_DHRYSTONE is not set
+CONFIG_RSA=y
+# CONFIG_SPL_RSA is not set
+CONFIG_RSA_SOFTWARE_EXP=y
+# CONFIG_TPM is not set
+
+#
+# Encryption Support
+#
+# CONFIG_AES is not set
+
+#
+# Hashing Support
+#
+# CONFIG_SHA1 is not set
+# CONFIG_SHA256 is not set
+# CONFIG_SHA_HW_ACCEL is not set
+
+#
+# Compression Support
+#
+# CONFIG_LZ4 is not set
+# CONFIG_ERRNO_STR is not set
+CONFIG_OF_LIBFDT=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
+CONFIG_SPL_OF_LIBFDT=y
+# CONFIG_FDT_FIXUP_PARTITIONS is not set
+
+#
+# System tables
+#
+CONFIG_GENERATE_SMBIOS_TABLE=y
+CONFIG_SMBIOS_MANUFACTURER="xilinx"
+CONFIG_EFI_LOADER=y
+# CONFIG_UNIT_TEST is not set
diff --git a/board/ciaa/acc/uEnv.txt b/board/ciaa/acc/uEnv.txt
new file mode 100644
index 0000000..1be170d
--- /dev/null
+++ b/board/ciaa/acc/uEnv.txt
@@ -0,0 +1,2 @@
+mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && mmcinfo && load mmc 0 ${loadbit_addr} fpga.bit && fpga loadb 0 ${loadbit_addr} ${filesize}
+sdboot=if mmcinfo; then run mmc_loadbit; echo Copying Linux from SD to RAM... && load mmc 0 ${kernel_load_address} ${kernel_image} && load mmc 0 ${devicetree_load_address} ${devicetree_image} && load mmc 0 ${ramdisk_load_address} ${ramdisk_image} && bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}; fi
diff --git a/board/ciaa/acc/zynq-ciaa_acc.dts b/board/ciaa/acc/zynq-ciaa_acc.dts
new file mode 100644
index 0000000..8454f8e
--- /dev/null
+++ b/board/ciaa/acc/zynq-ciaa_acc.dts
@@ -0,0 +1,147 @@
+/*
+ * Device Tree Generator version: 1.1
+ *
+ *
+ * (C) Copyright 2007-2017 Xilinx, Inc.
+ * (C) Copyright      2017 Martin Ribelotta@emtech
+ * Martin Ribelotta <mribelotta@emtech.com.ar>
+ *
+ * CAUTION: This file is automatically generated by Xilinx.
+ * Version: Today is: Sat Nov 11 16:59:04 2017
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+	compatible = "xlnx,zynq-ciaa_acc", "xlnx,zynq-7000";
+	model = "Xilinx Zynq";
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &qspi;
+		spi1 = &spi1;
+	};
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+        usb_phy0: phy0@e0002000 {
+                compatible = "ulpi-phy";
+                #phy-cells = <0>;
+                reg = <0xe0002000 0x1000>;
+                view-port = <0x0170>;
+                drv-vbus;
+        };
+};
+
+&can0 {
+	status = "okay";
+};
+
+&gem0 {
+	enet-reset = <&gpio0 7 0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+	xlnx,ptp-enet-clock = <0x69f6bcb>;
+};
+
+&gpio0 {
+	emio-gpio-width = <2>;
+	gpio-mask-high = <0x0>;
+	gpio-mask-low = <0x5600>;
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&intc {
+	num_cpus = <2>;
+	num_interrupts = <96>;
+};
+
+&qspi {
+	is-dual = <0>;
+	num-cs = <1>;
+	status = "okay";
+        flash@0 {
+                compatible = "n25q128a11";
+                reg = <0x0>;
+                spi-tx-bus-width = <1>;
+                spi-rx-bus-width = <4>;
+                spi-max-frequency = <50000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@qspi-fsbl-uboot {
+                        label = "qspi-fsbl-uboot";
+                        reg = <0x0 0x100000>;
+                };
+                partition@qspi-linux {
+                        label = "qspi-linux";
+                        reg = <0x100000 0x500000>;
+                };
+                partition@qspi-device-tree {
+                        label = "qspi-device-tree";
+                        reg = <0x600000 0x40000>;
+                };
+                partition@qspi-rootfs {
+                        label = "qspi-rootfs";
+                        reg = <0x640000 0x500000>;
+                };
+                partition@qspi-bitstream {
+                        label = "qspi-bitstream";
+                        reg = <0xC00000 0x400000>;
+                };
+        };
+};
+
+&sdhci0 {
+	status = "okay";
+	xlnx,has-cd = <0x0>;
+	xlnx,has-power = <0x0>;
+	xlnx,has-wp = <0x0>;
+};
+
+&spi1 {
+	is-decoded-cs = <0>;
+	num-cs = <1>;
+	status = "okay";
+};
+
+&uart0 {
+	device_type = "serial";
+	port-number = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	device_type = "serial";
+	port-number = <1>;
+	status = "okay";
+};
+
+&usb0 {
+	phy_type = "ulpi";
+	status = "okay";
+	usb-reset = <&gpio0 0 0>;
+        dr_mode = "host";
+        usb-phy = <&usb_phy0>;
+};
+
+&clkc {
+	fclk-enable = <0x1>;
+	ps-clk-frequency = <33333333>;
+};
diff --git a/configs/zynq_ciaa_acc_defconfig b/configs/zynq_ciaa_acc_defconfig
new file mode 100644
index 0000000..add3143
--- /dev/null
+++ b/configs/zynq_ciaa_acc_defconfig
@@ -0,0 +1,365 @@
+BR2_HAVE_DOT_CONFIG=y
+BR2_HOST_GCC_AT_LEAST_4_5=y
+BR2_HOST_GCC_AT_LEAST_4_6=y
+BR2_HOST_GCC_AT_LEAST_4_7=y
+BR2_HOST_GCC_AT_LEAST_4_8=y
+BR2_HOST_GCC_AT_LEAST_4_9=y
+BR2_HOST_GCC_AT_LEAST_5=y
+BR2_ARCH_HAS_MMU_OPTIONAL=y
+BR2_arm=y
+BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT=y
+BR2_ARCH="arm"
+BR2_ENDIAN="LITTLE"
+BR2_GCC_TARGET_ABI="aapcs-linux"
+BR2_GCC_TARGET_CPU="cortex-a9"
+BR2_GCC_TARGET_FPU="vfpv3-d16"
+BR2_GCC_TARGET_FLOAT_ABI="hard"
+BR2_GCC_TARGET_MODE="arm"
+BR2_BINFMT_SUPPORTS_SHARED=y
+BR2_READELF_ARCH_NAME="ARM"
+BR2_BINFMT_ELF=y
+BR2_ARM_CPU_HAS_NEON=y
+BR2_ARM_CPU_MAYBE_HAS_NEON=y
+BR2_ARM_CPU_MAYBE_HAS_VFPV2=y
+BR2_ARM_CPU_HAS_VFPV2=y
+BR2_ARM_CPU_MAYBE_HAS_VFPV3=y
+BR2_ARM_CPU_HAS_VFPV3=y
+BR2_ARM_CPU_HAS_ARM=y
+BR2_ARM_CPU_HAS_THUMB2=y
+BR2_ARM_CPU_ARMV7A=y
+BR2_cortex_a9=y
+BR2_ARM_ENABLE_NEON=y
+BR2_ARM_ENABLE_VFP=y
+BR2_ARM_EABIHF=y
+BR2_ARM_FPU_VFPV3D16=y
+BR2_ARM_INSTRUCTIONS_ARM=y
+BR2_WGET="wget --passive-ftp -nd -t 3"
+BR2_SVN="svn"
+BR2_BZR="bzr"
+BR2_GIT="git"
+BR2_CVS="cvs"
+BR2_LOCALFILES="cp"
+BR2_SCP="scp"
+BR2_SSH="ssh"
+BR2_HG="hg"
+BR2_ZCAT="gzip -d -c"
+BR2_BZCAT="bzcat"
+BR2_XZCAT="xzcat"
+BR2_LZCAT="lzip -d -c"
+BR2_TAR_OPTIONS=""
+BR2_DEFCONFIG="/home/martin/Proyectos/ciaa/acc/buildroot/configs/zynq_zc706_defconfig"
+BR2_DL_DIR="$(TOPDIR)/dl"
+BR2_HOST_DIR="$(BASE_DIR)/host"
+BR2_PRIMARY_SITE=""
+BR2_BACKUP_SITE="http://sources.buildroot.net"
+BR2_KERNEL_MIRROR="https://cdn.kernel.org/pub"
+BR2_GNU_MIRROR="http://ftpmirror.gnu.org"
+BR2_LUAROCKS_MIRROR="http://rocks.moonscript.org"
+BR2_CPAN_MIRROR="http://cpan.metacpan.org"
+BR2_JLEVEL=0
+BR2_STRIP_strip=y
+BR2_STRIP_EXCLUDE_FILES=""
+BR2_STRIP_EXCLUDE_DIRS=""
+BR2_OPTIMIZE_S=y
+BR2_SSP_NONE=y
+BR2_SHARED_LIBS=y
+BR2_PACKAGE_OVERRIDE_FILE="$(CONFIG_DIR)/local.mk"
+BR2_GLOBAL_PATCH_DIR=""
+BR2_COMPILER_PARANOID_UNSAFE_PATH=y
+BR2_TOOLCHAIN=y
+BR2_TOOLCHAIN_USES_GLIBC=y
+BR2_TOOLCHAIN_EXTERNAL=y
+BR2_TOOLCHAIN_EXTERNAL_LINARO_ARM=y
+BR2_TOOLCHAIN_EXTERNAL_DOWNLOAD=y
+BR2_TOOLCHAIN_EXTERNAL_GLIBC=y
+BR2_PACKAGE_HAS_TOOLCHAIN_EXTERNAL=y
+BR2_PACKAGE_PROVIDES_TOOLCHAIN_EXTERNAL="toolchain-external-linaro-arm"
+BR2_TOOLCHAIN_EXTERNAL_PREFIX="arm-linux-gnueabihf"
+BR2_PACKAGE_HOST_GDB_ARCH_SUPPORTS=y
+BR2_GDB_VERSION="7.11.1"
+BR2_TOOLCHAIN_HAS_NATIVE_RPC=y
+BR2_USE_WCHAR=y
+BR2_ENABLE_LOCALE=y
+BR2_INSTALL_LIBSTDCPP=y
+BR2_TOOLCHAIN_HAS_FORTRAN=y
+BR2_TOOLCHAIN_HAS_THREADS=y
+BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y
+BR2_TOOLCHAIN_HAS_THREADS_NPTL=y
+BR2_TOOLCHAIN_HAS_SHADOW_PASSWORDS=y
+BR2_TOOLCHAIN_HAS_SSP=y
+BR2_TOOLCHAIN_SUPPORTS_PIE=y
+BR2_TOOLCHAIN_HAS_FULL_GETTEXT=y
+BR2_USE_MMU=y
+BR2_TARGET_OPTIMIZATION=""
+BR2_TARGET_LDFLAGS=""
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_0=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_1=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_2=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_3=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_4=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_5=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_6=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_7=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_8=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_9=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_10=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_11=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_12=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_13=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_14=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_15=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_16=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_17=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_18=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_19=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_0=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_1=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_2=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_3=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_4=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_5=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_6=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST="4.6"
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_3=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_4=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_5=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_6=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_7=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_8=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_9=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_5=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_6=y
+BR2_TOOLCHAIN_GCC_AT_LEAST="6"
+BR2_TOOLCHAIN_HAS_MNAN_OPTION=y
+BR2_TOOLCHAIN_HAS_SYNC_1=y
+BR2_TOOLCHAIN_HAS_SYNC_2=y
+BR2_TOOLCHAIN_HAS_SYNC_4=y
+BR2_TOOLCHAIN_ARM_HAS_SYNC_8=y
+BR2_TOOLCHAIN_HAS_SYNC_8=y
+BR2_TOOLCHAIN_HAS_LIBATOMIC=y
+BR2_TOOLCHAIN_HAS_ATOMIC=y
+BR2_ROOTFS_SKELETON_DEFAULT=y
+BR2_ROOTFS_MERGED_USR=y
+BR2_TARGET_GENERIC_HOSTNAME="buildroot"
+BR2_TARGET_GENERIC_ISSUE="Welcome to Buildroot"
+BR2_TARGET_GENERIC_PASSWD_MD5=y
+BR2_TARGET_GENERIC_PASSWD_METHOD="md5"
+BR2_INIT_BUSYBOX=y
+BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS=y
+BR2_ROOTFS_DEVICE_TABLE="system/device_table.txt board/ciaa/acc/device_table.txt"
+BR2_TARGET_ENABLE_ROOT_LOGIN=y
+BR2_TARGET_GENERIC_ROOT_PASSWD=""
+BR2_SYSTEM_BIN_SH_BASH=y
+BR2_SYSTEM_BIN_SH="bash"
+BR2_TARGET_GENERIC_GETTY=y
+BR2_TARGET_GENERIC_GETTY_PORT="ttyPS0"
+BR2_TARGET_GENERIC_GETTY_BAUDRATE_KEEP=y
+BR2_TARGET_GENERIC_GETTY_BAUDRATE="0"
+BR2_TARGET_GENERIC_GETTY_TERM="vt100"
+BR2_TARGET_GENERIC_GETTY_OPTIONS=""
+BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y
+BR2_SYSTEM_DHCP=""
+BR2_ENABLE_LOCALE_PURGE=y
+BR2_ENABLE_LOCALE_WHITELIST="C en_US"
+BR2_GENERATE_LOCALE=""
+BR2_ROOTFS_USERS_TABLES=""
+BR2_ROOTFS_OVERLAY="board/ciaa/acc/overlay_fs"
+BR2_ROOTFS_POST_BUILD_SCRIPT=""
+BR2_ROOTFS_POST_FAKEROOT_SCRIPT=""
+BR2_ROOTFS_POST_IMAGE_SCRIPT="board/ciaa/acc/post-build.sh"
+BR2_ROOTFS_POST_SCRIPT_ARGS=""
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_GIT=y
+BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/Xilinx/linux-xlnx.git"
+BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="xilinx-v2017.3"
+BR2_LINUX_KERNEL_VERSION="xilinx-v2017.3"
+BR2_LINUX_KERNEL_PATCH=""
+BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
+BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="board/ciaa/acc/ciaa_acc_defconfig"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES=""
+BR2_LINUX_KERNEL_UIMAGE=y
+BR2_LINUX_KERNEL_GZIP=y
+BR2_LINUX_KERNEL_UIMAGE_LOADADDR="0x8000"
+BR2_LINUX_KERNEL_DTS_SUPPORT=y
+BR2_LINUX_KERNEL_USE_CUSTOM_DTS=y
+BR2_LINUX_KERNEL_CUSTOM_DTS_PATH="board/ciaa/acc/zynq-ciaa_acc.dts"
+BR2_PACKAGE_BUSYBOX=y
+BR2_PACKAGE_BUSYBOX_CONFIG="board/ciaa/acc/busybox_defconfig"
+BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES=""
+BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
+BR2_PACKAGE_SKELETON=y
+BR2_PACKAGE_HAS_SKELETON=y
+BR2_PACKAGE_PROVIDES_SKELETON="skeleton-init-sysv"
+BR2_PACKAGE_SKELETON_INIT_COMMON=y
+BR2_PACKAGE_SKELETON_INIT_SYSV=y
+BR2_PACKAGE_FFMPEG_ARCH_SUPPORTS=y
+BR2_PACKAGE_KODI_ARCH_SUPPORTS=y
+BR2_PACKAGE_MPLAYER_ARCH_SUPPORTS=y
+BR2_PACKAGE_PULSEAUDIO_HAS_ATOMIC=y
+BR2_PACKAGE_GDB_ARCH_SUPPORTS=y
+BR2_PACKAGE_GDB=y
+BR2_PACKAGE_GDB_SERVER=y
+BR2_PACKAGE_GDB_DEBUGGER=y
+BR2_PACKAGE_GOOGLE_BREAKPAD_ARCH_SUPPORTS=y
+BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y
+BR2_PACKAGE_LTRACE=y
+BR2_PACKAGE_OPROFILE_ARCH_SUPPORTS=y
+BR2_PACKAGE_SPIDEV_TEST=y
+BR2_PACKAGE_STRACE=y
+BR2_PACKAGE_TRINITY_ARCH_SUPPORTS=y
+BR2_PACKAGE_VALGRIND_ARCH_SUPPORTS=y
+BR2_PACKAGE_CMAKE_ARCH_SUPPORTS=y
+BR2_PACKAGE_JO=y
+BR2_PACKAGE_JQ=y
+BR2_PACKAGE_DOSFSTOOLS=y
+BR2_PACKAGE_DOSFSTOOLS_FATLABEL=y
+BR2_PACKAGE_DOSFSTOOLS_FSCK_FAT=y
+BR2_PACKAGE_DOSFSTOOLS_MKFS_FAT=y
+BR2_PACKAGE_E2FSPROGS=y
+BR2_PACKAGE_E2FSPROGS_FSCK=y
+BR2_PACKAGE_MMC_UTILS=y
+BR2_PACKAGE_MTD=y
+BR2_PACKAGE_MTD_JFFS_UTILS=y
+BR2_PACKAGE_MTD_FLASHCP=y
+BR2_PACKAGE_MTD_FLASH_ERASE=y
+BR2_PACKAGE_MTD_FLASH_LOCK=y
+BR2_PACKAGE_MTD_FLASH_UNLOCK=y
+BR2_PACKAGE_MTD_MKFSJFFS2=y
+BR2_PACKAGE_MTD_MTD_DEBUG=y
+BR2_PACKAGE_MTD_NANDDUMP=y
+BR2_PACKAGE_MTD_NANDTEST=y
+BR2_PACKAGE_MTD_NANDWRITE=y
+BR2_PACKAGE_MTD_MTDINFO=y
+BR2_PACKAGE_MTD_UBIATTACH=y
+BR2_PACKAGE_MTD_UBICRC32=y
+BR2_PACKAGE_MTD_UBIDETACH=y
+BR2_PACKAGE_MTD_UBIFORMAT=y
+BR2_PACKAGE_MTD_UBIMKVOL=y
+BR2_PACKAGE_MTD_UBINFO=y
+BR2_PACKAGE_MTD_UBINIZE=y
+BR2_PACKAGE_MTD_UBIRENAME=y
+BR2_PACKAGE_MTD_UBIRMVOL=y
+BR2_PACKAGE_MTD_UBIRSVOL=y
+BR2_PACKAGE_MTD_UBIUPDATEVOL=y
+BR2_PACKAGE_MTD_UBIBLOCK=y
+BR2_PACKAGE_MTOOLS=y
+BR2_PACKAGE_QT5_JSCORE_AVAILABLE=y
+BR2_PACKAGE_LM_SENSORS=y
+BR2_PACKAGE_LM_SENSORS_SENSORS=y
+BR2_PACKAGE_LM_SENSORS_FANCONTROL=y
+BR2_PACKAGE_LM_SENSORS_PWMCONFIG=y
+BR2_PACKAGE_LSHW=y
+BR2_PACKAGE_LSUIO=y
+BR2_PACKAGE_MEMTOOL=y
+BR2_PACKAGE_SPI_TOOLS=y
+BR2_PACKAGE_ERLANG_ARCH_SUPPORTS=y
+BR2_PACKAGE_GAUCHE_ARCH_SUPPORTS=y
+BR2_PACKAGE_JIMTCL=y
+BR2_PACKAGE_LUAJIT_ARCH_SUPPORTS=y
+BR2_PACKAGE_MICROPYTHON=y
+BR2_PACKAGE_MICROPYTHON_LIB=y
+BR2_PACKAGE_MONO_ARCH_SUPPORTS=y
+BR2_PACKAGE_NODEJS_ARCH_SUPPORTS=y
+BR2_PACKAGE_FDK_AAC_ARCH_SUPPORTS=y
+BR2_PACKAGE_OPENAL_ARCH_SUPPORTS=y
+BR2_PACKAGE_WEBRTC_AUDIO_PROCESSING_ARCH_SUPPORTS=y
+BR2_PACKAGE_LZO=y
+BR2_PACKAGE_ZLIB=y
+BR2_PACKAGE_BOTAN_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBGPG_ERROR_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBGPG_ERROR_SYSCFG="arm-unknown-linux-gnueabi"
+BR2_PACKAGE_PROVIDES_HOST_OPENSSL="host-libopenssl"
+BR2_PACKAGE_MONGODB_ARCH_SUPPORTS=y
+BR2_PACKAGE_JPEG_SIMD_SUPPORT=y
+BR2_PACKAGE_WEBKITGTK_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBAIO_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBOPENH264_ARCH_SUPPORTS=y
+BR2_PACKAGE_C_ARES=y
+BR2_PACKAGE_CANFESTIVAL_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBHTTPPARSER=y
+BR2_PACKAGE_CLASSPATH_ARCH_SUPPORTS=y
+BR2_PACKAGE_ELFUTILS=y
+BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBATOMIC_OPS_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBBSD_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBFFI=y
+BR2_PACKAGE_LIBNSPR_ARCH_SUPPORT=y
+BR2_PACKAGE_LIBSECCOMP_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBSIGSEGV_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBUNWIND_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBURCU_ARCH_SUPPORTS=y
+BR2_PACKAGE_LIBUV=y
+BR2_PACKAGE_OPENBLAS_DEFAULT_TARGET="CORTEXA9"
+BR2_PACKAGE_OPENBLAS_ARCH_SUPPORTS=y
+BR2_PACKAGE_PROTOBUF_ARCH_SUPPORTS=y
+BR2_PACKAGE_NCURSES=y
+BR2_PACKAGE_PCRE=y
+BR2_PACKAGE_READLINE=y
+BR2_PACKAGE_QEMU_ARCH_SUPPORTS_TARGET=y
+BR2_PACKAGE_CAN_UTILS=y
+BR2_PACKAGE_DROPBEAR=y
+BR2_PACKAGE_DROPBEAR_CLIENT=y
+BR2_PACKAGE_DROPBEAR_SMALL=y
+BR2_PACKAGE_ETHTOOL=y
+BR2_PACKAGE_ETHTOOL_PRETTY_PRINT=y
+BR2_PACKAGE_IFUPDOWN_SCRIPTS=y
+BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
+BR2_PACKAGE_MOSQUITTO=y
+BR2_PACKAGE_NETCAT=y
+BR2_PACKAGE_XENOMAI_ARCH_SUPPORTS=y
+BR2_PACKAGE_BASH=y
+BR2_PACKAGE_SCREEN=y
+BR2_PACKAGE_AUDIT_ARCH_SUPPORTS=y
+BR2_PACKAGE_EFIVAR_ARCH_SUPPORTS=y
+BR2_PACKAGE_HTOP=y
+BR2_PACKAGE_INITSCRIPTS=y
+BR2_PACKAGE_SYSTEMD_ARCH_SUPPORTS=y
+BR2_PACKAGE_UTIL_LINUX=y
+BR2_PACKAGE_UTIL_LINUX_LIBBLKID=y
+BR2_PACKAGE_UTIL_LINUX_LIBUUID=y
+BR2_PACKAGE_XVISOR_ARCH_SUPPORTS=y
+BR2_PACKAGE_NANO=y
+BR2_PACKAGE_NANO_TINY=y
+BR2_TARGET_ROOTFS_CPIO=y
+BR2_TARGET_ROOTFS_CPIO_GZIP=y
+BR2_TARGET_ROOTFS_CPIO_UIMAGE=y
+BR2_TARGET_ROOTFS_TAR=y
+BR2_TARGET_ROOTFS_TAR_NONE=y
+BR2_TARGET_ROOTFS_TAR_OPTIONS=""
+BR2_TARGET_UBOOT=y
+BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
+BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
+BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="https://github.com/Xilinx/u-boot-xlnx/archive/xilinx-v2017.3.tar.gz"
+BR2_TARGET_UBOOT_VERSION="custom"
+BR2_TARGET_UBOOT_PATCH="board/ciaa/acc/u-boot.patch"
+BR2_TARGET_UBOOT_USE_DEFCONFIG=y
+BR2_TARGET_UBOOT_BOARD_DEFCONFIG="zynq_ciaa_acc"
+BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES=""
+BR2_TARGET_UBOOT_NEEDS_DTC=y
+BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
+BR2_TARGET_UBOOT_FORMAT_BIN=y
+BR2_TARGET_UBOOT_FORMAT_DTB_IMG=y
+BR2_TARGET_UBOOT_FORMAT_IMG=y
+BR2_TARGET_UBOOT_SPL=y
+BR2_TARGET_UBOOT_SPL_NAME="spl/u-boot-spl.bin"
+BR2_TARGET_UBOOT_ZYNQ_IMAGE=y
+BR2_TARGET_UBOOT_CUSTOM_DTS_PATH=""
+BR2_PACKAGE_HOST_DTC=y
+BR2_PACKAGE_HOST_GO_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_GO_CGO_LINKING_SUPPORTS=y
+BR2_PACKAGE_HOST_GO_BOOTSTRAP_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_GOOGLE_BREAKPAD_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_PATCHELF=y
+BR2_PACKAGE_HOST_TI_CGT_PRU_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_UBOOT_TOOLS=y
+BR2_XTENSA_OVERLAY_DIR=""
+BR2_XTENSA_CUSTOM_NAME=""
+BR2_TARGET_ROOTFS_EXT2_BLOCKS=0
+BR2_TARGET_ROOTFS_EXT2_EXTRA_INODES=0
+BR2_TARGET_ROOTFS_EXT2_EXTRA_BLOCKS=0
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR=""
+BR2_PACKAGE_TZDATA_ZONELIST=""
+BR2_TARGET_UBOOT_CUSTOM_GIT_REPO_URL=""
+BR2_TARGET_UBOOT_CUSTOM_GIT_VERSION=""
+BR2_LINUX_KERNEL_CUSTOM_GIT_REPO_URL=""
+BR2_LINUX_KERNEL_CUSTOM_GIT_VERSION=""