Files

.github
rtl
- arbiter.v
- axi_adapter.v
- axi_adapter_rd.v
- axi_adapter_wr.v
- axi_axil_adapter.v
- axi_axil_adapter_rd.v
- axi_axil_adapter_wr.v
- axi_cdma.v
- axi_cdma_desc_mux.v
- axi_crossbar.v
- axi_crossbar_addr.v
- axi_crossbar_rd.v
- axi_crossbar_wr.v
- axi_crossbar_wrap.py
- axi_dma.v
- axi_dma_desc_mux.v
- axi_dma_rd.v
- axi_dma_wr.v
- axi_dp_ram.v
- axi_fifo.v
- axi_fifo_rd.v
- axi_fifo_wr.v
- axi_interconnect.v
- axi_interconnect_wrap.py
- axi_ram.v
- axi_ram_rd_if.v
- axi_ram_wr_if.v
- axi_ram_wr_rd_if.v
- axi_register.v
- axi_register_rd.v
- axi_register_wr.v
- axi_vfifo.v
- axi_vfifo_dec.v
- axi_vfifo_enc.v
- axi_vfifo_raw.v
- axi_vfifo_raw_rd.v
- axi_vfifo_raw_wr.v
- axil_adapter.v
- axil_adapter_rd.v
- axil_adapter_wr.v
- axil_cdc.v
- axil_cdc_rd.v
- axil_cdc_wr.v
- axil_crossbar.v
- axil_crossbar_addr.v
- axil_crossbar_rd.v
- axil_crossbar_wr.v
- axil_crossbar_wrap.py
- axil_dp_ram.v
- axil_interconnect.v
- axil_interconnect_wrap.py
- axil_ram.v
- axil_reg_if.v
- axil_reg_if_rd.v
- axil_reg_if_wr.v
- axil_register.v
- axil_register_rd.v
- axil_register_wr.v
- priority_encoder.v
syn
tb
.gitignore
.test_durations
AUTHORS
COPYING
README.md
tox.ini

rtl

alexforencich

Fix reset CDC in AXI VFIFO

Mar 30, 2023

38915fb · Mar 30, 2023

History

This branch is 1 commit behind alexforencich/verilog-axi:master.

Name	Name	Last commit message	Last commit date
parent directory ..
arbiter.v	arbiter.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_adapter.v	axi_adapter.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_adapter_rd.v	axi_adapter_rd.v	Fix unaligned operation handling in AXI adapter	Jan 26, 2023
axi_adapter_wr.v	axi_adapter_wr.v	Fix unaligned operation handling in AXI adapter	Jan 26, 2023
axi_axil_adapter.v	axi_axil_adapter.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_axil_adapter_rd.v	axi_axil_adapter_rd.v	Fix unaligned operation handling in AXI to AXIL adapter	Jan 26, 2023
axi_axil_adapter_wr.v	axi_axil_adapter_wr.v	Fix unaligned operation handling in AXI to AXIL adapter	Jan 26, 2023
axi_cdma.v	axi_cdma.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_cdma_desc_mux.v	axi_cdma_desc_mux.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_crossbar.v	axi_crossbar.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_crossbar_addr.v	axi_crossbar_addr.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_crossbar_rd.v	axi_crossbar_rd.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_crossbar_wr.v	axi_crossbar_wr.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_crossbar_wrap.py	axi_crossbar_wrap.py	Add default_nettype none and resetall directives	Oct 20, 2021
axi_dma.v	axi_dma.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_dma_desc_mux.v	axi_dma_desc_mux.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_dma_rd.v	axi_dma_rd.v	Add attributes to RAMs for proper synthesis in Quartus	Nov 5, 2021
axi_dma_wr.v	axi_dma_wr.v	Add attributes to RAMs for proper synthesis in Quartus	Nov 5, 2021
axi_dp_ram.v	axi_dp_ram.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_fifo.v	axi_fifo.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_fifo_rd.v	axi_fifo_rd.v	Add attributes to RAMs for proper synthesis in Quartus	Nov 5, 2021
axi_fifo_wr.v	axi_fifo_wr.v	Add attributes to RAMs for proper synthesis in Quartus	Nov 5, 2021
axi_interconnect.v	axi_interconnect.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_interconnect_wrap.py	axi_interconnect_wrap.py	Add default_nettype none and resetall directives	Oct 20, 2021
axi_ram.v	axi_ram.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_ram_rd_if.v	axi_ram_rd_if.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_ram_wr_if.v	axi_ram_wr_if.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_ram_wr_rd_if.v	axi_ram_wr_rd_if.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_register.v	axi_register.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_register_rd.v	axi_register_rd.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_register_wr.v	axi_register_wr.v	Add default_nettype none and resetall directives	Oct 20, 2021
axi_vfifo.v	axi_vfifo.v	Fix reset CDC in AXI VFIFO	Mar 30, 2023
axi_vfifo_dec.v	axi_vfifo_dec.v	Add AXI virtual FIFO	Mar 29, 2023
axi_vfifo_enc.v	axi_vfifo_enc.v	Add AXI virtual FIFO	Mar 29, 2023
axi_vfifo_raw.v	axi_vfifo_raw.v	Add AXI virtual FIFO	Mar 29, 2023
axi_vfifo_raw_rd.v	axi_vfifo_raw_rd.v	Add AXI virtual FIFO	Mar 29, 2023
axi_vfifo_raw_wr.v	axi_vfifo_raw_wr.v	Add AXI virtual FIFO	Mar 29, 2023
axil_adapter.v	axil_adapter.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_adapter_rd.v	axil_adapter_rd.v	Improve unaligned operation handling in AXIL adapter	Jan 26, 2023
axil_adapter_wr.v	axil_adapter_wr.v	Improve unaligned operation handling in AXIL adapter	Jan 26, 2023
axil_cdc.v	axil_cdc.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_cdc_rd.v	axil_cdc_rd.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_cdc_wr.v	axil_cdc_wr.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_crossbar.v	axil_crossbar.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_crossbar_addr.v	axil_crossbar_addr.v	Fix min address width checks in AXI lite components	Feb 13, 2023
axil_crossbar_rd.v	axil_crossbar_rd.v	Fix min address width checks in AXI lite components	Feb 13, 2023
axil_crossbar_wr.v	axil_crossbar_wr.v	Fix min address width checks in AXI lite components	Feb 13, 2023
axil_crossbar_wrap.py	axil_crossbar_wrap.py	Add default_nettype none and resetall directives	Oct 20, 2021
axil_dp_ram.v	axil_dp_ram.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_interconnect.v	axil_interconnect.v	Fix min address width checks in AXI lite components	Feb 13, 2023
axil_interconnect_wrap.py	axil_interconnect_wrap.py	Add default_nettype none and resetall directives	Oct 20, 2021
axil_ram.v	axil_ram.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_reg_if.v	axil_reg_if.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_reg_if_rd.v	axil_reg_if_rd.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_reg_if_wr.v	axil_reg_if_wr.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_register.v	axil_register.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_register_rd.v	axil_register_rd.v	Add default_nettype none and resetall directives	Oct 20, 2021
axil_register_wr.v	axil_register_wr.v	Fix typos	Nov 8, 2021
priority_encoder.v	priority_encoder.v	Add default_nettype none and resetall directives	Oct 20, 2021

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