-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy pathtb.v
133 lines (118 loc) · 4.2 KB
/
tb.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
`include "spi_defines.v"
module tb;
reg wb_clk_in, wb_rst_in;
wire wb_we_in, wb_stb_in, wb_cyc_in, miso;
wire [4:0]wb_adr_in;
wire [31:0]wb_dat_in;
wire [3:0]wb_sel_in;
wire [31:0]wb_dat_o;
wire wb_ack_out, wb_int_o, sclk_out, mosi;
wire [`SPI_SS_NB-1:0]ss_pad_o;
parameter T = 20;
wishbone_master MASTER(wb_clk_in,
wb_rst_in,
wb_ack_out,
wb_err_in,
wb_dat_o,
wb_adr_in,
wb_cyc_in,
wb_stb_in,
wb_we_in,
wb_dat_in,
wb_sel_in);
spi_top SPI_CORE(wb_clk_in,
wb_rst_in,
wb_adr_in,
wb_dat_o,
wb_sel_in,
wb_we_in,
wb_stb_in,
wb_cyc_in,
wb_ack_out,
wb_int_o,
wb_dat_in,
ss_pad_o,
sclk_out,
mosi,
miso);
spi_slave SLAVE(sclk_out,
mosi,
ss_pad_o,
miso);
initial
begin
wb_clk_in = 1'b0;
forever
#(T/2) wb_clk_in = ~wb_clk_in;
end
task rst();
begin
wb_rst_in = 1'b1;
#13;
wb_rst_in = 1'b0;
end
endtask
//tx_neg=1, rx_neg=0, LSB=1, char_len=4
/*initial
begin
rst;
//initialize the WISHBONE output signals
MASTER.initialize;
//configure control register with go_busy being low
MASTER.single_write(5'h10,32'h0000_3c04,4'b1111);
//configure divider with go_busy being low
MASTER.single_write(5'h14,32'h0000_0004,4'b1111);
//configure slave register with go_busy being low
MASTER.single_write(5'h18,32'h0000_0001,4'b1111);
//configure tx register with go_busy being low and processor is sending 4 bits
MASTER.single_write(5'h00,32'h0000_236f,4'b1111);
//configure control register with go_busy beingg high
MASTER.single_write(5'h10,32'h0000_3d04,4'b1111);
repeat(100)
@(negedge wb_clk_in);
$finish;
#10000 $finish;
end*/
//tx_neg=1, rx__neg=0, LSB=0, char_len=4
/*initial
begin
rst;
//initialize the WISHBONE output signals
MASTER.initialize;
//configure control register with go_busy being low
MASTER.single_write(5'h10,32'h0000_3404,4'b1111);
//configure divider with go_busy being low
MASTER.single_write(5'h14,32'h0000_0004,4'b1111);
//configure slave register with go_busy being low
MASTER.single_write(5'h18,32'h0000_0001,4'b1111);
//configure tx register with go_busy being low and processor is sending 4 bits
MASTER.single_write(5'h00,32'h0000_236f,4'b1111);
//configure control register with go_busy beingg high
MASTER.single_write(5'h10,32'h0000_3504,4'b1111);
repeat(100)
@(negedge wb_clk_in);
$finish;
#10000 $finish;
end*/
//tx_neg=0, rx__neg=1, LSB=1, char_len=4
initial
begin
rst;
//initialize the WISHBONE output signals
MASTER.initialize;
//configure control register with go_busy being low
MASTER.single_write(5'h10,32'h0000_3A04,4'b1111);
//configure divider with go_busy being low
MASTER.single_write(5'h14,32'h0000_0004,4'b1111);
//configure slave register with go_busy being low
MASTER.single_write(5'h18,32'h0000_0001,4'b1111);
//configure tx register with go_busy being low and processor is sending 4 bits
MASTER.single_write(5'h00,32'h0000_236f,4'b1111);
//configure control register with go_busy beingg high
MASTER.single_write(5'h10,32'h0000_3B04,4'b1111);
repeat(100)
@(negedge wb_clk_in);
$finish;
#10000 $finish;
end
endmodule