bus bridge to AXI

[samsoniuk]

Although the DarkRISCV native data bus is very simple, flexible and faster (although not faster and flexible at the same time), the standard bus for FPGAs appears to be converging to the AXI bus... so a bus bridge between the DarkRISCV bus and the AXI bus may increase the possibilities to interconnect the DarkRISCV with the available FPGA IPs, such as DDR controllers, 10GbE ethernet interfaces, etc.