- Circuit: 8-bit unsigned multipliers
- Selection criteria: pareto optimal sub-set wrt. WCED [%] and # LUTs parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | PowerW | Delayns | LUTs | Download |
|---|---|---|---|---|---|---|---|---|---|
| mul8u_1JD3 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | 1.3 | 12 | 74 | [Verilog] [VerilogPDK45] [C] |
| mul8u_78R | 0.0085 | 0.032 | 75.00 | 0.32 | 55 | 1.3 | 12 | 72 | [Verilog] [VerilogPDK45] [C] |
| mul8u_1G9M | 0.036 | 0.095 | 98.49 | 1.76 | 846 | 1.1 | 11 | 65 | [Verilog] [VerilogPDK45] [C] |
| mul8u_6LH | 0.051 | 0.25 | 84.76 | 1.28 | 2005 | 1.0 | 11 | 63 | [Verilog] [VerilogPDK45] [C] |
| mul8u_GT4 | 0.16 | 0.73 | 96.25 | 3.68 | 17466 | 0.85 | 9.7 | 48 | [Verilog] [VerilogPDK45] [C] |
| mul8u_176X | 0.47 | 2.06 | 98.93 | 9.37 | 145132 | 0.64 | 10 | 34 | [Verilog] [VerilogPDK45] [C] |
| mul8u_7T1 | 1.17 | 5.18 | 99.17 | 18.02 | 903134 | 0.42 | 8.4 | 16 | [Verilog] [VerilogPDK45] [C] |
| mul8u_17L5 | 3.75 | 13.58 | 99.21 | 40.54 | 92693.902e2 | 0.27 | 6.2 | 4.0 | [Verilog] [VerilogPDK45] [C] |
| mul8u_17A6 | 7.51 | 25.01 | 99.22 | 59.60 | 38114.505e3 | 0.26 | 6.2 | 1.0 | [Verilog] [VerilogPDK45] [C] |
| mul8u_199Z | 24.81 | 99.22 | 99.22 | 100.00 | 47164.981e4 | 0.24 | 0 | 0 | [Verilog] [VerilogPDK45] [C] |
PRABAKARAN B. S., MRAZEK V., VASICEK Z., SEKANINA L., SHAFIQUE M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020.