From c4b99a80bdd37de3279cec9c62fc725ebb990624 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 15:20:19 +0200 Subject: [PATCH 01/41] phy/xilinx_us(p): Remove debug logic and try to uniformize. --- .../phy/xilinx_us_gen3_x4/pcie_us_support.v | 207 +----------------- .../phy/xilinx_us_gen3_x8/pcie_us_support.v | 24 +- .../xilinx_usp_gen3_x16/pcie_usp_support.v | 25 +-- .../phy/xilinx_usp_gen3_x4/pcie_usp_support.v | 28 +-- .../phy/xilinx_usp_gen3_x8/pcie_usp_support.v | 22 +- 5 files changed, 29 insertions(+), 277 deletions(-) diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v index 7c102235..ee6b8a54 100644 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v @@ -59,86 +59,6 @@ // Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital -module axis_check_cmp - ( - input clk, - input rst, - - input i_vld, - input i_hdr3byte, - input [3:0] i_keep, - input i_sop, - input i_eop, - input [9:0] i_length, - - output reg o_err - ); - - reg [14:0] counter; - reg [9:0] length; - always @(posedge clk) - if (rst) length <= 10'd0; - else if (i_vld & i_sop) length <= i_length; - - wire [2:0] keep_sum = i_keep[3] + i_keep[2] + i_keep[1] + i_keep[0]; - - wire [14:0] crrcounter = i_sop ? i_keep[3] : (counter + keep_sum); - always @(posedge clk) - if (rst) counter <= 15'd0; - else if (i_vld) - begin - if (i_eop) counter <= 15'd0; - else counter <= crrcounter; - end - - - always @(posedge clk) - if (rst) o_err <= 1'd0; - else if (i_vld && i_eop) o_err <= i_sop ? (crrcounter != i_length) : (crrcounter != length); - -endmodule - -module axis_check_req - ( - input clk, - input rst, - - input i_vld, - input i_read, - input i_hdr3byte, - input [3:0] i_keep, - input i_eop, - input i_sop, - input [9:0] i_length, - - output reg o_err - ); - - reg [14:0] counter; - - reg [9:0] length; - always @(posedge clk) - if (rst) length <= 10'd0; - else if (i_vld & i_sop) length <= i_length; - - wire [2:0] keep_sum = i_keep[3] + i_keep[2] + i_keep[1] + i_keep[0]; - - wire [14:0] crrcounter = i_sop ? (i_hdr3byte ? i_keep[3] : 15'd0) : (counter + keep_sum); - always @(posedge clk) - if (rst) counter <= 15'd0; - else if (i_vld) - begin - if (i_eop) counter <= 15'd0; - else counter <= crrcounter; - end - - - always @(posedge clk) - if (rst) o_err <= 1'd0; - else if (i_vld && i_eop) o_err <= i_sop ? (i_read ? 1'b0 : (crrcounter != i_length)) : (crrcounter != length); - -endmodule - //----------------------------------------------------------------------------------------------------------------// // AXIS FIFO // //----------------------------------------------------------------------------------------------------------------// @@ -439,10 +359,7 @@ module pcie_support # ( output [11:0] cfg_interrupt_msi_mmenable, output cfg_interrupt_msi_mask_update, output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable, - - //Debug - output [15:0] debug //for cmp_source {error_code[3:], error_trigger} + output [7:0] cfg_interrupt_msi_vf_enable ); //----------------------------------------------------------------------------------------------------------------// @@ -571,7 +488,6 @@ module pcie_support # ( //Generae ready for TLP assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; @@ -628,34 +544,6 @@ module pcie_support # ( assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; - //Debug counter - reg [31:0] rqcnt_rd; - always @(posedge user_clk_out) - if (user_reset_out) rqcnt_rd <= 16'b0; - else if (s_axis_rq_tvalid_a && s_axis_rq_tready_a[0] && s_axis_rq_tfirst && s_axis_rq_read) rqcnt_rd <= rqcnt_rd + s_axis_rq_dwlen; - - reg [15:0] rqcnt_wr; - always @(posedge user_clk_out) - if (user_reset_out) rqcnt_wr <= 16'b0; - else if (s_axis_rq_tvalid_a && s_axis_rq_tready_a[0] && s_axis_rq_tfirst && (!s_axis_rq_read)) rqcnt_wr <= rqcnt_wr + 1; - - wire rq_err; - axis_check_req rq_check - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_rq_tvalid_a && s_axis_rq_tready_a[0]), - .i_read (s_axis_rq_read), - .i_hdr3byte (1'b0), - .i_keep (s_axis_rq_tkeep_a), - .i_eop (s_axis_rq_tlast_a), - .i_sop (s_axis_rq_tfirst), - .i_length (s_axis_rq_dwlen), - - .o_err (rq_err) - ); - //----------------------------------------------------- RC AXIS --------------------------------------------------// wire m_axis_rc_tvalid_a; wire m_axis_rc_tready_a; @@ -734,32 +622,6 @@ module pcie_support # ( m_axis_rc_tuser_a[42] //ECRC mapped to discontinue }; - wire [3:0] rc_errcode = m_axis_rc_tdata_a[15:12]; - wire rc_status_err = ((m_axis_rc_cmpstatus != 3'b0) | (rc_errcode != 4'b0)) && m_axis_rc_tvalid && m_axis_rc_tready && m_axis_rc_sop; - - //Debug counter - reg [31:0] rccnt; - always @(posedge user_clk_out) - if (user_reset_out) rccnt <= 32'b0; - else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a && m_axis_rc_sop) rccnt <= rccnt + m_axis_rc_dwlen; - - wire rc_err; - axis_check_cmp rc_check - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (m_axis_rc_tvalid && m_axis_rc_tready), - .i_hdr3byte (1'b1), - .i_keep ({m_axis_rc_tkeep[12],m_axis_rc_tkeep[8], - m_axis_rc_tkeep[4], m_axis_rc_tkeep[0]}), - .i_eop (m_axis_rc_tlast), - .i_sop (m_axis_rc_sop), - .i_length (m_axis_rc_dwlen), - - .o_err (rc_err) - ); - //----------------------------------------------------- CQ AXIS --------------------------------------------------// wire m_axis_cq_tvalid_a; wire m_axis_cq_tready_a; @@ -878,6 +740,7 @@ module pcie_support # ( wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[127:32]}; + assign m_axis_cq_tkeep = m_axis_cq_read_l ? 16'h0FFF : m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[15:4]} : 16'hFFFF; @@ -891,34 +754,6 @@ module pcie_support # ( m_axis_cq_ecrc //ECRC mapped to discontinue }; - //Debug counter - reg [31:0] cqcnt_rd; - always @(posedge user_clk_out) - if (user_reset_out) cqcnt_rd <= 16'b0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_sop && m_axis_cq_read) cqcnt_rd <= cqcnt_rd + m_axis_cq_dwlen; - - reg [15:0] cqcnt_wr; - always @(posedge user_clk_out) - if (user_reset_out) cqcnt_wr <= 16'b0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_sop && (!m_axis_cq_read)) cqcnt_wr <= cqcnt_wr + 1; - - wire cq_err; - axis_check_req cq_check - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (m_axis_cq_tvalid && m_axis_cq_tready), - .i_read (m_axis_cq_read_l), - .i_hdr3byte (1'b1), - .i_keep ({m_axis_cq_tkeep[12], m_axis_cq_tkeep[8], m_axis_cq_tkeep[4], m_axis_cq_tkeep[0]}), - .i_eop (m_axis_cq_tlast), - .i_sop (m_axis_cq_second | m_axis_cq_read_l), - .i_length (m_axis_cq_header[9:0]), - - .o_err (cq_err) - ); - //----------------------------------------------------- CC AXIS --------------------------------------------------// wire s_axis_cc_tready_ff, s_axis_cc_tvalid_ff, @@ -1009,41 +844,9 @@ module pcie_support # ( wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} - wire cc_status_err = (s_axis_cc_cmpstatus != 3'b0) && s_axis_cc_tvalid_ff && s_axis_cc_tready_ff && s_axis_cc_tfirst; - - reg [31:0] cccnt; - always @(posedge user_clk_out) - if (user_reset_out) cccnt <= 16'b0; - else if (s_axis_cc_tvalid_a && s_axis_cc_tready_a[0] && s_axis_cc_tfirst) cccnt <= cccnt + s_axis_cc_dwordcnt; - - - wire cc_err; - axis_check_cmp cc_check - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_cc_tvalid_a && s_axis_cc_tready_a[0]), - .i_hdr3byte (1'b1), - .i_keep (s_axis_cc_tkeep_a), - .i_eop (s_axis_cc_tlast_a), - .i_sop (s_axis_cc_tfirst), - .i_length (s_axis_cc_dwordcnt), - - .o_err (cc_err) - ); - - //----------------------------------------------------------------------------------------------------------------// - //Debug only - - //Condition trigger - wire cmperr_trigger = (m_axis_rc_tdata_a[15:12] != 4'b0) & m_axis_rc_tvalid_a & m_axis_rc_tready_a & m_axis_rc_sop; - //assign debug = {m_axis_rc_tdata_a[15:12], cmperr_trigger}; - assign debug = {rq_err, cq_err, rc_err, cc_err}; - - //----------------------------------------------------------------------------------------------------------------// - // MSI Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// + //---------------------------------------------------------------------------------------------------------------// + // MSI Adaptation Logic // + //---------------------------------------------------------------------------------------------------------------// wire [3:0] cfg_interrupt_msi_enable_x4; assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; diff --git a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v index e541e8a2..23160d70 100644 --- a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v @@ -57,6 +57,8 @@ `timescale 1ns / 1ps +// Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital + //----------------------------------------------------------------------------------------------------------------// // AXIS FIFO // //----------------------------------------------------------------------------------------------------------------// @@ -357,10 +359,7 @@ module pcie_support # ( output [11:0] cfg_interrupt_msi_mmenable, output cfg_interrupt_msi_mask_update, output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable, - - //Debug - output [7:0] debug //for cmp_source {error_code[3:], error_trigger} + output [7:0] cfg_interrupt_msi_vf_enable ); //----------------------------------------------------------------------------------------------------------------// @@ -476,8 +475,6 @@ module pcie_support # ( if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); - wire [10:0] s_axis_rq_dwlen; - always @(posedge user_clk_out) if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; @@ -494,7 +491,7 @@ module pcie_support # ( assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - assign s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request @@ -826,16 +823,9 @@ module pcie_support # ( wire [7:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} - //----------------------------------------------------------------------------------------------------------------// - //Debug only - - //Condition trigger - wire cmperr_trigger = (m_axis_rc_tdata_a[15:12] != 4'b0) & m_axis_rc_tvalid_a & m_axis_rc_tready_a & m_axis_rc_sop; - assign debug = {m_axis_rc_tdata_a[15:12], cmperr_trigger}; - - //----------------------------------------------------------------------------------------------------------------// - // MSI Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// + //---------------------------------------------------------------------------------------------------------------// + // MSI Adaptation Logic // + //---------------------------------------------------------------------------------------------------------------// wire [3:0] cfg_interrupt_msi_enable_x4; assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; diff --git a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v index 720c9cb8..79689f14 100644 --- a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v @@ -57,6 +57,8 @@ `timescale 1ns / 1ps +// Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital + //----------------------------------------------------------------------------------------------------------------// // AXIS FIFO // //----------------------------------------------------------------------------------------------------------------// @@ -175,7 +177,7 @@ endmodule (* DowngradeIPIdentifiedWarnings = "yes" *) module pcie_support # ( parameter LINK_CAP_MAX_LINK_WIDTH = 4, // PCIe Lane Width - parameter C_DATA_WIDTH = 128, // AXI interface data width + parameter C_DATA_WIDTH = 512, // AXI interface data width parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device parameter PCIE_USE_MODE = "2.0" // PCIe use mode @@ -357,10 +359,7 @@ module pcie_support # ( output [11:0] cfg_interrupt_msi_mmenable, output cfg_interrupt_msi_mask_update, output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable, - - //Debug - output [15:0] debug //for cmp_source {error_code[3:], error_trigger} + output [7:0] cfg_interrupt_msi_vf_enable ); //----------------------------------------------------------------------------------------------------------------// @@ -478,8 +477,6 @@ module pcie_support # ( if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[3:0] == 5'd13); - wire [10:0] s_axis_rq_dwlen; - always @(posedge user_clk_out) if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; @@ -496,7 +493,7 @@ module pcie_support # ( assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - assign s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request @@ -832,15 +829,9 @@ module pcie_support # ( wire [15:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} - //----------------------------------------------------------------------------------------------------------------// - //Debug only - - //Condition trigger - wire cmperr_trigger = (m_axis_rc_tdata_a[15:12] != 4'b0) & m_axis_rc_tvalid_a & m_axis_rc_tready_a & m_axis_rc_sop; - - //----------------------------------------------------------------------------------------------------------------// - // MSI Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// + //---------------------------------------------------------------------------------------------------------------// + // MSI Adaptation Logic // + //---------------------------------------------------------------------------------------------------------------// wire [3:0] cfg_interrupt_msi_enable_x4; assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; diff --git a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v index 2975977e..5fa4ad07 100644 --- a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v @@ -359,10 +359,7 @@ module pcie_support # ( output [11:0] cfg_interrupt_msi_mmenable, output cfg_interrupt_msi_mask_update, output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable, - - //Debug - output [15:0] debug //for cmp_source {error_code[3:], error_trigger} + output [7:0] cfg_interrupt_msi_vf_enable ); //----------------------------------------------------------------------------------------------------------------// @@ -637,9 +634,6 @@ module pcie_support # ( m_axis_rc_tuser_a[42] //ECRC mapped to discontinue }; - wire [3:0] rc_errcode = m_axis_rc_tdata_a[15:12]; - wire rc_status_err = ((m_axis_rc_cmpstatus != 3'b0) | (rc_errcode != 4'b0)) && m_axis_rc_tvalid && m_axis_rc_tready && m_axis_rc_sop; - //----------------------------------------------------- CQ AXIS --------------------------------------------------// wire m_axis_cq_tvalid_a; wire m_axis_cq_tready_a; @@ -862,23 +856,9 @@ module pcie_support # ( wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} - wire cc_status_err = (s_axis_cc_cmpstatus != 3'b0) && s_axis_cc_tvalid_ff && s_axis_cc_tready_ff && s_axis_cc_tfirst; - - reg [31:0] cccnt; - always @(posedge user_clk_out) - if (user_reset_out) cccnt <= 16'b0; - else if (s_axis_cc_tvalid_a && s_axis_cc_tready_a[0] && s_axis_cc_tfirst) cccnt <= cccnt + s_axis_cc_dwordcnt; - - //----------------------------------------------------------------------------------------------------------------// - //Debug only - - //Condition trigger - wire cmperr_trigger = (m_axis_rc_tdata_a[15:12] != 4'b0) & m_axis_rc_tvalid_a & m_axis_rc_tready_a & m_axis_rc_sop; - assign debug = {m_axis_rc_tdata_a[15:12], cmperr_trigger}; - - //----------------------------------------------------------------------------------------------------------------// - // MSI Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// + //---------------------------------------------------------------------------------------------------------------// + // MSI Adaptation Logic // + //---------------------------------------------------------------------------------------------------------------// wire [3:0] cfg_interrupt_msi_enable_x4; assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; diff --git a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v index be2c1513..98fca150 100644 --- a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v @@ -359,10 +359,7 @@ module pcie_support # ( output [11:0] cfg_interrupt_msi_mmenable, output cfg_interrupt_msi_mask_update, output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable, - - //Debug - output [7:0] debug //for cmp_source {error_code[3:], error_trigger} + output [7:0] cfg_interrupt_msi_vf_enable ); //----------------------------------------------------------------------------------------------------------------// @@ -478,8 +475,6 @@ module pcie_support # ( if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); - wire [10:0] s_axis_rq_dwlen; - always @(posedge user_clk_out) if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; @@ -496,7 +491,7 @@ module pcie_support # ( assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - assign s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request @@ -828,16 +823,9 @@ module pcie_support # ( wire [7:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} - //----------------------------------------------------------------------------------------------------------------// - //Debug only - - //Condition trigger - wire cmperr_trigger = (m_axis_rc_tdata_a[15:12] != 4'b0) & m_axis_rc_tvalid_a & m_axis_rc_tready_a & m_axis_rc_sop; - assign debug = {m_axis_rc_tdata_a[15:12], cmperr_trigger}; - - //----------------------------------------------------------------------------------------------------------------// - // MSI Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// + //---------------------------------------------------------------------------------------------------------------// + // MSI Adaptation Logic // + //---------------------------------------------------------------------------------------------------------------// wire [3:0] cfg_interrupt_msi_enable_x4; assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; From d276f17f78f85609f71179da5b4a6512a94ea48c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 15:45:38 +0200 Subject: [PATCH 02/41] phy/xilinx_us(p): Create axis_iff.v and avoid duplication in pcie_us(p)_support.v. --- litepcie/phy/uspciephy.py | 1 + litepcie/phy/usppciephy.py | 1 + .../phy/xilinx_us_gen3_x4/pcie_us_support.v | 111 ------------------ .../phy/xilinx_us_gen3_x8/pcie_us_support.v | 111 ------------------ .../xilinx_usp_gen3_x16/pcie_usp_support.v | 111 ------------------ .../phy/xilinx_usp_gen3_x4/pcie_usp_support.v | 111 ------------------ .../phy/xilinx_usp_gen3_x8/pcie_usp_support.v | 111 ------------------ .../xilinx_usp_hbm_gen3_x4/pcie_usp_support.v | 111 ------------------ 8 files changed, 2 insertions(+), 666 deletions(-) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index e989008d..826adf34 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -375,6 +375,7 @@ def add_ltssm_tracer(self): # Hard IP sources ------------------------------------------------------------------------------ def add_sources(self, platform, phy_path, phy_filename): platform.add_ip(os.path.join(phy_path, phy_filename)) + platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) # External Hard IP ----------------------------------------------------------------------------- diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py index 218bebd0..9d008f5a 100644 --- a/litepcie/phy/usppciephy.py +++ b/litepcie/phy/usppciephy.py @@ -374,6 +374,7 @@ def add_ltssm_tracer(self): # Hard IP sources ------------------------------------------------------------------------------ def add_sources(self, platform, phy_path, phy_filename): platform.add_ip(os.path.join(phy_path, phy_filename)) + platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) platform.add_source(os.path.join(phy_path, "pcie_usp_support.v")) # External Hard IP ----------------------------------------------------------------------------- diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v index ee6b8a54..8283aebb 100644 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v @@ -59,117 +59,6 @@ // Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital -//----------------------------------------------------------------------------------------------------------------// -// AXIS FIFO // -//----------------------------------------------------------------------------------------------------------------// - -module axis_iff - #( - parameter DAT_B = 32 - ) - ( - input clk, - input rst, - - input i_vld, - output o_rdy, - input i_sop, - input i_eop, - input [DAT_B-1:0] i_dat, - - - output o_vld, - input i_rdy, - output o_sop, - output o_eop, - output [DAT_B-1:0] o_dat - ); - - /////////////////////////////////////////////////////////////////////////// - //FIFO instance - localparam FF_B = 8; - localparam FF_L = 256; - - wire ff_empt, ff_full; - reg [FF_B:0] ff_len; - - wire ff_wr, ff_rd; - - reg [FF_B-1:0] wrcnt; - always @(posedge clk) - if (rst) wrcnt <= {FF_B{1'b0}}; - else if (ff_wr) wrcnt <= wrcnt + 1; - - always @(posedge clk) - if (rst) ff_len <= {FF_B+1{1'b0}}; - else - case ({ff_wr, ff_rd}) - 2'b10: ff_len <= ff_len + 1; - 2'b01: ff_len <= ff_len - 1; - default: ff_len <= ff_len; - endcase - - wire [FF_B-1:0] rdcnt; - assign rdcnt = wrcnt - ff_len[FF_B-1:0]; - - wire [FF_B-1:0] rda, wra; - assign rda = ff_rd ? (rdcnt + 1) : rdcnt; - assign wra = wrcnt; - - wire [DAT_B+1:0] ff_wdat; - wire [DAT_B+1:0] ff_rdat; - assign ff_wdat = {i_sop, i_eop, i_dat}; - assign {o_sop, o_eop, o_dat} = ff_rdat; - assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); - assign o_vld = (pktcnt > 0); - - reg [3:0] pktcnt; - assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); - assign ff_rd = i_rdy & (pktcnt > 0); - - /////////////////////////////////////////////////////////////////////////// - //Single dual port RAM 1-clock - - (* ram_style="block" *) - reg [DAT_B+1:0] ram [FF_L-1:0]; - - always @(posedge clk) - if (ff_wr) ram[wra] <= ff_wdat; - - reg [DAT_B+1:0] ff_rdat_m; - always @(posedge clk) - ff_rdat_m <= ram[rda]; - - /////////////////////////////////////////////////////////////////////////// - //same read/write - - wire readsame = ff_wr & (wra == rda); - reg readsame1; - always @(posedge clk) - if (rst) readsame1 <= 1'b0; - else readsame1 <= readsame; - - reg [DAT_B+1:0] ff_wdat1; - always @(posedge clk) - ff_wdat1 <= ff_wdat; - - assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; - - /////////////////////////////////////////////////////////////////////////// - //Store max 8 packet - - always @(posedge clk) - if (rst) pktcnt <= 4'd0; - else begin - case ({(ff_wr & i_eop), (ff_rd & o_eop)}) - 2'b10: pktcnt <= pktcnt + 1; - 2'b01: pktcnt <= pktcnt - 1; - default: pktcnt <= pktcnt; - endcase - end - -endmodule - //----------------------------------------------------------------------------------------------------------------// // PCIe // //----------------------------------------------------------------------------------------------------------------// diff --git a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v index 23160d70..4e48034d 100644 --- a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v @@ -59,117 +59,6 @@ // Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital -//----------------------------------------------------------------------------------------------------------------// -// AXIS FIFO // -//----------------------------------------------------------------------------------------------------------------// - -module axis_iff - #( - parameter DAT_B = 32 - ) - ( - input clk, - input rst, - - input i_vld, - output o_rdy, - input i_sop, - input i_eop, - input [DAT_B-1:0] i_dat, - - - output o_vld, - input i_rdy, - output o_sop, - output o_eop, - output [DAT_B-1:0] o_dat - ); - - /////////////////////////////////////////////////////////////////////////// - //FIFO instance - localparam FF_B = 8; - localparam FF_L = 256; - - wire ff_empt, ff_full; - reg [FF_B:0] ff_len; - - wire ff_wr, ff_rd; - - reg [FF_B-1:0] wrcnt; - always @(posedge clk) - if (rst) wrcnt <= {FF_B{1'b0}}; - else if (ff_wr) wrcnt <= wrcnt + 1; - - always @(posedge clk) - if (rst) ff_len <= {FF_B+1{1'b0}}; - else - case ({ff_wr, ff_rd}) - 2'b10: ff_len <= ff_len + 1; - 2'b01: ff_len <= ff_len - 1; - default: ff_len <= ff_len; - endcase - - wire [FF_B-1:0] rdcnt; - assign rdcnt = wrcnt - ff_len[FF_B-1:0]; - - wire [FF_B-1:0] rda, wra; - assign rda = ff_rd ? (rdcnt + 1) : rdcnt; - assign wra = wrcnt; - - wire [DAT_B+1:0] ff_wdat; - wire [DAT_B+1:0] ff_rdat; - assign ff_wdat = {i_sop, i_eop, i_dat}; - assign {o_sop, o_eop, o_dat} = ff_rdat; - assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); - assign o_vld = (pktcnt > 0); - - reg [3:0] pktcnt; - assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); - assign ff_rd = i_rdy & (pktcnt > 0); - - /////////////////////////////////////////////////////////////////////////// - //Single dual port RAM 1-clock - - (* ram_style="block" *) - reg [DAT_B+1:0] ram [FF_L-1:0]; - - always @(posedge clk) - if (ff_wr) ram[wra] <= ff_wdat; - - reg [DAT_B+1:0] ff_rdat_m; - always @(posedge clk) - ff_rdat_m <= ram[rda]; - - /////////////////////////////////////////////////////////////////////////// - //same read/write - - wire readsame = ff_wr & (wra == rda); - reg readsame1; - always @(posedge clk) - if (rst) readsame1 <= 1'b0; - else readsame1 <= readsame; - - reg [DAT_B+1:0] ff_wdat1; - always @(posedge clk) - ff_wdat1 <= ff_wdat; - - assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; - - /////////////////////////////////////////////////////////////////////////// - //Store max 8 packet - - always @(posedge clk) - if (rst) pktcnt <= 4'd0; - else begin - case ({(ff_wr & i_eop), (ff_rd & o_eop)}) - 2'b10: pktcnt <= pktcnt + 1; - 2'b01: pktcnt <= pktcnt - 1; - default: pktcnt <= pktcnt; - endcase - end - -endmodule - //----------------------------------------------------------------------------------------------------------------// // PCIe // //----------------------------------------------------------------------------------------------------------------// diff --git a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v index 79689f14..789801d8 100644 --- a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v @@ -59,117 +59,6 @@ // Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital -//----------------------------------------------------------------------------------------------------------------// -// AXIS FIFO // -//----------------------------------------------------------------------------------------------------------------// - -module axis_iff - #( - parameter DAT_B = 32 - ) - ( - input clk, - input rst, - - input i_vld, - output o_rdy, - input i_sop, - input i_eop, - input [DAT_B-1:0] i_dat, - - - output o_vld, - input i_rdy, - output o_sop, - output o_eop, - output [DAT_B-1:0] o_dat - ); - - /////////////////////////////////////////////////////////////////////////// - //FIFO instance - localparam FF_B = 8; - localparam FF_L = 256; - - wire ff_empt, ff_full; - reg [FF_B:0] ff_len; - - wire ff_wr, ff_rd; - - reg [FF_B-1:0] wrcnt; - always @(posedge clk) - if (rst) wrcnt <= {FF_B{1'b0}}; - else if (ff_wr) wrcnt <= wrcnt + 1; - - always @(posedge clk) - if (rst) ff_len <= {FF_B+1{1'b0}}; - else - case ({ff_wr, ff_rd}) - 2'b10: ff_len <= ff_len + 1; - 2'b01: ff_len <= ff_len - 1; - default: ff_len <= ff_len; - endcase - - wire [FF_B-1:0] rdcnt; - assign rdcnt = wrcnt - ff_len[FF_B-1:0]; - - wire [FF_B-1:0] rda, wra; - assign rda = ff_rd ? (rdcnt + 1) : rdcnt; - assign wra = wrcnt; - - wire [DAT_B+1:0] ff_wdat; - wire [DAT_B+1:0] ff_rdat; - assign ff_wdat = {i_sop, i_eop, i_dat}; - assign {o_sop, o_eop, o_dat} = ff_rdat; - assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); - assign o_vld = (pktcnt > 0); - - reg [3:0] pktcnt; - assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); - assign ff_rd = i_rdy & (pktcnt > 0); - - /////////////////////////////////////////////////////////////////////////// - //Single dual port RAM 1-clock - - (* ram_style="block" *) - reg [DAT_B+1:0] ram [FF_L-1:0]; - - always @(posedge clk) - if (ff_wr) ram[wra] <= ff_wdat; - - reg [DAT_B+1:0] ff_rdat_m; - always @(posedge clk) - ff_rdat_m <= ram[rda]; - - /////////////////////////////////////////////////////////////////////////// - //same read/write - - wire readsame = ff_wr & (wra == rda); - reg readsame1; - always @(posedge clk) - if (rst) readsame1 <= 1'b0; - else readsame1 <= readsame; - - reg [DAT_B+1:0] ff_wdat1; - always @(posedge clk) - ff_wdat1 <= ff_wdat; - - assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; - - /////////////////////////////////////////////////////////////////////////// - //Store max 8 packet - - always @(posedge clk) - if (rst) pktcnt <= 4'd0; - else begin - case ({(ff_wr & i_eop), (ff_rd & o_eop)}) - 2'b10: pktcnt <= pktcnt + 1; - 2'b01: pktcnt <= pktcnt - 1; - default: pktcnt <= pktcnt; - endcase - end - -endmodule - //----------------------------------------------------------------------------------------------------------------// // PCIe // //----------------------------------------------------------------------------------------------------------------// diff --git a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v index 5fa4ad07..359f7751 100644 --- a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v @@ -59,117 +59,6 @@ // Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital -//----------------------------------------------------------------------------------------------------------------// -// AXIS FIFO // -//----------------------------------------------------------------------------------------------------------------// - -module axis_iff - #( - parameter DAT_B = 32 - ) - ( - input clk, - input rst, - - input i_vld, - output o_rdy, - input i_sop, - input i_eop, - input [DAT_B-1:0] i_dat, - - - output o_vld, - input i_rdy, - output o_sop, - output o_eop, - output [DAT_B-1:0] o_dat - ); - - /////////////////////////////////////////////////////////////////////////// - //FIFO instance - localparam FF_B = 8; - localparam FF_L = 256; - - wire ff_empt, ff_full; - reg [FF_B:0] ff_len; - - wire ff_wr, ff_rd; - - reg [FF_B-1:0] wrcnt; - always @(posedge clk) - if (rst) wrcnt <= {FF_B{1'b0}}; - else if (ff_wr) wrcnt <= wrcnt + 1; - - always @(posedge clk) - if (rst) ff_len <= {FF_B+1{1'b0}}; - else - case ({ff_wr, ff_rd}) - 2'b10: ff_len <= ff_len + 1; - 2'b01: ff_len <= ff_len - 1; - default: ff_len <= ff_len; - endcase - - wire [FF_B-1:0] rdcnt; - assign rdcnt = wrcnt - ff_len[FF_B-1:0]; - - wire [FF_B-1:0] rda, wra; - assign rda = ff_rd ? (rdcnt + 1) : rdcnt; - assign wra = wrcnt; - - wire [DAT_B+1:0] ff_wdat; - wire [DAT_B+1:0] ff_rdat; - assign ff_wdat = {i_sop, i_eop, i_dat}; - assign {o_sop, o_eop, o_dat} = ff_rdat; - assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); - assign o_vld = (pktcnt > 0); - - reg [3:0] pktcnt; - assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); - assign ff_rd = i_rdy & (pktcnt > 0); - - /////////////////////////////////////////////////////////////////////////// - //Single dual port RAM 1-clock - - (* ram_style="block" *) - reg [DAT_B+1:0] ram [FF_L-1:0]; - - always @(posedge clk) - if (ff_wr) ram[wra] <= ff_wdat; - - reg [DAT_B+1:0] ff_rdat_m; - always @(posedge clk) - ff_rdat_m <= ram[rda]; - - /////////////////////////////////////////////////////////////////////////// - //same read/write - - wire readsame = ff_wr & (wra == rda); - reg readsame1; - always @(posedge clk) - if (rst) readsame1 <= 1'b0; - else readsame1 <= readsame; - - reg [DAT_B+1:0] ff_wdat1; - always @(posedge clk) - ff_wdat1 <= ff_wdat; - - assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; - - /////////////////////////////////////////////////////////////////////////// - //Store max 8 packet - - always @(posedge clk) - if (rst) pktcnt <= 4'd0; - else begin - case ({(ff_wr & i_eop), (ff_rd & o_eop)}) - 2'b10: pktcnt <= pktcnt + 1; - 2'b01: pktcnt <= pktcnt - 1; - default: pktcnt <= pktcnt; - endcase - end - -endmodule - //----------------------------------------------------------------------------------------------------------------// // PCIe // //----------------------------------------------------------------------------------------------------------------// diff --git a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v index 98fca150..fa9237d3 100644 --- a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v @@ -59,117 +59,6 @@ // Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital -//----------------------------------------------------------------------------------------------------------------// -// AXIS FIFO // -//----------------------------------------------------------------------------------------------------------------// - -module axis_iff - #( - parameter DAT_B = 32 - ) - ( - input clk, - input rst, - - input i_vld, - output o_rdy, - input i_sop, - input i_eop, - input [DAT_B-1:0] i_dat, - - - output o_vld, - input i_rdy, - output o_sop, - output o_eop, - output [DAT_B-1:0] o_dat - ); - - /////////////////////////////////////////////////////////////////////////// - //FIFO instance - localparam FF_B = 8; - localparam FF_L = 256; - - wire ff_empt, ff_full; - reg [FF_B:0] ff_len; - - wire ff_wr, ff_rd; - - reg [FF_B-1:0] wrcnt; - always @(posedge clk) - if (rst) wrcnt <= {FF_B{1'b0}}; - else if (ff_wr) wrcnt <= wrcnt + 1; - - always @(posedge clk) - if (rst) ff_len <= {FF_B+1{1'b0}}; - else - case ({ff_wr, ff_rd}) - 2'b10: ff_len <= ff_len + 1; - 2'b01: ff_len <= ff_len - 1; - default: ff_len <= ff_len; - endcase - - wire [FF_B-1:0] rdcnt; - assign rdcnt = wrcnt - ff_len[FF_B-1:0]; - - wire [FF_B-1:0] rda, wra; - assign rda = ff_rd ? (rdcnt + 1) : rdcnt; - assign wra = wrcnt; - - wire [DAT_B+1:0] ff_wdat; - wire [DAT_B+1:0] ff_rdat; - assign ff_wdat = {i_sop, i_eop, i_dat}; - assign {o_sop, o_eop, o_dat} = ff_rdat; - assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); - assign o_vld = (pktcnt > 0); - - reg [3:0] pktcnt; - assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); - assign ff_rd = i_rdy & (pktcnt > 0); - - /////////////////////////////////////////////////////////////////////////// - //Single dual port RAM 1-clock - - (* ram_style="block" *) - reg [DAT_B+1:0] ram [FF_L-1:0]; - - always @(posedge clk) - if (ff_wr) ram[wra] <= ff_wdat; - - reg [DAT_B+1:0] ff_rdat_m; - always @(posedge clk) - ff_rdat_m <= ram[rda]; - - /////////////////////////////////////////////////////////////////////////// - //same read/write - - wire readsame = ff_wr & (wra == rda); - reg readsame1; - always @(posedge clk) - if (rst) readsame1 <= 1'b0; - else readsame1 <= readsame; - - reg [DAT_B+1:0] ff_wdat1; - always @(posedge clk) - ff_wdat1 <= ff_wdat; - - assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; - - /////////////////////////////////////////////////////////////////////////// - //Store max 8 packet - - always @(posedge clk) - if (rst) pktcnt <= 4'd0; - else begin - case ({(ff_wr & i_eop), (ff_rd & o_eop)}) - 2'b10: pktcnt <= pktcnt + 1; - 2'b01: pktcnt <= pktcnt - 1; - default: pktcnt <= pktcnt; - endcase - end - -endmodule - //----------------------------------------------------------------------------------------------------------------// // PCIe // //----------------------------------------------------------------------------------------------------------------// diff --git a/litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v b/litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v index 2975977e..a3d83969 100644 --- a/litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v @@ -59,117 +59,6 @@ // Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital -//----------------------------------------------------------------------------------------------------------------// -// AXIS FIFO // -//----------------------------------------------------------------------------------------------------------------// - -module axis_iff - #( - parameter DAT_B = 32 - ) - ( - input clk, - input rst, - - input i_vld, - output o_rdy, - input i_sop, - input i_eop, - input [DAT_B-1:0] i_dat, - - - output o_vld, - input i_rdy, - output o_sop, - output o_eop, - output [DAT_B-1:0] o_dat - ); - - /////////////////////////////////////////////////////////////////////////// - //FIFO instance - localparam FF_B = 8; - localparam FF_L = 256; - - wire ff_empt, ff_full; - reg [FF_B:0] ff_len; - - wire ff_wr, ff_rd; - - reg [FF_B-1:0] wrcnt; - always @(posedge clk) - if (rst) wrcnt <= {FF_B{1'b0}}; - else if (ff_wr) wrcnt <= wrcnt + 1; - - always @(posedge clk) - if (rst) ff_len <= {FF_B+1{1'b0}}; - else - case ({ff_wr, ff_rd}) - 2'b10: ff_len <= ff_len + 1; - 2'b01: ff_len <= ff_len - 1; - default: ff_len <= ff_len; - endcase - - wire [FF_B-1:0] rdcnt; - assign rdcnt = wrcnt - ff_len[FF_B-1:0]; - - wire [FF_B-1:0] rda, wra; - assign rda = ff_rd ? (rdcnt + 1) : rdcnt; - assign wra = wrcnt; - - wire [DAT_B+1:0] ff_wdat; - wire [DAT_B+1:0] ff_rdat; - assign ff_wdat = {i_sop, i_eop, i_dat}; - assign {o_sop, o_eop, o_dat} = ff_rdat; - assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); - assign o_vld = (pktcnt > 0); - - reg [3:0] pktcnt; - assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); - assign ff_rd = i_rdy & (pktcnt > 0); - - /////////////////////////////////////////////////////////////////////////// - //Single dual port RAM 1-clock - - (* ram_style="block" *) - reg [DAT_B+1:0] ram [FF_L-1:0]; - - always @(posedge clk) - if (ff_wr) ram[wra] <= ff_wdat; - - reg [DAT_B+1:0] ff_rdat_m; - always @(posedge clk) - ff_rdat_m <= ram[rda]; - - /////////////////////////////////////////////////////////////////////////// - //same read/write - - wire readsame = ff_wr & (wra == rda); - reg readsame1; - always @(posedge clk) - if (rst) readsame1 <= 1'b0; - else readsame1 <= readsame; - - reg [DAT_B+1:0] ff_wdat1; - always @(posedge clk) - ff_wdat1 <= ff_wdat; - - assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; - - /////////////////////////////////////////////////////////////////////////// - //Store max 8 packet - - always @(posedge clk) - if (rst) pktcnt <= 4'd0; - else begin - case ({(ff_wr & i_eop), (ff_rd & o_eop)}) - 2'b10: pktcnt <= pktcnt + 1; - 2'b01: pktcnt <= pktcnt - 1; - default: pktcnt <= pktcnt; - endcase - end - -endmodule - //----------------------------------------------------------------------------------------------------------------// // PCIe // //----------------------------------------------------------------------------------------------------------------// From e2b0539f38fdf859071fea2fa360d7740093279f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 16:31:15 +0200 Subject: [PATCH 03/41] phy/xilinx_us_gen3_x4: Move AXIS RQ adaptation to s_axis_rq_adapt_x4.v. --- litepcie/phy/s_axis_rq_adapt_x4.v | 144 ++++++++++++++++++ litepcie/phy/uspciephy.py | 1 + .../phy/xilinx_us_gen3_x4/pcie_us_support.v | 141 +++-------------- 3 files changed, 166 insertions(+), 120 deletions(-) create mode 100644 litepcie/phy/s_axis_rq_adapt_x4.v diff --git a/litepcie/phy/s_axis_rq_adapt_x4.v b/litepcie/phy/s_axis_rq_adapt_x4.v new file mode 100644 index 00000000..d5d236be --- /dev/null +++ b/litepcie/phy/s_axis_rq_adapt_x4.v @@ -0,0 +1,144 @@ + module s_axis_rq_adapt_x4 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + output s_axis_rq_tlast, + input [3:0] s_axis_rq_tready, + output [3:0] s_axis_rq_tuser, + output s_axis_rq_tvalid, + + input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + input s_axis_rq_tlast_a, + output [3:0] s_axis_rq_tready_a, + input [3:0] s_axis_rq_tuser_a, + input s_axis_rq_tvalid_a + ); + + wire s_axis_rq_tready_ff, + s_axis_rq_tvalid_ff, + s_axis_rq_tlast_ff; + wire [3:0] s_axis_rq_tkeep_or = {|s_axis_rq_tkeep[15:12], |s_axis_rq_tkeep[11:8], |s_axis_rq_tkeep[7:4], |s_axis_rq_tkeep[3:0]}; + + wire [3:0] s_axis_rq_tuser_ff; + wire [3:0] s_axis_rq_tkeep_ff; + wire [127:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff + ( + .clk (user_clk), + .rst (user_reset), + + .i_vld (s_axis_rq_tvalid), + .o_rdy (s_axis_rq_tready), + .i_sop (1'b0), + .i_eop (s_axis_rq_tlast), + .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), + + .o_vld (s_axis_rq_tvalid_ff), + .i_rdy (s_axis_rq_tready_ff), + .o_sop (), + .o_eop (s_axis_rq_tlast_ff), + .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) + ); + + + reg [1:0] s_axis_rq_cnt; //0-2 + always @(posedge user_clk) + if (user_reset) s_axis_rq_cnt <= 2'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + begin + if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; + else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; + end + + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; + + //processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_write = !s_axis_rq_read; + reg s_axis_rq_tlast_dly_en; + reg s_axis_rq_tlast_lat; + wire [3:0] s_axis_rq_tready_a; + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); + + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + begin + if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword + else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; + end + + wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + + //Generae ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request + s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request + s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request + s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 + s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 + 4'b1111; + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; + + always @(posedge user_clk) + begin + if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) + begin + s_axis_rq_firstbe_l <= s_axis_rq_firstbe; + s_axis_rq_lastbe_l <= s_axis_rq_lastbe; + end + end + + reg [31:0] s_axis_rq_tdata_l; + always @(posedge user_clk) + if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; + + wire [127:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; + wire [3:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; //{s_axis_rq_tkeep_ff[2:0], 1'b1}; + wire [59:0] s_axis_rq_tuser_a; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 826adf34..6ac468e6 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -376,6 +376,7 @@ def add_ltssm_tracer(self): def add_sources(self, platform, phy_path, phy_filename): platform.add_ip(os.path.join(phy_path, phy_filename)) platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) + platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) # External Hard IP ----------------------------------------------------------------------------- diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v index 8283aebb..1460442a 100644 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v @@ -312,126 +312,27 @@ module pcie_support # ( // AXIS Adaption Logic // //----------------------------------------------------------------------------------------------------------------// - //----------------------------------------------------- RQ AXIS --------------------------------------------------// - wire s_axis_rq_tready_ff, - s_axis_rq_tvalid_ff, - s_axis_rq_tlast_ff; - wire [3:0] s_axis_rq_tkeep_or = {|s_axis_rq_tkeep[15:12], |s_axis_rq_tkeep[11:8], |s_axis_rq_tkeep[7:4], |s_axis_rq_tkeep[3:0]}; - - wire [3:0] s_axis_rq_tuser_ff; - wire [3:0] s_axis_rq_tkeep_ff; - wire [127:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_rq_tvalid), - .o_rdy (s_axis_rq_tready), - .i_sop (1'b0), - .i_eop (s_axis_rq_tlast), - .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), - - .o_vld (s_axis_rq_tvalid_ff), - .i_rdy (s_axis_rq_tready_ff), - .o_sop (), - .o_eop (s_axis_rq_tlast_ff), - .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) - ); - - - reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; - end - - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - - //processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); - - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) - begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; - end - - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; - - always @(posedge user_clk_out) - begin - if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) - begin - s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; - end - end - - reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) - if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; - - wire [127:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; - wire [3:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; //{s_axis_rq_tkeep_ff[2:0], 1'b1}; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + s_axis_rq_adapt_x4 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_rq_adapt_x4_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_rq_tdata(s_axis_rq_tdata), + .s_axis_rq_tkeep(s_axis_rq_tkeep), + .s_axis_rq_tlast(s_axis_rq_tlast), + .s_axis_rq_tready(s_axis_rq_tready), + .s_axis_rq_tuser(s_axis_rq_tuser), + .s_axis_rq_tvalid(s_axis_rq_tvalid), + + .s_axis_rq_tdata_a(s_axis_rq_tdata_a), + .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), + .s_axis_rq_tlast_a(s_axis_rq_tlast_a), + .s_axis_rq_tready_a(s_axis_rq_tready_a), + .s_axis_rq_tuser_a(s_axis_rq_tuser_a), + .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) + ); //----------------------------------------------------- RC AXIS --------------------------------------------------// wire m_axis_rc_tvalid_a; From 251ed222bcf78fa6d263a9219a8aa79b4577d689 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 16:39:08 +0200 Subject: [PATCH 04/41] phy/xilinx_us_gen3_x4: Move AXIS RC adaptation to m_axis_rc_adapt_x4.v. --- litepcie/phy/uspciephy.py | 1 + .../phy/xilinx_us_gen3_x4/pcie_us_support.v | 96 +++++-------------- 2 files changed, 23 insertions(+), 74 deletions(-) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 6ac468e6..fa8df3d6 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -377,6 +377,7 @@ def add_sources(self, platform, phy_path, phy_filename): platform.add_ip(os.path.join(phy_path, phy_filename)) platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "m_axis_rc_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) # External Hard IP ----------------------------------------------------------------------------- diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v index 1460442a..b33135f8 100644 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v @@ -312,6 +312,8 @@ module pcie_support # ( // AXIS Adaption Logic // //----------------------------------------------------------------------------------------------------------------// + //----------------------------------------------------- RQ AXIS -------------------------------------------------// + s_axis_rq_adapt_x4 #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) @@ -335,82 +337,28 @@ module pcie_support # ( ); //----------------------------------------------------- RC AXIS --------------------------------------------------// - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [3:0] m_axis_rc_tkeep_a; - wire [127:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - - reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; - else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) - begin - if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; - else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; - end - wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] - wire m_axis_rc_second = m_axis_rc_cnt == 1; - - //header process - wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; - reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) - if (m_axis_rc_tvalid_a && m_axis_rc_sop) - begin - m_axis_rc_poisoning_l <= m_axis_rc_poisoning; - end + m_axis_rc_adapt_x4 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_rc_adapt_x4_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; - wire [4:0] m_axis_rc_type; - wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; - wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; - wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; - - assign {m_axis_rc_fmt, - m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data - 8'b010_01011) : //Read-Locked Completion w/ data - ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data - 8'b010_01010); //Completion w/ data - - wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen}; - wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr}; - - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; - assign m_axis_rc_tuser = { - 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + .m_axis_rc_tdata( m_axis_rc_tdata), + .m_axis_rc_tkeep( m_axis_rc_tkeep), + .m_axis_rc_tlast( m_axis_rc_tlast), + .m_axis_rc_tready(m_axis_rc_tready), + .m_axis_rc_tuser( m_axis_rc_tuser), + .m_axis_rc_tvalid(m_axis_rc_tvalid), + + .m_axis_rc_tdata_a( s_axis_rc_tdata_a), + .m_axis_rc_tkeep_a( s_axis_rc_tkeep_a), + .m_axis_rc_tlast_a( s_axis_rc_tlast_a), + .m_axis_rc_tready_a(s_axis_rc_tready_a), + .m_axis_rc_tuser_a( s_axis_rc_tuser_a), + .m_axis_rc_tvalid_a(s_axis_rc_tvalid_a) + ); //----------------------------------------------------- CQ AXIS --------------------------------------------------// wire m_axis_cq_tvalid_a; From e7c78c7a932292c24df635bc330764b27433a877 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 17:09:13 +0200 Subject: [PATCH 05/41] phy/xilinx_us_gen3_x4: Move AXIS CQ adaptation to m_axis_cq_adapt_x4.v. --- litepcie/phy/m_axis_cq_adapt_x4.v | 155 +++++++++++++++++ litepcie/phy/m_axis_rc_adapt_x4.v | 95 ++++++++++ litepcie/phy/uspciephy.py | 1 + .../phy/xilinx_us_gen3_x4/pcie_us_support.v | 162 ++++-------------- 4 files changed, 285 insertions(+), 128 deletions(-) create mode 100644 litepcie/phy/m_axis_cq_adapt_x4.v create mode 100644 litepcie/phy/m_axis_rc_adapt_x4.v diff --git a/litepcie/phy/m_axis_cq_adapt_x4.v b/litepcie/phy/m_axis_cq_adapt_x4.v new file mode 100644 index 00000000..79f2944a --- /dev/null +++ b/litepcie/phy/m_axis_cq_adapt_x4.v @@ -0,0 +1,155 @@ + module m_axis_cq_adapt_x4 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_cq_tdata, + output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, + output m_axis_cq_tlast, + input [3:0] m_axis_cq_tready, + output [84:0] m_axis_cq_tuser, + output m_axis_cq_tvalid, + + input [DATA_WIDTH-1:0] m_axis_cq_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a, + input m_axis_cq_tlast_a, + output [3:0] m_axis_cq_tready_a, + input [84:0] m_axis_cq_tuser_a, + input m_axis_cq_tvalid_a + ); + + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [3:0] m_axis_cq_tkeep_a; + wire [127:0] m_axis_cq_tdata_a; + wire [84:0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; + + //dword counter: //0-2 & latch + reg [1:0] m_axis_cq_cnt; + always @(posedge user_clk) + if (user_reset) m_axis_cq_cnt <= 2'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; + else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; + end + + wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] + wire m_axis_cq_second = m_axis_cq_cnt == 1; + + wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request + wire m_axis_cq_write = !m_axis_cq_read; + reg m_axis_cq_read_l; + always @(posedge user_clk) + if (user_reset) m_axis_cq_read_l <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_read_l <= m_axis_cq_read; + + //processing for tlast + wire [9:0] m_axis_cq_dwlen; + reg m_axis_cq_tlast_dly_en; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) + begin + if (m_axis_cq_read) m_axis_cq_tlast_dly_en <= 1'b1; + else m_axis_cq_tlast_dly_en <= (m_axis_cq_dwlen[1:0] != 2'd1); + end + + reg m_axis_cq_tlast_lat; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) + begin + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read + else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; + end + + //Generae ready for PCIe IP + assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); + + //output for TLP + assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; + assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; + + + ////keep address (low) or data (high), not header + reg [127:0] m_axis_cq_tdata_a1; + reg [15:0] m_axis_cq_tlast_be1; + always @(posedge user_clk) + if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; + m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[23:8]; + end + + //data processing + wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; + + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + wire [4:0] m_axis_cq_type; + wire [2:0] m_axis_cq_fmt; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; + + assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request + m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked + m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request + m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request + m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request + m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 + m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 + 8'b000_00000; //Mem read Request + + reg [7:0] m_axis_cq_tuser_barhit; + always @(posedge user_clk) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop + + reg m_axis_cq_ecrc; + always @(posedge user_clk) + begin + m_axis_cq_ecrc <= m_axis_cq_tuser_a[41]; + end + + reg [63:0] m_axis_cq_header; + always @(posedge user_clk) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; + + wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; + assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : + {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[127:32]}; + + assign m_axis_cq_tkeep = m_axis_cq_read_l ? 16'h0FFF : + m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[15:4]} : 16'hFFFF; + + + assign m_axis_cq_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_ecrc //ECRC mapped to discontinue + }; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/m_axis_rc_adapt_x4.v b/litepcie/phy/m_axis_rc_adapt_x4.v new file mode 100644 index 00000000..6ad8c050 --- /dev/null +++ b/litepcie/phy/m_axis_rc_adapt_x4.v @@ -0,0 +1,95 @@ + module m_axis_rc_adapt_x4 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_rc_tdata, + output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, + output m_axis_rc_tlast, + input [3:0] m_axis_rc_tready, + output [84:0] m_axis_rc_tuser, + output m_axis_rc_tvalid, + + input [DATA_WIDTH-1:0] m_axis_rc_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_rc_tkeep_a, + input m_axis_rc_tlast_a, + output [3:0] m_axis_rc_tready_a, + input [84:0] m_axis_rc_tuser_a, + input m_axis_rc_tvalid_a + ); + + reg [1:0] m_axis_rc_cnt; //0-2 + always @(posedge user_clk) + if (user_reset) m_axis_rc_cnt <= 2'd0; + else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) + begin + if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; + else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; + end + + wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] + wire m_axis_rc_second = m_axis_rc_cnt == 1; + + //header process + wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; + reg m_axis_rc_poisoning_l; + always @(posedge user_clk) + if (m_axis_rc_tvalid_a && m_axis_rc_sop) + begin + m_axis_rc_poisoning_l <= m_axis_rc_poisoning; + end + + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [4:0] m_axis_rc_type; + wire [2:0] m_axis_rc_fmt; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; + + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; + + assign {m_axis_rc_fmt, + m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data + 8'b010_01011) : //Read-Locked Completion w/ data + ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data + 8'b010_01010); //Completion w/ data + + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; + assign m_axis_rc_tuser = { + 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; + + +endmodule \ No newline at end of file diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index fa8df3d6..5f985b9b 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -378,6 +378,7 @@ def add_sources(self, platform, phy_path, phy_filename): platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "..", "m_axis_rc_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "m_axis_cq_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) # External Hard IP ----------------------------------------------------------------------------- diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v index b33135f8..e247471e 100644 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v @@ -338,6 +338,13 @@ module pcie_support # ( //----------------------------------------------------- RC AXIS --------------------------------------------------// + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [3:0] m_axis_rc_tkeep_a; + wire [127:0] m_axis_rc_tdata_a; + wire [74:0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; + m_axis_rc_adapt_x4 #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) @@ -352,15 +359,16 @@ module pcie_support # ( .m_axis_rc_tuser( m_axis_rc_tuser), .m_axis_rc_tvalid(m_axis_rc_tvalid), - .m_axis_rc_tdata_a( s_axis_rc_tdata_a), - .m_axis_rc_tkeep_a( s_axis_rc_tkeep_a), - .m_axis_rc_tlast_a( s_axis_rc_tlast_a), - .m_axis_rc_tready_a(s_axis_rc_tready_a), - .m_axis_rc_tuser_a( s_axis_rc_tuser_a), - .m_axis_rc_tvalid_a(s_axis_rc_tvalid_a) + .m_axis_rc_tdata_a( m_axis_rc_tdata_a), + .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), + .m_axis_rc_tlast_a( m_axis_rc_tlast_a), + .m_axis_rc_tready_a(m_axis_rc_tready_a), + .m_axis_rc_tuser_a( m_axis_rc_tuser_a), + .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) ); //----------------------------------------------------- CQ AXIS --------------------------------------------------// + wire m_axis_cq_tvalid_a; wire m_axis_cq_tready_a; wire [3:0] m_axis_cq_tkeep_a; @@ -368,129 +376,27 @@ module pcie_support # ( wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch - reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; - else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; - end - - wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] - wire m_axis_cq_second = m_axis_cq_cnt == 1; - - wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request - wire m_axis_cq_write = !m_axis_cq_read; - reg m_axis_cq_read_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_read_l <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_read_l <= m_axis_cq_read; - - //processing for tlast - wire [9:0] m_axis_cq_dwlen; - reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) - begin - if (m_axis_cq_read) m_axis_cq_tlast_dly_en <= 1'b1; - else m_axis_cq_tlast_dly_en <= (m_axis_cq_dwlen[1:0] != 2'd1); - end - - reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) - begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read - else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; - end - - //Generae ready for PCIe IP - assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); - - //output for TLP - assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; - assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; - - - ////keep address (low) or data (high), not header - reg [127:0] m_axis_cq_tdata_a1; - reg [15:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; - m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[23:8]; - end - - //data processing - wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; - wire [4:0] m_axis_cq_type; - wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; - wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; - - assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request - m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked - m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request - m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request - m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request - m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 - m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 - 8'b000_00000; //Mem read Request - - reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop - - reg m_axis_cq_ecrc; - always @(posedge user_clk_out) - begin - m_axis_cq_ecrc <= m_axis_cq_tuser_a[41]; - end + m_axis_cq_adapt_x4 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_cq_adapt_x4_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), - reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = {m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen}; - - wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; - assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : - {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[127:32]}; - - assign m_axis_cq_tkeep = m_axis_cq_read_l ? 16'h0FFF : - m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[15:4]} : 16'hFFFF; - - - assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_ecrc //ECRC mapped to discontinue - }; + .m_axis_cq_tdata( m_axis_cq_tdata), + .m_axis_cq_tkeep( m_axis_cq_tkeep), + .m_axis_cq_tlast( m_axis_cq_tlast), + .m_axis_cq_tready(m_axis_cq_tready), + .m_axis_cq_tuser( m_axis_cq_tuser), + .m_axis_cq_tvalid(m_axis_cq_tvalid), + + .m_axis_cq_tdata_a( s_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( s_axis_cq_tlast_a), + .m_axis_cq_tready_a(s_axis_cq_tready_a), + .m_axis_cq_tuser_a( s_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + ); //----------------------------------------------------- CC AXIS --------------------------------------------------// wire s_axis_cc_tready_ff, From 917b3a3b6d078f628daaac946a1c1f81d1151983 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 17:23:50 +0200 Subject: [PATCH 06/41] phy/xilinx_us_gen3_x4: Move AXIS CC adaptation to s_axis_cc_adapt_x4.v. --- litepcie/phy/s_axis_cc_adapt_x4.v | 113 ++++++++++++++++++ litepcie/phy/uspciephy.py | 1 + .../phy/xilinx_us_gen3_x4/pcie_us_support.v | 110 ++++------------- 3 files changed, 136 insertions(+), 88 deletions(-) create mode 100644 litepcie/phy/s_axis_cc_adapt_x4.v diff --git a/litepcie/phy/s_axis_cc_adapt_x4.v b/litepcie/phy/s_axis_cc_adapt_x4.v new file mode 100644 index 00000000..0984c84e --- /dev/null +++ b/litepcie/phy/s_axis_cc_adapt_x4.v @@ -0,0 +1,113 @@ + module s_axis_cc_adapt_x4 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + output s_axis_cc_tlast, + input [3:0] s_axis_cc_tready, + output [3:0] s_axis_cc_tuser, + output s_axis_cc_tvalid, + + input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + input s_axis_cc_tlast_a, + output [3:0] s_axis_cc_tready_a, + input [3:0] s_axis_cc_tuser_a, + input s_axis_cc_tvalid_a + ); + + wire s_axis_cc_tready_ff, + s_axis_cc_tvalid_ff, + s_axis_cc_tlast_ff; + wire [3:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; + + wire [3:0] s_axis_cc_tuser_ff; + wire [3:0] s_axis_cc_tkeep_ff; + wire [127:0] s_axis_cc_tdata_ff; + + axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff + ( + .clk (user_clk), + .rst (user_reset), + + .i_vld (s_axis_cc_tvalid), + .o_rdy (s_axis_cc_tready), + .i_sop (1'b0), + .i_eop (s_axis_cc_tlast), + .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), + + .o_vld (s_axis_cc_tvalid_ff), + .i_rdy (s_axis_cc_tready_ff), + .o_sop (), + .o_eop (s_axis_cc_tlast_ff), + .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) + ); + + reg [1:0] s_axis_cc_cnt; //0-2 + always @(posedge user_clk) + if (user_reset) s_axis_cc_cnt <= 2'd0; + else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) + begin + if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; + else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; + end + + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; + + wire [3:0] s_axis_cc_tready_a; + + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; + + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; + + reg [3:0] s_axis_cc_firstbe; + reg [3:0] s_axis_cc_lastbe; + + reg s_axis_cc_tvalid_ff_lat; + always @(posedge user_clk) + if (user_reset) s_axis_cc_tvalid_ff_lat <= 1'd0; + else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) + begin + if (s_axis_cc_tlast_ff) s_axis_cc_tvalid_ff_lat <= 1'd0; + else if (s_axis_cc_tfirst) s_axis_cc_tvalid_ff_lat <= 1'd1; + end + + wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; + wire [127:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + +endmodule \ No newline at end of file diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 5f985b9b..010c5b2f 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -379,6 +379,7 @@ def add_sources(self, platform, phy_path, phy_filename): platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "..", "m_axis_rc_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "..", "m_axis_cq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "s_axis_cc_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) # External Hard IP ----------------------------------------------------------------------------- diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v index e247471e..b5c87536 100644 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v @@ -399,94 +399,28 @@ module pcie_support # ( ); //----------------------------------------------------- CC AXIS --------------------------------------------------// - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; - - wire [3:0] s_axis_cc_tuser_ff; - wire [3:0] s_axis_cc_tkeep_ff; - wire [127:0] s_axis_cc_tdata_ff; - - axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_cc_tvalid), - .o_rdy (s_axis_cc_tready), - .i_sop (1'b0), - .i_eop (s_axis_cc_tlast), - .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), - - .o_vld (s_axis_cc_tvalid_ff), - .i_rdy (s_axis_cc_tready_ff), - .o_sop (), - .o_eop (s_axis_cc_tlast_ff), - .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) - ); - - reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; - else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; - end - - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; - wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; - wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; - wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; - wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr}; - wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; - - reg [3:0] s_axis_cc_firstbe; - reg [3:0] s_axis_cc_lastbe; - - reg s_axis_cc_tvalid_ff_lat; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_tvalid_ff_lat <= 1'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_tvalid_ff_lat <= 1'd0; - else if (s_axis_cc_tfirst) s_axis_cc_tvalid_ff_lat <= 1'd1; - end - - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [127:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + + s_axis_cc_adapt_x4 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_cc_adapt_x4_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_cc_tdata(s_axis_cc_tdata), + .s_axis_cc_tkeep(s_axis_cc_tkeep), + .s_axis_cc_tlast(s_axis_cc_tlast), + .s_axis_cc_tready(s_axis_cc_tready), + .s_axis_cc_tuser(s_axis_cc_tuser), + .s_axis_cc_tvalid(s_axis_cc_tvalid), + + .s_axis_cc_tdata_a(s_axis_cc_tdata_a), + .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), + .s_axis_cc_tlast_a(s_axis_cc_tlast_a), + .s_axis_cc_tready_a(s_axis_cc_tready_a), + .s_axis_cc_tuser_a(s_axis_cc_tuser_a), + .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) + ); //---------------------------------------------------------------------------------------------------------------// // MSI Adaptation Logic // From 844ead5450dc40197484f94a518ab30568cdbd1b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 17:50:38 +0200 Subject: [PATCH 07/41] phy/xilinx_us_gen3_x8: Similar adaptation than x4. --- litepcie/phy/m_axis_cq_adapt_x8.v | 141 ++++++ litepcie/phy/m_axis_rc_adapt_x8.v | 101 ++++ litepcie/phy/s_axis_cc_adapt_x8.v | 104 ++++ litepcie/phy/s_axis_rq_adapt_x8.v | 146 ++++++ litepcie/phy/uspciephy.py | 7 + .../phy/xilinx_us_gen3_x8/pcie_us_support.v | 467 ++++-------------- 6 files changed, 588 insertions(+), 378 deletions(-) create mode 100644 litepcie/phy/m_axis_cq_adapt_x8.v create mode 100644 litepcie/phy/m_axis_rc_adapt_x8.v create mode 100644 litepcie/phy/s_axis_cc_adapt_x8.v create mode 100644 litepcie/phy/s_axis_rq_adapt_x8.v diff --git a/litepcie/phy/m_axis_cq_adapt_x8.v b/litepcie/phy/m_axis_cq_adapt_x8.v new file mode 100644 index 00000000..038e99b4 --- /dev/null +++ b/litepcie/phy/m_axis_cq_adapt_x8.v @@ -0,0 +1,141 @@ + module m_axis_cq_adapt_x8 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_cq_tdata, + output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, + output m_axis_cq_tlast, + input [3:0] m_axis_cq_tready, + output [84:0] m_axis_cq_tuser, + output m_axis_cq_tvalid, + + input [DATA_WIDTH-1:0] m_axis_cq_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a, + input m_axis_cq_tlast_a, + output [3:0] m_axis_cq_tready_a, + input [84:0] m_axis_cq_tuser_a, + input m_axis_cq_tvalid_a + ); + + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [7:0] m_axis_cq_tkeep_a; + wire [255:0] m_axis_cq_tdata_a; + wire [84:0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; + + //dword counter: //0-2 & latch + reg [1:0] m_axis_cq_cnt; + always @(posedge user_clk) + if (user_reset) m_axis_cq_cnt <= 2'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; + else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; + end + + wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] + wire m_axis_cq_second = m_axis_cq_cnt == 1; + + reg m_axis_cq_rdwr_l; + always @(posedge user_clk) + if (user_reset) m_axis_cq_rdwr_l <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_rdwr_l <= m_axis_cq_tlast_a; + + //processing for tlast: generate new last in case write & last num of dword != 5 + i*8 + wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request + wire m_axis_cq_write = !m_axis_cq_read; + wire [9:0] m_axis_cq_dwlen; + reg m_axis_cq_tlast_dly_en; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tlast_dly_en <= m_axis_cq_tlast_a | (m_axis_cq_dwlen[2:0] != 3'd5); + + reg m_axis_cq_tlast_lat; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) + begin + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; + else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; + end + + //Generae ready for PCIe IP + assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); + + //output for TLP + assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; + assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; + + + ////keep address (low) or data (high), not header + reg [255:0] m_axis_cq_tdata_a1; + reg [31:0] m_axis_cq_tlast_be1; + always @(posedge user_clk) + if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; + m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[39:8]; + end + + //data processing + wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; + + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + wire [4:0] m_axis_cq_type; + wire [2:0] m_axis_cq_fmt; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; + + assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request + m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked + m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request + m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request + m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request + m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 + m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 + 8'b000_00000; //Mem read Request + + reg [7:0] m_axis_cq_tuser_barhit; + always @(posedge user_clk) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop + + reg [63:0] m_axis_cq_header; + always @(posedge user_clk) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; + + assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : + {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:32]}; + assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[31:16], 12'hFFF} : + m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[31:4]} : 32'hFFFF_FFFF; + assign m_axis_cq_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_tuser_a[41] //ECRC mapped to discontinue + }; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/m_axis_rc_adapt_x8.v b/litepcie/phy/m_axis_rc_adapt_x8.v new file mode 100644 index 00000000..6f030512 --- /dev/null +++ b/litepcie/phy/m_axis_rc_adapt_x8.v @@ -0,0 +1,101 @@ + module m_axis_rc_adapt_x8 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_rc_tdata, + output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, + output m_axis_rc_tlast, + input [3:0] m_axis_rc_tready, + output [84:0] m_axis_rc_tuser, + output m_axis_rc_tvalid, + + input [DATA_WIDTH-1:0] m_axis_rc_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_rc_tkeep_a, + input m_axis_rc_tlast_a, + output [3:0] m_axis_rc_tready_a, + input [84:0] m_axis_rc_tuser_a, + input m_axis_rc_tvalid_a + ); + + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [7:0] m_axis_rc_tkeep_a; + wire [255:0] m_axis_rc_tdata_a; + wire [74:0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; + + reg [1:0] m_axis_rc_cnt; //0-2 + always @(posedge user_clk) + if (user_reset) m_axis_rc_cnt <= 2'd0; + else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) + begin + if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; + else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; + end + + wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] + wire m_axis_rc_second = m_axis_rc_cnt == 1; + + //header process + wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; + reg m_axis_rc_poisoning_l; + always @(posedge user_clk) + if (m_axis_rc_tvalid_a && m_axis_rc_sop) + begin + m_axis_rc_poisoning_l <= m_axis_rc_poisoning; + end + + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [4:0] m_axis_rc_type; + wire [2:0] m_axis_rc_fmt; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; + + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; + + assign {m_axis_rc_fmt, + m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data + 8'b010_01011) : //Read-Locked Completion w/ data + ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data + 8'b010_01010); //Completion w/ data + + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; + assign m_axis_rc_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/s_axis_cc_adapt_x8.v b/litepcie/phy/s_axis_cc_adapt_x8.v new file mode 100644 index 00000000..0bfc0775 --- /dev/null +++ b/litepcie/phy/s_axis_cc_adapt_x8.v @@ -0,0 +1,104 @@ + module s_axis_cc_adapt_x8 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + output s_axis_cc_tlast, + input [3:0] s_axis_cc_tready, + output [3:0] s_axis_cc_tuser, + output s_axis_cc_tvalid, + + input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + input s_axis_cc_tlast_a, + output [3:0] s_axis_cc_tready_a, + input [3:0] s_axis_cc_tuser_a, + input s_axis_cc_tvalid_a + ); + + wire s_axis_cc_tready_ff, + s_axis_cc_tvalid_ff, + s_axis_cc_tlast_ff; + wire [7:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[31:28], |s_axis_cc_tkeep[27:24], + |s_axis_cc_tkeep[23:20], |s_axis_cc_tkeep[19:16], + |s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; + + wire [3:0] s_axis_cc_tuser_ff; + wire [7:0] s_axis_cc_tkeep_ff; + wire [255:0] s_axis_cc_tdata_ff; + + axis_iff #(.DAT_B(256+8+4)) s_axis_cc_iff + ( + .clk (user_clk), + .rst (user_reset), + + .i_vld (s_axis_cc_tvalid), + .o_rdy (s_axis_cc_tready), + .i_sop (1'b0), + .i_eop (s_axis_cc_tlast), + .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), + + .o_vld (s_axis_cc_tvalid_ff), + .i_rdy (s_axis_cc_tready_ff), + .o_sop (), + .o_eop (s_axis_cc_tlast_ff), + .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) + ); + + reg [1:0] s_axis_cc_cnt; //0-2 + always @(posedge user_clk) + if (user_reset) s_axis_cc_cnt <= 2'd0; + else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) + begin + if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; + else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; + end + + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; + + wire [3:0] s_axis_cc_tready_a; + + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; + + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; + + wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + + assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; + wire [255:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + wire [7:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + +endmodule \ No newline at end of file diff --git a/litepcie/phy/s_axis_rq_adapt_x8.v b/litepcie/phy/s_axis_rq_adapt_x8.v new file mode 100644 index 00000000..46090f68 --- /dev/null +++ b/litepcie/phy/s_axis_rq_adapt_x8.v @@ -0,0 +1,146 @@ + module s_axis_rq_adapt_x8 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + output s_axis_rq_tlast, + input [3:0] s_axis_rq_tready, + output [3:0] s_axis_rq_tuser, + output s_axis_rq_tvalid, + + input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + input s_axis_rq_tlast_a, + output [3:0] s_axis_rq_tready_a, + input [3:0] s_axis_rq_tuser_a, + input s_axis_rq_tvalid_a + ); + + wire s_axis_rq_tready_ff, + s_axis_rq_tvalid_ff, + s_axis_rq_tlast_ff; + wire [7:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], + s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; + + wire [3:0] s_axis_rq_tuser_ff; + wire [7:0] s_axis_rq_tkeep_ff; + wire [255:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(256+8+4)) s_axis_rq_iff + ( + .clk (user_clk), + .rst (user_reset), + + .i_vld (s_axis_rq_tvalid), + .o_rdy (s_axis_rq_tready), + .i_sop (1'b0), + .i_eop (s_axis_rq_tlast), + .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), + + .o_vld (s_axis_rq_tvalid_ff), + .i_rdy (s_axis_rq_tready_ff), + .o_sop (), + .o_eop (s_axis_rq_tlast_ff), + .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) + ); + + + reg [1:0] s_axis_rq_cnt; //0-2 + always @(posedge user_clk) + if (user_reset) s_axis_rq_cnt <= 2'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + begin + if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; + else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; + end + + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; + + //processing for tlast: generate new last in case write & last num of dword = 5 + i*8 + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_write = !s_axis_rq_read; + reg s_axis_rq_tlast_dly_en; + reg s_axis_rq_tlast_lat; + wire [3:0] s_axis_rq_tready_a; + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); + + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + begin + if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd5) : 1'b0; //write 5 dwords + else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; + end + + wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + + //Generae ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request + s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request + s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request + s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 + s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 + 4'b1111; + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; + + always @(posedge user_clk) + begin + if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) + begin + s_axis_rq_firstbe_l <= s_axis_rq_firstbe; + s_axis_rq_lastbe_l <= s_axis_rq_lastbe; + end + end + + reg [31:0] s_axis_rq_tdata_l; + always @(posedge user_clk) + if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; + + wire [255:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : + {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; + wire [7:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; + wire [59:0] s_axis_rq_tuser_a; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 010c5b2f..b4bcdc1d 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -376,10 +376,17 @@ def add_ltssm_tracer(self): def add_sources(self, platform, phy_path, phy_filename): platform.add_ip(os.path.join(phy_path, phy_filename)) platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) + platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "..", "m_axis_rc_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "..", "m_axis_cq_adapt_x4.v")) platform.add_source(os.path.join(phy_path, "..", "s_axis_cc_adapt_x4.v")) + + platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "m_axis_rc_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "m_axis_cq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "s_axis_cc_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) # External Hard IP ----------------------------------------------------------------------------- diff --git a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v index 4e48034d..e60fe432 100644 --- a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v @@ -313,404 +313,115 @@ module pcie_support # ( //----------------------------------------------------------------------------------------------------------------// //----------------------------------------------------- RQ AXIS --------------------------------------------------// - wire s_axis_rq_tready_ff, - s_axis_rq_tvalid_ff, - s_axis_rq_tlast_ff; - wire [7:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], - s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; - - wire [3:0] s_axis_rq_tuser_ff; - wire [7:0] s_axis_rq_tkeep_ff; - wire [255:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(256+8+4)) s_axis_rq_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_rq_tvalid), - .o_rdy (s_axis_rq_tready), - .i_sop (1'b0), - .i_eop (s_axis_rq_tlast), - .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), - - .o_vld (s_axis_rq_tvalid_ff), - .i_rdy (s_axis_rq_tready_ff), - .o_sop (), - .o_eop (s_axis_rq_tlast_ff), - .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) - ); - - - reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; - end - - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - - //processing for tlast: generate new last in case write & last num of dword = 5 + i*8 - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); - - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) - begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd5) : 1'b0; //write 5 dwords - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; - end - - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; - always @(posedge user_clk_out) - begin - if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) - begin - s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; - end - end - - reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) - if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; - - wire [255:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : - {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; - wire [7:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; + s_axis_rq_adapt_x8 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_rq_adapt_x8_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_rq_tdata(s_axis_rq_tdata), + .s_axis_rq_tkeep(s_axis_rq_tkeep), + .s_axis_rq_tlast(s_axis_rq_tlast), + .s_axis_rq_tready(s_axis_rq_tready), + .s_axis_rq_tuser(s_axis_rq_tuser), + .s_axis_rq_tvalid(s_axis_rq_tvalid), + + .s_axis_rq_tdata_a(s_axis_rq_tdata_a), + .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), + .s_axis_rq_tlast_a(s_axis_rq_tlast_a), + .s_axis_rq_tready_a(s_axis_rq_tready_a), + .s_axis_rq_tuser_a(s_axis_rq_tuser_a), + .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) + ); //----------------------------------------------------- RC AXIS --------------------------------------------------// + wire m_axis_rc_tvalid_a; wire m_axis_rc_tready_a; wire [7:0] m_axis_rc_tkeep_a; - wire [255:0] m_axis_rc_tdata_a; + wire [127:0] m_axis_rc_tdata_a; wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; - else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) - begin - if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; - else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; - end - - wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] - wire m_axis_rc_second = m_axis_rc_cnt == 1; - - //header process - wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; - reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) - if (m_axis_rc_tvalid_a && m_axis_rc_sop) - begin - m_axis_rc_poisoning_l <= m_axis_rc_poisoning; - end - - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; - wire [4:0] m_axis_rc_type; - wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; - wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; - wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; - - assign {m_axis_rc_fmt, - m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data - 8'b010_01011) : //Read-Locked Completion w/ data - ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data - 8'b010_01010); //Completion w/ data - - wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen}; - wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr}; - - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; - assign m_axis_rc_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + m_axis_rc_adapt_x8 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_rc_adapt_x8_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_rc_tdata( m_axis_rc_tdata), + .m_axis_rc_tkeep( m_axis_rc_tkeep), + .m_axis_rc_tlast( m_axis_rc_tlast), + .m_axis_rc_tready(m_axis_rc_tready), + .m_axis_rc_tuser( m_axis_rc_tuser), + .m_axis_rc_tvalid(m_axis_rc_tvalid), + + .m_axis_rc_tdata_a( m_axis_rc_tdata_a), + .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), + .m_axis_rc_tlast_a( m_axis_rc_tlast_a), + .m_axis_rc_tready_a(m_axis_rc_tready_a), + .m_axis_rc_tuser_a( m_axis_rc_tuser_a), + .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) + ); //----------------------------------------------------- CQ AXIS --------------------------------------------------// + wire m_axis_cq_tvalid_a; wire m_axis_cq_tready_a; wire [7:0] m_axis_cq_tkeep_a; - wire [255:0] m_axis_cq_tdata_a; + wire [127:0] m_axis_cq_tdata_a; wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch - reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; - else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; - end + m_axis_cq_adapt_x8 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_cq_adapt_x8_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_cq_tdata( m_axis_cq_tdata), + .m_axis_cq_tkeep( m_axis_cq_tkeep), + .m_axis_cq_tlast( m_axis_cq_tlast), + .m_axis_cq_tready(m_axis_cq_tready), + .m_axis_cq_tuser( m_axis_cq_tuser), + .m_axis_cq_tvalid(m_axis_cq_tvalid), + + .m_axis_cq_tdata_a( s_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( s_axis_cq_tlast_a), + .m_axis_cq_tready_a(s_axis_cq_tready_a), + .m_axis_cq_tuser_a( s_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + ); - wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] - wire m_axis_cq_second = m_axis_cq_cnt == 1; - - reg m_axis_cq_rdwr_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_rdwr_l <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_rdwr_l <= m_axis_cq_tlast_a; - - //processing for tlast: generate new last in case write & last num of dword != 5 + i*8 - wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request - wire m_axis_cq_write = !m_axis_cq_read; - wire [9:0] m_axis_cq_dwlen; - reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tlast_dly_en <= m_axis_cq_tlast_a | (m_axis_cq_dwlen[2:0] != 3'd5); - - reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) - begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; - else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; - end - - //Generae ready for PCIe IP - assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); - - //output for TLP - assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; - assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; - - - ////keep address (low) or data (high), not header - reg [255:0] m_axis_cq_tdata_a1; - reg [31:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; - m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[39:8]; - end - - //data processing - wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; - wire [4:0] m_axis_cq_type; - wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; - wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; - - assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request - m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked - m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request - m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request - m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request - m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 - m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 - 8'b000_00000; //Mem read Request - - reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop - - reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = {m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen}; - - assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : - {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:32]}; - assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[31:16], 12'hFFF} : - m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[31:4]} : 32'hFFFF_FFFF; - assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_tuser_a[41] //ECRC mapped to discontinue - }; //----------------------------------------------------- CC AXIS --------------------------------------------------// - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; - wire [7:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[31:28], |s_axis_cc_tkeep[27:24], - |s_axis_cc_tkeep[23:20], |s_axis_cc_tkeep[19:16], - |s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; - - wire [3:0] s_axis_cc_tuser_ff; - wire [7:0] s_axis_cc_tkeep_ff; - wire [255:0] s_axis_cc_tdata_ff; - - axis_iff #(.DAT_B(256+8+4)) s_axis_cc_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_cc_tvalid), - .o_rdy (s_axis_cc_tready), - .i_sop (1'b0), - .i_eop (s_axis_cc_tlast), - .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), - - .o_vld (s_axis_cc_tvalid_ff), - .i_rdy (s_axis_cc_tready_ff), - .o_sop (), - .o_eop (s_axis_cc_tlast_ff), - .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) - ); - - reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; - else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; - end - - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; - wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; - wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; - wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; - wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr}; - wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; - - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [255:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [7:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + + s_axis_cc_adapt_x8 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_cc_adapt_x8_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_cc_tdata(s_axis_cc_tdata), + .s_axis_cc_tkeep(s_axis_cc_tkeep), + .s_axis_cc_tlast(s_axis_cc_tlast), + .s_axis_cc_tready(s_axis_cc_tready), + .s_axis_cc_tuser(s_axis_cc_tuser), + .s_axis_cc_tvalid(s_axis_cc_tvalid), + + .s_axis_cc_tdata_a(s_axis_cc_tdata_a), + .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), + .s_axis_cc_tlast_a(s_axis_cc_tlast_a), + .s_axis_cc_tready_a(s_axis_cc_tready_a), + .s_axis_cc_tuser_a(s_axis_cc_tuser_a), + .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) + ); //---------------------------------------------------------------------------------------------------------------// // MSI Adaptation Logic // From 390d21982bc5e9042c33a0499f6da23bc52cf903 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 18:06:20 +0200 Subject: [PATCH 08/41] phy/xilinx_us: Increase similarities between x4/x8. --- litepcie/phy/m_axis_cq_adapt_x4.v | 18 +++++++++--------- litepcie/phy/m_axis_cq_adapt_x8.v | 18 +++++++++--------- litepcie/phy/m_axis_rc_adapt_x8.v | 7 ------- litepcie/phy/s_axis_cc_adapt_x4.v | 18 +++++++++++------- litepcie/phy/s_axis_cc_adapt_x8.v | 24 +++++++++++++++--------- litepcie/phy/s_axis_rq_adapt_x4.v | 25 +++++++++++++++---------- litepcie/phy/s_axis_rq_adapt_x8.v | 30 +++++++++++++++++++----------- 7 files changed, 78 insertions(+), 62 deletions(-) diff --git a/litepcie/phy/m_axis_cq_adapt_x4.v b/litepcie/phy/m_axis_cq_adapt_x4.v index 79f2944a..93ee38c9 100644 --- a/litepcie/phy/m_axis_cq_adapt_x4.v +++ b/litepcie/phy/m_axis_cq_adapt_x4.v @@ -21,12 +21,12 @@ input m_axis_cq_tvalid_a ); - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [3:0] m_axis_cq_tkeep_a; - wire [127:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a; + wire [DATA_WIDTH-1:0] m_axis_cq_tdata_a; + wire [84:0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; //dword counter: //0-2 & latch reg [1:0] m_axis_cq_cnt; @@ -66,7 +66,7 @@ else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; end @@ -79,8 +79,8 @@ ////keep address (low) or data (high), not header - reg [127:0] m_axis_cq_tdata_a1; - reg [15:0] m_axis_cq_tlast_be1; + reg [DATA_WIDTH-1:0] m_axis_cq_tdata_a1; + reg [DATA_WIDTH/8-1:0] m_axis_cq_tlast_be1; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin diff --git a/litepcie/phy/m_axis_cq_adapt_x8.v b/litepcie/phy/m_axis_cq_adapt_x8.v index 038e99b4..9ff8bd21 100644 --- a/litepcie/phy/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/m_axis_cq_adapt_x8.v @@ -21,12 +21,12 @@ input m_axis_cq_tvalid_a ); - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [7:0] m_axis_cq_tkeep_a; - wire [255:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a; + wire [DATA_WIDTH-1:0] m_axis_cq_tdata_a; + wire [84:0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; //dword counter: //0-2 & latch reg [1:0] m_axis_cq_cnt; @@ -62,7 +62,7 @@ else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; end @@ -75,8 +75,8 @@ ////keep address (low) or data (high), not header - reg [255:0] m_axis_cq_tdata_a1; - reg [31:0] m_axis_cq_tlast_be1; + reg [DATA_WIDTH-1:0] m_axis_cq_tdata_a1; + reg [DATA_WIDTH/8-1:0] m_axis_cq_tlast_be1; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin diff --git a/litepcie/phy/m_axis_rc_adapt_x8.v b/litepcie/phy/m_axis_rc_adapt_x8.v index 6f030512..4dd6399a 100644 --- a/litepcie/phy/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/m_axis_rc_adapt_x8.v @@ -21,13 +21,6 @@ input m_axis_rc_tvalid_a ); - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [7:0] m_axis_rc_tkeep_a; - wire [255:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - reg [1:0] m_axis_rc_cnt; //0-2 always @(posedge user_clk) if (user_reset) m_axis_rc_cnt <= 2'd0; diff --git a/litepcie/phy/s_axis_cc_adapt_x4.v b/litepcie/phy/s_axis_cc_adapt_x4.v index 0984c84e..36adebff 100644 --- a/litepcie/phy/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/s_axis_cc_adapt_x4.v @@ -24,14 +24,18 @@ wire s_axis_cc_tready_ff, s_axis_cc_tvalid_ff, s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; + wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_or = { + |s_axis_cc_tkeep[15:12], + |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], + |s_axis_cc_tkeep[3:0] + }; wire [3:0] s_axis_cc_tuser_ff; - wire [3:0] s_axis_cc_tkeep_ff; - wire [127:0] s_axis_cc_tdata_ff; + wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_ff; + wire [DATA_WIDTH-1:0] s_axis_cc_tdata_ff; - axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff + axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_cc_iff ( .clk (user_clk), .rst (user_reset), @@ -105,9 +109,9 @@ wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [127:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + wire [DATA_WIDTH-1:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/s_axis_cc_adapt_x8.v b/litepcie/phy/s_axis_cc_adapt_x8.v index 0bfc0775..2c2d3f8a 100644 --- a/litepcie/phy/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/s_axis_cc_adapt_x8.v @@ -24,16 +24,22 @@ wire s_axis_cc_tready_ff, s_axis_cc_tvalid_ff, s_axis_cc_tlast_ff; - wire [7:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[31:28], |s_axis_cc_tkeep[27:24], - |s_axis_cc_tkeep[23:20], |s_axis_cc_tkeep[19:16], - |s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; + wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_or = { + |s_axis_cc_tkeep[31:28], + |s_axis_cc_tkeep[27:24], + |s_axis_cc_tkeep[23:20], + |s_axis_cc_tkeep[19:16], + |s_axis_cc_tkeep[15:12], + |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], + |s_axis_cc_tkeep[3:0] + }; wire [3:0] s_axis_cc_tuser_ff; - wire [7:0] s_axis_cc_tkeep_ff; - wire [255:0] s_axis_cc_tdata_ff; + wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_ff; + wire [DATA_WIDTH-1:0] s_axis_cc_tdata_ff; - axis_iff #(.DAT_B(256+8+4)) s_axis_cc_iff + axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_cc_iff ( .clk (user_clk), .rst (user_reset), @@ -96,9 +102,9 @@ wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [255:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + wire [DATA_WIDTH-1:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [7:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + wire [KEEP_WIDTH:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/s_axis_rq_adapt_x4.v b/litepcie/phy/s_axis_rq_adapt_x4.v index d5d236be..de63d82c 100644 --- a/litepcie/phy/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/s_axis_rq_adapt_x4.v @@ -24,13 +24,18 @@ wire s_axis_rq_tready_ff, s_axis_rq_tvalid_ff, s_axis_rq_tlast_ff; - wire [3:0] s_axis_rq_tkeep_or = {|s_axis_rq_tkeep[15:12], |s_axis_rq_tkeep[11:8], |s_axis_rq_tkeep[7:4], |s_axis_rq_tkeep[3:0]}; - - wire [3:0] s_axis_rq_tuser_ff; - wire [3:0] s_axis_rq_tkeep_ff; - wire [127:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff + wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_or = { + |s_axis_rq_tkeep[15:12], + |s_axis_rq_tkeep[11:8], + |s_axis_rq_tkeep[7:4], + |s_axis_rq_tkeep[3:0] + }; + + wire [3:0] s_axis_rq_tuser_ff; + wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_ff; + wire [DATA_WIDTH-1:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_rq_iff ( .clk (user_clk), .rst (user_reset), @@ -61,7 +66,7 @@ wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - //processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... + //processing for tlast: generate new last in case write & last num of dword = 5 + i*4 wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request wire s_axis_rq_write = !s_axis_rq_read; reg s_axis_rq_tlast_dly_en; @@ -135,8 +140,8 @@ if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; - wire [127:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; - wire [3:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; //{s_axis_rq_tkeep_ff[2:0], 1'b1}; + wire [DATA_WIDTH-1:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; + wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; //{s_axis_rq_tkeep_ff[2:0], 1'b1}; wire [59:0] s_axis_rq_tuser_a; assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; diff --git a/litepcie/phy/s_axis_rq_adapt_x8.v b/litepcie/phy/s_axis_rq_adapt_x8.v index 46090f68..4b417963 100644 --- a/litepcie/phy/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/s_axis_rq_adapt_x8.v @@ -21,17 +21,25 @@ input s_axis_rq_tvalid_a ); - wire s_axis_rq_tready_ff, + wire s_axis_rq_tready_ff, s_axis_rq_tvalid_ff, s_axis_rq_tlast_ff; - wire [7:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], - s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; - - wire [3:0] s_axis_rq_tuser_ff; - wire [7:0] s_axis_rq_tkeep_ff; - wire [255:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(256+8+4)) s_axis_rq_iff + wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_or = { + s_axis_rq_tkeep[28], + s_axis_rq_tkeep[24], + s_axis_rq_tkeep[20], + s_axis_rq_tkeep[16], + s_axis_rq_tkeep[12], + s_axis_rq_tkeep[8], + s_axis_rq_tkeep[4], + s_axis_rq_tkeep[0] + }; + + wire [3:0] s_axis_rq_tuser_ff; + wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_ff; + wire [DATA_WIDTH-1:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_rq_iff ( .clk (user_clk), .rst (user_reset), @@ -136,9 +144,9 @@ if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; - wire [255:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : + wire [DATA_WIDTH-1:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; - wire [7:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; + wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; wire [59:0] s_axis_rq_tuser_a; assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; From c096d3eab3c7949739c6242ba31ff7ab603b25eb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 18:55:28 +0200 Subject: [PATCH 09/41] phy/xilinx_us: Cleanup axis adapters. --- litepcie/phy/m_axis_cq_adapt_x4.v | 51 ++++++++++----------- litepcie/phy/m_axis_cq_adapt_x8.v | 51 ++++++++++----------- litepcie/phy/m_axis_rc_adapt_x4.v | 74 ++++++++++++++++--------------- litepcie/phy/m_axis_rc_adapt_x8.v | 74 ++++++++++++++++--------------- litepcie/phy/s_axis_cc_adapt_x4.v | 51 +++++++++++---------- litepcie/phy/s_axis_cc_adapt_x8.v | 73 +++++++++++++++--------------- litepcie/phy/s_axis_rq_adapt_x4.v | 52 +++++++++++----------- litepcie/phy/s_axis_rq_adapt_x8.v | 64 +++++++++++++------------- 8 files changed, 249 insertions(+), 241 deletions(-) diff --git a/litepcie/phy/m_axis_cq_adapt_x4.v b/litepcie/phy/m_axis_cq_adapt_x4.v index 93ee38c9..9a1c3467 100644 --- a/litepcie/phy/m_axis_cq_adapt_x4.v +++ b/litepcie/phy/m_axis_cq_adapt_x4.v @@ -21,13 +21,6 @@ input m_axis_cq_tvalid_a ); - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a; - wire [DATA_WIDTH-1:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch reg [1:0] m_axis_cq_cnt; always @(posedge user_clk) @@ -91,15 +84,15 @@ //data processing wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; wire [4:0] m_axis_cq_type; wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request @@ -127,13 +120,15 @@ reg [63:0] m_axis_cq_header; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = {m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen}; + m_axis_cq_header = { + m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen + }; wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : @@ -144,12 +139,12 @@ assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_ecrc //ECRC mapped to discontinue - }; + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_ecrc //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/m_axis_cq_adapt_x8.v b/litepcie/phy/m_axis_cq_adapt_x8.v index 9ff8bd21..d5f20b45 100644 --- a/litepcie/phy/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/m_axis_cq_adapt_x8.v @@ -21,13 +21,6 @@ input m_axis_cq_tvalid_a ); - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a; - wire [DATA_WIDTH-1:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch reg [1:0] m_axis_cq_cnt; always @(posedge user_clk) @@ -87,15 +80,15 @@ //data processing wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; wire [4:0] m_axis_cq_type; wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request @@ -117,25 +110,27 @@ reg [63:0] m_axis_cq_header; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = {m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen}; + m_axis_cq_header = { + m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen + }; assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:32]}; assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[31:16], 12'hFFF} : m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[31:4]} : 32'hFFFF_FFFF; assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_tuser_a[41] //ECRC mapped to discontinue - }; + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_tuser_a[41] //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/m_axis_rc_adapt_x4.v b/litepcie/phy/m_axis_rc_adapt_x4.v index 6ad8c050..3c0e94a8 100644 --- a/litepcie/phy/m_axis_rc_adapt_x4.v +++ b/litepcie/phy/m_axis_rc_adapt_x4.v @@ -42,20 +42,20 @@ m_axis_rc_poisoning_l <= m_axis_rc_poisoning; end - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; wire [4:0] m_axis_rc_type; wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; assign {m_axis_rc_fmt, @@ -64,32 +64,36 @@ ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data 8'b010_01010); //Completion w/ data - wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen}; - wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr}; + wire [63:0] m_axis_rc_header0 = { + m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen + }; + wire [63:0] m_axis_rc_header1 = { + m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr + }; - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; - assign m_axis_rc_tuser = { - 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; + assign m_axis_rc_tuser = { + 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/m_axis_rc_adapt_x8.v b/litepcie/phy/m_axis_rc_adapt_x8.v index 4dd6399a..1126d218 100644 --- a/litepcie/phy/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/m_axis_rc_adapt_x8.v @@ -42,20 +42,20 @@ m_axis_rc_poisoning_l <= m_axis_rc_poisoning; end - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; wire [4:0] m_axis_rc_type; wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; assign {m_axis_rc_fmt, @@ -64,31 +64,35 @@ ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data 8'b010_01010); //Completion w/ data - wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen}; - wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr}; + wire [63:0] m_axis_rc_header0 = { + m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen + }; + wire [63:0] m_axis_rc_header1 = { + m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr + }; - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; - assign m_axis_rc_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; + assign m_axis_rc_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/s_axis_cc_adapt_x4.v b/litepcie/phy/s_axis_cc_adapt_x4.v index 36adebff..b9e447e5 100644 --- a/litepcie/phy/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/s_axis_cc_adapt_x4.v @@ -62,38 +62,41 @@ else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; end - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; wire [3:0] s_axis_cc_tready_a; - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr}; - wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = { + s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr + }; + wire [63:0] s_axis_cc_header1 = { + s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; reg [3:0] s_axis_cc_firstbe; reg [3:0] s_axis_cc_lastbe; diff --git a/litepcie/phy/s_axis_cc_adapt_x8.v b/litepcie/phy/s_axis_cc_adapt_x8.v index 2c2d3f8a..3dabf845 100644 --- a/litepcie/phy/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/s_axis_cc_adapt_x8.v @@ -21,23 +21,23 @@ input s_axis_cc_tvalid_a ); - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; + wire s_axis_cc_tready_ff, + s_axis_cc_tvalid_ff, + s_axis_cc_tlast_ff; wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_or = { - |s_axis_cc_tkeep[31:28], - |s_axis_cc_tkeep[27:24], + |s_axis_cc_tkeep[31:28], + |s_axis_cc_tkeep[27:24], |s_axis_cc_tkeep[23:20], - |s_axis_cc_tkeep[19:16], + |s_axis_cc_tkeep[19:16], |s_axis_cc_tkeep[15:12], - |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[11:8], |s_axis_cc_tkeep[7:4], - |s_axis_cc_tkeep[3:0] + |s_axis_cc_tkeep[3:0] }; - wire [3:0] s_axis_cc_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_ff; + wire [3 :0] s_axis_cc_tuser_ff; + wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_ff; + wire [DATA_WIDTH-1:0] s_axis_cc_tdata_ff; axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_cc_iff ( @@ -66,38 +66,41 @@ else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; end - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; wire [3:0] s_axis_cc_tready_a; - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr}; - wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = { + s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr + }; + wire [63:0] s_axis_cc_header1 = { + s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; diff --git a/litepcie/phy/s_axis_rq_adapt_x4.v b/litepcie/phy/s_axis_rq_adapt_x4.v index de63d82c..8b57b0a0 100644 --- a/litepcie/phy/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/s_axis_rq_adapt_x4.v @@ -25,10 +25,10 @@ s_axis_rq_tvalid_ff, s_axis_rq_tlast_ff; wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_or = { - |s_axis_rq_tkeep[15:12], - |s_axis_rq_tkeep[11:8], - |s_axis_rq_tkeep[7:4], - |s_axis_rq_tkeep[3:0] + |s_axis_rq_tkeep[15:12], + |s_axis_rq_tkeep[11:8], + |s_axis_rq_tkeep[7:4], + |s_axis_rq_tkeep[3:0] }; wire [3:0] s_axis_rq_tuser_ff; @@ -103,28 +103,30 @@ s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = { + s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen + }; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; always @(posedge user_clk) begin diff --git a/litepcie/phy/s_axis_rq_adapt_x8.v b/litepcie/phy/s_axis_rq_adapt_x8.v index 4b417963..a3e62307 100644 --- a/litepcie/phy/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/s_axis_rq_adapt_x8.v @@ -25,14 +25,14 @@ s_axis_rq_tvalid_ff, s_axis_rq_tlast_ff; wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_or = { - s_axis_rq_tkeep[28], - s_axis_rq_tkeep[24], - s_axis_rq_tkeep[20], - s_axis_rq_tkeep[16], + s_axis_rq_tkeep[28], + s_axis_rq_tkeep[24], + s_axis_rq_tkeep[20], + s_axis_rq_tkeep[16], s_axis_rq_tkeep[12], - s_axis_rq_tkeep[8], - s_axis_rq_tkeep[4], - s_axis_rq_tkeep[0] + s_axis_rq_tkeep[8], + s_axis_rq_tkeep[4], + s_axis_rq_tkeep[0] }; wire [3:0] s_axis_rq_tuser_ff; @@ -67,11 +67,11 @@ else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; end - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; //processing for tlast: generate new last in case write & last num of dword = 5 + i*8 - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request wire s_axis_rq_write = !s_axis_rq_read; reg s_axis_rq_tlast_dly_en; reg s_axis_rq_tlast_lat; @@ -94,7 +94,7 @@ //Generae ready for TLP assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request @@ -107,28 +107,30 @@ s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = { + s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen + }; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; always @(posedge user_clk) begin From 872b1b1bda5dc8e0c4f08f6f6fe89c2c61be9ca8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 19:12:57 +0200 Subject: [PATCH 10/41] phy/s7pciephy: Indent tcl config. --- litepcie/phy/s7pciephy.py | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/litepcie/phy/s7pciephy.py b/litepcie/phy/s7pciephy.py index ff6b5792..159438e9 100644 --- a/litepcie/phy/s7pciephy.py +++ b/litepcie/phy/s7pciephy.py @@ -435,24 +435,24 @@ def add_sources(self, platform, phy_path, phy_filename=None): platform.add_ip(os.path.join(phy_path, phy_filename)) else: config = { - "Bar0_Scale" : "Megabytes", - "Bar0_Size" : 1, - "Buf_Opt_BMA" : True, - "Component_Name" : "pcie", - "Device_ID" : 7020 + self.nlanes, - "IntX_Generation" : False, - "Interface_Width" : f"{self.pcie_data_width}_bit", - "Legacy_Interrupt" : None, - "Multiple_Message_Capable" : '1_vector', - "Link_Speed" : "5.0_GT/s", - "MSI_64b" : False, - "Max_Payload_Size" : "512_bytes" if self.nlanes != 8 else "256_bytes", - "Maximum_Link_Width" : f"X{self.nlanes}", - "PCIe_Blk_Locn" : "X0Y0", - "Ref_Clk_Freq" : "100_MHz", - "Trans_Buf_Pipeline" : None, - "Trgt_Link_Speed" : "4'h2", - "User_Clk_Freq" : 125 if self.nlanes != 8 else 250, + "Bar0_Scale" : "Megabytes", + "Bar0_Size" : 1, + "Buf_Opt_BMA" : True, + "Component_Name" : "pcie", + "Device_ID" : 7020 + self.nlanes, + "IntX_Generation" : False, + "Interface_Width" : f"{self.pcie_data_width}_bit", + "Legacy_Interrupt" : None, + "Multiple_Message_Capable" : '1_vector', + "Link_Speed" : "5.0_GT/s", + "MSI_64b" : False, + "Max_Payload_Size" : "512_bytes" if self.nlanes != 8 else "256_bytes", + "Maximum_Link_Width" : f"X{self.nlanes}", + "PCIe_Blk_Locn" : "X0Y0", + "Ref_Clk_Freq" : "100_MHz", + "Trans_Buf_Pipeline" : None, + "Trgt_Link_Speed" : "4'h2", + "User_Clk_Freq" : 125 if self.nlanes != 8 else 250, } ip_tcl = [] ip_tcl.append("create_ip -vendor xilinx.com -name pcie_7x -module_name pcie_s7") From b0b485654828b60f50a79b911a40caba0dd98030 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 19:28:18 +0200 Subject: [PATCH 11/41] phy/xilix_us(p)_gen: Add missing axis_ff.v. --- litepcie/phy/axis_iff.v | 106 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 litepcie/phy/axis_iff.v diff --git a/litepcie/phy/axis_iff.v b/litepcie/phy/axis_iff.v new file mode 100644 index 00000000..bc0796f2 --- /dev/null +++ b/litepcie/phy/axis_iff.v @@ -0,0 +1,106 @@ +module axis_iff + #( + parameter DAT_B = 32 + ) + ( + input clk, + input rst, + + input i_vld, + output o_rdy, + input i_sop, + input i_eop, + input [DAT_B-1:0] i_dat, + + + output o_vld, + input i_rdy, + output o_sop, + output o_eop, + output [DAT_B-1:0] o_dat + ); + + /////////////////////////////////////////////////////////////////////////// + //FIFO instance + localparam FF_B = 8; + localparam FF_L = 256; + + wire ff_empt, ff_full; + reg [FF_B:0] ff_len; + + wire ff_wr, ff_rd; + + reg [FF_B-1:0] wrcnt; + always @(posedge clk) + if (rst) wrcnt <= {FF_B{1'b0}}; + else if (ff_wr) wrcnt <= wrcnt + 1; + + always @(posedge clk) + if (rst) ff_len <= {FF_B+1{1'b0}}; + else + case ({ff_wr, ff_rd}) + 2'b10: ff_len <= ff_len + 1; + 2'b01: ff_len <= ff_len - 1; + default: ff_len <= ff_len; + endcase + + wire [FF_B-1:0] rdcnt; + assign rdcnt = wrcnt - ff_len[FF_B-1:0]; + + wire [FF_B-1:0] rda, wra; + assign rda = ff_rd ? (rdcnt + 1) : rdcnt; + assign wra = wrcnt; + + wire [DAT_B+1:0] ff_wdat; + wire [DAT_B+1:0] ff_rdat; + assign ff_wdat = {i_sop, i_eop, i_dat}; + assign {o_sop, o_eop, o_dat} = ff_rdat; + assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); + assign o_vld = (pktcnt > 0); + + reg [3:0] pktcnt; + assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); + assign ff_rd = i_rdy & (pktcnt > 0); + + /////////////////////////////////////////////////////////////////////////// + //Single dual port RAM 1-clock + + (* ram_style="block" *) + reg [DAT_B+1:0] ram [FF_L-1:0]; + + always @(posedge clk) + if (ff_wr) ram[wra] <= ff_wdat; + + reg [DAT_B+1:0] ff_rdat_m; + always @(posedge clk) + ff_rdat_m <= ram[rda]; + + /////////////////////////////////////////////////////////////////////////// + //same read/write + + wire readsame = ff_wr & (wra == rda); + reg readsame1; + always @(posedge clk) + if (rst) readsame1 <= 1'b0; + else readsame1 <= readsame; + + reg [DAT_B+1:0] ff_wdat1; + always @(posedge clk) + ff_wdat1 <= ff_wdat; + + assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; + + /////////////////////////////////////////////////////////////////////////// + //Store max 8 packet + + always @(posedge clk) + if (rst) pktcnt <= 4'd0; + else begin + case ({(ff_wr & i_eop), (ff_rd & o_eop)}) + 2'b10: pktcnt <= pktcnt + 1; + 2'b01: pktcnt <= pktcnt - 1; + default: pktcnt <= pktcnt; + endcase + end + +endmodule \ No newline at end of file From c19ceb251e94d811c7c543aaae92f782b2f750b5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Apr 2023 19:42:44 +0200 Subject: [PATCH 12/41] phy/upciephy: Add ip_tcl config/build-time generation to avoid .xci files. --- litepcie/phy/s7pciephy.py | 2 +- litepcie/phy/uspciephy.py | 34 ++++++++++++++++++++++++++++++---- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/litepcie/phy/s7pciephy.py b/litepcie/phy/s7pciephy.py index 159438e9..9d85147e 100644 --- a/litepcie/phy/s7pciephy.py +++ b/litepcie/phy/s7pciephy.py @@ -481,6 +481,6 @@ def do_finalize(self): if not self.external_hard_ip: phy_path = "xilinx_s7_gen2" self.add_sources(self.platform, - phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), + phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), ) self.specials += Instance("pcie_s7", **self.pcie_phy_params) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index b4bcdc1d..29aaf92d 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -373,8 +373,35 @@ def add_ltssm_tracer(self): self.ltssm_tracer = LTSSMTracer(self._link_status.fields.ltssm) # Hard IP sources ------------------------------------------------------------------------------ - def add_sources(self, platform, phy_path, phy_filename): - platform.add_ip(os.path.join(phy_path, phy_filename)) + def add_sources(self, platform, phy_path, phy_filename=None): + if phy_filename is not None: + platform.add_ip(os.path.join(phy_path, phy_filename)) + else: + # FIXME: Add missing parameters? + config = { + "pf0_bar0_scale" : "Megabytes", + "pf0_bar0_size" : 1, + "PF0_INTERRUPT_PIN" : "NONE", + "PL_LINK_CAP_MAX_LINK_WIDTH" : f"X{self.nlanes}", + "PL_LINK_CAP_MAX_LINK_SPEED" : "8.0_GT/s", # CHECKME. + "axisten_if_width" : f"{self.pcie_data_width}_bit", + "AXISTEN_IF_RC_STRADDLE" : True, + "PF0_DEVICE_ID" : 8030 + self.nlanes, + "axisten_freq" : 250, # CHECKME. + "aspm_support" : "No_ASPM", + "coreclk_freq" : 500, # CHECKME. + "plltype" : "QPLL1", + } + ip_tcl = [] + ip_tcl.append("create_ip -vendor xilinx.com -name pcie3_ultrascale -module_name pcie_us") + ip_tcl.append("set obj [get_ips pcie_us]") + ip_tcl.append("set_property -dict [list \\") + for config, value in config.items(): + ip_tcl.append("CONFIG.{} {} \\".format(config, '{{' + str(value) + '}}')) + ip_tcl.append(f"] $obj") + ip_tcl.append("synth_ip $obj") + platform.toolchain.pre_synthesis_commands += ip_tcl + platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x4.v")) @@ -399,7 +426,6 @@ def do_finalize(self): if not self.external_hard_ip: phy_path = "xilinx_us_{}_x{}".format(self.speed, self.nlanes) self.add_sources(self.platform, - phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), - phy_filename = "pcie_us.xci" + phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), ) self.specials += Instance("pcie_support", **self.pcie_phy_params) From 5cb60832bf52f9bc6bc84e1ff31756cefe9eb715 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 09:18:09 +0200 Subject: [PATCH 13/41] phy/xilinx_us: Move axis adaptation files to xilinx_us directory. --- litepcie/phy/axis_iff.v | 106 ------------------ litepcie/phy/uspciephy.py | 18 +-- .../phy/{ => xilinx_us}/m_axis_cq_adapt_x4.v | 0 .../phy/{ => xilinx_us}/m_axis_cq_adapt_x8.v | 0 .../phy/{ => xilinx_us}/m_axis_rc_adapt_x4.v | 0 .../phy/{ => xilinx_us}/m_axis_rc_adapt_x8.v | 0 .../phy/{ => xilinx_us}/s_axis_cc_adapt_x4.v | 0 .../phy/{ => xilinx_us}/s_axis_cc_adapt_x8.v | 0 .../phy/{ => xilinx_us}/s_axis_rq_adapt_x4.v | 0 .../phy/{ => xilinx_us}/s_axis_rq_adapt_x8.v | 0 10 files changed, 9 insertions(+), 115 deletions(-) delete mode 100644 litepcie/phy/axis_iff.v rename litepcie/phy/{ => xilinx_us}/m_axis_cq_adapt_x4.v (100%) rename litepcie/phy/{ => xilinx_us}/m_axis_cq_adapt_x8.v (100%) rename litepcie/phy/{ => xilinx_us}/m_axis_rc_adapt_x4.v (100%) rename litepcie/phy/{ => xilinx_us}/m_axis_rc_adapt_x8.v (100%) rename litepcie/phy/{ => xilinx_us}/s_axis_cc_adapt_x4.v (100%) rename litepcie/phy/{ => xilinx_us}/s_axis_cc_adapt_x8.v (100%) rename litepcie/phy/{ => xilinx_us}/s_axis_rq_adapt_x4.v (100%) rename litepcie/phy/{ => xilinx_us}/s_axis_rq_adapt_x8.v (100%) diff --git a/litepcie/phy/axis_iff.v b/litepcie/phy/axis_iff.v deleted file mode 100644 index bc0796f2..00000000 --- a/litepcie/phy/axis_iff.v +++ /dev/null @@ -1,106 +0,0 @@ -module axis_iff - #( - parameter DAT_B = 32 - ) - ( - input clk, - input rst, - - input i_vld, - output o_rdy, - input i_sop, - input i_eop, - input [DAT_B-1:0] i_dat, - - - output o_vld, - input i_rdy, - output o_sop, - output o_eop, - output [DAT_B-1:0] o_dat - ); - - /////////////////////////////////////////////////////////////////////////// - //FIFO instance - localparam FF_B = 8; - localparam FF_L = 256; - - wire ff_empt, ff_full; - reg [FF_B:0] ff_len; - - wire ff_wr, ff_rd; - - reg [FF_B-1:0] wrcnt; - always @(posedge clk) - if (rst) wrcnt <= {FF_B{1'b0}}; - else if (ff_wr) wrcnt <= wrcnt + 1; - - always @(posedge clk) - if (rst) ff_len <= {FF_B+1{1'b0}}; - else - case ({ff_wr, ff_rd}) - 2'b10: ff_len <= ff_len + 1; - 2'b01: ff_len <= ff_len - 1; - default: ff_len <= ff_len; - endcase - - wire [FF_B-1:0] rdcnt; - assign rdcnt = wrcnt - ff_len[FF_B-1:0]; - - wire [FF_B-1:0] rda, wra; - assign rda = ff_rd ? (rdcnt + 1) : rdcnt; - assign wra = wrcnt; - - wire [DAT_B+1:0] ff_wdat; - wire [DAT_B+1:0] ff_rdat; - assign ff_wdat = {i_sop, i_eop, i_dat}; - assign {o_sop, o_eop, o_dat} = ff_rdat; - assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); - assign o_vld = (pktcnt > 0); - - reg [3:0] pktcnt; - assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); - assign ff_rd = i_rdy & (pktcnt > 0); - - /////////////////////////////////////////////////////////////////////////// - //Single dual port RAM 1-clock - - (* ram_style="block" *) - reg [DAT_B+1:0] ram [FF_L-1:0]; - - always @(posedge clk) - if (ff_wr) ram[wra] <= ff_wdat; - - reg [DAT_B+1:0] ff_rdat_m; - always @(posedge clk) - ff_rdat_m <= ram[rda]; - - /////////////////////////////////////////////////////////////////////////// - //same read/write - - wire readsame = ff_wr & (wra == rda); - reg readsame1; - always @(posedge clk) - if (rst) readsame1 <= 1'b0; - else readsame1 <= readsame; - - reg [DAT_B+1:0] ff_wdat1; - always @(posedge clk) - ff_wdat1 <= ff_wdat; - - assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; - - /////////////////////////////////////////////////////////////////////////// - //Store max 8 packet - - always @(posedge clk) - if (rst) pktcnt <= 4'd0; - else begin - case ({(ff_wr & i_eop), (ff_rd & o_eop)}) - 2'b10: pktcnt <= pktcnt + 1; - 2'b01: pktcnt <= pktcnt - 1; - default: pktcnt <= pktcnt; - endcase - end - -endmodule \ No newline at end of file diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 29aaf92d..d24f9384 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -402,17 +402,17 @@ def add_sources(self, platform, phy_path, phy_filename=None): ip_tcl.append("synth_ip $obj") platform.toolchain.pre_synthesis_commands += ip_tcl - platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "axis_iff.v")) - platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "m_axis_rc_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "m_axis_cq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "s_axis_cc_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_rq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_rc_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "s_axis_rq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "m_axis_rc_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "m_axis_cq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "s_axis_cc_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_rq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_rc_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x8.v")) platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) diff --git a/litepcie/phy/m_axis_cq_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v similarity index 100% rename from litepcie/phy/m_axis_cq_adapt_x4.v rename to litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v diff --git a/litepcie/phy/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v similarity index 100% rename from litepcie/phy/m_axis_cq_adapt_x8.v rename to litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v diff --git a/litepcie/phy/m_axis_rc_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v similarity index 100% rename from litepcie/phy/m_axis_rc_adapt_x4.v rename to litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v diff --git a/litepcie/phy/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v similarity index 100% rename from litepcie/phy/m_axis_rc_adapt_x8.v rename to litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v diff --git a/litepcie/phy/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v similarity index 100% rename from litepcie/phy/s_axis_cc_adapt_x4.v rename to litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v diff --git a/litepcie/phy/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v similarity index 100% rename from litepcie/phy/s_axis_cc_adapt_x8.v rename to litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v diff --git a/litepcie/phy/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v similarity index 100% rename from litepcie/phy/s_axis_rq_adapt_x4.v rename to litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v diff --git a/litepcie/phy/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v similarity index 100% rename from litepcie/phy/s_axis_rq_adapt_x8.v rename to litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v From f6b60bc6cb635bd409d453448aef96c2696ee359 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 10:13:43 +0200 Subject: [PATCH 14/41] phy/xilinx_usp: Move AXIS adaptation code to separate verilog files (similar to xilinx_us). Only for x4/x8 for now. --- litepcie/phy/usppciephy.py | 14 +- litepcie/phy/xilinx_usp/axis_iff.v | 106 ++++ litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v | 155 ++++++ litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v | 141 +++++ litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v | 101 ++++ litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v | 95 ++++ litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v | 113 ++++ litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v | 104 ++++ litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v | 24 + litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v | 146 +++++ .../phy/xilinx_usp_gen3_x4/pcie_usp_support.v | 501 ++++-------------- .../phy/xilinx_usp_gen3_x8/pcie_usp_support.v | 467 ++++------------ 12 files changed, 1176 insertions(+), 791 deletions(-) create mode 100644 litepcie/phy/xilinx_usp/axis_iff.v create mode 100644 litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v create mode 100644 litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v create mode 100644 litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v create mode 100644 litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v create mode 100644 litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v create mode 100644 litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v create mode 100644 litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v create mode 100644 litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py index 9d008f5a..1a298b38 100644 --- a/litepcie/phy/usppciephy.py +++ b/litepcie/phy/usppciephy.py @@ -374,7 +374,19 @@ def add_ltssm_tracer(self): # Hard IP sources ------------------------------------------------------------------------------ def add_sources(self, platform, phy_path, phy_filename): platform.add_ip(os.path.join(phy_path, phy_filename)) - platform.add_source(os.path.join(phy_path, "..", "axis_iff.v")) + + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "axis_iff.v")) + + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x4.v")) + + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "pcie_usp_support.v")) # External Hard IP ----------------------------------------------------------------------------- diff --git a/litepcie/phy/xilinx_usp/axis_iff.v b/litepcie/phy/xilinx_usp/axis_iff.v new file mode 100644 index 00000000..bc0796f2 --- /dev/null +++ b/litepcie/phy/xilinx_usp/axis_iff.v @@ -0,0 +1,106 @@ +module axis_iff + #( + parameter DAT_B = 32 + ) + ( + input clk, + input rst, + + input i_vld, + output o_rdy, + input i_sop, + input i_eop, + input [DAT_B-1:0] i_dat, + + + output o_vld, + input i_rdy, + output o_sop, + output o_eop, + output [DAT_B-1:0] o_dat + ); + + /////////////////////////////////////////////////////////////////////////// + //FIFO instance + localparam FF_B = 8; + localparam FF_L = 256; + + wire ff_empt, ff_full; + reg [FF_B:0] ff_len; + + wire ff_wr, ff_rd; + + reg [FF_B-1:0] wrcnt; + always @(posedge clk) + if (rst) wrcnt <= {FF_B{1'b0}}; + else if (ff_wr) wrcnt <= wrcnt + 1; + + always @(posedge clk) + if (rst) ff_len <= {FF_B+1{1'b0}}; + else + case ({ff_wr, ff_rd}) + 2'b10: ff_len <= ff_len + 1; + 2'b01: ff_len <= ff_len - 1; + default: ff_len <= ff_len; + endcase + + wire [FF_B-1:0] rdcnt; + assign rdcnt = wrcnt - ff_len[FF_B-1:0]; + + wire [FF_B-1:0] rda, wra; + assign rda = ff_rd ? (rdcnt + 1) : rdcnt; + assign wra = wrcnt; + + wire [DAT_B+1:0] ff_wdat; + wire [DAT_B+1:0] ff_rdat; + assign ff_wdat = {i_sop, i_eop, i_dat}; + assign {o_sop, o_eop, o_dat} = ff_rdat; + assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); + assign o_vld = (pktcnt > 0); + + reg [3:0] pktcnt; + assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); + assign ff_rd = i_rdy & (pktcnt > 0); + + /////////////////////////////////////////////////////////////////////////// + //Single dual port RAM 1-clock + + (* ram_style="block" *) + reg [DAT_B+1:0] ram [FF_L-1:0]; + + always @(posedge clk) + if (ff_wr) ram[wra] <= ff_wdat; + + reg [DAT_B+1:0] ff_rdat_m; + always @(posedge clk) + ff_rdat_m <= ram[rda]; + + /////////////////////////////////////////////////////////////////////////// + //same read/write + + wire readsame = ff_wr & (wra == rda); + reg readsame1; + always @(posedge clk) + if (rst) readsame1 <= 1'b0; + else readsame1 <= readsame; + + reg [DAT_B+1:0] ff_wdat1; + always @(posedge clk) + ff_wdat1 <= ff_wdat; + + assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; + + /////////////////////////////////////////////////////////////////////////// + //Store max 8 packet + + always @(posedge clk) + if (rst) pktcnt <= 4'd0; + else begin + case ({(ff_wr & i_eop), (ff_rd & o_eop)}) + 2'b10: pktcnt <= pktcnt + 1; + 2'b01: pktcnt <= pktcnt - 1; + default: pktcnt <= pktcnt; + endcase + end + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v new file mode 100644 index 00000000..4035dca8 --- /dev/null +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v @@ -0,0 +1,155 @@ + module m_axis_cq_adapt_x4 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_cq_tdata, + output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, + output m_axis_cq_tlast, + input [3:0] m_axis_cq_tready, + output [84:0] m_axis_cq_tuser, + output m_axis_cq_tvalid, + + input [DATA_WIDTH-1:0] m_axis_cq_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a, + input m_axis_cq_tlast_a, + output [3:0] m_axis_cq_tready_a, + input [84:0] m_axis_cq_tuser_a, + input m_axis_cq_tvalid_a + ); + + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [3:0] m_axis_cq_tkeep_a; + wire [127:0] m_axis_cq_tdata_a; + wire [84:0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; + + //dword counter: //0-2 & latch + reg [1:0] m_axis_cq_cnt; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_cnt <= 2'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; + else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; + end + + wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] + wire m_axis_cq_second = m_axis_cq_cnt == 1; + + wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request + wire m_axis_cq_write = !m_axis_cq_read; + reg m_axis_cq_read_l; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_read_l <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_read_l <= m_axis_cq_read; + + //processing for tlast + wire [9:0] m_axis_cq_dwlen; + reg m_axis_cq_tlast_dly_en; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) + begin + if (m_axis_cq_read) m_axis_cq_tlast_dly_en <= 1'b1; + else m_axis_cq_tlast_dly_en <= (m_axis_cq_dwlen[1:0] != 2'd1); + end + + reg m_axis_cq_tlast_lat; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) + begin + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read + else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; + end + + //Generae ready for PCIe IP + assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); + + //output for TLP + assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; + assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; + + + ////keep address (low) or data (high), not header + reg [127:0] m_axis_cq_tdata_a1; + reg [15:0] m_axis_cq_tlast_be1; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; + m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[23:8]; + end + + //data processing + wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; + + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + wire [4:0] m_axis_cq_type; + wire [2:0] m_axis_cq_fmt; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; + + assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request + m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked + m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request + m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request + m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request + m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 + m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 + 8'b000_00000; //Mem read Request + + reg [7:0] m_axis_cq_tuser_barhit; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop + + reg m_axis_cq_ecrc; + always @(posedge user_clk_out) + begin + m_axis_cq_ecrc <= m_axis_cq_tuser_a[41]; + end + + reg [63:0] m_axis_cq_header; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; + + wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; + assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : + {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[127:32]}; + + assign m_axis_cq_tkeep = m_axis_cq_read_l ? 16'h0FFF : + m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[15:4]} : 16'hFFFF; + + + assign m_axis_cq_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_ecrc //ECRC mapped to discontinue + }; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v new file mode 100644 index 00000000..8721e62a --- /dev/null +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v @@ -0,0 +1,141 @@ + module m_axis_cq_adapt_x8 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_cq_tdata, + output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, + output m_axis_cq_tlast, + input [3:0] m_axis_cq_tready, + output [84:0] m_axis_cq_tuser, + output m_axis_cq_tvalid, + + input [DATA_WIDTH-1:0] m_axis_cq_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a, + input m_axis_cq_tlast_a, + output [3:0] m_axis_cq_tready_a, + input [84:0] m_axis_cq_tuser_a, + input m_axis_cq_tvalid_a + ); + + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [7:0] m_axis_cq_tkeep_a; + wire [255:0] m_axis_cq_tdata_a; + wire [84:0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; + + //dword counter: //0-2 & latch + reg [1:0] m_axis_cq_cnt; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_cnt <= 2'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; + else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; + end + + wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] + wire m_axis_cq_second = m_axis_cq_cnt == 1; + + reg m_axis_cq_rdwr_l; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_rdwr_l <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_rdwr_l <= m_axis_cq_tlast_a; + + //processing for tlast: generate new last in case write & last num of dword != 5 + i*8 + wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request + wire m_axis_cq_write = !m_axis_cq_read; + wire [9:0] m_axis_cq_dwlen; + reg m_axis_cq_tlast_dly_en; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tlast_dly_en <= m_axis_cq_tlast_a | (m_axis_cq_dwlen[2:0] != 3'd5); + + reg m_axis_cq_tlast_lat; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) + begin + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; + else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; + end + + //Generae ready for PCIe IP + assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); + + //output for TLP + assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; + assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; + + + ////keep address (low) or data (high), not header + reg [255:0] m_axis_cq_tdata_a1; + reg [31:0] m_axis_cq_tlast_be1; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; + m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[39:8]; + end + + //data processing + wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; + + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + wire [4:0] m_axis_cq_type; + wire [2:0] m_axis_cq_fmt; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; + + assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request + m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked + m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request + m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request + m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request + m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 + m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 + 8'b000_00000; //Mem read Request + + reg [7:0] m_axis_cq_tuser_barhit; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop + + reg [63:0] m_axis_cq_header; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; + + assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : + {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:32]}; + assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[31:16], 12'hFFF} : + m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[31:4]} : 32'hFFFF_FFFF; + assign m_axis_cq_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_tuser_a[41] //ECRC mapped to discontinue + }; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v new file mode 100644 index 00000000..bbfa395f --- /dev/null +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v @@ -0,0 +1,101 @@ + module m_axis_rc_adapt_x4 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_rc_tdata, + output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, + output m_axis_rc_tlast, + input [3:0] m_axis_rc_tready, + output [84:0] m_axis_rc_tuser, + output m_axis_rc_tvalid, + + input [DATA_WIDTH-1:0] m_axis_rc_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_rc_tkeep_a, + input m_axis_rc_tlast_a, + output [3:0] m_axis_rc_tready_a, + input [84:0] m_axis_rc_tuser_a, + input m_axis_rc_tvalid_a + ); + + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [3:0] m_axis_rc_tkeep_a; + wire [127:0] m_axis_rc_tdata_a; + wire [74:0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; + + reg [1:0] m_axis_rc_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) m_axis_rc_cnt <= 2'd0; + else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) + begin + if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; + else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; + end + + wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] + wire m_axis_rc_second = m_axis_rc_cnt == 1; + + //header process + wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; + reg m_axis_rc_poisoning_l; + always @(posedge user_clk_out) + if (m_axis_rc_tvalid_a && m_axis_rc_sop) + begin + m_axis_rc_poisoning_l <= m_axis_rc_poisoning; + end + + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [4:0] m_axis_rc_type; + wire [2:0] m_axis_rc_fmt; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; + + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; + + assign {m_axis_rc_fmt, + m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data + 8'b010_01011) : //Read-Locked Completion w/ data + ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data + 8'b010_01010); //Completion w/ data + + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; + assign m_axis_rc_tuser = { + 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v new file mode 100644 index 00000000..0f9a1795 --- /dev/null +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v @@ -0,0 +1,95 @@ + module m_axis_rc_adapt_x8 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_rc_tdata, + output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, + output m_axis_rc_tlast, + input [3:0] m_axis_rc_tready, + output [84:0] m_axis_rc_tuser, + output m_axis_rc_tvalid, + + input [DATA_WIDTH-1:0] m_axis_rc_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_rc_tkeep_a, + input m_axis_rc_tlast_a, + output [3:0] m_axis_rc_tready_a, + input [84:0] m_axis_rc_tuser_a, + input m_axis_rc_tvalid_a + ); + + reg [1:0] m_axis_rc_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) m_axis_rc_cnt <= 2'd0; + else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) + begin + if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; + else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; + end + + wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] + wire m_axis_rc_second = m_axis_rc_cnt == 1; + + //header process + wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; + reg m_axis_rc_poisoning_l; + always @(posedge user_clk_out) + if (m_axis_rc_tvalid_a && m_axis_rc_sop) + begin + m_axis_rc_poisoning_l <= m_axis_rc_poisoning; + end + + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [4:0] m_axis_rc_type; + wire [2:0] m_axis_rc_fmt; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; + + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; + + assign {m_axis_rc_fmt, + m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data + 8'b010_01011) : //Read-Locked Completion w/ data + ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data + 8'b010_01010); //Completion w/ data + + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; + assign m_axis_rc_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; + + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v new file mode 100644 index 00000000..d7330164 --- /dev/null +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v @@ -0,0 +1,113 @@ + module s_axis_cc_adapt_x4 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + output s_axis_cc_tlast, + input [3:0] s_axis_cc_tready, + output [3:0] s_axis_cc_tuser, + output s_axis_cc_tvalid, + + input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + input s_axis_cc_tlast_a, + output [3:0] s_axis_cc_tready_a, + input [3:0] s_axis_cc_tuser_a, + input s_axis_cc_tvalid_a + ); + + wire s_axis_cc_tready_ff, + s_axis_cc_tvalid_ff, + s_axis_cc_tlast_ff; + wire [3:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; + + wire [3:0] s_axis_cc_tuser_ff; + wire [3:0] s_axis_cc_tkeep_ff; + wire [127:0] s_axis_cc_tdata_ff; + + axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff + ( + .clk (user_clk_out), + .rst (user_reset_out), + + .i_vld (s_axis_cc_tvalid), + .o_rdy (s_axis_cc_tready), + .i_sop (1'b0), + .i_eop (s_axis_cc_tlast), + .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), + + .o_vld (s_axis_cc_tvalid_ff), + .i_rdy (s_axis_cc_tready_ff), + .o_sop (), + .o_eop (s_axis_cc_tlast_ff), + .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) + ); + + reg [1:0] s_axis_cc_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) s_axis_cc_cnt <= 2'd0; + else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) + begin + if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; + else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; + end + + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; + + wire [3:0] s_axis_cc_tready_a; + + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; + + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; + + reg [3:0] s_axis_cc_firstbe; + reg [3:0] s_axis_cc_lastbe; + + reg s_axis_cc_tvalid_ff_lat; + always @(posedge user_clk_out) + if (user_reset_out) s_axis_cc_tvalid_ff_lat <= 1'd0; + else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) + begin + if (s_axis_cc_tlast_ff) s_axis_cc_tvalid_ff_lat <= 1'd0; + else if (s_axis_cc_tfirst) s_axis_cc_tvalid_ff_lat <= 1'd1; + end + + wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; + wire [127:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v new file mode 100644 index 00000000..6e7414ab --- /dev/null +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v @@ -0,0 +1,104 @@ + module s_axis_cc_adapt_x8 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + output s_axis_cc_tlast, + input [3:0] s_axis_cc_tready, + output [3:0] s_axis_cc_tuser, + output s_axis_cc_tvalid, + + input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + input s_axis_cc_tlast_a, + output [3:0] s_axis_cc_tready_a, + input [3:0] s_axis_cc_tuser_a, + input s_axis_cc_tvalid_a + ); + + wire s_axis_cc_tready_ff, + s_axis_cc_tvalid_ff, + s_axis_cc_tlast_ff; + wire [7:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[31:28], |s_axis_cc_tkeep[27:24], + |s_axis_cc_tkeep[23:20], |s_axis_cc_tkeep[19:16], + |s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; + + wire [3:0] s_axis_cc_tuser_ff; + wire [7:0] s_axis_cc_tkeep_ff; + wire [255:0] s_axis_cc_tdata_ff; + + axis_iff #(.DAT_B(256+8+4)) s_axis_cc_iff + ( + .clk (user_clk_out), + .rst (user_reset_out), + + .i_vld (s_axis_cc_tvalid), + .o_rdy (s_axis_cc_tready), + .i_sop (1'b0), + .i_eop (s_axis_cc_tlast), + .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), + + .o_vld (s_axis_cc_tvalid_ff), + .i_rdy (s_axis_cc_tready_ff), + .o_sop (), + .o_eop (s_axis_cc_tlast_ff), + .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) + ); + + reg [1:0] s_axis_cc_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) s_axis_cc_cnt <= 2'd0; + else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) + begin + if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; + else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; + end + + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; + + wire [3:0] s_axis_cc_tready_a; + + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; + + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; + + wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + + assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; + wire [255:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + wire [7:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v new file mode 100644 index 00000000..ce396ca9 --- /dev/null +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v @@ -0,0 +1,24 @@ + module s_axis_rq_adapt_x4 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + output s_axis_rq_tlast, + input [3:0] s_axis_rq_tready, + output [3:0] s_axis_rq_tuser, + output s_axis_rq_tvalid, + + input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + input s_axis_rq_tlast_a, + output [3:0] s_axis_rq_tready_a, + input [3:0] s_axis_rq_tuser_a, + input s_axis_rq_tvalid_a + ); + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v new file mode 100644 index 00000000..b9402b89 --- /dev/null +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v @@ -0,0 +1,146 @@ + module s_axis_rq_adapt_x8 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + output s_axis_rq_tlast, + input [3:0] s_axis_rq_tready, + output [3:0] s_axis_rq_tuser, + output s_axis_rq_tvalid, + + input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + input s_axis_rq_tlast_a, + output [3:0] s_axis_rq_tready_a, + input [3:0] s_axis_rq_tuser_a, + input s_axis_rq_tvalid_a + ); + + wire s_axis_rq_tready_ff, + s_axis_rq_tvalid_ff, + s_axis_rq_tlast_ff; + wire [7:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], + s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; + + wire [3:0] s_axis_rq_tuser_ff; + wire [7:0] s_axis_rq_tkeep_ff; + wire [255:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(256+8+4)) s_axis_rq_iff + ( + .clk (user_clk_out), + .rst (user_reset_out), + + .i_vld (s_axis_rq_tvalid), + .o_rdy (s_axis_rq_tready), + .i_sop (1'b0), + .i_eop (s_axis_rq_tlast), + .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), + + .o_vld (s_axis_rq_tvalid_ff), + .i_rdy (s_axis_rq_tready_ff), + .o_sop (), + .o_eop (s_axis_rq_tlast_ff), + .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) + ); + + + reg [1:0] s_axis_rq_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_cnt <= 2'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + begin + if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; + else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; + end + + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; + + //processing for tlast: generate new last in case write & last num of dword = 5 + i*8 + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_write = !s_axis_rq_read; + reg s_axis_rq_tlast_dly_en; + reg s_axis_rq_tlast_lat; + wire [3:0] s_axis_rq_tready_a; + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); + + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + begin + if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd5) : 1'b0; //write 5 dwords + else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; + end + + wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + + //Generae ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request + s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request + s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request + s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 + s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 + 4'b1111; + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; + + always @(posedge user_clk_out) + begin + if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) + begin + s_axis_rq_firstbe_l <= s_axis_rq_firstbe; + s_axis_rq_lastbe_l <= s_axis_rq_lastbe; + end + end + + reg [31:0] s_axis_rq_tdata_l; + always @(posedge user_clk_out) + if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; + + wire [255:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : + {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; + wire [7:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; + wire [59:0] s_axis_rq_tuser_a; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v index 359f7751..b99178a6 100644 --- a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v @@ -312,140 +312,32 @@ module pcie_support # ( // AXIS Adaption Logic // //----------------------------------------------------------------------------------------------------------------// - //----------------------------------------------------- RQ AXIS --------------------------------------------------// - wire s_axis_rq_tready_ff, - s_axis_rq_tvalid_ff, - s_axis_rq_tlast_ff; - wire [3:0] s_axis_rq_tkeep_or = {|s_axis_rq_tkeep[15:12], |s_axis_rq_tkeep[11:8], |s_axis_rq_tkeep[7:4], |s_axis_rq_tkeep[3:0]}; - - wire [3:0] s_axis_rq_tuser_ff; - wire [3:0] s_axis_rq_tkeep_ff; - wire [127:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_rq_tvalid), - .o_rdy (s_axis_rq_tready), - .i_sop (1'b0), - .i_eop (s_axis_rq_tlast), - .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), - - .o_vld (s_axis_rq_tvalid_ff), - .i_rdy (s_axis_rq_tready_ff), - .o_sop (), - .o_eop (s_axis_rq_tlast_ff), - .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) - ); - - - reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; - end - - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - - //processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); - - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) - begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; - end - - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - - //latch valid because it is uncontigous when coming from TLP request - reg s_axis_rq_tvalid_lat; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tvalid_lat <= 1'b0; - else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) - begin - if (s_axis_rq_tlast_dly_en) s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; - else s_axis_rq_tvalid_lat <= !(s_axis_rq_tlast_ff && s_axis_rq_tvalid_ff); - end - else if (s_axis_rq_tvalid_ff & s_axis_rq_tfirst & s_axis_rq_write) s_axis_rq_tvalid_lat <= 1'b1; //latche input valid (required by PCIe IP) - - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; - - always @(posedge user_clk_out) - begin - if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) - begin - s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; - end - end - - reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) - if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; - - wire [127:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; - wire [3:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + //----------------------------------------------------- RQ AXIS -------------------------------------------------// + + s_axis_rq_adapt_x4 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_rq_adapt_x4_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_rq_tdata(s_axis_rq_tdata), + .s_axis_rq_tkeep(s_axis_rq_tkeep), + .s_axis_rq_tlast(s_axis_rq_tlast), + .s_axis_rq_tready(s_axis_rq_tready), + .s_axis_rq_tuser(s_axis_rq_tuser), + .s_axis_rq_tvalid(s_axis_rq_tvalid), + + .s_axis_rq_tdata_a(s_axis_rq_tdata_a), + .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), + .s_axis_rq_tlast_a(s_axis_rq_tlast_a), + .s_axis_rq_tready_a(s_axis_rq_tready_a), + .s_axis_rq_tuser_a(s_axis_rq_tuser_a), + .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) + ); //----------------------------------------------------- RC AXIS --------------------------------------------------// + wire m_axis_rc_tvalid_a; wire m_axis_rc_tready_a; wire [3:0] m_axis_rc_tkeep_a; @@ -453,77 +345,30 @@ module pcie_support # ( wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; - else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) - begin - if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; - else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; - end - - wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] - wire m_axis_rc_second = m_axis_rc_cnt == 1; - - //header process - wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; - reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) - if (m_axis_rc_tvalid_a && m_axis_rc_sop) - begin - m_axis_rc_poisoning_l <= m_axis_rc_poisoning; - end - - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; - wire [4:0] m_axis_rc_type; - wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; - wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; - wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; - - assign {m_axis_rc_fmt, - m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data - 8'b010_01011) : //Read-Locked Completion w/ data - ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data - 8'b010_01010); //Completion w/ data - - wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen}; - wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr}; - - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; - assign m_axis_rc_tuser = { - 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + m_axis_rc_adapt_x4 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_rc_adapt_x4_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_rc_tdata( m_axis_rc_tdata), + .m_axis_rc_tkeep( m_axis_rc_tkeep), + .m_axis_rc_tlast( m_axis_rc_tlast), + .m_axis_rc_tready(m_axis_rc_tready), + .m_axis_rc_tuser( m_axis_rc_tuser), + .m_axis_rc_tvalid(m_axis_rc_tvalid), + + .m_axis_rc_tdata_a( m_axis_rc_tdata_a), + .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), + .m_axis_rc_tlast_a( m_axis_rc_tlast_a), + .m_axis_rc_tready_a(m_axis_rc_tready_a), + .m_axis_rc_tuser_a( m_axis_rc_tuser_a), + .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) + ); //----------------------------------------------------- CQ AXIS --------------------------------------------------// + wire m_axis_cq_tvalid_a; wire m_axis_cq_tready_a; wire [3:0] m_axis_cq_tkeep_a; @@ -531,219 +376,51 @@ module pcie_support # ( wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch - reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; - else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; - end - - wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] - wire m_axis_cq_second = m_axis_cq_cnt == 1; - - wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request - wire m_axis_cq_write = !m_axis_cq_read; - reg m_axis_cq_read_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_read_l <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_read_l <= m_axis_cq_read; - - //processing for tlast - wire [9:0] m_axis_cq_dwlen; - reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) - begin - if (m_axis_cq_read) m_axis_cq_tlast_dly_en <= 1'b1; - else m_axis_cq_tlast_dly_en <= (m_axis_cq_dwlen[1:0] != 2'd1); - end - - reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) - begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read - else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; - end - - //Generae ready for PCIe IP - assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); - - //output for TLP - assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; - assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; - - - ////keep address (low) or data (high), not header - reg [127:0] m_axis_cq_tdata_a1; - reg [15:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; - m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[23:8]; - end - - //data processing - wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; - wire [4:0] m_axis_cq_type; - wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; - wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; - - assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request - m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked - m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request - m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request - m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request - m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 - m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 - 8'b000_00000; //Mem read Request - - reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop - - reg m_axis_cq_ecrc; - always @(posedge user_clk_out) - begin - m_axis_cq_ecrc <= m_axis_cq_tuser_a[41]; - end - - reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = {m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen}; - - wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; - assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : - {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[127:32]}; - - assign m_axis_cq_tkeep = m_axis_cq_read_l ? 16'h0FFF : - m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[15:4]} : 16'hFFFF; - - - assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_ecrc //ECRC mapped to discontinue - }; + m_axis_cq_adapt_x4 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_cq_adapt_x4_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_cq_tdata( m_axis_cq_tdata), + .m_axis_cq_tkeep( m_axis_cq_tkeep), + .m_axis_cq_tlast( m_axis_cq_tlast), + .m_axis_cq_tready(m_axis_cq_tready), + .m_axis_cq_tuser( m_axis_cq_tuser), + .m_axis_cq_tvalid(m_axis_cq_tvalid), + + .m_axis_cq_tdata_a( s_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( s_axis_cq_tlast_a), + .m_axis_cq_tready_a(s_axis_cq_tready_a), + .m_axis_cq_tuser_a( s_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + ); //----------------------------------------------------- CC AXIS --------------------------------------------------// - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; - - wire [3:0] s_axis_cc_tuser_ff; - wire [3:0] s_axis_cc_tkeep_ff; - wire [127:0] s_axis_cc_tdata_ff; - - axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_cc_tvalid), - .o_rdy (s_axis_cc_tready), - .i_sop (1'b0), - .i_eop (s_axis_cc_tlast), - .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), - - .o_vld (s_axis_cc_tvalid_ff), - .i_rdy (s_axis_cc_tready_ff), - .o_sop (), - .o_eop (s_axis_cc_tlast_ff), - .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) - ); - - reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; - else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; - end - - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; - wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; - wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; - wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; - wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr}; - wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; - - reg [3:0] s_axis_cc_firstbe; - reg [3:0] s_axis_cc_lastbe; - - reg s_axis_cc_tvalid_ff_lat; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_tvalid_ff_lat <= 1'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_tvalid_ff_lat <= 1'd0; - else if (s_axis_cc_tfirst) s_axis_cc_tvalid_ff_lat <= 1'd1; - end - - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [127:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + + s_axis_cc_adapt_x4 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_cc_adapt_x4_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_cc_tdata(s_axis_cc_tdata), + .s_axis_cc_tkeep(s_axis_cc_tkeep), + .s_axis_cc_tlast(s_axis_cc_tlast), + .s_axis_cc_tready(s_axis_cc_tready), + .s_axis_cc_tuser(s_axis_cc_tuser), + .s_axis_cc_tvalid(s_axis_cc_tvalid), + + .s_axis_cc_tdata_a(s_axis_cc_tdata_a), + .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), + .s_axis_cc_tlast_a(s_axis_cc_tlast_a), + .s_axis_cc_tready_a(s_axis_cc_tready_a), + .s_axis_cc_tuser_a(s_axis_cc_tuser_a), + .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) + ); //---------------------------------------------------------------------------------------------------------------// // MSI Adaptation Logic // diff --git a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v index fa9237d3..8027ecb5 100644 --- a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v @@ -313,404 +313,115 @@ module pcie_support # ( //----------------------------------------------------------------------------------------------------------------// //----------------------------------------------------- RQ AXIS --------------------------------------------------// - wire s_axis_rq_tready_ff, - s_axis_rq_tvalid_ff, - s_axis_rq_tlast_ff; - wire [7:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], - s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; - - wire [3:0] s_axis_rq_tuser_ff; - wire [7:0] s_axis_rq_tkeep_ff; - wire [255:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(256+8+4)) s_axis_rq_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_rq_tvalid), - .o_rdy (s_axis_rq_tready), - .i_sop (1'b0), - .i_eop (s_axis_rq_tlast), - .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), - - .o_vld (s_axis_rq_tvalid_ff), - .i_rdy (s_axis_rq_tready_ff), - .o_sop (), - .o_eop (s_axis_rq_tlast_ff), - .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) - ); - - - reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; - end - - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - - //processing for tlast: generate new last in case write & last num of dword = 5 + i*8 - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); - - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) - begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd5) : 1'b0; //write 5 dwords - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; - end - - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; - always @(posedge user_clk_out) - begin - if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) - begin - s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; - end - end - - reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) - if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; - - wire [255:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : - {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; - wire [7:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; + s_axis_rq_adapt_x8 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_rq_adapt_x8_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_rq_tdata(s_axis_rq_tdata), + .s_axis_rq_tkeep(s_axis_rq_tkeep), + .s_axis_rq_tlast(s_axis_rq_tlast), + .s_axis_rq_tready(s_axis_rq_tready), + .s_axis_rq_tuser(s_axis_rq_tuser), + .s_axis_rq_tvalid(s_axis_rq_tvalid), + + .s_axis_rq_tdata_a(s_axis_rq_tdata_a), + .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), + .s_axis_rq_tlast_a(s_axis_rq_tlast_a), + .s_axis_rq_tready_a(s_axis_rq_tready_a), + .s_axis_rq_tuser_a(s_axis_rq_tuser_a), + .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) + ); //----------------------------------------------------- RC AXIS --------------------------------------------------// + wire m_axis_rc_tvalid_a; wire m_axis_rc_tready_a; wire [7:0] m_axis_rc_tkeep_a; - wire [255:0] m_axis_rc_tdata_a; + wire [127:0] m_axis_rc_tdata_a; wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; - else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) - begin - if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; - else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; - end - - wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] - wire m_axis_rc_second = m_axis_rc_cnt == 1; - - //header process - wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; - reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) - if (m_axis_rc_tvalid_a && m_axis_rc_sop) - begin - m_axis_rc_poisoning_l <= m_axis_rc_poisoning; - end - - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; - wire [4:0] m_axis_rc_type; - wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; - wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; - wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; - - assign {m_axis_rc_fmt, - m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data - 8'b010_01011) : //Read-Locked Completion w/ data - ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data - 8'b010_01010); //Completion w/ data - - wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen}; - wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr}; - - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; - assign m_axis_rc_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + m_axis_rc_adapt_x8 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_rc_adapt_x8_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_rc_tdata( m_axis_rc_tdata), + .m_axis_rc_tkeep( m_axis_rc_tkeep), + .m_axis_rc_tlast( m_axis_rc_tlast), + .m_axis_rc_tready(m_axis_rc_tready), + .m_axis_rc_tuser( m_axis_rc_tuser), + .m_axis_rc_tvalid(m_axis_rc_tvalid), + + .m_axis_rc_tdata_a( m_axis_rc_tdata_a), + .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), + .m_axis_rc_tlast_a( m_axis_rc_tlast_a), + .m_axis_rc_tready_a(m_axis_rc_tready_a), + .m_axis_rc_tuser_a( m_axis_rc_tuser_a), + .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) + ); //----------------------------------------------------- CQ AXIS --------------------------------------------------// + wire m_axis_cq_tvalid_a; wire m_axis_cq_tready_a; wire [7:0] m_axis_cq_tkeep_a; - wire [255:0] m_axis_cq_tdata_a; + wire [127:0] m_axis_cq_tdata_a; wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch - reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; - else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; - end + m_axis_cq_adapt_x8 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_cq_adapt_x8_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_cq_tdata( m_axis_cq_tdata), + .m_axis_cq_tkeep( m_axis_cq_tkeep), + .m_axis_cq_tlast( m_axis_cq_tlast), + .m_axis_cq_tready(m_axis_cq_tready), + .m_axis_cq_tuser( m_axis_cq_tuser), + .m_axis_cq_tvalid(m_axis_cq_tvalid), + + .m_axis_cq_tdata_a( s_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( s_axis_cq_tlast_a), + .m_axis_cq_tready_a(s_axis_cq_tready_a), + .m_axis_cq_tuser_a( s_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + ); - wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] - wire m_axis_cq_second = m_axis_cq_cnt == 1; - - reg m_axis_cq_rdwr_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_rdwr_l <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_rdwr_l <= m_axis_cq_tlast_a; - - //processing for tlast: generate new last in case write & last num of dword != 5 + i*8 - wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request - wire m_axis_cq_write = !m_axis_cq_read; - wire [9:0] m_axis_cq_dwlen; - reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tlast_dly_en <= m_axis_cq_tlast_a | (m_axis_cq_dwlen[2:0] != 3'd5); - - reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) - begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; - else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; - end - - //Generae ready for PCIe IP - assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); - - //output for TLP - assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; - assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; - - - ////keep address (low) or data (high), not header - reg [255:0] m_axis_cq_tdata_a1; - reg [31:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; - m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[39:8]; - end - - //data processing - wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; - wire [4:0] m_axis_cq_type; - wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; - wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; - - assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request - m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked - m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request - m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request - m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request - m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 - m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 - 8'b000_00000; //Mem read Request - - reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop - - reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = {m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen}; - - assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : - {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:32]}; - assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[31:16], 12'hFFF} : - m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[31:4]} : 32'hFFFF_FFFF; - assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_tuser_a[41] //ECRC mapped to discontinue - }; //----------------------------------------------------- CC AXIS --------------------------------------------------// - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; - wire [7:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[31:28], |s_axis_cc_tkeep[27:24], - |s_axis_cc_tkeep[23:20], |s_axis_cc_tkeep[19:16], - |s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; - - wire [3:0] s_axis_cc_tuser_ff; - wire [7:0] s_axis_cc_tkeep_ff; - wire [255:0] s_axis_cc_tdata_ff; - - axis_iff #(.DAT_B(256+8+4)) s_axis_cc_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_cc_tvalid), - .o_rdy (s_axis_cc_tready), - .i_sop (1'b0), - .i_eop (s_axis_cc_tlast), - .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), - - .o_vld (s_axis_cc_tvalid_ff), - .i_rdy (s_axis_cc_tready_ff), - .o_sop (), - .o_eop (s_axis_cc_tlast_ff), - .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) - ); - - reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; - else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; - end - - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; - wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; - wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; - wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; - wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr}; - wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; - - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [255:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [7:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + + s_axis_cc_adapt_x8 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_cc_adapt_x8_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_cc_tdata(s_axis_cc_tdata), + .s_axis_cc_tkeep(s_axis_cc_tkeep), + .s_axis_cc_tlast(s_axis_cc_tlast), + .s_axis_cc_tready(s_axis_cc_tready), + .s_axis_cc_tuser(s_axis_cc_tuser), + .s_axis_cc_tvalid(s_axis_cc_tvalid), + + .s_axis_cc_tdata_a(s_axis_cc_tdata_a), + .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), + .s_axis_cc_tlast_a(s_axis_cc_tlast_a), + .s_axis_cc_tready_a(s_axis_cc_tready_a), + .s_axis_cc_tuser_a(s_axis_cc_tuser_a), + .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) + ); //---------------------------------------------------------------------------------------------------------------// // MSI Adaptation Logic // From 304c7f0d56d2e2ef4e17ea73bd2f5643c2ad0935 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 15:41:46 +0200 Subject: [PATCH 15/41] phy/s7pciephy: Split config in generic/bar0/interrupt parameters. --- litepcie/phy/s7pciephy.py | 40 ++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/litepcie/phy/s7pciephy.py b/litepcie/phy/s7pciephy.py index 9d85147e..40030682 100644 --- a/litepcie/phy/s7pciephy.py +++ b/litepcie/phy/s7pciephy.py @@ -435,24 +435,42 @@ def add_sources(self, platform, phy_path, phy_filename=None): platform.add_ip(os.path.join(phy_path, phy_filename)) else: config = { - "Bar0_Scale" : "Megabytes", - "Bar0_Size" : 1, - "Buf_Opt_BMA" : True, + # Generic Config. + # --------------- "Component_Name" : "pcie", "Device_ID" : 7020 + self.nlanes, - "IntX_Generation" : False, - "Interface_Width" : f"{self.pcie_data_width}_bit", - "Legacy_Interrupt" : None, - "Multiple_Message_Capable" : '1_vector', "Link_Speed" : "5.0_GT/s", - "MSI_64b" : False, - "Max_Payload_Size" : "512_bytes" if self.nlanes != 8 else "256_bytes", + "Trgt_Link_Speed" : "4'h2", + "Max_Payload_Size" : { + 1 : "256_bytes", + 2 : "256_bytes", + 4 : "256_bytes", + 8 : "512_bytes", + }[self.nlanes], + "Interface_Width" : f"{self.pcie_data_width}_bit", + "Buf_Opt_BMA" : True, "Maximum_Link_Width" : f"X{self.nlanes}", "PCIe_Blk_Locn" : "X0Y0", "Ref_Clk_Freq" : "100_MHz", "Trans_Buf_Pipeline" : None, - "Trgt_Link_Speed" : "4'h2", - "User_Clk_Freq" : 125 if self.nlanes != 8 else 250, + "User_Clk_Freq" : { + 1 : 125, + 2 : 125, + 4 : 125, + 8 : 250, + }[self.nlanes], + + # BAR0 Config. + # ------------ + "Bar0_Scale" : "Megabytes", + "Bar0_Size" : 1, + + # Interrupt Config. + # ----------------- + "IntX_Generation" : False, + "Legacy_Interrupt" : None, + "MSI_64b" : False, + "Multiple_Message_Capable" : '1_vector', } ip_tcl = [] ip_tcl.append("create_ip -vendor xilinx.com -name pcie_7x -module_name pcie_s7") From 116baba4dc0c67686aed07219b62a4d62c42862a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 15:45:10 +0200 Subject: [PATCH 16/41] phy/uspciephy: Split config in generic/bar0/interrupt parameters. --- litepcie/phy/uspciephy.py | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index d24f9384..37e98829 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -379,9 +379,8 @@ def add_sources(self, platform, phy_path, phy_filename=None): else: # FIXME: Add missing parameters? config = { - "pf0_bar0_scale" : "Megabytes", - "pf0_bar0_size" : 1, - "PF0_INTERRUPT_PIN" : "NONE", + # Generic Config. + # --------------- "PL_LINK_CAP_MAX_LINK_WIDTH" : f"X{self.nlanes}", "PL_LINK_CAP_MAX_LINK_SPEED" : "8.0_GT/s", # CHECKME. "axisten_if_width" : f"{self.pcie_data_width}_bit", @@ -391,6 +390,15 @@ def add_sources(self, platform, phy_path, phy_filename=None): "aspm_support" : "No_ASPM", "coreclk_freq" : 500, # CHECKME. "plltype" : "QPLL1", + + # BAR0 Config. + # ------------ + "pf0_bar0_scale" : "Megabytes", + "pf0_bar0_size" : 1, + + # Interrupt Config. + # ----------------- + "PF0_INTERRUPT_PIN" : "NONE", } ip_tcl = [] ip_tcl.append("create_ip -vendor xilinx.com -name pcie3_ultrascale -module_name pcie_us") From 4e817fbd2d0751e8fc8feeb503237935055f9347 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 15:46:01 +0200 Subject: [PATCH 17/41] phy/xilinx_us: Add missing axis_iff.v. --- litepcie/phy/xilinx_us/axis_iff.v | 106 ++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 litepcie/phy/xilinx_us/axis_iff.v diff --git a/litepcie/phy/xilinx_us/axis_iff.v b/litepcie/phy/xilinx_us/axis_iff.v new file mode 100644 index 00000000..bc0796f2 --- /dev/null +++ b/litepcie/phy/xilinx_us/axis_iff.v @@ -0,0 +1,106 @@ +module axis_iff + #( + parameter DAT_B = 32 + ) + ( + input clk, + input rst, + + input i_vld, + output o_rdy, + input i_sop, + input i_eop, + input [DAT_B-1:0] i_dat, + + + output o_vld, + input i_rdy, + output o_sop, + output o_eop, + output [DAT_B-1:0] o_dat + ); + + /////////////////////////////////////////////////////////////////////////// + //FIFO instance + localparam FF_B = 8; + localparam FF_L = 256; + + wire ff_empt, ff_full; + reg [FF_B:0] ff_len; + + wire ff_wr, ff_rd; + + reg [FF_B-1:0] wrcnt; + always @(posedge clk) + if (rst) wrcnt <= {FF_B{1'b0}}; + else if (ff_wr) wrcnt <= wrcnt + 1; + + always @(posedge clk) + if (rst) ff_len <= {FF_B+1{1'b0}}; + else + case ({ff_wr, ff_rd}) + 2'b10: ff_len <= ff_len + 1; + 2'b01: ff_len <= ff_len - 1; + default: ff_len <= ff_len; + endcase + + wire [FF_B-1:0] rdcnt; + assign rdcnt = wrcnt - ff_len[FF_B-1:0]; + + wire [FF_B-1:0] rda, wra; + assign rda = ff_rd ? (rdcnt + 1) : rdcnt; + assign wra = wrcnt; + + wire [DAT_B+1:0] ff_wdat; + wire [DAT_B+1:0] ff_rdat; + assign ff_wdat = {i_sop, i_eop, i_dat}; + assign {o_sop, o_eop, o_dat} = ff_rdat; + assign o_rdy = !(ff_len[FF_B] | pktcnt[3]); + assign o_vld = (pktcnt > 0); + + reg [3:0] pktcnt; + assign ff_wr = i_vld & (!(ff_len[FF_B] | pktcnt[3])); + assign ff_rd = i_rdy & (pktcnt > 0); + + /////////////////////////////////////////////////////////////////////////// + //Single dual port RAM 1-clock + + (* ram_style="block" *) + reg [DAT_B+1:0] ram [FF_L-1:0]; + + always @(posedge clk) + if (ff_wr) ram[wra] <= ff_wdat; + + reg [DAT_B+1:0] ff_rdat_m; + always @(posedge clk) + ff_rdat_m <= ram[rda]; + + /////////////////////////////////////////////////////////////////////////// + //same read/write + + wire readsame = ff_wr & (wra == rda); + reg readsame1; + always @(posedge clk) + if (rst) readsame1 <= 1'b0; + else readsame1 <= readsame; + + reg [DAT_B+1:0] ff_wdat1; + always @(posedge clk) + ff_wdat1 <= ff_wdat; + + assign ff_rdat = readsame1 ? ff_wdat1 : ff_rdat_m; + + /////////////////////////////////////////////////////////////////////////// + //Store max 8 packet + + always @(posedge clk) + if (rst) pktcnt <= 4'd0; + else begin + case ({(ff_wr & i_eop), (ff_rd & o_eop)}) + 2'b10: pktcnt <= pktcnt + 1; + 2'b01: pktcnt <= pktcnt - 1; + default: pktcnt <= pktcnt; + endcase + end + +endmodule \ No newline at end of file From 31bbe4068351d2ce636e608a04cc09e37a88bccd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 15:50:08 +0200 Subject: [PATCH 18/41] phy/xilinx_us: Remove x4/x8 xci files no longer required. --- litepcie/phy/xilinx_us_gen3_x4/pcie_us.xci | 858 -------------------- litepcie/phy/xilinx_us_gen3_x8/pcie_us.xci | 859 --------------------- 2 files changed, 1717 deletions(-) delete mode 100644 litepcie/phy/xilinx_us_gen3_x4/pcie_us.xci delete mode 100644 litepcie/phy/xilinx_us_gen3_x8/pcie_us.xci diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us.xci b/litepcie/phy/xilinx_us_gen3_x4/pcie_us.xci deleted file mode 100644 index 4f6ddf6d..00000000 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us.xci +++ /dev/null @@ -1,858 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - pcie_us - - - - - - 100000000 - 0.000 - - - - 100000000 - 0.000 - - 0.000 - - 100000000 - 1 - 1 - 1 - 0 - undef - 0.000 - 16 - 0 - 0 - 85 - - 100000000 - 1 - 1 - 1 - 0 - undef - 0.000 - 16 - 0 - 0 - 75 - ACTIVE_LOW - - 100000000 - 1 - 1 - 1 - 0 - undef - 0.000 - 16 - 0 - 0 - 33 - - 100000000 - 1 - 1 - 1 - 0 - undef - 0.000 - 16 - 0 - 0 - 60 - 0x000 - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - 16KB - 2 - 128 - FALSE - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 1 - Add-in_Card - 0x000 - NONE - FALSE - TRUE - TRUE - FALSE - FALSE - NONE - 3 - 2.0 - TRUE - FALSE - FALSE - 0x300 - 0x000 - 0x00 - 0x0B - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8034 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - FALSE - FALSE - 0x2 - 0x300 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x300 - 0x00 - FALSE - 0x0 - 0 - TRUE - 0x300 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0xC0 - 0x274 - 0x90 - FALSE - FALSE - FALSE - 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0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - TRUE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - Production - 0 - true - false - pcie_us - 15 - false - false - 058000 - 8034 - false - false - false - 00_Not_Supported - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - false - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - From 539f8deb4bcf1d2fddaa1aaebd8934bd60cbd1a7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 16:03:26 +0200 Subject: [PATCH 19/41] phy/s7pciephy/usppciephy: Allow bar0 size configuration (needs to be improved). --- litepcie/phy/s7pciephy.py | 4 ++-- litepcie/phy/uspciephy.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/litepcie/phy/s7pciephy.py b/litepcie/phy/s7pciephy.py index 40030682..61b4d35e 100644 --- a/litepcie/phy/s7pciephy.py +++ b/litepcie/phy/s7pciephy.py @@ -462,8 +462,8 @@ def add_sources(self, platform, phy_path, phy_filename=None): # BAR0 Config. # ------------ - "Bar0_Scale" : "Megabytes", - "Bar0_Size" : 1, + "Bar0_Scale" : "Megabytes", # FIXME. + "Bar0_Size" : max(self.bar0_size/MB, 1), # FIXME. # Interrupt Config. # ----------------- diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 37e98829..529c7e46 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -393,8 +393,8 @@ def add_sources(self, platform, phy_path, phy_filename=None): # BAR0 Config. # ------------ - "pf0_bar0_scale" : "Megabytes", - "pf0_bar0_size" : 1, + "pf0_bar0_scale" : "Megabytes", # FIXME. + "pf0_bar0_size" : max(self.bar0_size/MB, 1), # FIXME. # Interrupt Config. # ----------------- From 85d62d58c54460b9a37c7c0172bdec1c13ae8aca Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 16:21:10 +0200 Subject: [PATCH 20/41] phy/uspciephy: Add axisten_if_enable_client_tag. --- litepcie/phy/uspciephy.py | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 529c7e46..daf446b6 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -381,24 +381,26 @@ def add_sources(self, platform, phy_path, phy_filename=None): config = { # Generic Config. # --------------- - "PL_LINK_CAP_MAX_LINK_WIDTH" : f"X{self.nlanes}", - "PL_LINK_CAP_MAX_LINK_SPEED" : "8.0_GT/s", # CHECKME. - "axisten_if_width" : f"{self.pcie_data_width}_bit", - "AXISTEN_IF_RC_STRADDLE" : True, - "PF0_DEVICE_ID" : 8030 + self.nlanes, - "axisten_freq" : 250, # CHECKME. - "aspm_support" : "No_ASPM", - "coreclk_freq" : 500, # CHECKME. - "plltype" : "QPLL1", + "Component_Name" : "pcie_us", + "PL_LINK_CAP_MAX_LINK_WIDTH " : f"X{self.nlanes}", + "PL_LINK_CAP_MAX_LINK_SPEED " : "8.0_GT/s", # CHECKME. + "axisten_if_width" : f"{self.pcie_data_width}_bit", + "AXISTEN_IF_RC_STRADDLE" : True, + "PF0_DEVICE_ID" : 8030 + self.nlanes, + "axisten_freq" : 250, # CHECKME. + "axisten_if_enable_client_tag" : True, + "aspm_support" : "No_ASPM", + "coreclk_freq" : 500, # CHECKME. + "plltype" : "QPLL1", # BAR0 Config. # ------------ - "pf0_bar0_scale" : "Megabytes", # FIXME. - "pf0_bar0_size" : max(self.bar0_size/MB, 1), # FIXME. + "pf0_bar0_scale" : "Megabytes", # FIXME. + "pf0_bar0_size" : max(self.bar0_size/MB, 1), # FIXME. # Interrupt Config. # ----------------- - "PF0_INTERRUPT_PIN" : "NONE", + "PF0_INTERRUPT_PIN" : "NONE", } ip_tcl = [] ip_tcl.append("create_ip -vendor xilinx.com -name pcie3_ultrascale -module_name pcie_us") From 16bff28a4ca1e7ec5f7109b54b02af6250672777 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 16:22:34 +0200 Subject: [PATCH 21/41] phy/usppciephy: Add ip_tcl config/build-time generation to avoid .xci files. --- litepcie/phy/uspciephy.py | 4 ++-- litepcie/phy/usppciephy.py | 45 ++++++++++++++++++++++++++++++++++---- 2 files changed, 43 insertions(+), 6 deletions(-) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index daf446b6..9626f072 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -382,8 +382,8 @@ def add_sources(self, platform, phy_path, phy_filename=None): # Generic Config. # --------------- "Component_Name" : "pcie_us", - "PL_LINK_CAP_MAX_LINK_WIDTH " : f"X{self.nlanes}", - "PL_LINK_CAP_MAX_LINK_SPEED " : "8.0_GT/s", # CHECKME. + "PL_LINK_CAP_MAX_LINK_WIDTH" : f"X{self.nlanes}", + "PL_LINK_CAP_MAX_LINK_SPEED" : "8.0_GT/s", # CHECKME. "axisten_if_width" : f"{self.pcie_data_width}_bit", "AXISTEN_IF_RC_STRADDLE" : True, "PF0_DEVICE_ID" : 8030 + self.nlanes, diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py index 1a298b38..2027b7dc 100644 --- a/litepcie/phy/usppciephy.py +++ b/litepcie/phy/usppciephy.py @@ -9,6 +9,8 @@ from migen import * +from litex.gen import * + from litex.soc.interconnect.csr import * from litepcie.common import * @@ -372,8 +374,44 @@ def add_ltssm_tracer(self): self.ltssm_tracer = LTSSMTracer(self._link_status.fields.ltssm) # Hard IP sources ------------------------------------------------------------------------------ - def add_sources(self, platform, phy_path, phy_filename): - platform.add_ip(os.path.join(phy_path, phy_filename)) + def add_sources(self, platform, phy_path, phy_filename=None): + if phy_filename is not None: + platform.add_ip(os.path.join(phy_path, phy_filename)) + else: + # FIXME: Add missing parameters? + config = { + # Generic Config. + # --------------- + "Component_Name" : "pcie_usp", + "PL_LINK_CAP_MAX_LINK_WIDTH" : f"X{self.nlanes}", + "PL_LINK_CAP_MAX_LINK_SPEED" : "8.0_GT/s", # CHECKME. + "axisten_if_width" : f"{self.pcie_data_width}_bit", + "AXISTEN_IF_RC_STRADDLE" : True, + "PF0_DEVICE_ID" : 9030 + self.nlanes, + "axisten_freq" : 250, # CHECKME. + "axisten_if_enable_client_tag" : True, + "aspm_support" : "No_ASPM", + "coreclk_freq" : 500, # CHECKME. + "plltype" : "QPLL1", + + # BAR0 Config. + # ------------ + "pf0_bar0_scale" : "Megabytes", # FIXME. + "pf0_bar0_size" : max(self.bar0_size/MB, 1), # FIXME. + + # Interrupt Config. + # ----------------- + "PF0_INTERRUPT_PIN" : "NONE", + } + ip_tcl = [] + ip_tcl.append("create_ip -vendor xilinx.com -name pcie4_uscale_plus -module_name pcie_usp") + ip_tcl.append("set obj [get_ips pcie_usp]") + ip_tcl.append("set_property -dict [list \\") + for config, value in config.items(): + ip_tcl.append("CONFIG.{} {} \\".format(config, '{{' + str(value) + '}}')) + ip_tcl.append(f"] $obj") + ip_tcl.append("synth_ip $obj") + platform.toolchain.pre_synthesis_commands += ip_tcl platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "axis_iff.v")) @@ -403,8 +441,7 @@ def do_finalize(self): self.nlanes ) self.add_sources(self.platform, - phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), - phy_filename = "pcie_usp.xci" + phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), ) self.specials += Instance("pcie_support", **self.pcie_phy_params) From 26b97b4280e67bcf36852a5ad4f68d697c8bdf92 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 16:42:55 +0200 Subject: [PATCH 22/41] phy/xilinx_usp: Remove .xci files that should no longer be required. --- litepcie/phy/xilinx_usp_gen3_x16/pcie_usp.xci | 1104 --------------- litepcie/phy/xilinx_usp_gen3_x4/pcie_usp.xci | 1101 --------------- litepcie/phy/xilinx_usp_gen3_x8/pcie_usp.xci | 1106 --------------- .../phy/xilinx_usp_hbm_gen3_x4/pcie_usp.xci | 1212 ----------------- 4 files changed, 4523 deletions(-) delete mode 100644 litepcie/phy/xilinx_usp_gen3_x16/pcie_usp.xci delete mode 100644 litepcie/phy/xilinx_usp_gen3_x4/pcie_usp.xci delete mode 100644 litepcie/phy/xilinx_usp_gen3_x8/pcie_usp.xci delete mode 100644 litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp.xci diff --git a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp.xci b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp.xci deleted file mode 100644 index a7896b95..00000000 --- a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp.xci +++ /dev/null @@ -1,1104 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - pcie_usp - - - - - - 0.000 - - - - 0.000 - - - - 100000000 - 0.000 - - - - 100000000 - 0.000 - - 0.000 - - 100000000 - 1 - 1 - 1 - 0 - undef - 0.000 - 64 - 0 - 0 - 183 - - 100000000 - 1 - 1 - 1 - 0 - undef - 0.000 - 64 - 0 - 0 - 161 - ACTIVE_LOW - - 100000000 - 1 - 1 - 1 - 0 - undef - 0.000 - 64 - 0 - 0 - 81 - - 100000000 - 1 - 1 - 1 - 0 - undef - 0.000 - 64 - 0 - 0 - 137 - 0x000 - FALSE - FALSE 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fsvh2104 - VERILOG - es1 - MIXED - -2L - E - TRUE - TRUE - IP_Flow - 3 - TRUE - . - - . - 2018.2 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - From 9cd8596b8911307fe87bf5784245f5723fd9901e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 16:56:19 +0200 Subject: [PATCH 23/41] phy/xilinx_usp_gen3_x16: Move code to xilinx_usp and separate adaptation files. --- litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v | 141 +++++ litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v | 101 ++++ litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v | 109 ++++ litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v | 148 ++++++ .../xilinx_usp_gen3_x16/pcie_usp_support.v | 480 ++++-------------- 5 files changed, 591 insertions(+), 388 deletions(-) create mode 100644 litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v create mode 100644 litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v create mode 100644 litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v create mode 100644 litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v new file mode 100644 index 00000000..d5e5fb60 --- /dev/null +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v @@ -0,0 +1,141 @@ + module m_axis_cq_adapt_x16 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_cq_tdata, + output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, + output m_axis_cq_tlast, + input [3:0] m_axis_cq_tready, + output [84:0] m_axis_cq_tuser, + output m_axis_cq_tvalid, + + input [DATA_WIDTH-1:0] m_axis_cq_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_cq_tkeep_a, + input m_axis_cq_tlast_a, + output [3:0] m_axis_cq_tready_a, + input [84:0] m_axis_cq_tuser_a, + input m_axis_cq_tvalid_a + ); + + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [15:0] m_axis_cq_tkeep_a; + wire [511:0] m_axis_cq_tdata_a; + wire [96:0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; + + //dword counter: //0-2 & latch + reg [1:0] m_axis_cq_cnt; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_cnt <= 2'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; + else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; + end + + wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); + wire m_axis_cq_second = m_axis_cq_cnt == 1; + + reg m_axis_cq_rdwr_l; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_rdwr_l <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_rdwr_l <= m_axis_cq_tlast_a; + + //processing for tlast: generate new last in case write & last num of dword != 13 + i*16 + wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request + wire m_axis_cq_write = !m_axis_cq_read; + wire [9:0] m_axis_cq_dwlen; + reg m_axis_cq_tlast_dly_en; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tlast_dly_en <= m_axis_cq_tlast_a | (m_axis_cq_dwlen[3:0] != 4'd13); + + reg m_axis_cq_tlast_lat; + always @(posedge user_clk_out) + if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; + else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) + begin + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read or write + else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; + end + + //Generae ready for PCIe IP + assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); + + //output for TLP + assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; + assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; + + + ////keep address (low) or data (high), not header + reg [511:0] m_axis_cq_tdata_a1; + reg [63:0] m_axis_cq_tlast_be1; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) + begin + m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; + m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[79:16]; + end + + //data processing + wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; + + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + wire [4:0] m_axis_cq_type; + wire [2:0] m_axis_cq_fmt; + wire [7:0] m_axis_cq_be = {m_axis_cq_tuser_a[11:8], m_axis_cq_tuser_a[3:0]}; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; + + assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request + m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked + m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request + m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request + m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request + m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 + m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 + m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 + 8'b000_00000; //Mem read Request + + reg [7:0] m_axis_cq_tuser_barhit; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop + + reg [63:0] m_axis_cq_header; + always @(posedge user_clk_out) + if (m_axis_cq_tvalid_a && m_axis_cq_sop) + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; + + assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[511:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : + {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[511:32]}; + assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[63:16], 12'hFFF} : + m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[63:4]} : {64{1'b1}}; + assign m_axis_cq_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_tuser_a[96] //ECRC mapped to discontinue + }; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v new file mode 100644 index 00000000..0e718b53 --- /dev/null +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v @@ -0,0 +1,101 @@ + module m_axis_rc_adapt_x16 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] m_axis_rc_tdata, + output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, + output m_axis_rc_tlast, + input [3:0] m_axis_rc_tready, + output [84:0] m_axis_rc_tuser, + output m_axis_rc_tvalid, + + input [DATA_WIDTH-1:0] m_axis_rc_tdata_a, + input [KEEP_WIDTH-1:0] m_axis_rc_tkeep_a, + input m_axis_rc_tlast_a, + output [3:0] m_axis_rc_tready_a, + input [84:0] m_axis_rc_tuser_a, + input m_axis_rc_tvalid_a + ); + + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [15:0] m_axis_rc_tkeep_a; + wire [511:0] m_axis_rc_tdata_a; + wire [74:0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; + + reg [1:0] m_axis_rc_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) m_axis_rc_cnt <= 2'd0; + else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) + begin + if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; + else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; + end + + wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] + wire m_axis_rc_second = m_axis_rc_cnt == 1; + + //header process + wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; + reg m_axis_rc_poisoning_l; + always @(posedge user_clk_out) + if (m_axis_rc_tvalid_a && m_axis_rc_sop) + begin + m_axis_rc_poisoning_l <= m_axis_rc_poisoning; + end + + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [4:0] m_axis_rc_type; + wire [2:0] m_axis_rc_fmt; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; + + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; + + assign {m_axis_rc_fmt, + m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data + 8'b010_01011) : //Read-Locked Completion w/ data + ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data + 8'b010_01010); //Completion w/ data + + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[511:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[63:12], 12'hFFF} : m_axis_rc_tuser_a[63:0]; + assign m_axis_rc_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v new file mode 100644 index 00000000..7c1992c6 --- /dev/null +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v @@ -0,0 +1,109 @@ + module s_axis_cc_adapt_x16 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + output s_axis_cc_tlast, + input [3:0] s_axis_cc_tready, + output [3:0] s_axis_cc_tuser, + output s_axis_cc_tvalid, + + input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + input s_axis_cc_tlast_a, + output [3:0] s_axis_cc_tready_a, + input [3:0] s_axis_cc_tuser_a, + input s_axis_cc_tvalid_a + ); + + wire s_axis_cc_tready_ff, + s_axis_cc_tvalid_ff, + s_axis_cc_tlast_ff; + wire [15:0] s_axis_cc_tkeep_or = {s_axis_cc_tkeep[60], s_axis_cc_tkeep[56], + s_axis_cc_tkeep[52], s_axis_cc_tkeep[48], + s_axis_cc_tkeep[44], s_axis_cc_tkeep[40], + s_axis_cc_tkeep[36], s_axis_cc_tkeep[32], + s_axis_cc_tkeep[28], s_axis_cc_tkeep[24], + s_axis_cc_tkeep[20], s_axis_cc_tkeep[16], + s_axis_cc_tkeep[12], s_axis_cc_tkeep[8], + s_axis_cc_tkeep[4], s_axis_cc_tkeep[0]}; + + wire [3:0] s_axis_cc_tuser_ff; + wire [15:0] s_axis_cc_tkeep_ff; + wire [511:0] s_axis_cc_tdata_ff; + + axis_iff #(.DAT_B(512+16+4)) s_axis_cc_iff + ( + .clk (user_clk_out), + .rst (user_reset_out), + + .i_vld (s_axis_cc_tvalid), + .o_rdy (s_axis_cc_tready), + .i_sop (1'b0), + .i_eop (s_axis_cc_tlast), + .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), + + .o_vld (s_axis_cc_tvalid_ff), + .i_rdy (s_axis_cc_tready_ff), + .o_sop (), + .o_eop (s_axis_cc_tlast_ff), + .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) + ); + + reg [1:0] s_axis_cc_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) s_axis_cc_cnt <= 2'd0; + else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) + begin + if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; + else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; + end + + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; + + wire [3:0] s_axis_cc_tready_a; + + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; + + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; + + wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + + assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; + wire [511:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[511:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + wire [15:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v new file mode 100644 index 00000000..4955a414 --- /dev/null +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v @@ -0,0 +1,148 @@ +module s_axis_rq_adapt_x16 # ( + parameter DATA_WIDTH = 128, + parameter KEEP_WIDTH = DATA_WIDTH/8 + )( + + input user_clk, + input user_reset, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + output s_axis_rq_tlast, + input [3:0] s_axis_rq_tready, + output [3:0] s_axis_rq_tuser, + output s_axis_rq_tvalid, + + input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + input s_axis_rq_tlast_a, + output [3:0] s_axis_rq_tready_a, + input [3:0] s_axis_rq_tuser_a, + input s_axis_rq_tvalid_a + ); + + wire s_axis_rq_tready_ff, + s_axis_rq_tvalid_ff, + s_axis_rq_tlast_ff; + wire [15:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[60], s_axis_rq_tkeep[56], s_axis_rq_tkeep[52], s_axis_rq_tkeep[48], + s_axis_rq_tkeep[44], s_axis_rq_tkeep[40], s_axis_rq_tkeep[36], s_axis_rq_tkeep[32], + s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], + s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; + + wire [3:0] s_axis_rq_tuser_ff; + wire [15:0] s_axis_rq_tkeep_ff; + wire [511:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(512+16+4)) s_axis_rq_iff + ( + .clk (user_clk_out), + .rst (user_reset_out), + + .i_vld (s_axis_rq_tvalid), + .o_rdy (s_axis_rq_tready), + .i_sop (1'b0), + .i_eop (s_axis_rq_tlast), + .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), + + .o_vld (s_axis_rq_tvalid_ff), + .i_rdy (s_axis_rq_tready_ff), + .o_sop (), + .o_eop (s_axis_rq_tlast_ff), + .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) + ); + + + reg [1:0] s_axis_rq_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_cnt <= 2'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + begin + if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; + else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; + end + + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; + + //processing for tlast: generate new last in case write & last num of dword = 13 + i*16 + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_write = !s_axis_rq_read; + reg s_axis_rq_tlast_dly_en; + reg s_axis_rq_tlast_lat; + wire [3:0] s_axis_rq_tready_a; + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[3:0] == 5'd13); + + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + begin + if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd13) : 1'b0; //write 13 dwords + else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; + end + + wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd13)) : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + + //Generae ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request + s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request + s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request + s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 + s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 + 4'b1111; + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; + + always @(posedge user_clk_out) + begin + if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) + begin + s_axis_rq_firstbe_l <= s_axis_rq_firstbe; + s_axis_rq_lastbe_l <= s_axis_rq_lastbe; + end + end + + reg [31:0] s_axis_rq_tdata_l; + always @(posedge user_clk_out) + if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[511:480]; + + wire [511:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[479:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : + {s_axis_rq_tdata_ff[479:0], s_axis_rq_tdata_l[31:0]}; + wire [15:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 16'h1 : {s_axis_rq_tkeep_ff[14:0], 1'b1}; + wire [136:0] s_axis_rq_tuser_a; + assign s_axis_rq_tuser_a[36] = s_axis_rq_tuser_ff[3]; //discontinue + assign s_axis_rq_tuser_a[15:0] = {4'b0, s_axis_rq_lastbe, 4'b0, s_axis_rq_firstbe}; + +endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v index 789801d8..5194379a 100644 --- a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v @@ -313,410 +313,114 @@ module pcie_support # ( //----------------------------------------------------------------------------------------------------------------// //----------------------------------------------------- RQ AXIS --------------------------------------------------// - wire s_axis_rq_tready_ff, - s_axis_rq_tvalid_ff, - s_axis_rq_tlast_ff; - wire [15:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[60], s_axis_rq_tkeep[56], s_axis_rq_tkeep[52], s_axis_rq_tkeep[48], - s_axis_rq_tkeep[44], s_axis_rq_tkeep[40], s_axis_rq_tkeep[36], s_axis_rq_tkeep[32], - s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], - s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; - - wire [3:0] s_axis_rq_tuser_ff; - wire [15:0] s_axis_rq_tkeep_ff; - wire [511:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(512+16+4)) s_axis_rq_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_rq_tvalid), - .o_rdy (s_axis_rq_tready), - .i_sop (1'b0), - .i_eop (s_axis_rq_tlast), - .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), - - .o_vld (s_axis_rq_tvalid_ff), - .i_rdy (s_axis_rq_tready_ff), - .o_sop (), - .o_eop (s_axis_rq_tlast_ff), - .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) - ); - - - reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; - end - - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - - //processing for tlast: generate new last in case write & last num of dword = 13 + i*16 - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[3:0] == 5'd13); - - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) - begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd13) : 1'b0; //write 13 dwords - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; - end - - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd13)) : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; - always @(posedge user_clk_out) - begin - if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) - begin - s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; - end - end - - reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) - if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[511:480]; - - wire [511:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[479:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : - {s_axis_rq_tdata_ff[479:0], s_axis_rq_tdata_l[31:0]}; - wire [15:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 16'h1 : {s_axis_rq_tkeep_ff[14:0], 1'b1}; - wire [136:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[36] = s_axis_rq_tuser_ff[3]; //discontinue - assign s_axis_rq_tuser_a[15:0] = {4'b0, s_axis_rq_lastbe, 4'b0, s_axis_rq_firstbe}; + s_axis_rq_adapt_x16 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_rq_adapt_x16_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_rq_tdata(s_axis_rq_tdata), + .s_axis_rq_tkeep(s_axis_rq_tkeep), + .s_axis_rq_tlast(s_axis_rq_tlast), + .s_axis_rq_tready(s_axis_rq_tready), + .s_axis_rq_tuser(s_axis_rq_tuser), + .s_axis_rq_tvalid(s_axis_rq_tvalid), + + .s_axis_rq_tdata_a(s_axis_rq_tdata_a), + .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), + .s_axis_rq_tlast_a(s_axis_rq_tlast_a), + .s_axis_rq_tready_a(s_axis_rq_tready_a), + .s_axis_rq_tuser_a(s_axis_rq_tuser_a), + .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) + ); //----------------------------------------------------- RC AXIS --------------------------------------------------// + wire m_axis_rc_tvalid_a; wire m_axis_rc_tready_a; - wire [15:0] m_axis_rc_tkeep_a; - wire [511:0] m_axis_rc_tdata_a; + wire [7:0] m_axis_rc_tkeep_a; + wire [127:0] m_axis_rc_tdata_a; wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; - else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) - begin - if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; - else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; - end - - wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] - wire m_axis_rc_second = m_axis_rc_cnt == 1; - - //header process - wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; - reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) - if (m_axis_rc_tvalid_a && m_axis_rc_sop) - begin - m_axis_rc_poisoning_l <= m_axis_rc_poisoning; - end - - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; - wire [4:0] m_axis_rc_type; - wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; - wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; - wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; - - assign {m_axis_rc_fmt, - m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data - 8'b010_01011) : //Read-Locked Completion w/ data - ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data - 8'b010_01010); //Completion w/ data - - wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen}; - wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr}; - - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[511:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[63:12], 12'hFFF} : m_axis_rc_tuser_a[63:0]; - assign m_axis_rc_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + m_axis_rc_adapt_x16 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_rc_adapt_x16_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_rc_tdata( m_axis_rc_tdata), + .m_axis_rc_tkeep( m_axis_rc_tkeep), + .m_axis_rc_tlast( m_axis_rc_tlast), + .m_axis_rc_tready(m_axis_rc_tready), + .m_axis_rc_tuser( m_axis_rc_tuser), + .m_axis_rc_tvalid(m_axis_rc_tvalid), + + .m_axis_rc_tdata_a( m_axis_rc_tdata_a), + .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), + .m_axis_rc_tlast_a( m_axis_rc_tlast_a), + .m_axis_rc_tready_a(m_axis_rc_tready_a), + .m_axis_rc_tuser_a( m_axis_rc_tuser_a), + .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) + ); //----------------------------------------------------- CQ AXIS --------------------------------------------------// + wire m_axis_cq_tvalid_a; wire m_axis_cq_tready_a; - wire [15:0] m_axis_cq_tkeep_a; - wire [511:0] m_axis_cq_tdata_a; - wire [96:0] m_axis_cq_tuser_a; + wire [7:0] m_axis_cq_tkeep_a; + wire [127:0] m_axis_cq_tdata_a; + wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch - reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; - else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; - end - - wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); - wire m_axis_cq_second = m_axis_cq_cnt == 1; - - reg m_axis_cq_rdwr_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_rdwr_l <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_rdwr_l <= m_axis_cq_tlast_a; - - //processing for tlast: generate new last in case write & last num of dword != 13 + i*16 - wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request - wire m_axis_cq_write = !m_axis_cq_read; - wire [9:0] m_axis_cq_dwlen; - reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tlast_dly_en <= m_axis_cq_tlast_a | (m_axis_cq_dwlen[3:0] != 4'd13); - - reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) - begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read or write - else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; - end - - //Generae ready for PCIe IP - assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); - - //output for TLP - assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; - assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; - - - ////keep address (low) or data (high), not header - reg [511:0] m_axis_cq_tdata_a1; - reg [63:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; - m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[79:16]; - end - - //data processing - wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; - wire [4:0] m_axis_cq_type; - wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = {m_axis_cq_tuser_a[11:8], m_axis_cq_tuser_a[3:0]}; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; - wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; - - assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request - m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked - m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request - m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request - m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request - m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 - m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 - 8'b000_00000; //Mem read Request - - reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop - - reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = {m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen}; - - assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[511:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : - {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[511:32]}; - assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[63:16], 12'hFFF} : - m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[63:4]} : {64{1'b1}}; - assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_tuser_a[96] //ECRC mapped to discontinue - }; + m_axis_cq_adapt_x16 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_cq_adapt_x16_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_cq_tdata( m_axis_cq_tdata), + .m_axis_cq_tkeep( m_axis_cq_tkeep), + .m_axis_cq_tlast( m_axis_cq_tlast), + .m_axis_cq_tready(m_axis_cq_tready), + .m_axis_cq_tuser( m_axis_cq_tuser), + .m_axis_cq_tvalid(m_axis_cq_tvalid), + + .m_axis_cq_tdata_a( s_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( s_axis_cq_tlast_a), + .m_axis_cq_tready_a(s_axis_cq_tready_a), + .m_axis_cq_tuser_a( s_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + ); //----------------------------------------------------- CC AXIS --------------------------------------------------// - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; - wire [15:0] s_axis_cc_tkeep_or = {s_axis_cc_tkeep[60], s_axis_cc_tkeep[56], - s_axis_cc_tkeep[52], s_axis_cc_tkeep[48], - s_axis_cc_tkeep[44], s_axis_cc_tkeep[40], - s_axis_cc_tkeep[36], s_axis_cc_tkeep[32], - s_axis_cc_tkeep[28], s_axis_cc_tkeep[24], - s_axis_cc_tkeep[20], s_axis_cc_tkeep[16], - s_axis_cc_tkeep[12], s_axis_cc_tkeep[8], - s_axis_cc_tkeep[4], s_axis_cc_tkeep[0]}; - - wire [3:0] s_axis_cc_tuser_ff; - wire [15:0] s_axis_cc_tkeep_ff; - wire [511:0] s_axis_cc_tdata_ff; - - axis_iff #(.DAT_B(512+16+4)) s_axis_cc_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_cc_tvalid), - .o_rdy (s_axis_cc_tready), - .i_sop (1'b0), - .i_eop (s_axis_cc_tlast), - .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), - - .o_vld (s_axis_cc_tvalid_ff), - .i_rdy (s_axis_cc_tready_ff), - .o_sop (), - .o_eop (s_axis_cc_tlast_ff), - .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) - ); - - reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; - else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; - end - - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; - wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; - wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; - wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; - wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr}; - wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; - - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [511:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[511:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [15:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + + s_axis_cc_adapt_x16 #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_cc_adapt_x16_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_cc_tdata(s_axis_cc_tdata), + .s_axis_cc_tkeep(s_axis_cc_tkeep), + .s_axis_cc_tlast(s_axis_cc_tlast), + .s_axis_cc_tready(s_axis_cc_tready), + .s_axis_cc_tuser(s_axis_cc_tuser), + .s_axis_cc_tvalid(s_axis_cc_tvalid), + + .s_axis_cc_tdata_a(s_axis_cc_tdata_a), + .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), + .s_axis_cc_tlast_a(s_axis_cc_tlast_a), + .s_axis_cc_tready_a(s_axis_cc_tready_a), + .s_axis_cc_tuser_a(s_axis_cc_tuser_a), + .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) + ); //---------------------------------------------------------------------------------------------------------------// // MSI Adaptation Logic // From 27e849814a8f70a5570b61ce7cdb144edb885c4f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 16:56:53 +0200 Subject: [PATCH 24/41] phy/us(p)pciephy: Ony add appropriate adaptation files based on nlanes. --- litepcie/phy/uspciephy.py | 20 +++++++++++--------- litepcie/phy/usppciephy.py | 24 +++++++++++++++--------- 2 files changed, 26 insertions(+), 18 deletions(-) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 9626f072..c44955e9 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -414,15 +414,17 @@ def add_sources(self, platform, phy_path, phy_filename=None): platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "axis_iff.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_rq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_rc_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x4.v")) - - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_rq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_rc_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x8.v")) + if self.nlanes == 4: + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_rq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_rc_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x4.v")) + + if self.nlanes == 8: + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_rq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_rc_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x8.v")) platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py index 2027b7dc..2e89e495 100644 --- a/litepcie/phy/usppciephy.py +++ b/litepcie/phy/usppciephy.py @@ -415,15 +415,21 @@ def add_sources(self, platform, phy_path, phy_filename=None): platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "axis_iff.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x4.v")) - - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x8.v")) + if self.nlanes == 4: + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x4.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x4.v")) + if self.nlanes == 8: + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x8.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x8.v")) + if self.nlanes == 16: + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x16.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x16.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x16.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x16.v")) platform.add_source(os.path.join(phy_path, "pcie_usp_support.v")) From c25efc8e69155bb1edaed87e73bd008d479cf468 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 17:14:25 +0200 Subject: [PATCH 25/41] bench/fk33/xu1525: Support x4/x8 and x16 configs. --- bench/fk33.py | 6 ++++-- bench/xcu1525.py | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/bench/fk33.py b/bench/fk33.py index 068c2d73..f84d5301 100755 --- a/bench/fk33.py +++ b/bench/fk33.py @@ -42,7 +42,9 @@ def __init__(self, platform, sys_clk_freq): class LitePCIeSoC(SoCMini): configs = { # Gen3 data_width, sys_clk_freq - "gen3:x4": (128, int(200e6)), + "gen3:x4" : (128, int(200e6)), + "gen3:x8" : (256, int(200e6)), + "gen3:x16": (512, int(200e6)), } def __init__(self, platform, speed="gen3", nlanes=4): data_width, sys_clk_freq = self.configs[speed + f":x{nlanes}"] @@ -109,7 +111,7 @@ def main(): parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") parser.add_argument("--speed", default="gen3", help="PCIe speed: gen3") - parser.add_argument("--nlanes", default=4, help="PCIe lanes: 4 (default) or 8") + parser.add_argument("--nlanes", default=4, help="PCIe lanes: 4 (default), 8 or 16") args = parser.parse_args() platform = sqrl_fk33.Platform() diff --git a/bench/xcu1525.py b/bench/xcu1525.py index 742c9ccc..1b54bf99 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -112,7 +112,7 @@ def main(): parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") parser.add_argument("--speed", default="gen3", help="PCIe speed: gen3") - parser.add_argument("--nlanes", default=4, help="PCIe lanes: 4 (default) or 8") + parser.add_argument("--nlanes", default=4, help="PCIe lanes: 4 (default), 8 or 16") args = parser.parse_args() platform = sqrl_xcu1525.Platform() From c540ef3c892b2c3f60325d77e32e31b69b54a843 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 17:30:36 +0200 Subject: [PATCH 26/41] phy/xilinx_us(p): Only keep xn suffix in filenames, not module names and minor others cleanups. --- litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v | 2 +- litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v | 2 +- litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v | 2 +- litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v | 2 +- litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v | 2 +- litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v | 2 +- litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v | 2 +- litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v | 2 +- .../phy/xilinx_us_gen3_x4/pcie_us_support.v | 16 +-- .../phy/xilinx_us_gen3_x8/pcie_us_support.v | 16 +-- litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v | 31 ++-- litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v | 33 ++--- litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v | 31 ++-- litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v | 15 +- litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v | 15 +- litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v | 8 +- litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v | 10 +- litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v | 14 +- litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v | 10 +- litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v | 22 +-- litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v | 135 +++++++++++++++++- litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v | 22 +-- .../xilinx_usp_gen3_x16/pcie_usp_support.v | 16 +-- .../phy/xilinx_usp_gen3_x4/pcie_usp_support.v | 16 +-- .../phy/xilinx_usp_gen3_x8/pcie_usp_support.v | 16 +-- 25 files changed, 270 insertions(+), 172 deletions(-) diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v index 9a1c3467..2bc4f0da 100644 --- a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v @@ -1,4 +1,4 @@ - module m_axis_cq_adapt_x4 # ( +module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v index d5f20b45..242efc7c 100644 --- a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v @@ -1,4 +1,4 @@ - module m_axis_cq_adapt_x8 # ( +module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v index 3c0e94a8..a01301c0 100644 --- a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v +++ b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v @@ -1,4 +1,4 @@ - module m_axis_rc_adapt_x4 # ( +module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v index 1126d218..fa0dae2f 100644 --- a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v @@ -1,4 +1,4 @@ - module m_axis_rc_adapt_x8 # ( +module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v index b9e447e5..34fa9026 100644 --- a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v @@ -1,4 +1,4 @@ - module s_axis_cc_adapt_x4 # ( +module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v index 3dabf845..533be5d5 100644 --- a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v @@ -1,4 +1,4 @@ - module s_axis_cc_adapt_x8 # ( +module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v index 8b57b0a0..25527df1 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v @@ -1,4 +1,4 @@ - module s_axis_rq_adapt_x4 # ( +module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v index a3e62307..49391c43 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v @@ -1,4 +1,4 @@ - module s_axis_rq_adapt_x8 # ( +module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v index b5c87536..8c84c812 100644 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v @@ -314,10 +314,10 @@ module pcie_support # ( //----------------------------------------------------- RQ AXIS -------------------------------------------------// - s_axis_rq_adapt_x4 #( + s_axis_rq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_x4_i ( + ) s_axis_rq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -345,10 +345,10 @@ module pcie_support # ( wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - m_axis_rc_adapt_x4 #( + m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_x4_i ( + ) m_axis_rc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -376,10 +376,10 @@ module pcie_support # ( wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - m_axis_cq_adapt_x4 #( + m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_x4_i ( + ) m_axis_cq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -400,10 +400,10 @@ module pcie_support # ( //----------------------------------------------------- CC AXIS --------------------------------------------------// - s_axis_cc_adapt_x4 #( + s_axis_cc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_x4_i ( + ) s_axis_cc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), diff --git a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v index e60fe432..565d7a16 100644 --- a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v @@ -314,10 +314,10 @@ module pcie_support # ( //----------------------------------------------------- RQ AXIS --------------------------------------------------// - s_axis_rq_adapt_x8 #( + s_axis_rq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_x8_i ( + ) s_axis_rq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -345,10 +345,10 @@ module pcie_support # ( wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - m_axis_rc_adapt_x8 #( + m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_x8_i ( + ) m_axis_rc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -376,10 +376,10 @@ module pcie_support # ( wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - m_axis_cq_adapt_x8 #( + m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_x8_i ( + ) m_axis_cq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -401,10 +401,10 @@ module pcie_support # ( //----------------------------------------------------- CC AXIS --------------------------------------------------// - s_axis_cc_adapt_x8 #( + s_axis_cc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_x8_i ( + ) s_axis_cc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v index d5e5fb60..e27500c2 100644 --- a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v @@ -1,4 +1,4 @@ - module m_axis_cq_adapt_x16 # ( +module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -21,17 +21,10 @@ input m_axis_cq_tvalid_a ); - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [15:0] m_axis_cq_tkeep_a; - wire [511:0] m_axis_cq_tdata_a; - wire [96:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_cnt <= 2'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; @@ -42,8 +35,8 @@ wire m_axis_cq_second = m_axis_cq_cnt == 1; reg m_axis_cq_rdwr_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_rdwr_l <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_rdwr_l <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_rdwr_l <= m_axis_cq_tlast_a; //processing for tlast: generate new last in case write & last num of dword != 13 + i*16 @@ -51,14 +44,14 @@ wire m_axis_cq_write = !m_axis_cq_read; wire [9:0] m_axis_cq_dwlen; reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_dly_en <= 1'd0; else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tlast_dly_en <= m_axis_cq_tlast_a | (m_axis_cq_dwlen[3:0] != 4'd13); reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin @@ -77,7 +70,7 @@ ////keep address (low) or data (high), not header reg [511:0] m_axis_cq_tdata_a1; reg [63:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; @@ -110,12 +103,12 @@ 8'b000_00000; //Mem read Request reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_header = {m_axis_cq_requesterid, m_axis_cq_tag, diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v index 4035dca8..9693f082 100644 --- a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v @@ -1,4 +1,4 @@ - module m_axis_cq_adapt_x4 # ( +module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -21,17 +21,10 @@ input m_axis_cq_tvalid_a ); - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [3:0] m_axis_cq_tkeep_a; - wire [127:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_cnt <= 2'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; @@ -44,15 +37,15 @@ wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request wire m_axis_cq_write = !m_axis_cq_read; reg m_axis_cq_read_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_read_l <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_read_l <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_read_l <= m_axis_cq_read; //processing for tlast wire [9:0] m_axis_cq_dwlen; reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_dly_en <= 1'd0; else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_sop) begin @@ -61,8 +54,8 @@ end reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin @@ -81,7 +74,7 @@ ////keep address (low) or data (high), not header reg [127:0] m_axis_cq_tdata_a1; reg [15:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; @@ -114,18 +107,18 @@ 8'b000_00000; //Mem read Request reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop reg m_axis_cq_ecrc; - always @(posedge user_clk_out) + always @(posedge user_clk) begin m_axis_cq_ecrc <= m_axis_cq_tuser_a[41]; end reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_header = {m_axis_cq_requesterid, m_axis_cq_tag, diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v index 8721e62a..0aef7324 100644 --- a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v @@ -1,4 +1,4 @@ - module m_axis_cq_adapt_x8 # ( +module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -21,17 +21,10 @@ input m_axis_cq_tvalid_a ); - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [7:0] m_axis_cq_tkeep_a; - wire [255:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - //dword counter: //0-2 & latch reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_cnt <= 2'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; @@ -42,8 +35,8 @@ wire m_axis_cq_second = m_axis_cq_cnt == 1; reg m_axis_cq_rdwr_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_rdwr_l <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_rdwr_l <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_rdwr_l <= m_axis_cq_tlast_a; //processing for tlast: generate new last in case write & last num of dword != 5 + i*8 @@ -51,14 +44,14 @@ wire m_axis_cq_write = !m_axis_cq_read; wire [9:0] m_axis_cq_dwlen; reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_dly_en <= 1'd0; else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tlast_dly_en <= m_axis_cq_tlast_a | (m_axis_cq_dwlen[2:0] != 3'd5); reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; + always @(posedge user_clk) + if (user_reset) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin @@ -77,7 +70,7 @@ ////keep address (low) or data (high), not header reg [255:0] m_axis_cq_tdata_a1; reg [31:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; @@ -110,12 +103,12 @@ 8'b000_00000; //Mem read Request reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_header = {m_axis_cq_requesterid, m_axis_cq_tag, diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v index 0e718b53..9930da16 100644 --- a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v @@ -1,4 +1,4 @@ - module m_axis_rc_adapt_x16 # ( +module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -21,16 +21,9 @@ input m_axis_rc_tvalid_a ); - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [15:0] m_axis_rc_tkeep_a; - wire [511:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) m_axis_rc_cnt <= 2'd0; else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) begin if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; @@ -43,7 +36,7 @@ //header process wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_rc_tvalid_a && m_axis_rc_sop) begin m_axis_rc_poisoning_l <= m_axis_rc_poisoning; diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v index bbfa395f..4f042b64 100644 --- a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v @@ -1,4 +1,4 @@ - module m_axis_rc_adapt_x4 # ( +module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -21,16 +21,9 @@ input m_axis_rc_tvalid_a ); - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [3:0] m_axis_rc_tkeep_a; - wire [127:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) m_axis_rc_cnt <= 2'd0; else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) begin if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; @@ -43,7 +36,7 @@ //header process wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_rc_tvalid_a && m_axis_rc_sop) begin m_axis_rc_poisoning_l <= m_axis_rc_poisoning; diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v index 0f9a1795..694f464e 100644 --- a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v @@ -1,4 +1,4 @@ - module m_axis_rc_adapt_x8 # ( +module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -22,8 +22,8 @@ ); reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) m_axis_rc_cnt <= 2'd0; else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) begin if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; @@ -36,7 +36,7 @@ //header process wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) + always @(posedge user_clk) if (m_axis_rc_tvalid_a && m_axis_rc_sop) begin m_axis_rc_poisoning_l <= m_axis_rc_poisoning; diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v index 7c1992c6..8cb8680c 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v @@ -1,4 +1,4 @@ - module s_axis_cc_adapt_x16 # ( +module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -39,8 +39,8 @@ axis_iff #(.DAT_B(512+16+4)) s_axis_cc_iff ( - .clk (user_clk_out), - .rst (user_reset_out), + .clk (user_clk), + .rst (user_reset), .i_vld (s_axis_cc_tvalid), .o_rdy (s_axis_cc_tready), @@ -56,8 +56,8 @@ ); reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) s_axis_cc_cnt <= 2'd0; else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) begin if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v index d7330164..5cd4bb44 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v @@ -1,4 +1,4 @@ - module s_axis_cc_adapt_x4 # ( +module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -33,8 +33,8 @@ axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff ( - .clk (user_clk_out), - .rst (user_reset_out), + .clk (user_clk), + .rst (user_reset), .i_vld (s_axis_cc_tvalid), .o_rdy (s_axis_cc_tready), @@ -50,8 +50,8 @@ ); reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) s_axis_cc_cnt <= 2'd0; else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) begin if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; @@ -95,8 +95,8 @@ reg [3:0] s_axis_cc_lastbe; reg s_axis_cc_tvalid_ff_lat; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_tvalid_ff_lat <= 1'd0; + always @(posedge user_clk) + if (user_reset) s_axis_cc_tvalid_ff_lat <= 1'd0; else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) begin if (s_axis_cc_tlast_ff) s_axis_cc_tvalid_ff_lat <= 1'd0; diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v index 6e7414ab..b2373b3b 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v @@ -1,4 +1,4 @@ - module s_axis_cc_adapt_x8 # ( +module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -35,8 +35,8 @@ axis_iff #(.DAT_B(256+8+4)) s_axis_cc_iff ( - .clk (user_clk_out), - .rst (user_reset_out), + .clk (user_clk), + .rst (user_reset), .i_vld (s_axis_cc_tvalid), .o_rdy (s_axis_cc_tready), @@ -52,8 +52,8 @@ ); reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) s_axis_cc_cnt <= 2'd0; else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) begin if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v index 4955a414..e2f8350b 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v @@ -1,4 +1,4 @@ -module s_axis_rq_adapt_x16 # ( +module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -35,8 +35,8 @@ module s_axis_rq_adapt_x16 # ( axis_iff #(.DAT_B(512+16+4)) s_axis_rq_iff ( - .clk (user_clk_out), - .rst (user_reset_out), + .clk (user_clk), + .rst (user_reset), .i_vld (s_axis_rq_tvalid), .o_rdy (s_axis_rq_tready), @@ -53,8 +53,8 @@ module s_axis_rq_adapt_x16 # ( reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) s_axis_rq_cnt <= 2'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) begin if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; @@ -70,12 +70,12 @@ module s_axis_rq_adapt_x16 # ( reg s_axis_rq_tlast_dly_en; reg s_axis_rq_tlast_lat; wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[3:0] == 5'd13); - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) begin @@ -124,7 +124,7 @@ module s_axis_rq_adapt_x16 # ( reg [3:0] s_axis_rq_firstbe_l; reg [3:0] s_axis_rq_lastbe_l; - always @(posedge user_clk_out) + always @(posedge user_clk) begin if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) begin @@ -134,7 +134,7 @@ module s_axis_rq_adapt_x16 # ( end reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) + always @(posedge user_clk) if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[511:480]; diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v index ce396ca9..f1bd0c6f 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v @@ -1,4 +1,4 @@ - module s_axis_rq_adapt_x4 # ( +module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -21,4 +21,137 @@ input s_axis_rq_tvalid_a ); + wire s_axis_rq_tready_ff, + s_axis_rq_tvalid_ff, + s_axis_rq_tlast_ff; + wire [3:0] s_axis_rq_tkeep_or = {|s_axis_rq_tkeep[15:12], |s_axis_rq_tkeep[11:8], |s_axis_rq_tkeep[7:4], |s_axis_rq_tkeep[3:0]}; + + wire [3:0] s_axis_rq_tuser_ff; + wire [3:0] s_axis_rq_tkeep_ff; + wire [127:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff + ( + .clk (user_clk_out), + .rst (user_reset_out), + + .i_vld (s_axis_rq_tvalid), + .o_rdy (s_axis_rq_tready), + .i_sop (1'b0), + .i_eop (s_axis_rq_tlast), + .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), + + .o_vld (s_axis_rq_tvalid_ff), + .i_rdy (s_axis_rq_tready_ff), + .o_sop (), + .o_eop (s_axis_rq_tlast_ff), + .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) + ); + + + reg [1:0] s_axis_rq_cnt; //0-2 + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_cnt <= 2'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + begin + if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; + else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; + end + + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; + + //processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_write = !s_axis_rq_read; + reg s_axis_rq_tlast_dly_en; + reg s_axis_rq_tlast_lat; + wire [3:0] s_axis_rq_tready_a; + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); + + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + begin + if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword + else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; + end + + wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + + //Generae ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + + //latch valid because it is uncontigous when coming from TLP request + reg s_axis_rq_tvalid_lat; + always @(posedge user_clk_out) + if (user_reset_out) s_axis_rq_tvalid_lat <= 1'b0; + else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) + begin + if (s_axis_rq_tlast_dly_en) s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; + else s_axis_rq_tvalid_lat <= !(s_axis_rq_tlast_ff && s_axis_rq_tvalid_ff); + end + else if (s_axis_rq_tvalid_ff & s_axis_rq_tfirst & s_axis_rq_write) s_axis_rq_tvalid_lat <= 1'b1; //latche input valid (required by PCIe IP) + + wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request + s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request + s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request + s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 + s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 + 4'b1111; + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; + + always @(posedge user_clk_out) + begin + if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) + begin + s_axis_rq_firstbe_l <= s_axis_rq_firstbe; + s_axis_rq_lastbe_l <= s_axis_rq_lastbe; + end + end + + reg [31:0] s_axis_rq_tdata_l; + always @(posedge user_clk_out) + if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) + s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; + + wire [127:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; + wire [3:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; + wire [59:0] s_axis_rq_tuser_a; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + + endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v index b9402b89..077ef563 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v @@ -1,4 +1,4 @@ - module s_axis_rq_adapt_x8 # ( +module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -33,8 +33,8 @@ axis_iff #(.DAT_B(256+8+4)) s_axis_rq_iff ( - .clk (user_clk_out), - .rst (user_reset_out), + .clk (user_clk), + .rst (user_reset), .i_vld (s_axis_rq_tvalid), .o_rdy (s_axis_rq_tready), @@ -51,8 +51,8 @@ reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; + always @(posedge user_clk) + if (user_reset) s_axis_rq_cnt <= 2'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) begin if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; @@ -68,12 +68,12 @@ reg s_axis_rq_tlast_dly_en; reg s_axis_rq_tlast_lat; wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) begin @@ -122,7 +122,7 @@ reg [3:0] s_axis_rq_firstbe_l; reg [3:0] s_axis_rq_lastbe_l; - always @(posedge user_clk_out) + always @(posedge user_clk) begin if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) begin @@ -132,7 +132,7 @@ end reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) + always @(posedge user_clk) if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; diff --git a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v index 5194379a..af28cb8a 100644 --- a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v @@ -314,10 +314,10 @@ module pcie_support # ( //----------------------------------------------------- RQ AXIS --------------------------------------------------// - s_axis_rq_adapt_x16 #( + s_axis_rq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_x16_i ( + ) s_axis_rq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -345,10 +345,10 @@ module pcie_support # ( wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - m_axis_rc_adapt_x16 #( + m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_x16_i ( + ) m_axis_rc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -376,10 +376,10 @@ module pcie_support # ( wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - m_axis_cq_adapt_x16 #( + m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_x16_i ( + ) m_axis_cq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -400,10 +400,10 @@ module pcie_support # ( //----------------------------------------------------- CC AXIS --------------------------------------------------// - s_axis_cc_adapt_x16 #( + s_axis_cc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_x16_i ( + ) s_axis_cc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), diff --git a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v index b99178a6..2c097f64 100644 --- a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v @@ -314,10 +314,10 @@ module pcie_support # ( //----------------------------------------------------- RQ AXIS -------------------------------------------------// - s_axis_rq_adapt_x4 #( + s_axis_rq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_x4_i ( + ) s_axis_rq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -345,10 +345,10 @@ module pcie_support # ( wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - m_axis_rc_adapt_x4 #( + m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_x4_i ( + ) m_axis_rc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -376,10 +376,10 @@ module pcie_support # ( wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - m_axis_cq_adapt_x4 #( + m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_x4_i ( + ) m_axis_cq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -400,10 +400,10 @@ module pcie_support # ( //----------------------------------------------------- CC AXIS --------------------------------------------------// - s_axis_cc_adapt_x4 #( + s_axis_cc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_x4_i ( + ) s_axis_cc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), diff --git a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v index 8027ecb5..7872b2ec 100644 --- a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v @@ -314,10 +314,10 @@ module pcie_support # ( //----------------------------------------------------- RQ AXIS --------------------------------------------------// - s_axis_rq_adapt_x8 #( + s_axis_rq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_x8_i ( + ) s_axis_rq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -345,10 +345,10 @@ module pcie_support # ( wire [74:0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; - m_axis_rc_adapt_x8 #( + m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_x8_i ( + ) m_axis_rc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -376,10 +376,10 @@ module pcie_support # ( wire [84:0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; - m_axis_cq_adapt_x8 #( + m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_x8_i ( + ) m_axis_cq_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), @@ -401,10 +401,10 @@ module pcie_support # ( //----------------------------------------------------- CC AXIS --------------------------------------------------// - s_axis_cc_adapt_x8 #( + s_axis_cc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_x8_i ( + ) s_axis_cc_adapt_i ( .user_clk(user_clk_out), .user_reset(user_reset_out), From 01f15bd88a8f5c13afb15c60f4e2b51f6083f9e4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 17:31:20 +0200 Subject: [PATCH 27/41] phy/xilinx_usp: Remove specific hbm config (will no longer be required). --- .../xilinx_usp_hbm_gen3_x4/pcie_usp_support.v | 1005 ----------------- 1 file changed, 1005 deletions(-) delete mode 100644 litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v diff --git a/litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v b/litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v deleted file mode 100644 index a3d83969..00000000 --- a/litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v +++ /dev/null @@ -1,1005 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Ultrascale Integrated Block for PCI Express -// File : pcie_support.v -// Version : 4.4 -//-- -//-- Description: PCI Express Endpoint Shared Logic Wrapper -//-- -//------------------------------------------------------------------------------ - -`timescale 1ns / 1ps - -// Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital - -//----------------------------------------------------------------------------------------------------------------// -// PCIe // -//----------------------------------------------------------------------------------------------------------------// - -(* DowngradeIPIdentifiedWarnings = "yes" *) -module pcie_support # ( - parameter LINK_CAP_MAX_LINK_WIDTH = 4, // PCIe Lane Width - parameter C_DATA_WIDTH = 128, // AXI interface data width - parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width - parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device - parameter PCIE_USE_MODE = "2.0" // PCIe use mode -) -( - - input sys_clk, - input sys_clk_gt, - input sys_rst_n, - - //----------------------------------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //----------------------------------------------------------------------------------------------------------------// - - // Tx - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, - - // Rx - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, - - //----------------------------------------------------------------------------------------------------------------// - // AXI-S Interface // - //----------------------------------------------------------------------------------------------------------------// - - output user_clk_out, - output user_reset_out, - output user_lnk_up, - output user_app_rdy, - - //Requester Request - output [1:0] pcie_tfc_nph_av, //Transmit flow control non-posted header credit & data available - output [1:0] pcie_tfc_npd_av, - output [3:0] pcie_rq_seq_num, - output pcie_rq_seq_num_vld, - output [5:0] pcie_rq_tag, - output pcie_rq_tag_vld, - output [1:0] pcie_rq_tag_av, - input s_axis_rq_tlast, - input [C_DATA_WIDTH-1:0] s_axis_rq_tdata, - input [3:0] s_axis_rq_tuser, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tready, - input s_axis_rq_tvalid, - - //Requester Completion - output [C_DATA_WIDTH-1:0] m_axis_rc_tdata, - output [21:0] m_axis_rc_tuser, - output m_axis_rc_tlast, - output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, - output m_axis_rc_tvalid, - input m_axis_rc_tready, - - //Completer Request - output [C_DATA_WIDTH-1:0] m_axis_cq_tdata, - output [21:0] m_axis_cq_tuser, - output m_axis_cq_tlast, - output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, - output m_axis_cq_tvalid, - input m_axis_cq_tready, - - //Completer Completion - input [C_DATA_WIDTH-1:0] s_axis_cc_tdata, - input [3:0] s_axis_cc_tuser, - input s_axis_cc_tlast, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - input s_axis_cc_tvalid, - output s_axis_cc_tready, - - //----------------------------------------------------------------------------------------------------------------// - // Sequence & Tag Report // - //----------------------------------------------------------------------------------------------------------------// - - - input pcie_cq_np_req, - output [5:0] pcie_cq_np_req_count, - - //----------------------------------------------------------------------------------------------------------------// - // Error Reporting Interface // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_phy_link_down, - output [1:0] cfg_phy_link_status, - output [2:0] cfg_negotiated_width, - output [1:0] cfg_current_speed, - output [2:0] cfg_max_payload, - output [2:0] cfg_max_read_req, - output [15:0] cfg_function_status, - output [11:0] cfg_function_power_state, - output [15:0] cfg_vf_status, - output [23:0] cfg_vf_power_state, - output [1:0] cfg_link_power_state, - - output cfg_err_cor_out, - output cfg_err_nonfatal_out, - output cfg_err_fatal_out, - output cfg_ltr_enable, - output [5:0] cfg_ltssm_state, - output [3:0] cfg_rcb_status, - output [3:0] cfg_dpa_substate_change, - output [1:0] cfg_obff_enable, - output cfg_pl_status_change, - - output [3:0] cfg_tph_requester_enable, - output [11:0] cfg_tph_st_mode, - output [7:0] cfg_vf_tph_requester_enable, - output [23:0] cfg_vf_tph_st_mode, - - //----------------------------------------------------------------------------------------------------------------// - // Management Interface // - //----------------------------------------------------------------------------------------------------------------// - - output [31:0] cfg_mgmt_do, - output cfg_mgmt_rd_wr_done, - input [31:0] cfg_mgmt_di, - input [3:0] cfg_mgmt_byte_en, - input [18:0] cfg_mgmt_dwaddr, - input cfg_mgmt_wr_en, - input cfg_mgmt_rd_en, - - //----------------------------------------------------------------------------------------------------------------// - // Flow control // - //----------------------------------------------------------------------------------------------------------------// - - output [7:0] cfg_fc_ph, - output [11:0] cfg_fc_pd, - output [7:0] cfg_fc_nph, - output [11:0] cfg_fc_npd, - output [7:0] cfg_fc_cplh, - output [11:0] cfg_fc_cpld, - input [2:0] cfg_fc_sel, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Tx/Rx Message // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_msg_received, - output [7:0] cfg_msg_received_data, - output [4:0] cfg_msg_received_type, - - input cfg_msg_transmit, - input [31:0] cfg_msg_transmit_data, - input [2:0] cfg_msg_transmit_type, - output cfg_msg_transmit_done, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Control Interface // - //----------------------------------------------------------------------------------------------------------------// - - output pl_received_hot_rst, - input pl_transmit_hot_rst, - - // power-down request TLP - input cfg_power_state_change_ack, - output cfg_power_state_change_interrupt, - - // Indentication & Routing // - - input [63:0] cfg_dsn, //Device Serial Number - input [7:0] cfg_ds_bus_number, - input [4:0] cfg_ds_device_number, - input [2:0] cfg_ds_function_number, - input [7:0] cfg_ds_port_number, - input [15:0] cfg_subsys_vend_id, - //----------------------------------------------------------------------------------------------------------------// - // Interrupt Interface Signals - //----------------------------------------------------------------------------------------------------------------// - input [3:0] cfg_interrupt_int, - input cfg_interrupt_pending, - output cfg_interrupt_sent, - - output cfg_interrupt_msi_enable, //0: Legacy; 1: MSI - input [7:0] cfg_interrupt_msi_int, - input cfg_interrupt_msi_int_valid, - output cfg_interrupt_msi_sent, - output cfg_interrupt_msi_fail, - - output [11:0] cfg_interrupt_msi_mmenable, - output cfg_interrupt_msi_mask_update, - output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable, - - //Debug - output [15:0] debug //for cmp_source {error_code[3:], error_trigger} -); - - //----------------------------------------------------------------------------------------------------------------// - // System(SYS) Interface // - //----------------------------------------------------------------------------------------------------------------// - - wire [7:0] led_out; - - //----------------------------------------------------------------------------------------------------------------// - // Function request // - //----------------------------------------------------------------------------------------------------------------// - - wire [2:0] cfg_per_func_status_control = 3'b0; //request only function #0 - wire [15:0] cfg_per_func_status_data; - - //----------------------------------------------------------------------------------------------------------------// - // Function Level Reset Handle // - //----------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_flr_in_process; - wire [7:0] cfg_vf_flr_in_process; - reg [3:0] cfg_flr_done_reg0; - reg [7:0] cfg_vf_flr_done_reg0; - reg [3:0] cfg_flr_done_reg1; - reg [7:0] cfg_vf_flr_done_reg1; - - wire [1:0] cfg_flr_done; - wire [5:0] cfg_vf_flr_done; - - always @(posedge user_clk_out) - if (user_reset_out) begin - cfg_flr_done_reg0 <= 4'b0; - cfg_vf_flr_done_reg0 <= 8'b0; - cfg_flr_done_reg1 <= 4'b0; - cfg_vf_flr_done_reg1 <= 8'b0; - end - else begin - cfg_flr_done_reg0 <= cfg_flr_in_process; - cfg_vf_flr_done_reg0 <= cfg_vf_flr_in_process; - cfg_flr_done_reg1 <= cfg_flr_done_reg0; - cfg_vf_flr_done_reg1 <= cfg_vf_flr_done_reg0; - end - - assign cfg_flr_done[0] = ~cfg_flr_done_reg1[0] && cfg_flr_done_reg0[0]; - assign cfg_flr_done[1] = ~cfg_flr_done_reg1[1] && cfg_flr_done_reg0[1]; - - assign cfg_vf_flr_done[0] = ~cfg_vf_flr_done_reg1[0] && cfg_vf_flr_done_reg0[0]; - assign cfg_vf_flr_done[1] = ~cfg_vf_flr_done_reg1[1] && cfg_vf_flr_done_reg0[1]; - assign cfg_vf_flr_done[2] = ~cfg_vf_flr_done_reg1[2] && cfg_vf_flr_done_reg0[2]; - assign cfg_vf_flr_done[3] = ~cfg_vf_flr_done_reg1[3] && cfg_vf_flr_done_reg0[3]; - assign cfg_vf_flr_done[4] = ~cfg_vf_flr_done_reg1[4] && cfg_vf_flr_done_reg0[4]; - assign cfg_vf_flr_done[5] = ~cfg_vf_flr_done_reg1[5] && cfg_vf_flr_done_reg0[5]; - - // Device Information - wire [15:0] cfg_vend_id = 16'h10EE; - wire [15:0] cfg_dev_id = 16'h7021; - wire [15:0] cfg_subsys_id = 16'h0007; - wire [7:0] cfg_rev_id = 8'h00; - - //----------------------------------------------------------------------------------------------------------------// - // AXIS Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// - - //----------------------------------------------------- RQ AXIS --------------------------------------------------// - wire s_axis_rq_tready_ff, - s_axis_rq_tvalid_ff, - s_axis_rq_tlast_ff; - wire [3:0] s_axis_rq_tkeep_or = {|s_axis_rq_tkeep[15:12], |s_axis_rq_tkeep[11:8], |s_axis_rq_tkeep[7:4], |s_axis_rq_tkeep[3:0]}; - - wire [3:0] s_axis_rq_tuser_ff; - wire [3:0] s_axis_rq_tkeep_ff; - wire [127:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_rq_tvalid), - .o_rdy (s_axis_rq_tready), - .i_sop (1'b0), - .i_eop (s_axis_rq_tlast), - .i_dat ({s_axis_rq_tuser, s_axis_rq_tkeep_or, s_axis_rq_tdata}), - - .o_vld (s_axis_rq_tvalid_ff), - .i_rdy (s_axis_rq_tready_ff), - .o_sop (), - .o_eop (s_axis_rq_tlast_ff), - .o_dat ({s_axis_rq_tuser_ff, s_axis_rq_tkeep_ff, s_axis_rq_tdata_ff}) - ); - - - reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; - end - - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - - //processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); - - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) - begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; - end - - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - - //latch valid because it is uncontigous when coming from TLP request - reg s_axis_rq_tvalid_lat; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tvalid_lat <= 1'b0; - else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) - begin - if (s_axis_rq_tlast_dly_en) s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; - else s_axis_rq_tvalid_lat <= !(s_axis_rq_tlast_ff && s_axis_rq_tvalid_ff); - end - else if (s_axis_rq_tvalid_ff & s_axis_rq_tfirst & s_axis_rq_write) s_axis_rq_tvalid_lat <= 1'b1; //latche input valid (required by PCIe IP) - - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; - - always @(posedge user_clk_out) - begin - if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) - begin - s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; - end - end - - reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) - if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) - s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; - - wire [127:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; - wire [3:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; - - //----------------------------------------------------- RC AXIS --------------------------------------------------// - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [3:0] m_axis_rc_tkeep_a; - wire [127:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - - reg [1:0] m_axis_rc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) m_axis_rc_cnt <= 2'd0; - else if (m_axis_rc_tvalid_a && m_axis_rc_tready_a) - begin - if (m_axis_rc_tlast_a) m_axis_rc_cnt <= 2'd0; - else if (!m_axis_rc_cnt[1]) m_axis_rc_cnt <= m_axis_rc_cnt + 1; - end - - wire m_axis_rc_sop = (m_axis_rc_cnt == 0); //m_axis_rc_tuser_a[40] - wire m_axis_rc_second = m_axis_rc_cnt == 1; - - //header process - wire m_axis_rc_poisoning = m_axis_rc_tdata_a[46]; - reg m_axis_rc_poisoning_l; - always @(posedge user_clk_out) - if (m_axis_rc_tvalid_a && m_axis_rc_sop) - begin - m_axis_rc_poisoning_l <= m_axis_rc_poisoning; - end - - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; - wire [4:0] m_axis_rc_type; - wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; - wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; - wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; - - assign {m_axis_rc_fmt, - m_axis_rc_type} = m_axis_rc_tdata_a[29] ? ((m_axis_rc_bytecnt == 0) ? 8'b000_01011 : //Read-Locked Completion w/o data - 8'b010_01011) : //Read-Locked Completion w/ data - ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data - 8'b010_01010); //Completion w/ data - - wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen}; - wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr}; - - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; - assign m_axis_rc_tuser = { - 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; - - wire [3:0] rc_errcode = m_axis_rc_tdata_a[15:12]; - wire rc_status_err = ((m_axis_rc_cmpstatus != 3'b0) | (rc_errcode != 4'b0)) && m_axis_rc_tvalid && m_axis_rc_tready && m_axis_rc_sop; - - //----------------------------------------------------- CQ AXIS --------------------------------------------------// - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [3:0] m_axis_cq_tkeep_a; - wire [127:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - - //dword counter: //0-2 & latch - reg [1:0] m_axis_cq_cnt; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_cnt <= 2'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - if (m_axis_cq_tlast_a) m_axis_cq_cnt <= 2'd0; - else if (!m_axis_cq_cnt[1]) m_axis_cq_cnt <= m_axis_cq_cnt + 1; - end - - wire m_axis_cq_sop = (m_axis_cq_cnt == 0) && (!m_axis_cq_tlast_lat); //m_axis_cq_tuser_a[40] - wire m_axis_cq_second = m_axis_cq_cnt == 1; - - wire m_axis_cq_read = (m_axis_cq_fmt[1:0] == 2'b0); //Read request - wire m_axis_cq_write = !m_axis_cq_read; - reg m_axis_cq_read_l; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_read_l <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) m_axis_cq_read_l <= m_axis_cq_read; - - //processing for tlast - wire [9:0] m_axis_cq_dwlen; - reg m_axis_cq_tlast_dly_en; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_dly_en <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_sop) - begin - if (m_axis_cq_read) m_axis_cq_tlast_dly_en <= 1'b1; - else m_axis_cq_tlast_dly_en <= (m_axis_cq_dwlen[1:0] != 2'd1); - end - - reg m_axis_cq_tlast_lat; - always @(posedge user_clk_out) - if (user_reset_out) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; - else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) - begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read - else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; - end - - //Generae ready for PCIe IP - assign m_axis_cq_tready_a = ((m_axis_cq_cnt == 0) | m_axis_cq_tready) && (!m_axis_cq_tlast_lat); - - //output for TLP - assign m_axis_cq_tlast = m_axis_cq_tlast_dly_en ? m_axis_cq_tlast_lat : m_axis_cq_tlast_a; - assign m_axis_cq_tvalid = (m_axis_cq_tvalid_a & (|m_axis_cq_cnt)) | m_axis_cq_tlast_lat; - - - ////keep address (low) or data (high), not header - reg [127:0] m_axis_cq_tdata_a1; - reg [15:0] m_axis_cq_tlast_be1; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) - begin - m_axis_cq_tdata_a1 <= m_axis_cq_tdata_a; - m_axis_cq_tlast_be1 <= m_axis_cq_tuser_a[23:8]; - end - - //data processing - wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; - wire [4:0] m_axis_cq_type; - wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; - wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; - - assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request - m_axis_cq_tdata_hdr[14:11] == 4'b0111 ? 8'b000_00001 : //Mem Read request-locked - m_axis_cq_tdata_hdr[14:11] == 4'b0001 ? 8'b010_00000 : //Mem write request - m_axis_cq_tdata_hdr[14:11] == 4'b0010 ? 8'b000_00010 : //I/O Read request - m_axis_cq_tdata_hdr[14:11] == 4'b0011 ? 8'b010_00010 : //I/O Write request - m_axis_cq_tdata_hdr[14:11] == 4'b1000 ? 8'b000_00100 : //Cfg Read Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1010 ? 8'b010_00100 : //Cfg Write Type 0 - m_axis_cq_tdata_hdr[14:11] == 4'b1001 ? 8'b000_00101 : //Cfg Read Type 1 - m_axis_cq_tdata_hdr[14:11] == 4'b1011 ? 8'b010_00101 : //Cfg Write Type 1 - 8'b000_00000; //Mem read Request - - reg [7:0] m_axis_cq_tuser_barhit; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_tuser_barhit <= {1'b0, m_axis_cq_tdata_hdr[50:48], m_axis_cq_tdata_hdr[14:11]}; //only valid @sop - - reg m_axis_cq_ecrc; - always @(posedge user_clk_out) - begin - m_axis_cq_ecrc <= m_axis_cq_tuser_a[41]; - end - - reg [63:0] m_axis_cq_header; - always @(posedge user_clk_out) - if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = {m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen}; - - wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; - assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : - {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[127:32]}; - - assign m_axis_cq_tkeep = m_axis_cq_read_l ? 16'h0FFF : - m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[15:4]} : 16'hFFFF; - - - assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_ecrc //ECRC mapped to discontinue - }; - - //----------------------------------------------------- CC AXIS --------------------------------------------------// - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; - - wire [3:0] s_axis_cc_tuser_ff; - wire [3:0] s_axis_cc_tkeep_ff; - wire [127:0] s_axis_cc_tdata_ff; - - axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff - ( - .clk (user_clk_out), - .rst (user_reset_out), - - .i_vld (s_axis_cc_tvalid), - .o_rdy (s_axis_cc_tready), - .i_sop (1'b0), - .i_eop (s_axis_cc_tlast), - .i_dat ({s_axis_cc_tuser, s_axis_cc_tkeep_or, s_axis_cc_tdata}), - - .o_vld (s_axis_cc_tvalid_ff), - .i_rdy (s_axis_cc_tready_ff), - .o_sop (), - .o_eop (s_axis_cc_tlast_ff), - .o_dat ({s_axis_cc_tuser_ff, s_axis_cc_tkeep_ff, s_axis_cc_tdata_ff}) - ); - - reg [1:0] s_axis_cc_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_cnt <= 2'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_cnt <= 2'd0; - else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; - end - - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; - wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; - wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; - wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; - wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr}; - wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; - - reg [3:0] s_axis_cc_firstbe; - reg [3:0] s_axis_cc_lastbe; - - reg s_axis_cc_tvalid_ff_lat; - always @(posedge user_clk_out) - if (user_reset_out) s_axis_cc_tvalid_ff_lat <= 1'd0; - else if (s_axis_cc_tvalid_ff && s_axis_cc_tready_ff) - begin - if (s_axis_cc_tlast_ff) s_axis_cc_tvalid_ff_lat <= 1'd0; - else if (s_axis_cc_tfirst) s_axis_cc_tvalid_ff_lat <= 1'd1; - end - - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [127:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} - - wire cc_status_err = (s_axis_cc_cmpstatus != 3'b0) && s_axis_cc_tvalid_ff && s_axis_cc_tready_ff && s_axis_cc_tfirst; - - reg [31:0] cccnt; - always @(posedge user_clk_out) - if (user_reset_out) cccnt <= 16'b0; - else if (s_axis_cc_tvalid_a && s_axis_cc_tready_a[0] && s_axis_cc_tfirst) cccnt <= cccnt + s_axis_cc_dwordcnt; - - //----------------------------------------------------------------------------------------------------------------// - //Debug only - - //Condition trigger - wire cmperr_trigger = (m_axis_rc_tdata_a[15:12] != 4'b0) & m_axis_rc_tvalid_a & m_axis_rc_tready_a & m_axis_rc_sop; - assign debug = {m_axis_rc_tdata_a[15:12], cmperr_trigger}; - - //----------------------------------------------------------------------------------------------------------------// - // MSI Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_interrupt_msi_enable_x4; - assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; - - reg [31:0] cfg_interrupt_msi_int_enc; - always @(cfg_interrupt_msi_mmenable[2:0]) - case (cfg_interrupt_msi_mmenable[2:0]) - 3'd0 : cfg_interrupt_msi_int_enc <= 32'h0000_0001; - 3'd1 : cfg_interrupt_msi_int_enc <= 32'h0000_0002; - 3'd2 : cfg_interrupt_msi_int_enc <= 32'h0000_0010; - 3'd3 : cfg_interrupt_msi_int_enc <= 32'h0000_0100; - 3'd4 : cfg_interrupt_msi_int_enc <= 32'h0001_0000; - default: cfg_interrupt_msi_int_enc <= 32'h8000_0000; - endcase - - //edge detect valid - reg [1:0] cfg_interrupt_msi_int_valid_sh; - wire cfg_interrupt_msi_int_valid_edge = cfg_interrupt_msi_int_valid_sh == 2'b01; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_sh <= 2'd0; - else cfg_interrupt_msi_int_valid_sh <= {cfg_interrupt_msi_int_valid_sh[0], cfg_interrupt_msi_int_valid}; - - //latch int_enc - reg [31:0] cfg_interrupt_msi_int_enc_lat = 32'b0; - always @(posedge user_clk_out) - if (cfg_interrupt_msi_int_valid_edge) cfg_interrupt_msi_int_enc_lat <= cfg_interrupt_msi_int_enc; - else if (cfg_interrupt_msi_sent) cfg_interrupt_msi_int_enc_lat <= 32'b0; - - - reg cfg_interrupt_msi_int_valid_edge1; - wire [31:0] cfg_interrupt_msi_int_enc_mux = cfg_interrupt_msi_int_valid_edge1 ? cfg_interrupt_msi_int_enc_lat : 32'b0; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_edge1 <= 1'd0; - else cfg_interrupt_msi_int_valid_edge1 <= cfg_interrupt_msi_int_valid_edge; - - //----------------------------------------------------------------------------------------------------------------// - // Core instance // - //----------------------------------------------------------------------------------------------------------------// - - pcie_usp pcie_usp_i ( - - //---------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //---------------------------------------------------------------------------------------// - - // Tx - .pci_exp_txn ( pci_exp_txn ), - .pci_exp_txp ( pci_exp_txp ), - - // Rx - .pci_exp_rxn ( pci_exp_rxn ), - .pci_exp_rxp ( pci_exp_rxp ), - - //---------------------------------------------------------------------------------------// - // AXI Interface // - //---------------------------------------------------------------------------------------// - - .user_clk ( user_clk_out ), - .user_reset ( user_reset_out ), - .user_lnk_up ( user_lnk_up ), - .phy_rdy_out ( user_app_rdy ), - - .s_axis_rq_tlast ( s_axis_rq_tlast_a ), - .s_axis_rq_tdata ( s_axis_rq_tdata_a ), - .s_axis_rq_tuser ( s_axis_rq_tuser_a ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep_a ), - .s_axis_rq_tready ( s_axis_rq_tready_a ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid_a ), - - .m_axis_rc_tdata ( m_axis_rc_tdata_a ), - .m_axis_rc_tuser ( m_axis_rc_tuser_a ), - .m_axis_rc_tlast ( m_axis_rc_tlast_a ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep_a ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid_a ), - .m_axis_rc_tready ( m_axis_rc_tready_a ), - - .m_axis_cq_tdata ( m_axis_cq_tdata_a ), - .m_axis_cq_tuser ( m_axis_cq_tuser_a ), - .m_axis_cq_tlast ( m_axis_cq_tlast_a ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep_a ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid_a ), - .m_axis_cq_tready ( m_axis_cq_tready_a ), - - .s_axis_cc_tdata ( s_axis_cc_tdata_a ), - .s_axis_cc_tuser ( s_axis_cc_tuser_a ), - .s_axis_cc_tlast ( s_axis_cc_tlast_a ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep_a ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid_a ), - .s_axis_cc_tready ( s_axis_cc_tready_a ), - - //---------------------------------------------------------------------------------------// - // Configuration (CFG) Interface // - //---------------------------------------------------------------------------------------// - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_rq_tag_av ( pcie_rq_tag_av ), - - //---------------------------------------------------------------------------------------// - // Error Reporting Interface - //---------------------------------------------------------------------------------------// - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status ), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - - //-------------------------------------------------------------------------------// - // Management Interface // - //-------------------------------------------------------------------------------// - .cfg_mgmt_addr ( cfg_mgmt_dwaddr ), - .cfg_mgmt_write ( cfg_mgmt_wr_en ), - .cfg_mgmt_write_data ( cfg_mgmt_di ), - .cfg_mgmt_byte_enable ( cfg_mgmt_byte_en ), - .cfg_mgmt_read ( cfg_mgmt_rd_en ), - .cfg_mgmt_read_data ( cfg_mgmt_do ), - .cfg_mgmt_read_write_done ( cfg_mgmt_rd_wr_done ), - .cfg_mgmt_function_number ( 8'b0 ), - .cfg_mgmt_debug_access ( 1'b0 ), - - //-------------------------------------------------------------------------------// - // Flow control // - //-------------------------------------------------------------------------------// - - .pcie_tfc_nph_av ( pcie_tfc_nph_av ), //Transmit flow control non-posted header credit available - .pcie_tfc_npd_av ( pcie_tfc_npd_av ), //Transmit flow control non-posted payload credit available - .cfg_msg_received ( cfg_msg_received ), - .cfg_msg_received_data ( cfg_msg_received_data ), - .cfg_msg_received_type ( cfg_msg_received_type ), - - .cfg_msg_transmit ( cfg_msg_transmit ), - .cfg_msg_transmit_type ( cfg_msg_transmit_type ), - .cfg_msg_transmit_data ( cfg_msg_transmit_data ), - .cfg_msg_transmit_done ( cfg_msg_transmit_done ), - - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - - //-----------------------------------------------------------------------------// - // Configuration Control Interface // - // ----------------------------------------------------------------------------// - - // Hot reset enable - .cfg_hot_reset_in ( pl_transmit_hot_rst ), - .cfg_hot_reset_out ( pl_received_hot_rst ), - - //Power state change interupt - .cfg_power_state_change_ack ( cfg_power_state_change_ack ), - .cfg_power_state_change_interrupt ( cfg_power_state_change_interrupt ), - - .cfg_err_cor_in ( 1'b0 ), // Never report Correctable Error - .cfg_err_uncor_in ( 1'b0 ), // Never report UnCorrectable Error - - .cfg_flr_in_process ( cfg_flr_in_process ), - .cfg_flr_done ( {2'b0,cfg_flr_done} ), - .cfg_vf_flr_in_process ( cfg_vf_flr_in_process ), - .cfg_vf_flr_done ( {2'b0,cfg_vf_flr_done} ), - .cfg_vf_flr_func_num ( 8'b0 ), - - .cfg_link_training_enable ( 1'b1 ), // Always enable LTSSM to bring up the Link - - .cfg_pm_aspm_l1_entry_reject ( 1'b0 ), - .cfg_pm_aspm_tx_l0s_entry_disable ( 1'b0 ), - - // EP only - .cfg_config_space_enable ( 1'b1 ), //ref pcie_app_uscale - .cfg_req_pm_transition_l23_ready ( 1'b0 ), - - //----------------------------------------------------------------------------------------------------------------// - // Indentication & Routing // - //----------------------------------------------------------------------------------------------------------------// - - .cfg_dsn ( cfg_dsn ), - .cfg_ds_bus_number ( cfg_ds_bus_number ), - .cfg_ds_device_number ( cfg_ds_device_number ), - .cfg_ds_port_number ( cfg_ds_port_number ), - - //-------------------------------------------------------------------------------// - // Interrupt Interface Signals - //-------------------------------------------------------------------------------// - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( {3'b0,cfg_interrupt_pending} ), //only one function 0 - .cfg_interrupt_sent ( cfg_interrupt_sent ), - - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable_x4 ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int_enc_mux ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( 4'b0 ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_int_enc_lat ), - .cfg_interrupt_msi_attr ( 3'b0 ), - .cfg_interrupt_msi_tph_present ( 1'b0 ), - .cfg_interrupt_msi_tph_type ( 2'b0 ), - .cfg_interrupt_msi_tph_st_tag ( 9'b0 ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0 ), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0 ), - .cfg_interrupt_msi_function_number ( 4'b0 ), - - //--------------------------------------------------------------------------------------// - // System(SYS) Interface // - //--------------------------------------------------------------------------------------// - - .sys_clk ( sys_clk ), - .sys_clk_gt ( sys_clk_gt ), - .sys_reset ( sys_rst_n ) - ); - -endmodule From 0999396e8e2c6cad3a23f20d97c6e714d7d1bddf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 17:38:58 +0200 Subject: [PATCH 28/41] phy/xilinx_us(p)/pcie_us(p)_support: Use KEEP_WIDTH/DATA_WIDTH on internal signals to avoid hardcoded values. --- .../phy/xilinx_us_gen3_x4/pcie_us_support.v | 24 +++++++++---------- .../phy/xilinx_us_gen3_x8/pcie_us_support.v | 24 +++++++++---------- .../xilinx_usp_gen3_x16/pcie_usp_support.v | 24 +++++++++---------- .../phy/xilinx_usp_gen3_x4/pcie_usp_support.v | 24 +++++++++---------- .../phy/xilinx_usp_gen3_x8/pcie_usp_support.v | 24 +++++++++---------- 5 files changed, 60 insertions(+), 60 deletions(-) diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v index 8c84c812..265cbdea 100644 --- a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v @@ -338,12 +338,12 @@ module pcie_support # ( //----------------------------------------------------- RC AXIS --------------------------------------------------// - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [3:0] m_axis_rc_tkeep_a; - wire [127:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; + wire [74 :0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), @@ -369,12 +369,12 @@ module pcie_support # ( //----------------------------------------------------- CQ AXIS --------------------------------------------------// - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [3:0] m_axis_cq_tkeep_a; - wire [127:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; + wire [74 :0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), diff --git a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v index 565d7a16..3e7db9b9 100644 --- a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v +++ b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v @@ -338,12 +338,12 @@ module pcie_support # ( //----------------------------------------------------- RC AXIS --------------------------------------------------// - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [7:0] m_axis_rc_tkeep_a; - wire [127:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; + wire [74 :0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), @@ -369,12 +369,12 @@ module pcie_support # ( //----------------------------------------------------- CQ AXIS --------------------------------------------------// - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [7:0] m_axis_cq_tkeep_a; - wire [127:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; + wire [74 :0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), diff --git a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v index af28cb8a..3958072d 100644 --- a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v @@ -338,12 +338,12 @@ module pcie_support # ( //----------------------------------------------------- RC AXIS --------------------------------------------------// - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [7:0] m_axis_rc_tkeep_a; - wire [127:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; + wire [74 :0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), @@ -369,12 +369,12 @@ module pcie_support # ( //----------------------------------------------------- CQ AXIS --------------------------------------------------// - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [7:0] m_axis_cq_tkeep_a; - wire [127:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; + wire [74 :0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), diff --git a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v index 2c097f64..1eb305c4 100644 --- a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v @@ -338,12 +338,12 @@ module pcie_support # ( //----------------------------------------------------- RC AXIS --------------------------------------------------// - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [3:0] m_axis_rc_tkeep_a; - wire [127:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; + wire [74 :0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), @@ -369,12 +369,12 @@ module pcie_support # ( //----------------------------------------------------- CQ AXIS --------------------------------------------------// - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [3:0] m_axis_cq_tkeep_a; - wire [127:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; + wire [74 :0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), diff --git a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v index 7872b2ec..6bb3e96f 100644 --- a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v @@ -338,12 +338,12 @@ module pcie_support # ( //----------------------------------------------------- RC AXIS --------------------------------------------------// - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [7:0] m_axis_rc_tkeep_a; - wire [127:0] m_axis_rc_tdata_a; - wire [74:0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; + wire [74 :0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; m_axis_rc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), @@ -369,12 +369,12 @@ module pcie_support # ( //----------------------------------------------------- CQ AXIS --------------------------------------------------// - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [7:0] m_axis_cq_tkeep_a; - wire [127:0] m_axis_cq_tdata_a; - wire [84:0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; + wire [74 :0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; m_axis_cq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), From 179a543019e0b679440eb70f82c449fd53599f86 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 17:43:38 +0200 Subject: [PATCH 29/41] phy/uspciephy: Only keep a single version of pcie_us_support.v in xilinx_us. --- litepcie/phy/uspciephy.py | 2 +- .../pcie_us_support.v | 0 .../phy/xilinx_us_gen3_x8/pcie_us_support.v | 688 ------------------ 3 files changed, 1 insertion(+), 689 deletions(-) rename litepcie/phy/{xilinx_us_gen3_x4 => xilinx_us}/pcie_us_support.v (100%) delete mode 100644 litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index c44955e9..6c199ab3 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -426,7 +426,7 @@ def add_sources(self, platform, phy_path, phy_filename=None): platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x8.v")) platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "pcie_us_support.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "pcie_us_support.v")) # External Hard IP ----------------------------------------------------------------------------- def use_external_hard_ip(self, hard_ip_path, hard_ip_filename): diff --git a/litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v b/litepcie/phy/xilinx_us/pcie_us_support.v similarity index 100% rename from litepcie/phy/xilinx_us_gen3_x4/pcie_us_support.v rename to litepcie/phy/xilinx_us/pcie_us_support.v diff --git a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v b/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v deleted file mode 100644 index 3e7db9b9..00000000 --- a/litepcie/phy/xilinx_us_gen3_x8/pcie_us_support.v +++ /dev/null @@ -1,688 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Ultrascale Integrated Block for PCI Express -// File : pcie_support.v -// Version : 4.4 -//-- -//-- Description: PCI Express Endpoint Shared Logic Wrapper -//-- -//------------------------------------------------------------------------------ - -`timescale 1ns / 1ps - -// Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital - -//----------------------------------------------------------------------------------------------------------------// -// PCIe // -//----------------------------------------------------------------------------------------------------------------// - -(* DowngradeIPIdentifiedWarnings = "yes" *) -module pcie_support # ( - parameter LINK_CAP_MAX_LINK_WIDTH = 4, // PCIe Lane Width - parameter C_DATA_WIDTH = 256, // AXI interface data width - parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width - parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device - parameter PCIE_USE_MODE = "2.0" // PCIe use mode -) -( - - input sys_clk, - input sys_clk_gt, - input sys_rst_n, - - //----------------------------------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //----------------------------------------------------------------------------------------------------------------// - - // Tx - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, - - // Rx - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, - - //----------------------------------------------------------------------------------------------------------------// - // AXI-S Interface // - //----------------------------------------------------------------------------------------------------------------// - - output user_clk_out, - output user_reset_out, - output user_lnk_up, - output user_app_rdy, - - //Requester Request - output [1:0] pcie_tfc_nph_av, //Transmit flow control non-posted header credit & data available - output [1:0] pcie_tfc_npd_av, - output [3:0] pcie_rq_seq_num, - output pcie_rq_seq_num_vld, - output [5:0] pcie_rq_tag, - output pcie_rq_tag_vld, - output [1:0] pcie_rq_tag_av, - input s_axis_rq_tlast, - input [C_DATA_WIDTH-1:0] s_axis_rq_tdata, - input [3:0] s_axis_rq_tuser, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tready, - input s_axis_rq_tvalid, - - //Requester Completion - output [C_DATA_WIDTH-1:0] m_axis_rc_tdata, - output [21:0] m_axis_rc_tuser, - output m_axis_rc_tlast, - output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, - output m_axis_rc_tvalid, - input m_axis_rc_tready, - - //Completer Request - output [C_DATA_WIDTH-1:0] m_axis_cq_tdata, - output [21:0] m_axis_cq_tuser, - output m_axis_cq_tlast, - output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, - output m_axis_cq_tvalid, - input m_axis_cq_tready, - - //Completer Completion - input [C_DATA_WIDTH-1:0] s_axis_cc_tdata, - input [3:0] s_axis_cc_tuser, - input s_axis_cc_tlast, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - input s_axis_cc_tvalid, - output s_axis_cc_tready, - - //----------------------------------------------------------------------------------------------------------------// - // Sequence & Tag Report // - //----------------------------------------------------------------------------------------------------------------// - - - input pcie_cq_np_req, - output [5:0] pcie_cq_np_req_count, - - //----------------------------------------------------------------------------------------------------------------// - // Error Reporting Interface // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_phy_link_down, - output [1:0] cfg_phy_link_status, - output [3:0] cfg_negotiated_width, - output [2:0] cfg_current_speed, - output [2:0] cfg_max_payload, - output [2:0] cfg_max_read_req, - output [15:0] cfg_function_status, - output [11:0] cfg_function_power_state, - output [15:0] cfg_vf_status, - output [23:0] cfg_vf_power_state, - output [1:0] cfg_link_power_state, - - output cfg_err_cor_out, - output cfg_err_nonfatal_out, - output cfg_err_fatal_out, - output cfg_ltr_enable, - output [5:0] cfg_ltssm_state, - output [3:0] cfg_rcb_status, - output [3:0] cfg_dpa_substate_change, - output [1:0] cfg_obff_enable, - output cfg_pl_status_change, - - output [3:0] cfg_tph_requester_enable, - output [11:0] cfg_tph_st_mode, - output [7:0] cfg_vf_tph_requester_enable, - output [23:0] cfg_vf_tph_st_mode, - - //----------------------------------------------------------------------------------------------------------------// - // Management Interface // - //----------------------------------------------------------------------------------------------------------------// - - output [31:0] cfg_mgmt_do, - output cfg_mgmt_rd_wr_done, - input [31:0] cfg_mgmt_di, - input [3:0] cfg_mgmt_byte_en, - input [18:0] cfg_mgmt_dwaddr, - input cfg_mgmt_wr_en, - input cfg_mgmt_rd_en, - - //----------------------------------------------------------------------------------------------------------------// - // Flow control // - //----------------------------------------------------------------------------------------------------------------// - - output [7:0] cfg_fc_ph, - output [11:0] cfg_fc_pd, - output [7:0] cfg_fc_nph, - output [11:0] cfg_fc_npd, - output [7:0] cfg_fc_cplh, - output [11:0] cfg_fc_cpld, - input [2:0] cfg_fc_sel, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Tx/Rx Message // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_msg_received, - output [7:0] cfg_msg_received_data, - output [4:0] cfg_msg_received_type, - - input cfg_msg_transmit, - input [31:0] cfg_msg_transmit_data, - input [2:0] cfg_msg_transmit_type, - output cfg_msg_transmit_done, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Control Interface // - //----------------------------------------------------------------------------------------------------------------// - - output pl_received_hot_rst, - input pl_transmit_hot_rst, - - // power-down request TLP - input cfg_power_state_change_ack, - output cfg_power_state_change_interrupt, - - // Indentication & Routing // - - input [63:0] cfg_dsn, //Device Serial Number - input [7:0] cfg_ds_bus_number, - input [4:0] cfg_ds_device_number, - input [2:0] cfg_ds_function_number, - input [7:0] cfg_ds_port_number, - input [15:0] cfg_subsys_vend_id, - //----------------------------------------------------------------------------------------------------------------// - // Interrupt Interface Signals - //----------------------------------------------------------------------------------------------------------------// - input [3:0] cfg_interrupt_int, - input cfg_interrupt_pending, - output cfg_interrupt_sent, - - output cfg_interrupt_msi_enable, //0: Legacy; 1: MSI - input [7:0] cfg_interrupt_msi_int, - input cfg_interrupt_msi_int_valid, - output cfg_interrupt_msi_sent, - output cfg_interrupt_msi_fail, - - output [11:0] cfg_interrupt_msi_mmenable, - output cfg_interrupt_msi_mask_update, - output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable -); - - //----------------------------------------------------------------------------------------------------------------// - // System(SYS) Interface // - //----------------------------------------------------------------------------------------------------------------// - - wire [7:0] led_out; - - //----------------------------------------------------------------------------------------------------------------// - // Function request // - //----------------------------------------------------------------------------------------------------------------// - - wire [2:0] cfg_per_func_status_control = 3'b0; //request only function #0 - wire [15:0] cfg_per_func_status_data; - - //----------------------------------------------------------------------------------------------------------------// - // Function Level Reset Handle // - //----------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_flr_in_process; - wire [7:0] cfg_vf_flr_in_process; - reg [3:0] cfg_flr_done_reg0; - reg [7:0] cfg_vf_flr_done_reg0; - reg [3:0] cfg_flr_done_reg1; - reg [7:0] cfg_vf_flr_done_reg1; - - wire [1:0] cfg_flr_done; - wire [5:0] cfg_vf_flr_done; - - always @(posedge user_clk_out) - if (user_reset_out) begin - cfg_flr_done_reg0 <= 4'b0; - cfg_vf_flr_done_reg0 <= 8'b0; - cfg_flr_done_reg1 <= 4'b0; - cfg_vf_flr_done_reg1 <= 8'b0; - end - else begin - cfg_flr_done_reg0 <= cfg_flr_in_process; - cfg_vf_flr_done_reg0 <= cfg_vf_flr_in_process; - cfg_flr_done_reg1 <= cfg_flr_done_reg0; - cfg_vf_flr_done_reg1 <= cfg_vf_flr_done_reg0; - end - - assign cfg_flr_done[0] = ~cfg_flr_done_reg1[0] && cfg_flr_done_reg0[0]; - assign cfg_flr_done[1] = ~cfg_flr_done_reg1[1] && cfg_flr_done_reg0[1]; - - assign cfg_vf_flr_done[0] = ~cfg_vf_flr_done_reg1[0] && cfg_vf_flr_done_reg0[0]; - assign cfg_vf_flr_done[1] = ~cfg_vf_flr_done_reg1[1] && cfg_vf_flr_done_reg0[1]; - assign cfg_vf_flr_done[2] = ~cfg_vf_flr_done_reg1[2] && cfg_vf_flr_done_reg0[2]; - assign cfg_vf_flr_done[3] = ~cfg_vf_flr_done_reg1[3] && cfg_vf_flr_done_reg0[3]; - assign cfg_vf_flr_done[4] = ~cfg_vf_flr_done_reg1[4] && cfg_vf_flr_done_reg0[4]; - assign cfg_vf_flr_done[5] = ~cfg_vf_flr_done_reg1[5] && cfg_vf_flr_done_reg0[5]; - - // Device Information - wire [15:0] cfg_vend_id = 16'h10EE; - wire [15:0] cfg_dev_id = 16'h7021; - wire [15:0] cfg_subsys_id = 16'h0007; - wire [7:0] cfg_rev_id = 8'h00; - - //----------------------------------------------------------------------------------------------------------------// - // AXIS Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// - - //----------------------------------------------------- RQ AXIS --------------------------------------------------// - - s_axis_rq_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .s_axis_rq_tdata(s_axis_rq_tdata), - .s_axis_rq_tkeep(s_axis_rq_tkeep), - .s_axis_rq_tlast(s_axis_rq_tlast), - .s_axis_rq_tready(s_axis_rq_tready), - .s_axis_rq_tuser(s_axis_rq_tuser), - .s_axis_rq_tvalid(s_axis_rq_tvalid), - - .s_axis_rq_tdata_a(s_axis_rq_tdata_a), - .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), - .s_axis_rq_tlast_a(s_axis_rq_tlast_a), - .s_axis_rq_tready_a(s_axis_rq_tready_a), - .s_axis_rq_tuser_a(s_axis_rq_tuser_a), - .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) - ); - - //----------------------------------------------------- RC AXIS --------------------------------------------------// - - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; - wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; - wire [74 :0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - - m_axis_rc_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .m_axis_rc_tdata( m_axis_rc_tdata), - .m_axis_rc_tkeep( m_axis_rc_tkeep), - .m_axis_rc_tlast( m_axis_rc_tlast), - .m_axis_rc_tready(m_axis_rc_tready), - .m_axis_rc_tuser( m_axis_rc_tuser), - .m_axis_rc_tvalid(m_axis_rc_tvalid), - - .m_axis_rc_tdata_a( m_axis_rc_tdata_a), - .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), - .m_axis_rc_tlast_a( m_axis_rc_tlast_a), - .m_axis_rc_tready_a(m_axis_rc_tready_a), - .m_axis_rc_tuser_a( m_axis_rc_tuser_a), - .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) - ); - - //----------------------------------------------------- CQ AXIS --------------------------------------------------// - - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; - wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; - wire [74 :0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - - m_axis_cq_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .m_axis_cq_tdata( m_axis_cq_tdata), - .m_axis_cq_tkeep( m_axis_cq_tkeep), - .m_axis_cq_tlast( m_axis_cq_tlast), - .m_axis_cq_tready(m_axis_cq_tready), - .m_axis_cq_tuser( m_axis_cq_tuser), - .m_axis_cq_tvalid(m_axis_cq_tvalid), - - .m_axis_cq_tdata_a( s_axis_cq_tdata_a), - .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), - .m_axis_cq_tlast_a( s_axis_cq_tlast_a), - .m_axis_cq_tready_a(s_axis_cq_tready_a), - .m_axis_cq_tuser_a( s_axis_cq_tuser_a), - .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) - ); - - - //----------------------------------------------------- CC AXIS --------------------------------------------------// - - s_axis_cc_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .s_axis_cc_tdata(s_axis_cc_tdata), - .s_axis_cc_tkeep(s_axis_cc_tkeep), - .s_axis_cc_tlast(s_axis_cc_tlast), - .s_axis_cc_tready(s_axis_cc_tready), - .s_axis_cc_tuser(s_axis_cc_tuser), - .s_axis_cc_tvalid(s_axis_cc_tvalid), - - .s_axis_cc_tdata_a(s_axis_cc_tdata_a), - .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), - .s_axis_cc_tlast_a(s_axis_cc_tlast_a), - .s_axis_cc_tready_a(s_axis_cc_tready_a), - .s_axis_cc_tuser_a(s_axis_cc_tuser_a), - .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) - ); - - //---------------------------------------------------------------------------------------------------------------// - // MSI Adaptation Logic // - //---------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_interrupt_msi_enable_x4; - assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; - - reg [31:0] cfg_interrupt_msi_int_enc; - always @(cfg_interrupt_msi_mmenable[2:0]) - case (cfg_interrupt_msi_mmenable[2:0]) - 3'd0 : cfg_interrupt_msi_int_enc <= 32'h0000_0001; - 3'd1 : cfg_interrupt_msi_int_enc <= 32'h0000_0002; - 3'd2 : cfg_interrupt_msi_int_enc <= 32'h0000_0010; - 3'd3 : cfg_interrupt_msi_int_enc <= 32'h0000_0100; - 3'd4: cfg_interrupt_msi_int_enc <= 32'h0001_0000; - default: cfg_interrupt_msi_int_enc <= 32'h8000_0000; - endcase - - //edge detect valid - reg [1:0] cfg_interrupt_msi_int_valid_sh; - wire cfg_interrupt_msi_int_valid_edge = cfg_interrupt_msi_int_valid_sh == 2'b01; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_sh <= 2'd0; - else cfg_interrupt_msi_int_valid_sh <= {cfg_interrupt_msi_int_valid_sh[0], cfg_interrupt_msi_int_valid}; - - //latch int_enc - reg [31:0] cfg_interrupt_msi_int_enc_lat = 32'b0; - always @(posedge user_clk_out) - if (cfg_interrupt_msi_int_valid_edge) cfg_interrupt_msi_int_enc_lat <= cfg_interrupt_msi_int_enc; - else if (cfg_interrupt_msi_sent) cfg_interrupt_msi_int_enc_lat <= 32'b0; - - - reg cfg_interrupt_msi_int_valid_edge1; - wire [31:0] cfg_interrupt_msi_int_enc_mux = cfg_interrupt_msi_int_valid_edge1 ? cfg_interrupt_msi_int_enc_lat : 32'b0; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_edge1 <= 1'd0; - else cfg_interrupt_msi_int_valid_edge1 <= cfg_interrupt_msi_int_valid_edge; - - //----------------------------------------------------------------------------------------------------------------// - // Core instance // - //----------------------------------------------------------------------------------------------------------------// - - pcie_us pcie_us_i ( - - //---------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //---------------------------------------------------------------------------------------// - - // Tx - .pci_exp_txn ( pci_exp_txn ), - .pci_exp_txp ( pci_exp_txp ), - - // Rx - .pci_exp_rxn ( pci_exp_rxn ), - .pci_exp_rxp ( pci_exp_rxp ), - - //---------- Shared Logic Internal ------------------------- - .int_qpll1lock_out ( ), - .int_qpll1outrefclk_out ( ), - .int_qpll1outclk_out ( ), - - //---------------------------------------------------------------------------------------// - // AXI Interface // - //---------------------------------------------------------------------------------------// - - .user_clk ( user_clk_out ), - .user_reset ( user_reset_out ), - .user_lnk_up ( user_lnk_up ), - .phy_rdy_out ( user_app_rdy ), - - .s_axis_rq_tlast ( s_axis_rq_tlast_a ), - .s_axis_rq_tdata ( s_axis_rq_tdata_a ), - .s_axis_rq_tuser ( s_axis_rq_tuser_a ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep_a ), - .s_axis_rq_tready ( s_axis_rq_tready_a ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid_a ), - - .m_axis_rc_tdata ( m_axis_rc_tdata_a ), - .m_axis_rc_tuser ( m_axis_rc_tuser_a ), - .m_axis_rc_tlast ( m_axis_rc_tlast_a ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep_a ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid_a ), - .m_axis_rc_tready ( m_axis_rc_tready_a ), - - .m_axis_cq_tdata ( m_axis_cq_tdata_a ), - .m_axis_cq_tuser ( m_axis_cq_tuser_a ), - .m_axis_cq_tlast ( m_axis_cq_tlast_a ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep_a ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid_a ), - .m_axis_cq_tready ( m_axis_cq_tready_a ), - - .s_axis_cc_tdata ( s_axis_cc_tdata_a ), - .s_axis_cc_tuser ( s_axis_cc_tuser_a ), - .s_axis_cc_tlast ( s_axis_cc_tlast_a ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep_a ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid_a ), - .s_axis_cc_tready ( s_axis_cc_tready_a ), - - //---------------------------------------------------------------------------------------// - // Configuration (CFG) Interface // - //---------------------------------------------------------------------------------------// - .pcie_rq_seq_num ( pcie_rq_seq_num ), - .pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ), - .pcie_rq_tag ( pcie_rq_tag ), - .pcie_rq_tag_vld ( pcie_rq_tag_vld ), - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_rq_tag_av ( pcie_rq_tag_av ), - - //---------------------------------------------------------------------------------------// - // Error Reporting Interface - //---------------------------------------------------------------------------------------// - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status ), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltr_enable ( cfg_ltr_enable ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_dpa_substate_change ( cfg_dpa_substate_change ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - - //-------------------------------------------------------------------------------// - // Management Interface // - //-------------------------------------------------------------------------------// - .cfg_mgmt_addr ( cfg_mgmt_dwaddr ), - .cfg_mgmt_write ( cfg_mgmt_wr_en ), - .cfg_mgmt_write_data ( cfg_mgmt_di ), - .cfg_mgmt_byte_enable ( cfg_mgmt_byte_en ), - .cfg_mgmt_read ( cfg_mgmt_rd_en ), - .cfg_mgmt_read_data ( cfg_mgmt_do ), - .cfg_mgmt_read_write_done ( cfg_mgmt_rd_wr_done ), - .cfg_mgmt_type1_cfg_reg_access ( 1'b0 ), //This input has no effect when the core is in the Endpoint mode - - //-------------------------------------------------------------------------------// - // Flow control // - //-------------------------------------------------------------------------------// - - .pcie_tfc_nph_av ( pcie_tfc_nph_av ), //Transmit flow control non-posted header credit available - .pcie_tfc_npd_av ( pcie_tfc_npd_av ), //Transmit flow control non-posted payload credit available - .cfg_msg_received ( cfg_msg_received ), - .cfg_msg_received_data ( cfg_msg_received_data ), - .cfg_msg_received_type ( cfg_msg_received_type ), - - .cfg_msg_transmit ( cfg_msg_transmit ), - .cfg_msg_transmit_type ( cfg_msg_transmit_type ), - .cfg_msg_transmit_data ( cfg_msg_transmit_data ), - .cfg_msg_transmit_done ( cfg_msg_transmit_done ), - - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - - .cfg_per_func_status_control ( cfg_per_func_status_control ), //Request only for PF#0 - .cfg_per_func_status_data ( cfg_per_func_status_data ), - - //-----------------------------------------------------------------------------// - // Configuration Control Interface // - // ----------------------------------------------------------------------------// - - // Hot reset enable - .cfg_hot_reset_in ( pl_transmit_hot_rst ), - .cfg_hot_reset_out ( pl_received_hot_rst ), - - .cfg_per_function_number ( 4'b0 ), - .cfg_per_function_output_request ( 1'b0 ), // Do not request configuration status update - .cfg_per_function_update_done ( ), - - //Power state change interupt - .cfg_power_state_change_ack ( cfg_power_state_change_ack ), - .cfg_power_state_change_interrupt ( cfg_power_state_change_interrupt ), - - .cfg_err_cor_in ( 1'b0 ), // Never report Correctable Error - .cfg_err_uncor_in ( 1'b0 ), // Never report UnCorrectable Error - - .cfg_flr_in_process ( cfg_flr_in_process ), - .cfg_flr_done ( {2'b0,cfg_flr_done} ), - .cfg_vf_flr_in_process ( cfg_vf_flr_in_process ), - .cfg_vf_flr_done ( {2'b0,cfg_vf_flr_done} ), - .cfg_local_error ( ), - - .cfg_link_training_enable ( 1'b1 ), // Always enable LTSSM to bring up the Link - - // EP only - .cfg_config_space_enable ( 1'b1 ), //ref pcie_app_uscale - .cfg_req_pm_transition_l23_ready ( 1'b0 ), - - //----------------------------------------------------------------------------------------------------------------// - // Indentication & Routing // - //----------------------------------------------------------------------------------------------------------------// - - .cfg_dsn ( cfg_dsn ), - .cfg_ds_bus_number ( cfg_ds_bus_number ), - .cfg_ds_device_number ( cfg_ds_device_number ), - .cfg_ds_function_number ( cfg_ds_function_number ), - .cfg_ds_port_number ( cfg_ds_port_number ), - .cfg_subsys_vend_id ( cfg_subsys_vend_id ), - - //-------------------------------------------------------------------------------// - // Interrupt Interface Signals - //-------------------------------------------------------------------------------// - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( {3'b0,cfg_interrupt_pending} ), //only one function 0 - .cfg_interrupt_sent ( cfg_interrupt_sent ), - - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable_x4 ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int_enc_mux ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - - .cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( 4'b0 ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_int_enc_lat ), - .cfg_interrupt_msi_attr ( 3'b0 ), - .cfg_interrupt_msi_tph_present ( 1'b0 ), - .cfg_interrupt_msi_tph_type ( 2'b0 ), - .cfg_interrupt_msi_tph_st_tag ( 9'b0 ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0 ), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0 ), - .cfg_interrupt_msi_function_number ( 4'b0 ), - - //--------------------------------------------------------------------------------------// - // Reset Pass Through Signals - // - Only used for PCIe_X0Y0 - //--------------------------------------------------------------------------------------// - .pcie_perstn0_out (), - .pcie_perstn1_in (1'b0), - .pcie_perstn1_out (), - - //--------------------------------------------------------------------------------------// - // System(SYS) Interface // - //--------------------------------------------------------------------------------------// - - .sys_clk ( sys_clk ), - .sys_clk_gt ( sys_clk_gt ), - .sys_reset ( sys_rst_n ) - ); - -endmodule From 0ace5e64191bef64576df436963b3706250a94dc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 17:47:33 +0200 Subject: [PATCH 30/41] phy/usppciephy: Only keep a single version of pcie_usp_support.v in xilinx_usp. --- litepcie/phy/usppciephy.py | 2 +- .../xilinx_usp_gen3_x16/pcie_usp_support.v | 662 ----------------- .../phy/xilinx_usp_gen3_x4/pcie_usp_support.v | 662 ----------------- .../phy/xilinx_usp_gen3_x8/pcie_usp_support.v | 663 ------------------ 4 files changed, 1 insertion(+), 1988 deletions(-) delete mode 100644 litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v delete mode 100644 litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v delete mode 100644 litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py index 2e89e495..613eb11b 100644 --- a/litepcie/phy/usppciephy.py +++ b/litepcie/phy/usppciephy.py @@ -431,7 +431,7 @@ def add_sources(self, platform, phy_path, phy_filename=None): platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x16.v")) platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x16.v")) - platform.add_source(os.path.join(phy_path, "pcie_usp_support.v")) + platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "pcie_usp_support.v")) # External Hard IP ----------------------------------------------------------------------------- def use_external_hard_ip(self, hard_ip_path, hard_ip_filename): diff --git a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v deleted file mode 100644 index 3958072d..00000000 --- a/litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v +++ /dev/null @@ -1,662 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Ultrascale Integrated Block for PCI Express -// File : pcie_support.v -// Version : 4.4 -//-- -//-- Description: PCI Express Endpoint Shared Logic Wrapper -//-- -//------------------------------------------------------------------------------ - -`timescale 1ns / 1ps - -// Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital - -//----------------------------------------------------------------------------------------------------------------// -// PCIe // -//----------------------------------------------------------------------------------------------------------------// - -(* DowngradeIPIdentifiedWarnings = "yes" *) -module pcie_support # ( - parameter LINK_CAP_MAX_LINK_WIDTH = 4, // PCIe Lane Width - parameter C_DATA_WIDTH = 512, // AXI interface data width - parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width - parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device - parameter PCIE_USE_MODE = "2.0" // PCIe use mode -) -( - - input sys_clk, - input sys_clk_gt, - input sys_rst_n, - - //----------------------------------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //----------------------------------------------------------------------------------------------------------------// - - // Tx - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, - - // Rx - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, - - //----------------------------------------------------------------------------------------------------------------// - // AXI-S Interface // - //----------------------------------------------------------------------------------------------------------------// - - output user_clk_out, - output user_reset_out, - output user_lnk_up, - output user_app_rdy, - - //Requester Request - output [1:0] pcie_tfc_nph_av, //Transmit flow control non-posted header credit & data available - output [1:0] pcie_tfc_npd_av, - output [3:0] pcie_rq_seq_num, - output pcie_rq_seq_num_vld, - output [5:0] pcie_rq_tag, - output pcie_rq_tag_vld, - output [1:0] pcie_rq_tag_av, - input s_axis_rq_tlast, - input [C_DATA_WIDTH-1:0] s_axis_rq_tdata, - input [3:0] s_axis_rq_tuser, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tready, - input s_axis_rq_tvalid, - - //Requester Completion - output [C_DATA_WIDTH-1:0] m_axis_rc_tdata, - output [21:0] m_axis_rc_tuser, - output m_axis_rc_tlast, - output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, - output m_axis_rc_tvalid, - input m_axis_rc_tready, - - //Completer Request - output [C_DATA_WIDTH-1:0] m_axis_cq_tdata, - output [21:0] m_axis_cq_tuser, - output m_axis_cq_tlast, - output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, - output m_axis_cq_tvalid, - input m_axis_cq_tready, - - //Completer Completion - input [C_DATA_WIDTH-1:0] s_axis_cc_tdata, - input [3:0] s_axis_cc_tuser, - input s_axis_cc_tlast, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - input s_axis_cc_tvalid, - output s_axis_cc_tready, - - //----------------------------------------------------------------------------------------------------------------// - // Sequence & Tag Report // - //----------------------------------------------------------------------------------------------------------------// - - - input pcie_cq_np_req, - output [5:0] pcie_cq_np_req_count, - - //----------------------------------------------------------------------------------------------------------------// - // Error Reporting Interface // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_phy_link_down, - output [1:0] cfg_phy_link_status, - output [2:0] cfg_negotiated_width, - output [1:0] cfg_current_speed, - output [2:0] cfg_max_payload, - output [2:0] cfg_max_read_req, - output [15:0] cfg_function_status, - output [11:0] cfg_function_power_state, - output [15:0] cfg_vf_status, - output [23:0] cfg_vf_power_state, - output [1:0] cfg_link_power_state, - - output cfg_err_cor_out, - output cfg_err_nonfatal_out, - output cfg_err_fatal_out, - output cfg_ltr_enable, - output [5:0] cfg_ltssm_state, - output [3:0] cfg_rcb_status, - output [3:0] cfg_dpa_substate_change, - output [1:0] cfg_obff_enable, - output cfg_pl_status_change, - - output [3:0] cfg_tph_requester_enable, - output [11:0] cfg_tph_st_mode, - output [7:0] cfg_vf_tph_requester_enable, - output [23:0] cfg_vf_tph_st_mode, - - //----------------------------------------------------------------------------------------------------------------// - // Management Interface // - //----------------------------------------------------------------------------------------------------------------// - - output [31:0] cfg_mgmt_do, - output cfg_mgmt_rd_wr_done, - input [31:0] cfg_mgmt_di, - input [3:0] cfg_mgmt_byte_en, - input [18:0] cfg_mgmt_dwaddr, - input cfg_mgmt_wr_en, - input cfg_mgmt_rd_en, - - //----------------------------------------------------------------------------------------------------------------// - // Flow control // - //----------------------------------------------------------------------------------------------------------------// - - output [7:0] cfg_fc_ph, - output [11:0] cfg_fc_pd, - output [7:0] cfg_fc_nph, - output [11:0] cfg_fc_npd, - output [7:0] cfg_fc_cplh, - output [11:0] cfg_fc_cpld, - input [2:0] cfg_fc_sel, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Tx/Rx Message // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_msg_received, - output [7:0] cfg_msg_received_data, - output [4:0] cfg_msg_received_type, - - input cfg_msg_transmit, - input [31:0] cfg_msg_transmit_data, - input [2:0] cfg_msg_transmit_type, - output cfg_msg_transmit_done, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Control Interface // - //----------------------------------------------------------------------------------------------------------------// - - output pl_received_hot_rst, - input pl_transmit_hot_rst, - - // power-down request TLP - input cfg_power_state_change_ack, - output cfg_power_state_change_interrupt, - - // Indentication & Routing // - - input [63:0] cfg_dsn, //Device Serial Number - input [7:0] cfg_ds_bus_number, - input [4:0] cfg_ds_device_number, - input [2:0] cfg_ds_function_number, - input [7:0] cfg_ds_port_number, - input [15:0] cfg_subsys_vend_id, - //----------------------------------------------------------------------------------------------------------------// - // Interrupt Interface Signals - //----------------------------------------------------------------------------------------------------------------// - input [3:0] cfg_interrupt_int, - input cfg_interrupt_pending, - output cfg_interrupt_sent, - - output cfg_interrupt_msi_enable, //0: Legacy; 1: MSI - input [7:0] cfg_interrupt_msi_int, - input cfg_interrupt_msi_int_valid, - output cfg_interrupt_msi_sent, - output cfg_interrupt_msi_fail, - - output [11:0] cfg_interrupt_msi_mmenable, - output cfg_interrupt_msi_mask_update, - output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable -); - - //----------------------------------------------------------------------------------------------------------------// - // System(SYS) Interface // - //----------------------------------------------------------------------------------------------------------------// - - wire [7:0] led_out; - - //----------------------------------------------------------------------------------------------------------------// - // Function request // - //----------------------------------------------------------------------------------------------------------------// - - wire [2:0] cfg_per_func_status_control = 3'b0; //request only function #0 - wire [15:0] cfg_per_func_status_data; - - //----------------------------------------------------------------------------------------------------------------// - // Function Level Reset Handle // - //----------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_flr_in_process; - wire [7:0] cfg_vf_flr_in_process; - reg [3:0] cfg_flr_done_reg0; - reg [7:0] cfg_vf_flr_done_reg0; - reg [3:0] cfg_flr_done_reg1; - reg [7:0] cfg_vf_flr_done_reg1; - - wire [1:0] cfg_flr_done; - wire [5:0] cfg_vf_flr_done; - - always @(posedge user_clk_out) - if (user_reset_out) begin - cfg_flr_done_reg0 <= 4'b0; - cfg_vf_flr_done_reg0 <= 8'b0; - cfg_flr_done_reg1 <= 4'b0; - cfg_vf_flr_done_reg1 <= 8'b0; - end - else begin - cfg_flr_done_reg0 <= cfg_flr_in_process; - cfg_vf_flr_done_reg0 <= cfg_vf_flr_in_process; - cfg_flr_done_reg1 <= cfg_flr_done_reg0; - cfg_vf_flr_done_reg1 <= cfg_vf_flr_done_reg0; - end - - assign cfg_flr_done[0] = ~cfg_flr_done_reg1[0] && cfg_flr_done_reg0[0]; - assign cfg_flr_done[1] = ~cfg_flr_done_reg1[1] && cfg_flr_done_reg0[1]; - - assign cfg_vf_flr_done[0] = ~cfg_vf_flr_done_reg1[0] && cfg_vf_flr_done_reg0[0]; - assign cfg_vf_flr_done[1] = ~cfg_vf_flr_done_reg1[1] && cfg_vf_flr_done_reg0[1]; - assign cfg_vf_flr_done[2] = ~cfg_vf_flr_done_reg1[2] && cfg_vf_flr_done_reg0[2]; - assign cfg_vf_flr_done[3] = ~cfg_vf_flr_done_reg1[3] && cfg_vf_flr_done_reg0[3]; - assign cfg_vf_flr_done[4] = ~cfg_vf_flr_done_reg1[4] && cfg_vf_flr_done_reg0[4]; - assign cfg_vf_flr_done[5] = ~cfg_vf_flr_done_reg1[5] && cfg_vf_flr_done_reg0[5]; - - // Device Information - wire [15:0] cfg_vend_id = 16'h10EE; - wire [15:0] cfg_dev_id = 16'h7021; - wire [15:0] cfg_subsys_id = 16'h0007; - wire [7:0] cfg_rev_id = 8'h00; - - //----------------------------------------------------------------------------------------------------------------// - // AXIS Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// - - //----------------------------------------------------- RQ AXIS --------------------------------------------------// - - s_axis_rq_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .s_axis_rq_tdata(s_axis_rq_tdata), - .s_axis_rq_tkeep(s_axis_rq_tkeep), - .s_axis_rq_tlast(s_axis_rq_tlast), - .s_axis_rq_tready(s_axis_rq_tready), - .s_axis_rq_tuser(s_axis_rq_tuser), - .s_axis_rq_tvalid(s_axis_rq_tvalid), - - .s_axis_rq_tdata_a(s_axis_rq_tdata_a), - .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), - .s_axis_rq_tlast_a(s_axis_rq_tlast_a), - .s_axis_rq_tready_a(s_axis_rq_tready_a), - .s_axis_rq_tuser_a(s_axis_rq_tuser_a), - .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) - ); - - //----------------------------------------------------- RC AXIS --------------------------------------------------// - - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; - wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; - wire [74 :0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - - m_axis_rc_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .m_axis_rc_tdata( m_axis_rc_tdata), - .m_axis_rc_tkeep( m_axis_rc_tkeep), - .m_axis_rc_tlast( m_axis_rc_tlast), - .m_axis_rc_tready(m_axis_rc_tready), - .m_axis_rc_tuser( m_axis_rc_tuser), - .m_axis_rc_tvalid(m_axis_rc_tvalid), - - .m_axis_rc_tdata_a( m_axis_rc_tdata_a), - .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), - .m_axis_rc_tlast_a( m_axis_rc_tlast_a), - .m_axis_rc_tready_a(m_axis_rc_tready_a), - .m_axis_rc_tuser_a( m_axis_rc_tuser_a), - .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) - ); - - //----------------------------------------------------- CQ AXIS --------------------------------------------------// - - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; - wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; - wire [74 :0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - - m_axis_cq_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .m_axis_cq_tdata( m_axis_cq_tdata), - .m_axis_cq_tkeep( m_axis_cq_tkeep), - .m_axis_cq_tlast( m_axis_cq_tlast), - .m_axis_cq_tready(m_axis_cq_tready), - .m_axis_cq_tuser( m_axis_cq_tuser), - .m_axis_cq_tvalid(m_axis_cq_tvalid), - - .m_axis_cq_tdata_a( s_axis_cq_tdata_a), - .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), - .m_axis_cq_tlast_a( s_axis_cq_tlast_a), - .m_axis_cq_tready_a(s_axis_cq_tready_a), - .m_axis_cq_tuser_a( s_axis_cq_tuser_a), - .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) - ); - - //----------------------------------------------------- CC AXIS --------------------------------------------------// - - s_axis_cc_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .s_axis_cc_tdata(s_axis_cc_tdata), - .s_axis_cc_tkeep(s_axis_cc_tkeep), - .s_axis_cc_tlast(s_axis_cc_tlast), - .s_axis_cc_tready(s_axis_cc_tready), - .s_axis_cc_tuser(s_axis_cc_tuser), - .s_axis_cc_tvalid(s_axis_cc_tvalid), - - .s_axis_cc_tdata_a(s_axis_cc_tdata_a), - .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), - .s_axis_cc_tlast_a(s_axis_cc_tlast_a), - .s_axis_cc_tready_a(s_axis_cc_tready_a), - .s_axis_cc_tuser_a(s_axis_cc_tuser_a), - .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) - ); - - //---------------------------------------------------------------------------------------------------------------// - // MSI Adaptation Logic // - //---------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_interrupt_msi_enable_x4; - assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; - - reg [31:0] cfg_interrupt_msi_int_enc; - always @(cfg_interrupt_msi_mmenable[2:0]) - case (cfg_interrupt_msi_mmenable[2:0]) - 3'd0 : cfg_interrupt_msi_int_enc <= 32'h0000_0001; - 3'd1 : cfg_interrupt_msi_int_enc <= 32'h0000_0002; - 3'd2 : cfg_interrupt_msi_int_enc <= 32'h0000_0010; - 3'd3 : cfg_interrupt_msi_int_enc <= 32'h0000_0100; - 3'd4: cfg_interrupt_msi_int_enc <= 32'h0001_0000; - default: cfg_interrupt_msi_int_enc <= 32'h8000_0000; - endcase - - //edge detect valid - reg [1:0] cfg_interrupt_msi_int_valid_sh; - wire cfg_interrupt_msi_int_valid_edge = cfg_interrupt_msi_int_valid_sh == 2'b01; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_sh <= 2'd0; - else cfg_interrupt_msi_int_valid_sh <= {cfg_interrupt_msi_int_valid_sh[0], cfg_interrupt_msi_int_valid}; - - //latch int_enc - reg [31:0] cfg_interrupt_msi_int_enc_lat = 32'b0; - always @(posedge user_clk_out) - if (cfg_interrupt_msi_int_valid_edge) cfg_interrupt_msi_int_enc_lat <= cfg_interrupt_msi_int_enc; - else if (cfg_interrupt_msi_sent) cfg_interrupt_msi_int_enc_lat <= 32'b0; - - - reg cfg_interrupt_msi_int_valid_edge1; - wire [31:0] cfg_interrupt_msi_int_enc_mux = cfg_interrupt_msi_int_valid_edge1 ? cfg_interrupt_msi_int_enc_lat : 32'b0; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_edge1 <= 1'd0; - else cfg_interrupt_msi_int_valid_edge1 <= cfg_interrupt_msi_int_valid_edge; - - //----------------------------------------------------------------------------------------------------------------// - // Core instance // - //----------------------------------------------------------------------------------------------------------------// - - pcie_usp pcie_usp_i ( - - //---------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //---------------------------------------------------------------------------------------// - - // Tx - .pci_exp_txn ( pci_exp_txn ), - .pci_exp_txp ( pci_exp_txp ), - - // Rx - .pci_exp_rxn ( pci_exp_rxn ), - .pci_exp_rxp ( pci_exp_rxp ), - - //---------------------------------------------------------------------------------------// - // AXI Interface // - //---------------------------------------------------------------------------------------// - - .user_clk ( user_clk_out ), - .user_reset ( user_reset_out ), - .user_lnk_up ( user_lnk_up ), - .phy_rdy_out ( user_app_rdy ), - - .s_axis_rq_tlast ( s_axis_rq_tlast_a ), - .s_axis_rq_tdata ( s_axis_rq_tdata_a ), - .s_axis_rq_tuser ( s_axis_rq_tuser_a ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep_a ), - .s_axis_rq_tready ( s_axis_rq_tready_a ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid_a ), - - .m_axis_rc_tdata ( m_axis_rc_tdata_a ), - .m_axis_rc_tuser ( m_axis_rc_tuser_a ), - .m_axis_rc_tlast ( m_axis_rc_tlast_a ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep_a ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid_a ), - .m_axis_rc_tready ( m_axis_rc_tready_a ), - - .m_axis_cq_tdata ( m_axis_cq_tdata_a ), - .m_axis_cq_tuser ( m_axis_cq_tuser_a ), - .m_axis_cq_tlast ( m_axis_cq_tlast_a ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep_a ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid_a ), - .m_axis_cq_tready ( m_axis_cq_tready_a ), - - .s_axis_cc_tdata ( s_axis_cc_tdata_a ), - .s_axis_cc_tuser ( s_axis_cc_tuser_a ), - .s_axis_cc_tlast ( s_axis_cc_tlast_a ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep_a ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid_a ), - .s_axis_cc_tready ( s_axis_cc_tready_a ), - - //---------------------------------------------------------------------------------------// - // Configuration (CFG) Interface // - //---------------------------------------------------------------------------------------// - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_rq_tag_av ( pcie_rq_tag_av ), - - //---------------------------------------------------------------------------------------// - // Error Reporting Interface - //---------------------------------------------------------------------------------------// - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status ), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - - //-------------------------------------------------------------------------------// - // Management Interface // - //-------------------------------------------------------------------------------// - .cfg_mgmt_addr ( cfg_mgmt_dwaddr ), - .cfg_mgmt_write ( cfg_mgmt_wr_en ), - .cfg_mgmt_write_data ( cfg_mgmt_di ), - .cfg_mgmt_byte_enable ( cfg_mgmt_byte_en ), - .cfg_mgmt_read ( cfg_mgmt_rd_en ), - .cfg_mgmt_read_data ( cfg_mgmt_do ), - .cfg_mgmt_read_write_done ( cfg_mgmt_rd_wr_done ), - .cfg_mgmt_function_number ( 8'b0 ), - .cfg_mgmt_debug_access ( 1'b0 ), - - //-------------------------------------------------------------------------------// - // Flow control // - //-------------------------------------------------------------------------------// - - .pcie_tfc_nph_av ( pcie_tfc_nph_av ), //Transmit flow control non-posted header credit available - .pcie_tfc_npd_av ( pcie_tfc_npd_av ), //Transmit flow control non-posted payload credit available - .cfg_msg_received ( cfg_msg_received ), - .cfg_msg_received_data ( cfg_msg_received_data ), - .cfg_msg_received_type ( cfg_msg_received_type ), - - .cfg_msg_transmit ( cfg_msg_transmit ), - .cfg_msg_transmit_type ( cfg_msg_transmit_type ), - .cfg_msg_transmit_data ( cfg_msg_transmit_data ), - .cfg_msg_transmit_done ( cfg_msg_transmit_done ), - - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - - //-----------------------------------------------------------------------------// - // Configuration Control Interface // - // ----------------------------------------------------------------------------// - - // Hot reset enable - .cfg_hot_reset_in ( pl_transmit_hot_rst ), - .cfg_hot_reset_out ( pl_received_hot_rst ), - - //Power state change interupt - .cfg_power_state_change_ack ( cfg_power_state_change_ack ), - .cfg_power_state_change_interrupt ( cfg_power_state_change_interrupt ), - - .cfg_err_cor_in ( 1'b0 ), // Never report Correctable Error - .cfg_err_uncor_in ( 1'b0 ), // Never report UnCorrectable Error - - .cfg_flr_in_process ( cfg_flr_in_process ), - .cfg_flr_done ( {2'b0,cfg_flr_done} ), - .cfg_vf_flr_in_process ( cfg_vf_flr_in_process ), - .cfg_vf_flr_done ( {2'b0,cfg_vf_flr_done} ), - .cfg_vf_flr_func_num ( 8'b0 ), - - .cfg_link_training_enable ( 1'b1 ), // Always enable LTSSM to bring up the Link - - .cfg_pm_aspm_l1_entry_reject ( 1'b0 ), - .cfg_pm_aspm_tx_l0s_entry_disable ( 1'b0 ), - - // EP only - .cfg_config_space_enable ( 1'b1 ), //ref pcie_app_uscale - .cfg_req_pm_transition_l23_ready ( 1'b0 ), - - //----------------------------------------------------------------------------------------------------------------// - // Indentication & Routing // - //----------------------------------------------------------------------------------------------------------------// - - .cfg_dsn ( cfg_dsn ), - .cfg_ds_bus_number ( cfg_ds_bus_number ), - .cfg_ds_device_number ( cfg_ds_device_number ), - .cfg_ds_port_number ( cfg_ds_port_number ), - - //-------------------------------------------------------------------------------// - // Interrupt Interface Signals - //-------------------------------------------------------------------------------// - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( {3'b0,cfg_interrupt_pending} ), //only one function 0 - .cfg_interrupt_sent ( cfg_interrupt_sent ), - - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable_x4 ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int_enc_mux ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( 4'b0 ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_int_enc_lat ), - .cfg_interrupt_msi_attr ( 3'b0 ), - .cfg_interrupt_msi_tph_present ( 1'b0 ), - .cfg_interrupt_msi_tph_type ( 2'b0 ), - .cfg_interrupt_msi_tph_st_tag ( 9'b0 ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0 ), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0 ), - .cfg_interrupt_msi_function_number ( 4'b0 ), - - //--------------------------------------------------------------------------------------// - // System(SYS) Interface // - //--------------------------------------------------------------------------------------// - - .sys_clk ( sys_clk ), - .sys_clk_gt ( sys_clk_gt ), - .sys_reset ( sys_rst_n ) - ); - -endmodule diff --git a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v deleted file mode 100644 index 1eb305c4..00000000 --- a/litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v +++ /dev/null @@ -1,662 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Ultrascale Integrated Block for PCI Express -// File : pcie_support.v -// Version : 4.4 -//-- -//-- Description: PCI Express Endpoint Shared Logic Wrapper -//-- -//------------------------------------------------------------------------------ - -`timescale 1ns / 1ps - -// Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital - -//----------------------------------------------------------------------------------------------------------------// -// PCIe // -//----------------------------------------------------------------------------------------------------------------// - -(* DowngradeIPIdentifiedWarnings = "yes" *) -module pcie_support # ( - parameter LINK_CAP_MAX_LINK_WIDTH = 4, // PCIe Lane Width - parameter C_DATA_WIDTH = 128, // AXI interface data width - parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width - parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device - parameter PCIE_USE_MODE = "2.0" // PCIe use mode -) -( - - input sys_clk, - input sys_clk_gt, - input sys_rst_n, - - //----------------------------------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //----------------------------------------------------------------------------------------------------------------// - - // Tx - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, - - // Rx - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, - - //----------------------------------------------------------------------------------------------------------------// - // AXI-S Interface // - //----------------------------------------------------------------------------------------------------------------// - - output user_clk_out, - output user_reset_out, - output user_lnk_up, - output user_app_rdy, - - //Requester Request - output [1:0] pcie_tfc_nph_av, //Transmit flow control non-posted header credit & data available - output [1:0] pcie_tfc_npd_av, - output [3:0] pcie_rq_seq_num, - output pcie_rq_seq_num_vld, - output [5:0] pcie_rq_tag, - output pcie_rq_tag_vld, - output [1:0] pcie_rq_tag_av, - input s_axis_rq_tlast, - input [C_DATA_WIDTH-1:0] s_axis_rq_tdata, - input [3:0] s_axis_rq_tuser, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tready, - input s_axis_rq_tvalid, - - //Requester Completion - output [C_DATA_WIDTH-1:0] m_axis_rc_tdata, - output [21:0] m_axis_rc_tuser, - output m_axis_rc_tlast, - output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, - output m_axis_rc_tvalid, - input m_axis_rc_tready, - - //Completer Request - output [C_DATA_WIDTH-1:0] m_axis_cq_tdata, - output [21:0] m_axis_cq_tuser, - output m_axis_cq_tlast, - output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, - output m_axis_cq_tvalid, - input m_axis_cq_tready, - - //Completer Completion - input [C_DATA_WIDTH-1:0] s_axis_cc_tdata, - input [3:0] s_axis_cc_tuser, - input s_axis_cc_tlast, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - input s_axis_cc_tvalid, - output s_axis_cc_tready, - - //----------------------------------------------------------------------------------------------------------------// - // Sequence & Tag Report // - //----------------------------------------------------------------------------------------------------------------// - - - input pcie_cq_np_req, - output [5:0] pcie_cq_np_req_count, - - //----------------------------------------------------------------------------------------------------------------// - // Error Reporting Interface // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_phy_link_down, - output [1:0] cfg_phy_link_status, - output [2:0] cfg_negotiated_width, - output [1:0] cfg_current_speed, - output [2:0] cfg_max_payload, - output [2:0] cfg_max_read_req, - output [15:0] cfg_function_status, - output [11:0] cfg_function_power_state, - output [15:0] cfg_vf_status, - output [23:0] cfg_vf_power_state, - output [1:0] cfg_link_power_state, - - output cfg_err_cor_out, - output cfg_err_nonfatal_out, - output cfg_err_fatal_out, - output cfg_ltr_enable, - output [5:0] cfg_ltssm_state, - output [3:0] cfg_rcb_status, - output [3:0] cfg_dpa_substate_change, - output [1:0] cfg_obff_enable, - output cfg_pl_status_change, - - output [3:0] cfg_tph_requester_enable, - output [11:0] cfg_tph_st_mode, - output [7:0] cfg_vf_tph_requester_enable, - output [23:0] cfg_vf_tph_st_mode, - - //----------------------------------------------------------------------------------------------------------------// - // Management Interface // - //----------------------------------------------------------------------------------------------------------------// - - output [31:0] cfg_mgmt_do, - output cfg_mgmt_rd_wr_done, - input [31:0] cfg_mgmt_di, - input [3:0] cfg_mgmt_byte_en, - input [18:0] cfg_mgmt_dwaddr, - input cfg_mgmt_wr_en, - input cfg_mgmt_rd_en, - - //----------------------------------------------------------------------------------------------------------------// - // Flow control // - //----------------------------------------------------------------------------------------------------------------// - - output [7:0] cfg_fc_ph, - output [11:0] cfg_fc_pd, - output [7:0] cfg_fc_nph, - output [11:0] cfg_fc_npd, - output [7:0] cfg_fc_cplh, - output [11:0] cfg_fc_cpld, - input [2:0] cfg_fc_sel, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Tx/Rx Message // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_msg_received, - output [7:0] cfg_msg_received_data, - output [4:0] cfg_msg_received_type, - - input cfg_msg_transmit, - input [31:0] cfg_msg_transmit_data, - input [2:0] cfg_msg_transmit_type, - output cfg_msg_transmit_done, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Control Interface // - //----------------------------------------------------------------------------------------------------------------// - - output pl_received_hot_rst, - input pl_transmit_hot_rst, - - // power-down request TLP - input cfg_power_state_change_ack, - output cfg_power_state_change_interrupt, - - // Indentication & Routing // - - input [63:0] cfg_dsn, //Device Serial Number - input [7:0] cfg_ds_bus_number, - input [4:0] cfg_ds_device_number, - input [2:0] cfg_ds_function_number, - input [7:0] cfg_ds_port_number, - input [15:0] cfg_subsys_vend_id, - //----------------------------------------------------------------------------------------------------------------// - // Interrupt Interface Signals - //----------------------------------------------------------------------------------------------------------------// - input [3:0] cfg_interrupt_int, - input cfg_interrupt_pending, - output cfg_interrupt_sent, - - output cfg_interrupt_msi_enable, //0: Legacy; 1: MSI - input [7:0] cfg_interrupt_msi_int, - input cfg_interrupt_msi_int_valid, - output cfg_interrupt_msi_sent, - output cfg_interrupt_msi_fail, - - output [11:0] cfg_interrupt_msi_mmenable, - output cfg_interrupt_msi_mask_update, - output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable -); - - //----------------------------------------------------------------------------------------------------------------// - // System(SYS) Interface // - //----------------------------------------------------------------------------------------------------------------// - - wire [7:0] led_out; - - //----------------------------------------------------------------------------------------------------------------// - // Function request // - //----------------------------------------------------------------------------------------------------------------// - - wire [2:0] cfg_per_func_status_control = 3'b0; //request only function #0 - wire [15:0] cfg_per_func_status_data; - - //----------------------------------------------------------------------------------------------------------------// - // Function Level Reset Handle // - //----------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_flr_in_process; - wire [7:0] cfg_vf_flr_in_process; - reg [3:0] cfg_flr_done_reg0; - reg [7:0] cfg_vf_flr_done_reg0; - reg [3:0] cfg_flr_done_reg1; - reg [7:0] cfg_vf_flr_done_reg1; - - wire [1:0] cfg_flr_done; - wire [5:0] cfg_vf_flr_done; - - always @(posedge user_clk_out) - if (user_reset_out) begin - cfg_flr_done_reg0 <= 4'b0; - cfg_vf_flr_done_reg0 <= 8'b0; - cfg_flr_done_reg1 <= 4'b0; - cfg_vf_flr_done_reg1 <= 8'b0; - end - else begin - cfg_flr_done_reg0 <= cfg_flr_in_process; - cfg_vf_flr_done_reg0 <= cfg_vf_flr_in_process; - cfg_flr_done_reg1 <= cfg_flr_done_reg0; - cfg_vf_flr_done_reg1 <= cfg_vf_flr_done_reg0; - end - - assign cfg_flr_done[0] = ~cfg_flr_done_reg1[0] && cfg_flr_done_reg0[0]; - assign cfg_flr_done[1] = ~cfg_flr_done_reg1[1] && cfg_flr_done_reg0[1]; - - assign cfg_vf_flr_done[0] = ~cfg_vf_flr_done_reg1[0] && cfg_vf_flr_done_reg0[0]; - assign cfg_vf_flr_done[1] = ~cfg_vf_flr_done_reg1[1] && cfg_vf_flr_done_reg0[1]; - assign cfg_vf_flr_done[2] = ~cfg_vf_flr_done_reg1[2] && cfg_vf_flr_done_reg0[2]; - assign cfg_vf_flr_done[3] = ~cfg_vf_flr_done_reg1[3] && cfg_vf_flr_done_reg0[3]; - assign cfg_vf_flr_done[4] = ~cfg_vf_flr_done_reg1[4] && cfg_vf_flr_done_reg0[4]; - assign cfg_vf_flr_done[5] = ~cfg_vf_flr_done_reg1[5] && cfg_vf_flr_done_reg0[5]; - - // Device Information - wire [15:0] cfg_vend_id = 16'h10EE; - wire [15:0] cfg_dev_id = 16'h7021; - wire [15:0] cfg_subsys_id = 16'h0007; - wire [7:0] cfg_rev_id = 8'h00; - - //----------------------------------------------------------------------------------------------------------------// - // AXIS Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// - - //----------------------------------------------------- RQ AXIS -------------------------------------------------// - - s_axis_rq_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .s_axis_rq_tdata(s_axis_rq_tdata), - .s_axis_rq_tkeep(s_axis_rq_tkeep), - .s_axis_rq_tlast(s_axis_rq_tlast), - .s_axis_rq_tready(s_axis_rq_tready), - .s_axis_rq_tuser(s_axis_rq_tuser), - .s_axis_rq_tvalid(s_axis_rq_tvalid), - - .s_axis_rq_tdata_a(s_axis_rq_tdata_a), - .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), - .s_axis_rq_tlast_a(s_axis_rq_tlast_a), - .s_axis_rq_tready_a(s_axis_rq_tready_a), - .s_axis_rq_tuser_a(s_axis_rq_tuser_a), - .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) - ); - - //----------------------------------------------------- RC AXIS --------------------------------------------------// - - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; - wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; - wire [74 :0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - - m_axis_rc_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .m_axis_rc_tdata( m_axis_rc_tdata), - .m_axis_rc_tkeep( m_axis_rc_tkeep), - .m_axis_rc_tlast( m_axis_rc_tlast), - .m_axis_rc_tready(m_axis_rc_tready), - .m_axis_rc_tuser( m_axis_rc_tuser), - .m_axis_rc_tvalid(m_axis_rc_tvalid), - - .m_axis_rc_tdata_a( m_axis_rc_tdata_a), - .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), - .m_axis_rc_tlast_a( m_axis_rc_tlast_a), - .m_axis_rc_tready_a(m_axis_rc_tready_a), - .m_axis_rc_tuser_a( m_axis_rc_tuser_a), - .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) - ); - - //----------------------------------------------------- CQ AXIS --------------------------------------------------// - - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; - wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; - wire [74 :0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - - m_axis_cq_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .m_axis_cq_tdata( m_axis_cq_tdata), - .m_axis_cq_tkeep( m_axis_cq_tkeep), - .m_axis_cq_tlast( m_axis_cq_tlast), - .m_axis_cq_tready(m_axis_cq_tready), - .m_axis_cq_tuser( m_axis_cq_tuser), - .m_axis_cq_tvalid(m_axis_cq_tvalid), - - .m_axis_cq_tdata_a( s_axis_cq_tdata_a), - .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), - .m_axis_cq_tlast_a( s_axis_cq_tlast_a), - .m_axis_cq_tready_a(s_axis_cq_tready_a), - .m_axis_cq_tuser_a( s_axis_cq_tuser_a), - .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) - ); - - //----------------------------------------------------- CC AXIS --------------------------------------------------// - - s_axis_cc_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .s_axis_cc_tdata(s_axis_cc_tdata), - .s_axis_cc_tkeep(s_axis_cc_tkeep), - .s_axis_cc_tlast(s_axis_cc_tlast), - .s_axis_cc_tready(s_axis_cc_tready), - .s_axis_cc_tuser(s_axis_cc_tuser), - .s_axis_cc_tvalid(s_axis_cc_tvalid), - - .s_axis_cc_tdata_a(s_axis_cc_tdata_a), - .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), - .s_axis_cc_tlast_a(s_axis_cc_tlast_a), - .s_axis_cc_tready_a(s_axis_cc_tready_a), - .s_axis_cc_tuser_a(s_axis_cc_tuser_a), - .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) - ); - - //---------------------------------------------------------------------------------------------------------------// - // MSI Adaptation Logic // - //---------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_interrupt_msi_enable_x4; - assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; - - reg [31:0] cfg_interrupt_msi_int_enc; - always @(cfg_interrupt_msi_mmenable[2:0]) - case (cfg_interrupt_msi_mmenable[2:0]) - 3'd0 : cfg_interrupt_msi_int_enc <= 32'h0000_0001; - 3'd1 : cfg_interrupt_msi_int_enc <= 32'h0000_0002; - 3'd2 : cfg_interrupt_msi_int_enc <= 32'h0000_0010; - 3'd3 : cfg_interrupt_msi_int_enc <= 32'h0000_0100; - 3'd4 : cfg_interrupt_msi_int_enc <= 32'h0001_0000; - default: cfg_interrupt_msi_int_enc <= 32'h8000_0000; - endcase - - //edge detect valid - reg [1:0] cfg_interrupt_msi_int_valid_sh; - wire cfg_interrupt_msi_int_valid_edge = cfg_interrupt_msi_int_valid_sh == 2'b01; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_sh <= 2'd0; - else cfg_interrupt_msi_int_valid_sh <= {cfg_interrupt_msi_int_valid_sh[0], cfg_interrupt_msi_int_valid}; - - //latch int_enc - reg [31:0] cfg_interrupt_msi_int_enc_lat = 32'b0; - always @(posedge user_clk_out) - if (cfg_interrupt_msi_int_valid_edge) cfg_interrupt_msi_int_enc_lat <= cfg_interrupt_msi_int_enc; - else if (cfg_interrupt_msi_sent) cfg_interrupt_msi_int_enc_lat <= 32'b0; - - - reg cfg_interrupt_msi_int_valid_edge1; - wire [31:0] cfg_interrupt_msi_int_enc_mux = cfg_interrupt_msi_int_valid_edge1 ? cfg_interrupt_msi_int_enc_lat : 32'b0; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_edge1 <= 1'd0; - else cfg_interrupt_msi_int_valid_edge1 <= cfg_interrupt_msi_int_valid_edge; - - //----------------------------------------------------------------------------------------------------------------// - // Core instance // - //----------------------------------------------------------------------------------------------------------------// - - pcie_usp pcie_usp_i ( - - //---------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //---------------------------------------------------------------------------------------// - - // Tx - .pci_exp_txn ( pci_exp_txn ), - .pci_exp_txp ( pci_exp_txp ), - - // Rx - .pci_exp_rxn ( pci_exp_rxn ), - .pci_exp_rxp ( pci_exp_rxp ), - - //---------------------------------------------------------------------------------------// - // AXI Interface // - //---------------------------------------------------------------------------------------// - - .user_clk ( user_clk_out ), - .user_reset ( user_reset_out ), - .user_lnk_up ( user_lnk_up ), - .phy_rdy_out ( user_app_rdy ), - - .s_axis_rq_tlast ( s_axis_rq_tlast_a ), - .s_axis_rq_tdata ( s_axis_rq_tdata_a ), - .s_axis_rq_tuser ( s_axis_rq_tuser_a ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep_a ), - .s_axis_rq_tready ( s_axis_rq_tready_a ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid_a ), - - .m_axis_rc_tdata ( m_axis_rc_tdata_a ), - .m_axis_rc_tuser ( m_axis_rc_tuser_a ), - .m_axis_rc_tlast ( m_axis_rc_tlast_a ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep_a ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid_a ), - .m_axis_rc_tready ( m_axis_rc_tready_a ), - - .m_axis_cq_tdata ( m_axis_cq_tdata_a ), - .m_axis_cq_tuser ( m_axis_cq_tuser_a ), - .m_axis_cq_tlast ( m_axis_cq_tlast_a ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep_a ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid_a ), - .m_axis_cq_tready ( m_axis_cq_tready_a ), - - .s_axis_cc_tdata ( s_axis_cc_tdata_a ), - .s_axis_cc_tuser ( s_axis_cc_tuser_a ), - .s_axis_cc_tlast ( s_axis_cc_tlast_a ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep_a ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid_a ), - .s_axis_cc_tready ( s_axis_cc_tready_a ), - - //---------------------------------------------------------------------------------------// - // Configuration (CFG) Interface // - //---------------------------------------------------------------------------------------// - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_rq_tag_av ( pcie_rq_tag_av ), - - //---------------------------------------------------------------------------------------// - // Error Reporting Interface - //---------------------------------------------------------------------------------------// - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status ), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - - //-------------------------------------------------------------------------------// - // Management Interface // - //-------------------------------------------------------------------------------// - .cfg_mgmt_addr ( cfg_mgmt_dwaddr ), - .cfg_mgmt_write ( cfg_mgmt_wr_en ), - .cfg_mgmt_write_data ( cfg_mgmt_di ), - .cfg_mgmt_byte_enable ( cfg_mgmt_byte_en ), - .cfg_mgmt_read ( cfg_mgmt_rd_en ), - .cfg_mgmt_read_data ( cfg_mgmt_do ), - .cfg_mgmt_read_write_done ( cfg_mgmt_rd_wr_done ), - .cfg_mgmt_function_number ( 8'b0 ), - .cfg_mgmt_debug_access ( 1'b0 ), - - //-------------------------------------------------------------------------------// - // Flow control // - //-------------------------------------------------------------------------------// - - .pcie_tfc_nph_av ( pcie_tfc_nph_av ), //Transmit flow control non-posted header credit available - .pcie_tfc_npd_av ( pcie_tfc_npd_av ), //Transmit flow control non-posted payload credit available - .cfg_msg_received ( cfg_msg_received ), - .cfg_msg_received_data ( cfg_msg_received_data ), - .cfg_msg_received_type ( cfg_msg_received_type ), - - .cfg_msg_transmit ( cfg_msg_transmit ), - .cfg_msg_transmit_type ( cfg_msg_transmit_type ), - .cfg_msg_transmit_data ( cfg_msg_transmit_data ), - .cfg_msg_transmit_done ( cfg_msg_transmit_done ), - - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - - //-----------------------------------------------------------------------------// - // Configuration Control Interface // - // ----------------------------------------------------------------------------// - - // Hot reset enable - .cfg_hot_reset_in ( pl_transmit_hot_rst ), - .cfg_hot_reset_out ( pl_received_hot_rst ), - - //Power state change interupt - .cfg_power_state_change_ack ( cfg_power_state_change_ack ), - .cfg_power_state_change_interrupt ( cfg_power_state_change_interrupt ), - - .cfg_err_cor_in ( 1'b0 ), // Never report Correctable Error - .cfg_err_uncor_in ( 1'b0 ), // Never report UnCorrectable Error - - .cfg_flr_in_process ( cfg_flr_in_process ), - .cfg_flr_done ( {2'b0,cfg_flr_done} ), - .cfg_vf_flr_in_process ( cfg_vf_flr_in_process ), - .cfg_vf_flr_done ( {2'b0,cfg_vf_flr_done} ), - .cfg_vf_flr_func_num ( 8'b0 ), - - .cfg_link_training_enable ( 1'b1 ), // Always enable LTSSM to bring up the Link - - .cfg_pm_aspm_l1_entry_reject ( 1'b0 ), - .cfg_pm_aspm_tx_l0s_entry_disable ( 1'b0 ), - - // EP only - .cfg_config_space_enable ( 1'b1 ), //ref pcie_app_uscale - .cfg_req_pm_transition_l23_ready ( 1'b0 ), - - //----------------------------------------------------------------------------------------------------------------// - // Indentication & Routing // - //----------------------------------------------------------------------------------------------------------------// - - .cfg_dsn ( cfg_dsn ), - .cfg_ds_bus_number ( cfg_ds_bus_number ), - .cfg_ds_device_number ( cfg_ds_device_number ), - .cfg_ds_port_number ( cfg_ds_port_number ), - - //-------------------------------------------------------------------------------// - // Interrupt Interface Signals - //-------------------------------------------------------------------------------// - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( {3'b0,cfg_interrupt_pending} ), //only one function 0 - .cfg_interrupt_sent ( cfg_interrupt_sent ), - - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable_x4 ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int_enc_mux ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( 4'b0 ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_int_enc_lat ), - .cfg_interrupt_msi_attr ( 3'b0 ), - .cfg_interrupt_msi_tph_present ( 1'b0 ), - .cfg_interrupt_msi_tph_type ( 2'b0 ), - .cfg_interrupt_msi_tph_st_tag ( 9'b0 ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0 ), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0 ), - .cfg_interrupt_msi_function_number ( 4'b0 ), - - //--------------------------------------------------------------------------------------// - // System(SYS) Interface // - //--------------------------------------------------------------------------------------// - - .sys_clk ( sys_clk ), - .sys_clk_gt ( sys_clk_gt ), - .sys_reset ( sys_rst_n ) - ); - -endmodule diff --git a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v b/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v deleted file mode 100644 index 6bb3e96f..00000000 --- a/litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v +++ /dev/null @@ -1,663 +0,0 @@ -//----------------------------------------------------------------------------- -// -// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//----------------------------------------------------------------------------- -// Project : Ultrascale Integrated Block for PCI Express -// File : pcie_support.v -// Version : 4.4 -//-- -//-- Description: PCI Express Endpoint Shared Logic Wrapper -//-- -//------------------------------------------------------------------------------ - -`timescale 1ns / 1ps - -// Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital - -//----------------------------------------------------------------------------------------------------------------// -// PCIe // -//----------------------------------------------------------------------------------------------------------------// - -(* DowngradeIPIdentifiedWarnings = "yes" *) -module pcie_support # ( - parameter LINK_CAP_MAX_LINK_WIDTH = 4, // PCIe Lane Width - parameter C_DATA_WIDTH = 256, // AXI interface data width - parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width - parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device - parameter PCIE_USE_MODE = "2.0" // PCIe use mode -) -( - - input sys_clk, - input sys_clk_gt, - input sys_rst_n, - - //----------------------------------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //----------------------------------------------------------------------------------------------------------------// - - // Tx - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, - output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, - - // Rx - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, - input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, - - //----------------------------------------------------------------------------------------------------------------// - // AXI-S Interface // - //----------------------------------------------------------------------------------------------------------------// - - output user_clk_out, - output user_reset_out, - output user_lnk_up, - output user_app_rdy, - - //Requester Request - output [1:0] pcie_tfc_nph_av, //Transmit flow control non-posted header credit & data available - output [1:0] pcie_tfc_npd_av, - output [3:0] pcie_rq_seq_num, - output pcie_rq_seq_num_vld, - output [5:0] pcie_rq_tag, - output pcie_rq_tag_vld, - output [1:0] pcie_rq_tag_av, - input s_axis_rq_tlast, - input [C_DATA_WIDTH-1:0] s_axis_rq_tdata, - input [3:0] s_axis_rq_tuser, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tready, - input s_axis_rq_tvalid, - - //Requester Completion - output [C_DATA_WIDTH-1:0] m_axis_rc_tdata, - output [21:0] m_axis_rc_tuser, - output m_axis_rc_tlast, - output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, - output m_axis_rc_tvalid, - input m_axis_rc_tready, - - //Completer Request - output [C_DATA_WIDTH-1:0] m_axis_cq_tdata, - output [21:0] m_axis_cq_tuser, - output m_axis_cq_tlast, - output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, - output m_axis_cq_tvalid, - input m_axis_cq_tready, - - //Completer Completion - input [C_DATA_WIDTH-1:0] s_axis_cc_tdata, - input [3:0] s_axis_cc_tuser, - input s_axis_cc_tlast, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - input s_axis_cc_tvalid, - output s_axis_cc_tready, - - //----------------------------------------------------------------------------------------------------------------// - // Sequence & Tag Report // - //----------------------------------------------------------------------------------------------------------------// - - - input pcie_cq_np_req, - output [5:0] pcie_cq_np_req_count, - - //----------------------------------------------------------------------------------------------------------------// - // Error Reporting Interface // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_phy_link_down, - output [1:0] cfg_phy_link_status, - output [2:0] cfg_negotiated_width, - output [1:0] cfg_current_speed, - output [2:0] cfg_max_payload, - output [2:0] cfg_max_read_req, - output [15:0] cfg_function_status, - output [11:0] cfg_function_power_state, - output [15:0] cfg_vf_status, - output [23:0] cfg_vf_power_state, - output [1:0] cfg_link_power_state, - - output cfg_err_cor_out, - output cfg_err_nonfatal_out, - output cfg_err_fatal_out, - output cfg_ltr_enable, - output [5:0] cfg_ltssm_state, - output [3:0] cfg_rcb_status, - output [3:0] cfg_dpa_substate_change, - output [1:0] cfg_obff_enable, - output cfg_pl_status_change, - - output [3:0] cfg_tph_requester_enable, - output [11:0] cfg_tph_st_mode, - output [7:0] cfg_vf_tph_requester_enable, - output [23:0] cfg_vf_tph_st_mode, - - //----------------------------------------------------------------------------------------------------------------// - // Management Interface // - //----------------------------------------------------------------------------------------------------------------// - - output [31:0] cfg_mgmt_do, - output cfg_mgmt_rd_wr_done, - input [31:0] cfg_mgmt_di, - input [3:0] cfg_mgmt_byte_en, - input [18:0] cfg_mgmt_dwaddr, - input cfg_mgmt_wr_en, - input cfg_mgmt_rd_en, - - //----------------------------------------------------------------------------------------------------------------// - // Flow control // - //----------------------------------------------------------------------------------------------------------------// - - output [7:0] cfg_fc_ph, - output [11:0] cfg_fc_pd, - output [7:0] cfg_fc_nph, - output [11:0] cfg_fc_npd, - output [7:0] cfg_fc_cplh, - output [11:0] cfg_fc_cpld, - input [2:0] cfg_fc_sel, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Tx/Rx Message // - //----------------------------------------------------------------------------------------------------------------// - - output cfg_msg_received, - output [7:0] cfg_msg_received_data, - output [4:0] cfg_msg_received_type, - - input cfg_msg_transmit, - input [31:0] cfg_msg_transmit_data, - input [2:0] cfg_msg_transmit_type, - output cfg_msg_transmit_done, - - //----------------------------------------------------------------------------------------------------------------// - // Configuration Control Interface // - //----------------------------------------------------------------------------------------------------------------// - - output pl_received_hot_rst, - input pl_transmit_hot_rst, - - // power-down request TLP - input cfg_power_state_change_ack, - output cfg_power_state_change_interrupt, - - // Indentication & Routing // - - input [63:0] cfg_dsn, //Device Serial Number - input [7:0] cfg_ds_bus_number, - input [4:0] cfg_ds_device_number, - input [2:0] cfg_ds_function_number, - input [7:0] cfg_ds_port_number, - input [15:0] cfg_subsys_vend_id, - //----------------------------------------------------------------------------------------------------------------// - // Interrupt Interface Signals - //----------------------------------------------------------------------------------------------------------------// - input [3:0] cfg_interrupt_int, - input cfg_interrupt_pending, - output cfg_interrupt_sent, - - output cfg_interrupt_msi_enable, //0: Legacy; 1: MSI - input [7:0] cfg_interrupt_msi_int, - input cfg_interrupt_msi_int_valid, - output cfg_interrupt_msi_sent, - output cfg_interrupt_msi_fail, - - output [11:0] cfg_interrupt_msi_mmenable, - output cfg_interrupt_msi_mask_update, - output [31:0] cfg_interrupt_msi_data, - output [7:0] cfg_interrupt_msi_vf_enable -); - - //----------------------------------------------------------------------------------------------------------------// - // System(SYS) Interface // - //----------------------------------------------------------------------------------------------------------------// - - wire [7:0] led_out; - - //----------------------------------------------------------------------------------------------------------------// - // Function request // - //----------------------------------------------------------------------------------------------------------------// - - wire [2:0] cfg_per_func_status_control = 3'b0; //request only function #0 - wire [15:0] cfg_per_func_status_data; - - //----------------------------------------------------------------------------------------------------------------// - // Function Level Reset Handle // - //----------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_flr_in_process; - wire [7:0] cfg_vf_flr_in_process; - reg [3:0] cfg_flr_done_reg0; - reg [7:0] cfg_vf_flr_done_reg0; - reg [3:0] cfg_flr_done_reg1; - reg [7:0] cfg_vf_flr_done_reg1; - - wire [1:0] cfg_flr_done; - wire [5:0] cfg_vf_flr_done; - - always @(posedge user_clk_out) - if (user_reset_out) begin - cfg_flr_done_reg0 <= 4'b0; - cfg_vf_flr_done_reg0 <= 8'b0; - cfg_flr_done_reg1 <= 4'b0; - cfg_vf_flr_done_reg1 <= 8'b0; - end - else begin - cfg_flr_done_reg0 <= cfg_flr_in_process; - cfg_vf_flr_done_reg0 <= cfg_vf_flr_in_process; - cfg_flr_done_reg1 <= cfg_flr_done_reg0; - cfg_vf_flr_done_reg1 <= cfg_vf_flr_done_reg0; - end - - assign cfg_flr_done[0] = ~cfg_flr_done_reg1[0] && cfg_flr_done_reg0[0]; - assign cfg_flr_done[1] = ~cfg_flr_done_reg1[1] && cfg_flr_done_reg0[1]; - - assign cfg_vf_flr_done[0] = ~cfg_vf_flr_done_reg1[0] && cfg_vf_flr_done_reg0[0]; - assign cfg_vf_flr_done[1] = ~cfg_vf_flr_done_reg1[1] && cfg_vf_flr_done_reg0[1]; - assign cfg_vf_flr_done[2] = ~cfg_vf_flr_done_reg1[2] && cfg_vf_flr_done_reg0[2]; - assign cfg_vf_flr_done[3] = ~cfg_vf_flr_done_reg1[3] && cfg_vf_flr_done_reg0[3]; - assign cfg_vf_flr_done[4] = ~cfg_vf_flr_done_reg1[4] && cfg_vf_flr_done_reg0[4]; - assign cfg_vf_flr_done[5] = ~cfg_vf_flr_done_reg1[5] && cfg_vf_flr_done_reg0[5]; - - // Device Information - wire [15:0] cfg_vend_id = 16'h10EE; - wire [15:0] cfg_dev_id = 16'h7021; - wire [15:0] cfg_subsys_id = 16'h0007; - wire [7:0] cfg_rev_id = 8'h00; - - //----------------------------------------------------------------------------------------------------------------// - // AXIS Adaption Logic // - //----------------------------------------------------------------------------------------------------------------// - - //----------------------------------------------------- RQ AXIS --------------------------------------------------// - - s_axis_rq_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_rq_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .s_axis_rq_tdata(s_axis_rq_tdata), - .s_axis_rq_tkeep(s_axis_rq_tkeep), - .s_axis_rq_tlast(s_axis_rq_tlast), - .s_axis_rq_tready(s_axis_rq_tready), - .s_axis_rq_tuser(s_axis_rq_tuser), - .s_axis_rq_tvalid(s_axis_rq_tvalid), - - .s_axis_rq_tdata_a(s_axis_rq_tdata_a), - .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), - .s_axis_rq_tlast_a(s_axis_rq_tlast_a), - .s_axis_rq_tready_a(s_axis_rq_tready_a), - .s_axis_rq_tuser_a(s_axis_rq_tuser_a), - .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) - ); - - //----------------------------------------------------- RC AXIS --------------------------------------------------// - - wire m_axis_rc_tvalid_a; - wire m_axis_rc_tready_a; - wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; - wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; - wire [74 :0] m_axis_rc_tuser_a; - wire m_axis_rc_tlast_a; - - m_axis_rc_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_rc_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .m_axis_rc_tdata( m_axis_rc_tdata), - .m_axis_rc_tkeep( m_axis_rc_tkeep), - .m_axis_rc_tlast( m_axis_rc_tlast), - .m_axis_rc_tready(m_axis_rc_tready), - .m_axis_rc_tuser( m_axis_rc_tuser), - .m_axis_rc_tvalid(m_axis_rc_tvalid), - - .m_axis_rc_tdata_a( m_axis_rc_tdata_a), - .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), - .m_axis_rc_tlast_a( m_axis_rc_tlast_a), - .m_axis_rc_tready_a(m_axis_rc_tready_a), - .m_axis_rc_tuser_a( m_axis_rc_tuser_a), - .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) - ); - - //----------------------------------------------------- CQ AXIS --------------------------------------------------// - - wire m_axis_cq_tvalid_a; - wire m_axis_cq_tready_a; - wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; - wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; - wire [74 :0] m_axis_cq_tuser_a; - wire m_axis_cq_tlast_a; - - m_axis_cq_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) m_axis_cq_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .m_axis_cq_tdata( m_axis_cq_tdata), - .m_axis_cq_tkeep( m_axis_cq_tkeep), - .m_axis_cq_tlast( m_axis_cq_tlast), - .m_axis_cq_tready(m_axis_cq_tready), - .m_axis_cq_tuser( m_axis_cq_tuser), - .m_axis_cq_tvalid(m_axis_cq_tvalid), - - .m_axis_cq_tdata_a( s_axis_cq_tdata_a), - .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), - .m_axis_cq_tlast_a( s_axis_cq_tlast_a), - .m_axis_cq_tready_a(s_axis_cq_tready_a), - .m_axis_cq_tuser_a( s_axis_cq_tuser_a), - .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) - ); - - - //----------------------------------------------------- CC AXIS --------------------------------------------------// - - s_axis_cc_adapt #( - .DATA_WIDTH(C_DATA_WIDTH), - .KEEP_WIDTH(KEEP_WIDTH) - ) s_axis_cc_adapt_i ( - .user_clk(user_clk_out), - .user_reset(user_reset_out), - - .s_axis_cc_tdata(s_axis_cc_tdata), - .s_axis_cc_tkeep(s_axis_cc_tkeep), - .s_axis_cc_tlast(s_axis_cc_tlast), - .s_axis_cc_tready(s_axis_cc_tready), - .s_axis_cc_tuser(s_axis_cc_tuser), - .s_axis_cc_tvalid(s_axis_cc_tvalid), - - .s_axis_cc_tdata_a(s_axis_cc_tdata_a), - .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), - .s_axis_cc_tlast_a(s_axis_cc_tlast_a), - .s_axis_cc_tready_a(s_axis_cc_tready_a), - .s_axis_cc_tuser_a(s_axis_cc_tuser_a), - .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) - ); - - //---------------------------------------------------------------------------------------------------------------// - // MSI Adaptation Logic // - //---------------------------------------------------------------------------------------------------------------// - - wire [3:0] cfg_interrupt_msi_enable_x4; - assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; - - reg [31:0] cfg_interrupt_msi_int_enc; - always @(cfg_interrupt_msi_mmenable[2:0]) - case (cfg_interrupt_msi_mmenable[2:0]) - 3'd0 : cfg_interrupt_msi_int_enc <= 32'h0000_0001; - 3'd1 : cfg_interrupt_msi_int_enc <= 32'h0000_0002; - 3'd2 : cfg_interrupt_msi_int_enc <= 32'h0000_0010; - 3'd3 : cfg_interrupt_msi_int_enc <= 32'h0000_0100; - 3'd4: cfg_interrupt_msi_int_enc <= 32'h0001_0000; - default: cfg_interrupt_msi_int_enc <= 32'h8000_0000; - endcase - - //edge detect valid - reg [1:0] cfg_interrupt_msi_int_valid_sh; - wire cfg_interrupt_msi_int_valid_edge = cfg_interrupt_msi_int_valid_sh == 2'b01; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_sh <= 2'd0; - else cfg_interrupt_msi_int_valid_sh <= {cfg_interrupt_msi_int_valid_sh[0], cfg_interrupt_msi_int_valid}; - - //latch int_enc - reg [31:0] cfg_interrupt_msi_int_enc_lat = 32'b0; - always @(posedge user_clk_out) - if (cfg_interrupt_msi_int_valid_edge) cfg_interrupt_msi_int_enc_lat <= cfg_interrupt_msi_int_enc; - else if (cfg_interrupt_msi_sent) cfg_interrupt_msi_int_enc_lat <= 32'b0; - - - reg cfg_interrupt_msi_int_valid_edge1; - wire [31:0] cfg_interrupt_msi_int_enc_mux = cfg_interrupt_msi_int_valid_edge1 ? cfg_interrupt_msi_int_enc_lat : 32'b0; - always @(posedge user_clk_out) - if (user_reset_out) cfg_interrupt_msi_int_valid_edge1 <= 1'd0; - else cfg_interrupt_msi_int_valid_edge1 <= cfg_interrupt_msi_int_valid_edge; - - //----------------------------------------------------------------------------------------------------------------// - // Core instance // - //----------------------------------------------------------------------------------------------------------------// - - pcie_usp pcie_usp_i ( - - //---------------------------------------------------------------------------------------// - // PCI Express (pci_exp) Interface // - //---------------------------------------------------------------------------------------// - - // Tx - .pci_exp_txn ( pci_exp_txn ), - .pci_exp_txp ( pci_exp_txp ), - - // Rx - .pci_exp_rxn ( pci_exp_rxn ), - .pci_exp_rxp ( pci_exp_rxp ), - - //---------------------------------------------------------------------------------------// - // AXI Interface // - //---------------------------------------------------------------------------------------// - - .user_clk ( user_clk_out ), - .user_reset ( user_reset_out ), - .user_lnk_up ( user_lnk_up ), - .phy_rdy_out ( user_app_rdy ), - - .s_axis_rq_tlast ( s_axis_rq_tlast_a ), - .s_axis_rq_tdata ( s_axis_rq_tdata_a ), - .s_axis_rq_tuser ( s_axis_rq_tuser_a ), - .s_axis_rq_tkeep ( s_axis_rq_tkeep_a ), - .s_axis_rq_tready ( s_axis_rq_tready_a ), - .s_axis_rq_tvalid ( s_axis_rq_tvalid_a ), - - .m_axis_rc_tdata ( m_axis_rc_tdata_a ), - .m_axis_rc_tuser ( m_axis_rc_tuser_a ), - .m_axis_rc_tlast ( m_axis_rc_tlast_a ), - .m_axis_rc_tkeep ( m_axis_rc_tkeep_a ), - .m_axis_rc_tvalid ( m_axis_rc_tvalid_a ), - .m_axis_rc_tready ( m_axis_rc_tready_a ), - - .m_axis_cq_tdata ( m_axis_cq_tdata_a ), - .m_axis_cq_tuser ( m_axis_cq_tuser_a ), - .m_axis_cq_tlast ( m_axis_cq_tlast_a ), - .m_axis_cq_tkeep ( m_axis_cq_tkeep_a ), - .m_axis_cq_tvalid ( m_axis_cq_tvalid_a ), - .m_axis_cq_tready ( m_axis_cq_tready_a ), - - .s_axis_cc_tdata ( s_axis_cc_tdata_a ), - .s_axis_cc_tuser ( s_axis_cc_tuser_a ), - .s_axis_cc_tlast ( s_axis_cc_tlast_a ), - .s_axis_cc_tkeep ( s_axis_cc_tkeep_a ), - .s_axis_cc_tvalid ( s_axis_cc_tvalid_a ), - .s_axis_cc_tready ( s_axis_cc_tready_a ), - - //---------------------------------------------------------------------------------------// - // Configuration (CFG) Interface // - //---------------------------------------------------------------------------------------// - .pcie_cq_np_req_count ( pcie_cq_np_req_count ), - .pcie_cq_np_req ( pcie_cq_np_req ), - .pcie_rq_tag_av ( pcie_rq_tag_av ), - - //---------------------------------------------------------------------------------------// - // Error Reporting Interface - //---------------------------------------------------------------------------------------// - .cfg_phy_link_down ( cfg_phy_link_down ), - .cfg_phy_link_status ( cfg_phy_link_status ), - .cfg_negotiated_width ( cfg_negotiated_width ), - .cfg_current_speed ( cfg_current_speed ), - .cfg_max_payload ( cfg_max_payload ), - .cfg_max_read_req ( cfg_max_read_req ), - .cfg_function_status ( cfg_function_status ), - .cfg_function_power_state ( cfg_function_power_state ), - .cfg_vf_status ( cfg_vf_status ), - .cfg_vf_power_state ( cfg_vf_power_state ), - .cfg_link_power_state ( cfg_link_power_state ), - - .cfg_err_cor_out ( cfg_err_cor_out ), - .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), - .cfg_err_fatal_out ( cfg_err_fatal_out ), - .cfg_ltssm_state ( cfg_ltssm_state ), - .cfg_rcb_status ( cfg_rcb_status ), - .cfg_obff_enable ( cfg_obff_enable ), - .cfg_pl_status_change ( cfg_pl_status_change ), - - .cfg_tph_requester_enable ( cfg_tph_requester_enable ), - .cfg_tph_st_mode ( cfg_tph_st_mode ), - .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), - .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), - - //-------------------------------------------------------------------------------// - // Management Interface // - //-------------------------------------------------------------------------------// - .cfg_mgmt_addr ( cfg_mgmt_dwaddr ), - .cfg_mgmt_write ( cfg_mgmt_wr_en ), - .cfg_mgmt_write_data ( cfg_mgmt_di ), - .cfg_mgmt_byte_enable ( cfg_mgmt_byte_en ), - .cfg_mgmt_read ( cfg_mgmt_rd_en ), - .cfg_mgmt_read_data ( cfg_mgmt_do ), - .cfg_mgmt_read_write_done ( cfg_mgmt_rd_wr_done ), - .cfg_mgmt_function_number ( 8'b0 ), - .cfg_mgmt_debug_access ( 1'b0 ), - - //-------------------------------------------------------------------------------// - // Flow control // - //-------------------------------------------------------------------------------// - - .pcie_tfc_nph_av ( pcie_tfc_nph_av ), //Transmit flow control non-posted header credit available - .pcie_tfc_npd_av ( pcie_tfc_npd_av ), //Transmit flow control non-posted payload credit available - .cfg_msg_received ( cfg_msg_received ), - .cfg_msg_received_data ( cfg_msg_received_data ), - .cfg_msg_received_type ( cfg_msg_received_type ), - - .cfg_msg_transmit ( cfg_msg_transmit ), - .cfg_msg_transmit_type ( cfg_msg_transmit_type ), - .cfg_msg_transmit_data ( cfg_msg_transmit_data ), - .cfg_msg_transmit_done ( cfg_msg_transmit_done ), - - .cfg_fc_ph ( cfg_fc_ph ), - .cfg_fc_pd ( cfg_fc_pd ), - .cfg_fc_nph ( cfg_fc_nph ), - .cfg_fc_npd ( cfg_fc_npd ), - .cfg_fc_cplh ( cfg_fc_cplh ), - .cfg_fc_cpld ( cfg_fc_cpld ), - .cfg_fc_sel ( cfg_fc_sel ), - - //-----------------------------------------------------------------------------// - // Configuration Control Interface // - // ----------------------------------------------------------------------------// - - // Hot reset enable - .cfg_hot_reset_in ( pl_transmit_hot_rst ), - .cfg_hot_reset_out ( pl_received_hot_rst ), - - //Power state change interupt - .cfg_power_state_change_ack ( cfg_power_state_change_ack ), - .cfg_power_state_change_interrupt ( cfg_power_state_change_interrupt ), - - .cfg_err_cor_in ( 1'b0 ), // Never report Correctable Error - .cfg_err_uncor_in ( 1'b0 ), // Never report UnCorrectable Error - - .cfg_flr_in_process ( cfg_flr_in_process ), - .cfg_flr_done ( {2'b0,cfg_flr_done} ), - .cfg_vf_flr_in_process ( cfg_vf_flr_in_process ), - .cfg_vf_flr_done ( {2'b0,cfg_vf_flr_done} ), - .cfg_vf_flr_func_num ( 8'b0 ), - - .cfg_link_training_enable ( 1'b1 ), // Always enable LTSSM to bring up the Link - - .cfg_pm_aspm_l1_entry_reject ( 1'b0 ), - .cfg_pm_aspm_tx_l0s_entry_disable ( 1'b0 ), - - // EP only - .cfg_config_space_enable ( 1'b1 ), //ref pcie_app_uscale - .cfg_req_pm_transition_l23_ready ( 1'b0 ), - - //----------------------------------------------------------------------------------------------------------------// - // Indentication & Routing // - //----------------------------------------------------------------------------------------------------------------// - - .cfg_dsn ( cfg_dsn ), - .cfg_ds_bus_number ( cfg_ds_bus_number ), - .cfg_ds_device_number ( cfg_ds_device_number ), - .cfg_ds_port_number ( cfg_ds_port_number ), - - //-------------------------------------------------------------------------------// - // Interrupt Interface Signals - //-------------------------------------------------------------------------------// - .cfg_interrupt_int ( cfg_interrupt_int ), - .cfg_interrupt_pending ( {3'b0,cfg_interrupt_pending} ), //only one function 0 - .cfg_interrupt_sent ( cfg_interrupt_sent ), - - .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable_x4 ), - .cfg_interrupt_msi_int ( cfg_interrupt_msi_int_enc_mux ), - .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), - .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), - - .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), - .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), - .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), - .cfg_interrupt_msi_select ( 4'b0 ), - .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_int_enc_lat ), - .cfg_interrupt_msi_attr ( 3'b0 ), - .cfg_interrupt_msi_tph_present ( 1'b0 ), - .cfg_interrupt_msi_tph_type ( 2'b0 ), - .cfg_interrupt_msi_tph_st_tag ( 9'b0 ), - .cfg_interrupt_msi_pending_status_function_num ( 4'b0 ), - .cfg_interrupt_msi_pending_status_data_enable ( 1'b0 ), - .cfg_interrupt_msi_function_number ( 4'b0 ), - - //--------------------------------------------------------------------------------------// - // System(SYS) Interface // - //--------------------------------------------------------------------------------------// - - .sys_clk ( sys_clk ), - .sys_clk_gt ( sys_clk_gt ), - .sys_reset ( sys_rst_n ) - ); - -endmodule From 41b1fd68ef3f070a4634a3f00eeef182903979fa Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 18:09:05 +0200 Subject: [PATCH 31/41] phy/usppciephy: Add HBM support to ip_tcl config (pcie4c_uscale_plus ip instead of pcie4_uscale_plus). --- litepcie/phy/usppciephy.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py index 613eb11b..54d2eead 100644 --- a/litepcie/phy/usppciephy.py +++ b/litepcie/phy/usppciephy.py @@ -374,7 +374,7 @@ def add_ltssm_tracer(self): self.ltssm_tracer = LTSSMTracer(self._link_status.fields.ltssm) # Hard IP sources ------------------------------------------------------------------------------ - def add_sources(self, platform, phy_path, phy_filename=None): + def add_sources(self, platform, phy_path, phy_filename=None, hbm=False): if phy_filename is not None: platform.add_ip(os.path.join(phy_path, phy_filename)) else: @@ -404,7 +404,8 @@ def add_sources(self, platform, phy_path, phy_filename=None): "PF0_INTERRUPT_PIN" : "NONE", } ip_tcl = [] - ip_tcl.append("create_ip -vendor xilinx.com -name pcie4_uscale_plus -module_name pcie_usp") + ip_name = {False: "pcie4_uscale_plus", True: "pcie4c_uscale_plus"}[hbm] + ip_tcl.append(f"create_ip -vendor xilinx.com -name {ip_name} -module_name pcie_usp") ip_tcl.append("set obj [get_ips pcie_usp]") ip_tcl.append("set_property -dict [list \\") for config, value in config.items(): @@ -448,6 +449,7 @@ def do_finalize(self): ) self.add_sources(self.platform, phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), + hbm = isinstance(self, USPHBMPCIEPHY), ) self.specials += Instance("pcie_support", **self.pcie_phy_params) From 9b603d0e115941c225993b14b068cdaa5ef159c8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 18:40:17 +0200 Subject: [PATCH 32/41] phy/us(p)pciephy: Remove useless code in do_finalize and rename phy_path to verilog_path in add_sources. --- litepcie/phy/uspciephy.py | 29 ++++++++++++-------------- litepcie/phy/usppciephy.py | 42 +++++++++++++++----------------------- 2 files changed, 30 insertions(+), 41 deletions(-) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index 6c199ab3..d79975d9 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -373,7 +373,7 @@ def add_ltssm_tracer(self): self.ltssm_tracer = LTSSMTracer(self._link_status.fields.ltssm) # Hard IP sources ------------------------------------------------------------------------------ - def add_sources(self, platform, phy_path, phy_filename=None): + def add_sources(self, platform, phy_path=None, phy_filename=None): if phy_filename is not None: platform.add_ip(os.path.join(phy_path, phy_filename)) else: @@ -412,21 +412,21 @@ def add_sources(self, platform, phy_path, phy_filename=None): ip_tcl.append("synth_ip $obj") platform.toolchain.pre_synthesis_commands += ip_tcl - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "axis_iff.v")) - + verilog_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "xilinx_us") + platform.add_source(os.path.join(verilog_path, "axis_iff.v")) if self.nlanes == 4: - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_rq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_rc_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x4.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_rq_adapt_x4.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_rc_adapt_x4.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_cq_adapt_x4.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_cc_adapt_x4.v")) if self.nlanes == 8: - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_rq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_rc_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "m_axis_cq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "s_axis_cc_adapt_x8.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_rq_adapt_x8.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_rc_adapt_x8.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_cq_adapt_x8.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_cc_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_us", "pcie_us_support.v")) + platform.add_source(os.path.join(verilog_path, "pcie_us_support.v")) # External Hard IP ----------------------------------------------------------------------------- def use_external_hard_ip(self, hard_ip_path, hard_ip_filename): @@ -436,8 +436,5 @@ def use_external_hard_ip(self, hard_ip_path, hard_ip_filename): # Finalize ------------------------------------------------------------------------------------- def do_finalize(self): if not self.external_hard_ip: - phy_path = "xilinx_us_{}_x{}".format(self.speed, self.nlanes) - self.add_sources(self.platform, - phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), - ) + self.add_sources(self.platform) self.specials += Instance("pcie_support", **self.pcie_phy_params) diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py index 54d2eead..5df75a7e 100644 --- a/litepcie/phy/usppciephy.py +++ b/litepcie/phy/usppciephy.py @@ -374,7 +374,7 @@ def add_ltssm_tracer(self): self.ltssm_tracer = LTSSMTracer(self._link_status.fields.ltssm) # Hard IP sources ------------------------------------------------------------------------------ - def add_sources(self, platform, phy_path, phy_filename=None, hbm=False): + def add_sources(self, platform, phy_path=None, phy_filename=None, hbm=False): if phy_filename is not None: platform.add_ip(os.path.join(phy_path, phy_filename)) else: @@ -414,25 +414,25 @@ def add_sources(self, platform, phy_path, phy_filename=None, hbm=False): ip_tcl.append("synth_ip $obj") platform.toolchain.pre_synthesis_commands += ip_tcl - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "axis_iff.v")) - + verilog_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "xilinx_usp") + platform.add_source(os.path.join(verilog_path, "axis_iff.v")) if self.nlanes == 4: - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x4.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x4.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_rq_adapt_x4.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_rc_adapt_x4.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_cq_adapt_x4.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_cc_adapt_x4.v")) if self.nlanes == 8: - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x8.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x8.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_rq_adapt_x8.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_rc_adapt_x8.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_cq_adapt_x8.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_cc_adapt_x8.v")) if self.nlanes == 16: - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_rq_adapt_x16.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_rc_adapt_x16.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "m_axis_cq_adapt_x16.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "s_axis_cc_adapt_x16.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_rq_adapt_x16.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_rc_adapt_x16.v")) + platform.add_source(os.path.join(verilog_path, "m_axis_cq_adapt_x16.v")) + platform.add_source(os.path.join(verilog_path, "s_axis_cc_adapt_x16.v")) - platform.add_source(os.path.join(phy_path, "..", "xilinx_usp", "pcie_usp_support.v")) + platform.add_source(os.path.join(verilog_path, "pcie_usp_support.v")) # External Hard IP ----------------------------------------------------------------------------- def use_external_hard_ip(self, hard_ip_path, hard_ip_filename): @@ -442,15 +442,7 @@ def use_external_hard_ip(self, hard_ip_path, hard_ip_filename): # Finalize ------------------------------------------------------------------------------------- def do_finalize(self): if not self.external_hard_ip: - phy_path = "xilinx_usp{}_{}_x{}".format( - "_hbm" if isinstance(self, USPHBMPCIEPHY) else "", - self.speed, - self.nlanes - ) - self.add_sources(self.platform, - phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), - hbm = isinstance(self, USPHBMPCIEPHY), - ) + self.add_sources(self.platform, hbm=isinstance(self, USPHBMPCIEPHY)) self.specials += Instance("pcie_support", **self.pcie_phy_params) # USPHBMPCIEPHY ------------------------------------------------------------------------------------ From 82c8e2d054e24b163c985c3d4d25af13ee623367 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 19:08:02 +0200 Subject: [PATCH 33/41] phy/xilinx_us(p): Add license on adaptation files. --- litepcie/phy/xilinx_us/axis_iff.v | 5 +++++ litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v | 5 +++++ litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v | 5 +++++ litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v | 5 +++++ litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v | 5 +++++ litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v | 5 +++++ litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v | 5 +++++ litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v | 5 +++++ litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v | 5 +++++ litepcie/phy/xilinx_usp/axis_iff.v | 5 +++++ litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v | 5 +++++ litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v | 5 +++++ litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v | 5 +++++ litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v | 5 +++++ litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v | 5 +++++ litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v | 5 +++++ litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v | 5 +++++ litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v | 5 +++++ litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v | 5 +++++ litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v | 5 +++++ litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v | 5 +++++ litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v | 5 +++++ 22 files changed, 110 insertions(+) diff --git a/litepcie/phy/xilinx_us/axis_iff.v b/litepcie/phy/xilinx_us/axis_iff.v index bc0796f2..8b836d99 100644 --- a/litepcie/phy/xilinx_us/axis_iff.v +++ b/litepcie/phy/xilinx_us/axis_iff.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module axis_iff #( parameter DAT_B = 32 diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v index 2bc4f0da..384334d7 100644 --- a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v index 242efc7c..df99038d 100644 --- a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v index a01301c0..f22a94c6 100644 --- a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v +++ b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v index fa0dae2f..0e5e04e7 100644 --- a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v index 34fa9026..b04e728c 100644 --- a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v index 533be5d5..e401c10f 100644 --- a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v index 25527df1..d204a911 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v index 49391c43..900f23e0 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/axis_iff.v b/litepcie/phy/xilinx_usp/axis_iff.v index bc0796f2..8b836d99 100644 --- a/litepcie/phy/xilinx_usp/axis_iff.v +++ b/litepcie/phy/xilinx_usp/axis_iff.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module axis_iff #( parameter DAT_B = 32 diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v index e27500c2..8748e4d4 100644 --- a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v index 9693f082..1861e7f1 100644 --- a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v index 0aef7324..7a37051a 100644 --- a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_cq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v index 9930da16..ccc39249 100644 --- a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v index 4f042b64..fb857ef1 100644 --- a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v index 694f464e..7dd7ae72 100644 --- a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module m_axis_rc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v index 8cb8680c..b79bb120 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v index 5cd4bb44..01e3d2ef 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v index b2373b3b..fd4906d6 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_cc_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v index e2f8350b..8df40829 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v index f1bd0c6f..01fbfc66 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v index 077ef563..00e84c18 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v @@ -1,3 +1,8 @@ +// This file is part of LitePCIe. +// +// Copyright (c) 2020-2023 Enjoy-Digital +// SPDX-License-Identifier: BSD-2-Clause + module s_axis_rq_adapt # ( parameter DATA_WIDTH = 128, parameter KEEP_WIDTH = DATA_WIDTH/8 From 4d28959a6686e47f8fc934e64c69ac4f0fd2b1b2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Apr 2023 19:08:42 +0200 Subject: [PATCH 34/41] phy/xilinx_usp: Add missing pcie_usp_support.v. --- litepcie/phy/xilinx_usp/pcie_usp_support.v | 662 +++++++++++++++++++++ 1 file changed, 662 insertions(+) create mode 100644 litepcie/phy/xilinx_usp/pcie_usp_support.v diff --git a/litepcie/phy/xilinx_usp/pcie_usp_support.v b/litepcie/phy/xilinx_usp/pcie_usp_support.v new file mode 100644 index 00000000..1eb305c4 --- /dev/null +++ b/litepcie/phy/xilinx_usp/pcie_usp_support.v @@ -0,0 +1,662 @@ +//----------------------------------------------------------------------------- +// +// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//----------------------------------------------------------------------------- +// Project : Ultrascale Integrated Block for PCI Express +// File : pcie_support.v +// Version : 4.4 +//-- +//-- Description: PCI Express Endpoint Shared Logic Wrapper +//-- +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +// Adaptation from/to Xilinx format to/from standardized TLPs Copyright (c) 2020 Enjoy-Digital + +//----------------------------------------------------------------------------------------------------------------// +// PCIe // +//----------------------------------------------------------------------------------------------------------------// + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module pcie_support # ( + parameter LINK_CAP_MAX_LINK_WIDTH = 4, // PCIe Lane Width + parameter C_DATA_WIDTH = 128, // AXI interface data width + parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width + parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device + parameter PCIE_USE_MODE = "2.0" // PCIe use mode +) +( + + input sys_clk, + input sys_clk_gt, + input sys_rst_n, + + //----------------------------------------------------------------------------------------------------------------// + // PCI Express (pci_exp) Interface // + //----------------------------------------------------------------------------------------------------------------// + + // Tx + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn, + output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp, + + // Rx + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn, + input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp, + + //----------------------------------------------------------------------------------------------------------------// + // AXI-S Interface // + //----------------------------------------------------------------------------------------------------------------// + + output user_clk_out, + output user_reset_out, + output user_lnk_up, + output user_app_rdy, + + //Requester Request + output [1:0] pcie_tfc_nph_av, //Transmit flow control non-posted header credit & data available + output [1:0] pcie_tfc_npd_av, + output [3:0] pcie_rq_seq_num, + output pcie_rq_seq_num_vld, + output [5:0] pcie_rq_tag, + output pcie_rq_tag_vld, + output [1:0] pcie_rq_tag_av, + input s_axis_rq_tlast, + input [C_DATA_WIDTH-1:0] s_axis_rq_tdata, + input [3:0] s_axis_rq_tuser, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + output s_axis_rq_tready, + input s_axis_rq_tvalid, + + //Requester Completion + output [C_DATA_WIDTH-1:0] m_axis_rc_tdata, + output [21:0] m_axis_rc_tuser, + output m_axis_rc_tlast, + output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, + output m_axis_rc_tvalid, + input m_axis_rc_tready, + + //Completer Request + output [C_DATA_WIDTH-1:0] m_axis_cq_tdata, + output [21:0] m_axis_cq_tuser, + output m_axis_cq_tlast, + output [KEEP_WIDTH-1:0] m_axis_cq_tkeep, + output m_axis_cq_tvalid, + input m_axis_cq_tready, + + //Completer Completion + input [C_DATA_WIDTH-1:0] s_axis_cc_tdata, + input [3:0] s_axis_cc_tuser, + input s_axis_cc_tlast, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + input s_axis_cc_tvalid, + output s_axis_cc_tready, + + //----------------------------------------------------------------------------------------------------------------// + // Sequence & Tag Report // + //----------------------------------------------------------------------------------------------------------------// + + + input pcie_cq_np_req, + output [5:0] pcie_cq_np_req_count, + + //----------------------------------------------------------------------------------------------------------------// + // Error Reporting Interface // + //----------------------------------------------------------------------------------------------------------------// + + output cfg_phy_link_down, + output [1:0] cfg_phy_link_status, + output [2:0] cfg_negotiated_width, + output [1:0] cfg_current_speed, + output [2:0] cfg_max_payload, + output [2:0] cfg_max_read_req, + output [15:0] cfg_function_status, + output [11:0] cfg_function_power_state, + output [15:0] cfg_vf_status, + output [23:0] cfg_vf_power_state, + output [1:0] cfg_link_power_state, + + output cfg_err_cor_out, + output cfg_err_nonfatal_out, + output cfg_err_fatal_out, + output cfg_ltr_enable, + output [5:0] cfg_ltssm_state, + output [3:0] cfg_rcb_status, + output [3:0] cfg_dpa_substate_change, + output [1:0] cfg_obff_enable, + output cfg_pl_status_change, + + output [3:0] cfg_tph_requester_enable, + output [11:0] cfg_tph_st_mode, + output [7:0] cfg_vf_tph_requester_enable, + output [23:0] cfg_vf_tph_st_mode, + + //----------------------------------------------------------------------------------------------------------------// + // Management Interface // + //----------------------------------------------------------------------------------------------------------------// + + output [31:0] cfg_mgmt_do, + output cfg_mgmt_rd_wr_done, + input [31:0] cfg_mgmt_di, + input [3:0] cfg_mgmt_byte_en, + input [18:0] cfg_mgmt_dwaddr, + input cfg_mgmt_wr_en, + input cfg_mgmt_rd_en, + + //----------------------------------------------------------------------------------------------------------------// + // Flow control // + //----------------------------------------------------------------------------------------------------------------// + + output [7:0] cfg_fc_ph, + output [11:0] cfg_fc_pd, + output [7:0] cfg_fc_nph, + output [11:0] cfg_fc_npd, + output [7:0] cfg_fc_cplh, + output [11:0] cfg_fc_cpld, + input [2:0] cfg_fc_sel, + + //----------------------------------------------------------------------------------------------------------------// + // Configuration Tx/Rx Message // + //----------------------------------------------------------------------------------------------------------------// + + output cfg_msg_received, + output [7:0] cfg_msg_received_data, + output [4:0] cfg_msg_received_type, + + input cfg_msg_transmit, + input [31:0] cfg_msg_transmit_data, + input [2:0] cfg_msg_transmit_type, + output cfg_msg_transmit_done, + + //----------------------------------------------------------------------------------------------------------------// + // Configuration Control Interface // + //----------------------------------------------------------------------------------------------------------------// + + output pl_received_hot_rst, + input pl_transmit_hot_rst, + + // power-down request TLP + input cfg_power_state_change_ack, + output cfg_power_state_change_interrupt, + + // Indentication & Routing // + + input [63:0] cfg_dsn, //Device Serial Number + input [7:0] cfg_ds_bus_number, + input [4:0] cfg_ds_device_number, + input [2:0] cfg_ds_function_number, + input [7:0] cfg_ds_port_number, + input [15:0] cfg_subsys_vend_id, + //----------------------------------------------------------------------------------------------------------------// + // Interrupt Interface Signals + //----------------------------------------------------------------------------------------------------------------// + input [3:0] cfg_interrupt_int, + input cfg_interrupt_pending, + output cfg_interrupt_sent, + + output cfg_interrupt_msi_enable, //0: Legacy; 1: MSI + input [7:0] cfg_interrupt_msi_int, + input cfg_interrupt_msi_int_valid, + output cfg_interrupt_msi_sent, + output cfg_interrupt_msi_fail, + + output [11:0] cfg_interrupt_msi_mmenable, + output cfg_interrupt_msi_mask_update, + output [31:0] cfg_interrupt_msi_data, + output [7:0] cfg_interrupt_msi_vf_enable +); + + //----------------------------------------------------------------------------------------------------------------// + // System(SYS) Interface // + //----------------------------------------------------------------------------------------------------------------// + + wire [7:0] led_out; + + //----------------------------------------------------------------------------------------------------------------// + // Function request // + //----------------------------------------------------------------------------------------------------------------// + + wire [2:0] cfg_per_func_status_control = 3'b0; //request only function #0 + wire [15:0] cfg_per_func_status_data; + + //----------------------------------------------------------------------------------------------------------------// + // Function Level Reset Handle // + //----------------------------------------------------------------------------------------------------------------// + + wire [3:0] cfg_flr_in_process; + wire [7:0] cfg_vf_flr_in_process; + reg [3:0] cfg_flr_done_reg0; + reg [7:0] cfg_vf_flr_done_reg0; + reg [3:0] cfg_flr_done_reg1; + reg [7:0] cfg_vf_flr_done_reg1; + + wire [1:0] cfg_flr_done; + wire [5:0] cfg_vf_flr_done; + + always @(posedge user_clk_out) + if (user_reset_out) begin + cfg_flr_done_reg0 <= 4'b0; + cfg_vf_flr_done_reg0 <= 8'b0; + cfg_flr_done_reg1 <= 4'b0; + cfg_vf_flr_done_reg1 <= 8'b0; + end + else begin + cfg_flr_done_reg0 <= cfg_flr_in_process; + cfg_vf_flr_done_reg0 <= cfg_vf_flr_in_process; + cfg_flr_done_reg1 <= cfg_flr_done_reg0; + cfg_vf_flr_done_reg1 <= cfg_vf_flr_done_reg0; + end + + assign cfg_flr_done[0] = ~cfg_flr_done_reg1[0] && cfg_flr_done_reg0[0]; + assign cfg_flr_done[1] = ~cfg_flr_done_reg1[1] && cfg_flr_done_reg0[1]; + + assign cfg_vf_flr_done[0] = ~cfg_vf_flr_done_reg1[0] && cfg_vf_flr_done_reg0[0]; + assign cfg_vf_flr_done[1] = ~cfg_vf_flr_done_reg1[1] && cfg_vf_flr_done_reg0[1]; + assign cfg_vf_flr_done[2] = ~cfg_vf_flr_done_reg1[2] && cfg_vf_flr_done_reg0[2]; + assign cfg_vf_flr_done[3] = ~cfg_vf_flr_done_reg1[3] && cfg_vf_flr_done_reg0[3]; + assign cfg_vf_flr_done[4] = ~cfg_vf_flr_done_reg1[4] && cfg_vf_flr_done_reg0[4]; + assign cfg_vf_flr_done[5] = ~cfg_vf_flr_done_reg1[5] && cfg_vf_flr_done_reg0[5]; + + // Device Information + wire [15:0] cfg_vend_id = 16'h10EE; + wire [15:0] cfg_dev_id = 16'h7021; + wire [15:0] cfg_subsys_id = 16'h0007; + wire [7:0] cfg_rev_id = 8'h00; + + //----------------------------------------------------------------------------------------------------------------// + // AXIS Adaption Logic // + //----------------------------------------------------------------------------------------------------------------// + + //----------------------------------------------------- RQ AXIS -------------------------------------------------// + + s_axis_rq_adapt #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_rq_adapt_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_rq_tdata(s_axis_rq_tdata), + .s_axis_rq_tkeep(s_axis_rq_tkeep), + .s_axis_rq_tlast(s_axis_rq_tlast), + .s_axis_rq_tready(s_axis_rq_tready), + .s_axis_rq_tuser(s_axis_rq_tuser), + .s_axis_rq_tvalid(s_axis_rq_tvalid), + + .s_axis_rq_tdata_a(s_axis_rq_tdata_a), + .s_axis_rq_tkeep_a(s_axis_rq_tkeep_a), + .s_axis_rq_tlast_a(s_axis_rq_tlast_a), + .s_axis_rq_tready_a(s_axis_rq_tready_a), + .s_axis_rq_tuser_a(s_axis_rq_tuser_a), + .s_axis_rq_tvalid_a(s_axis_rq_tvalid_a) + ); + + //----------------------------------------------------- RC AXIS --------------------------------------------------// + + wire m_axis_rc_tvalid_a; + wire m_axis_rc_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; + wire [74 :0] m_axis_rc_tuser_a; + wire m_axis_rc_tlast_a; + + m_axis_rc_adapt #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_rc_adapt_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_rc_tdata( m_axis_rc_tdata), + .m_axis_rc_tkeep( m_axis_rc_tkeep), + .m_axis_rc_tlast( m_axis_rc_tlast), + .m_axis_rc_tready(m_axis_rc_tready), + .m_axis_rc_tuser( m_axis_rc_tuser), + .m_axis_rc_tvalid(m_axis_rc_tvalid), + + .m_axis_rc_tdata_a( m_axis_rc_tdata_a), + .m_axis_rc_tkeep_a( m_axis_rc_tkeep_a), + .m_axis_rc_tlast_a( m_axis_rc_tlast_a), + .m_axis_rc_tready_a(m_axis_rc_tready_a), + .m_axis_rc_tuser_a( m_axis_rc_tuser_a), + .m_axis_rc_tvalid_a(m_axis_rc_tvalid_a) + ); + + //----------------------------------------------------- CQ AXIS --------------------------------------------------// + + wire m_axis_cq_tvalid_a; + wire m_axis_cq_tready_a; + wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; + wire [74 :0] m_axis_cq_tuser_a; + wire m_axis_cq_tlast_a; + + m_axis_cq_adapt #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) m_axis_cq_adapt_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .m_axis_cq_tdata( m_axis_cq_tdata), + .m_axis_cq_tkeep( m_axis_cq_tkeep), + .m_axis_cq_tlast( m_axis_cq_tlast), + .m_axis_cq_tready(m_axis_cq_tready), + .m_axis_cq_tuser( m_axis_cq_tuser), + .m_axis_cq_tvalid(m_axis_cq_tvalid), + + .m_axis_cq_tdata_a( s_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( s_axis_cq_tlast_a), + .m_axis_cq_tready_a(s_axis_cq_tready_a), + .m_axis_cq_tuser_a( s_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + ); + + //----------------------------------------------------- CC AXIS --------------------------------------------------// + + s_axis_cc_adapt #( + .DATA_WIDTH(C_DATA_WIDTH), + .KEEP_WIDTH(KEEP_WIDTH) + ) s_axis_cc_adapt_i ( + .user_clk(user_clk_out), + .user_reset(user_reset_out), + + .s_axis_cc_tdata(s_axis_cc_tdata), + .s_axis_cc_tkeep(s_axis_cc_tkeep), + .s_axis_cc_tlast(s_axis_cc_tlast), + .s_axis_cc_tready(s_axis_cc_tready), + .s_axis_cc_tuser(s_axis_cc_tuser), + .s_axis_cc_tvalid(s_axis_cc_tvalid), + + .s_axis_cc_tdata_a(s_axis_cc_tdata_a), + .s_axis_cc_tkeep_a(s_axis_cc_tkeep_a), + .s_axis_cc_tlast_a(s_axis_cc_tlast_a), + .s_axis_cc_tready_a(s_axis_cc_tready_a), + .s_axis_cc_tuser_a(s_axis_cc_tuser_a), + .s_axis_cc_tvalid_a(s_axis_cc_tvalid_a) + ); + + //---------------------------------------------------------------------------------------------------------------// + // MSI Adaptation Logic // + //---------------------------------------------------------------------------------------------------------------// + + wire [3:0] cfg_interrupt_msi_enable_x4; + assign cfg_interrupt_msi_enable = cfg_interrupt_msi_enable_x4[0]; + + reg [31:0] cfg_interrupt_msi_int_enc; + always @(cfg_interrupt_msi_mmenable[2:0]) + case (cfg_interrupt_msi_mmenable[2:0]) + 3'd0 : cfg_interrupt_msi_int_enc <= 32'h0000_0001; + 3'd1 : cfg_interrupt_msi_int_enc <= 32'h0000_0002; + 3'd2 : cfg_interrupt_msi_int_enc <= 32'h0000_0010; + 3'd3 : cfg_interrupt_msi_int_enc <= 32'h0000_0100; + 3'd4 : cfg_interrupt_msi_int_enc <= 32'h0001_0000; + default: cfg_interrupt_msi_int_enc <= 32'h8000_0000; + endcase + + //edge detect valid + reg [1:0] cfg_interrupt_msi_int_valid_sh; + wire cfg_interrupt_msi_int_valid_edge = cfg_interrupt_msi_int_valid_sh == 2'b01; + always @(posedge user_clk_out) + if (user_reset_out) cfg_interrupt_msi_int_valid_sh <= 2'd0; + else cfg_interrupt_msi_int_valid_sh <= {cfg_interrupt_msi_int_valid_sh[0], cfg_interrupt_msi_int_valid}; + + //latch int_enc + reg [31:0] cfg_interrupt_msi_int_enc_lat = 32'b0; + always @(posedge user_clk_out) + if (cfg_interrupt_msi_int_valid_edge) cfg_interrupt_msi_int_enc_lat <= cfg_interrupt_msi_int_enc; + else if (cfg_interrupt_msi_sent) cfg_interrupt_msi_int_enc_lat <= 32'b0; + + + reg cfg_interrupt_msi_int_valid_edge1; + wire [31:0] cfg_interrupt_msi_int_enc_mux = cfg_interrupt_msi_int_valid_edge1 ? cfg_interrupt_msi_int_enc_lat : 32'b0; + always @(posedge user_clk_out) + if (user_reset_out) cfg_interrupt_msi_int_valid_edge1 <= 1'd0; + else cfg_interrupt_msi_int_valid_edge1 <= cfg_interrupt_msi_int_valid_edge; + + //----------------------------------------------------------------------------------------------------------------// + // Core instance // + //----------------------------------------------------------------------------------------------------------------// + + pcie_usp pcie_usp_i ( + + //---------------------------------------------------------------------------------------// + // PCI Express (pci_exp) Interface // + //---------------------------------------------------------------------------------------// + + // Tx + .pci_exp_txn ( pci_exp_txn ), + .pci_exp_txp ( pci_exp_txp ), + + // Rx + .pci_exp_rxn ( pci_exp_rxn ), + .pci_exp_rxp ( pci_exp_rxp ), + + //---------------------------------------------------------------------------------------// + // AXI Interface // + //---------------------------------------------------------------------------------------// + + .user_clk ( user_clk_out ), + .user_reset ( user_reset_out ), + .user_lnk_up ( user_lnk_up ), + .phy_rdy_out ( user_app_rdy ), + + .s_axis_rq_tlast ( s_axis_rq_tlast_a ), + .s_axis_rq_tdata ( s_axis_rq_tdata_a ), + .s_axis_rq_tuser ( s_axis_rq_tuser_a ), + .s_axis_rq_tkeep ( s_axis_rq_tkeep_a ), + .s_axis_rq_tready ( s_axis_rq_tready_a ), + .s_axis_rq_tvalid ( s_axis_rq_tvalid_a ), + + .m_axis_rc_tdata ( m_axis_rc_tdata_a ), + .m_axis_rc_tuser ( m_axis_rc_tuser_a ), + .m_axis_rc_tlast ( m_axis_rc_tlast_a ), + .m_axis_rc_tkeep ( m_axis_rc_tkeep_a ), + .m_axis_rc_tvalid ( m_axis_rc_tvalid_a ), + .m_axis_rc_tready ( m_axis_rc_tready_a ), + + .m_axis_cq_tdata ( m_axis_cq_tdata_a ), + .m_axis_cq_tuser ( m_axis_cq_tuser_a ), + .m_axis_cq_tlast ( m_axis_cq_tlast_a ), + .m_axis_cq_tkeep ( m_axis_cq_tkeep_a ), + .m_axis_cq_tvalid ( m_axis_cq_tvalid_a ), + .m_axis_cq_tready ( m_axis_cq_tready_a ), + + .s_axis_cc_tdata ( s_axis_cc_tdata_a ), + .s_axis_cc_tuser ( s_axis_cc_tuser_a ), + .s_axis_cc_tlast ( s_axis_cc_tlast_a ), + .s_axis_cc_tkeep ( s_axis_cc_tkeep_a ), + .s_axis_cc_tvalid ( s_axis_cc_tvalid_a ), + .s_axis_cc_tready ( s_axis_cc_tready_a ), + + //---------------------------------------------------------------------------------------// + // Configuration (CFG) Interface // + //---------------------------------------------------------------------------------------// + .pcie_cq_np_req_count ( pcie_cq_np_req_count ), + .pcie_cq_np_req ( pcie_cq_np_req ), + .pcie_rq_tag_av ( pcie_rq_tag_av ), + + //---------------------------------------------------------------------------------------// + // Error Reporting Interface + //---------------------------------------------------------------------------------------// + .cfg_phy_link_down ( cfg_phy_link_down ), + .cfg_phy_link_status ( cfg_phy_link_status ), + .cfg_negotiated_width ( cfg_negotiated_width ), + .cfg_current_speed ( cfg_current_speed ), + .cfg_max_payload ( cfg_max_payload ), + .cfg_max_read_req ( cfg_max_read_req ), + .cfg_function_status ( cfg_function_status ), + .cfg_function_power_state ( cfg_function_power_state ), + .cfg_vf_status ( cfg_vf_status ), + .cfg_vf_power_state ( cfg_vf_power_state ), + .cfg_link_power_state ( cfg_link_power_state ), + + .cfg_err_cor_out ( cfg_err_cor_out ), + .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), + .cfg_err_fatal_out ( cfg_err_fatal_out ), + .cfg_ltssm_state ( cfg_ltssm_state ), + .cfg_rcb_status ( cfg_rcb_status ), + .cfg_obff_enable ( cfg_obff_enable ), + .cfg_pl_status_change ( cfg_pl_status_change ), + + .cfg_tph_requester_enable ( cfg_tph_requester_enable ), + .cfg_tph_st_mode ( cfg_tph_st_mode ), + .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), + .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), + + //-------------------------------------------------------------------------------// + // Management Interface // + //-------------------------------------------------------------------------------// + .cfg_mgmt_addr ( cfg_mgmt_dwaddr ), + .cfg_mgmt_write ( cfg_mgmt_wr_en ), + .cfg_mgmt_write_data ( cfg_mgmt_di ), + .cfg_mgmt_byte_enable ( cfg_mgmt_byte_en ), + .cfg_mgmt_read ( cfg_mgmt_rd_en ), + .cfg_mgmt_read_data ( cfg_mgmt_do ), + .cfg_mgmt_read_write_done ( cfg_mgmt_rd_wr_done ), + .cfg_mgmt_function_number ( 8'b0 ), + .cfg_mgmt_debug_access ( 1'b0 ), + + //-------------------------------------------------------------------------------// + // Flow control // + //-------------------------------------------------------------------------------// + + .pcie_tfc_nph_av ( pcie_tfc_nph_av ), //Transmit flow control non-posted header credit available + .pcie_tfc_npd_av ( pcie_tfc_npd_av ), //Transmit flow control non-posted payload credit available + .cfg_msg_received ( cfg_msg_received ), + .cfg_msg_received_data ( cfg_msg_received_data ), + .cfg_msg_received_type ( cfg_msg_received_type ), + + .cfg_msg_transmit ( cfg_msg_transmit ), + .cfg_msg_transmit_type ( cfg_msg_transmit_type ), + .cfg_msg_transmit_data ( cfg_msg_transmit_data ), + .cfg_msg_transmit_done ( cfg_msg_transmit_done ), + + .cfg_fc_ph ( cfg_fc_ph ), + .cfg_fc_pd ( cfg_fc_pd ), + .cfg_fc_nph ( cfg_fc_nph ), + .cfg_fc_npd ( cfg_fc_npd ), + .cfg_fc_cplh ( cfg_fc_cplh ), + .cfg_fc_cpld ( cfg_fc_cpld ), + .cfg_fc_sel ( cfg_fc_sel ), + + //-----------------------------------------------------------------------------// + // Configuration Control Interface // + // ----------------------------------------------------------------------------// + + // Hot reset enable + .cfg_hot_reset_in ( pl_transmit_hot_rst ), + .cfg_hot_reset_out ( pl_received_hot_rst ), + + //Power state change interupt + .cfg_power_state_change_ack ( cfg_power_state_change_ack ), + .cfg_power_state_change_interrupt ( cfg_power_state_change_interrupt ), + + .cfg_err_cor_in ( 1'b0 ), // Never report Correctable Error + .cfg_err_uncor_in ( 1'b0 ), // Never report UnCorrectable Error + + .cfg_flr_in_process ( cfg_flr_in_process ), + .cfg_flr_done ( {2'b0,cfg_flr_done} ), + .cfg_vf_flr_in_process ( cfg_vf_flr_in_process ), + .cfg_vf_flr_done ( {2'b0,cfg_vf_flr_done} ), + .cfg_vf_flr_func_num ( 8'b0 ), + + .cfg_link_training_enable ( 1'b1 ), // Always enable LTSSM to bring up the Link + + .cfg_pm_aspm_l1_entry_reject ( 1'b0 ), + .cfg_pm_aspm_tx_l0s_entry_disable ( 1'b0 ), + + // EP only + .cfg_config_space_enable ( 1'b1 ), //ref pcie_app_uscale + .cfg_req_pm_transition_l23_ready ( 1'b0 ), + + //----------------------------------------------------------------------------------------------------------------// + // Indentication & Routing // + //----------------------------------------------------------------------------------------------------------------// + + .cfg_dsn ( cfg_dsn ), + .cfg_ds_bus_number ( cfg_ds_bus_number ), + .cfg_ds_device_number ( cfg_ds_device_number ), + .cfg_ds_port_number ( cfg_ds_port_number ), + + //-------------------------------------------------------------------------------// + // Interrupt Interface Signals + //-------------------------------------------------------------------------------// + .cfg_interrupt_int ( cfg_interrupt_int ), + .cfg_interrupt_pending ( {3'b0,cfg_interrupt_pending} ), //only one function 0 + .cfg_interrupt_sent ( cfg_interrupt_sent ), + + .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable_x4 ), + .cfg_interrupt_msi_int ( cfg_interrupt_msi_int_enc_mux ), + .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), + .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), + + .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), + .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), + .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), + .cfg_interrupt_msi_select ( 4'b0 ), + .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_int_enc_lat ), + .cfg_interrupt_msi_attr ( 3'b0 ), + .cfg_interrupt_msi_tph_present ( 1'b0 ), + .cfg_interrupt_msi_tph_type ( 2'b0 ), + .cfg_interrupt_msi_tph_st_tag ( 9'b0 ), + .cfg_interrupt_msi_pending_status_function_num ( 4'b0 ), + .cfg_interrupt_msi_pending_status_data_enable ( 1'b0 ), + .cfg_interrupt_msi_function_number ( 4'b0 ), + + //--------------------------------------------------------------------------------------// + // System(SYS) Interface // + //--------------------------------------------------------------------------------------// + + .sys_clk ( sys_clk ), + .sys_clk_gt ( sys_clk_gt ), + .sys_reset ( sys_rst_n ) + ); + +endmodule From 9abe50879a787313f81b2ab263eae178d1763d68 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 11 Apr 2023 11:28:50 +0200 Subject: [PATCH 35/41] phy/usp/s_axis_rq_adapt_x4: Minor cosmetic cleanup. --- litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v | 144 ++++++++++--------- 1 file changed, 80 insertions(+), 64 deletions(-) diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v index 01fbfc66..ac4261aa 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v @@ -56,94 +56,110 @@ module s_axis_rq_adapt # ( reg [1:0] s_axis_rq_cnt; //0-2 always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_cnt <= 2'd0; + if (user_reset_out) + s_axis_rq_cnt <= 2'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; + if (s_axis_rq_tlast_ff) + s_axis_rq_cnt <= 2'd0; + else if (!s_axis_rq_cnt[1]) + s_axis_rq_cnt <= s_axis_rq_cnt + 1; end - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - //processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; + // processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_write = !s_axis_rq_read; + reg s_axis_rq_tlast_dly_en; + reg s_axis_rq_tlast_lat; + wire [3:0] s_axis_rq_tready_a; always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); + if (user_reset_out) + s_axis_rq_tlast_dly_en <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) + s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; + if (user_reset_out) + s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) + s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; + if (s_axis_rq_tfirst) + s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword + else + s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; end - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + // Generate ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - //latch valid because it is uncontigous when coming from TLP request - reg s_axis_rq_tvalid_lat; + // Latch valid because it is uncontigous when coming from TLP request + reg s_axis_rq_tvalid_lat; always @(posedge user_clk_out) - if (user_reset_out) s_axis_rq_tvalid_lat <= 1'b0; + if (user_reset_out) + s_axis_rq_tvalid_lat <= 1'b0; else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) begin - if (s_axis_rq_tlast_dly_en) s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; - else s_axis_rq_tvalid_lat <= !(s_axis_rq_tlast_ff && s_axis_rq_tvalid_ff); + if (s_axis_rq_tlast_dly_en) + s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; + else + s_axis_rq_tvalid_lat <= !(s_axis_rq_tlast_ff && s_axis_rq_tvalid_ff); end - else if (s_axis_rq_tvalid_ff & s_axis_rq_tfirst & s_axis_rq_write) s_axis_rq_tvalid_lat <= 1'b1; //latche input valid (required by PCIe IP) - - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; + else if (s_axis_rq_tvalid_ff & s_axis_rq_tfirst & s_axis_rq_write) + s_axis_rq_tvalid_lat <= 1'b1; //latche input valid (required by PCIe IP) + + wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [3:0] s_axis_rq_reqtype = + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request + s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request + s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request + s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 + s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 + 4'b1111; + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; // Applicable only to Configuration requests and messages routed by ID. + wire s_axis_rq_requester_en = 1'b0; // Must be 0 for Endpoint. + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = { + s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen + }; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; always @(posedge user_clk_out) begin if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) begin s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; + s_axis_rq_lastbe_l <= s_axis_rq_lastbe; end end From 0ce9fe14ad875fcb60503032074786bb954f47e3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 7 Nov 2023 17:32:14 +0100 Subject: [PATCH 36/41] phy: Update with master. --- litepcie/phy/s7pciephy.py | 97 +++++++++++++++++++++++--------------- litepcie/phy/uspciephy.py | 6 ++- litepcie/phy/usppciephy.py | 6 ++- 3 files changed, 69 insertions(+), 40 deletions(-) diff --git a/litepcie/phy/s7pciephy.py b/litepcie/phy/s7pciephy.py index 61b4d35e..79aae73b 100644 --- a/litepcie/phy/s7pciephy.py +++ b/litepcie/phy/s7pciephy.py @@ -22,7 +22,13 @@ class S7PCIEPHY(LiteXModule): endianness = "big" qword_aligned = False - def __init__(self, platform, pads, data_width=64, bar0_size=1*MB, cd="sys", pcie_data_width=None): + def __init__(self, platform, pads, data_width=64, cd="sys", + # PCIe hardblock parameters. + pcie_data_width = None, + bar0_size = 0x100000, + msi_type = "msi", + with_ptm = False, + ): # Streams ---------------------------------------------------------------------------------- self.sink = stream.Endpoint(phy_layout(data_width)) self.source = stream.Endpoint(phy_layout(data_width)) @@ -434,44 +440,58 @@ def add_sources(self, platform, phy_path, phy_filename=None): if phy_filename is not None: platform.add_ip(os.path.join(phy_path, phy_filename)) else: + # Global parameters. config = { - # Generic Config. - # --------------- - "Component_Name" : "pcie", - "Device_ID" : 7020 + self.nlanes, - "Link_Speed" : "5.0_GT/s", - "Trgt_Link_Speed" : "4'h2", - "Max_Payload_Size" : { - 1 : "256_bytes", - 2 : "256_bytes", - 4 : "256_bytes", - 8 : "512_bytes", - }[self.nlanes], - "Interface_Width" : f"{self.pcie_data_width}_bit", - "Buf_Opt_BMA" : True, - "Maximum_Link_Width" : f"X{self.nlanes}", - "PCIe_Blk_Locn" : "X0Y0", - "Ref_Clk_Freq" : "100_MHz", - "Trans_Buf_Pipeline" : None, - "User_Clk_Freq" : { - 1 : 125, - 2 : 125, - 4 : 125, - 8 : 250, - }[self.nlanes], - - # BAR0 Config. - # ------------ - "Bar0_Scale" : "Megabytes", # FIXME. - "Bar0_Size" : max(self.bar0_size/MB, 1), # FIXME. - - # Interrupt Config. - # ----------------- - "IntX_Generation" : False, - "Legacy_Interrupt" : None, - "MSI_64b" : False, - "Multiple_Message_Capable" : '1_vector', + "Bar0_Scale" : "Megabytes", + "Bar0_Size" : 1, + "Buf_Opt_BMA" : True, + "Component_Name" : "pcie", + "Device_ID" : 7020 + self.nlanes, + "Interface_Width" : f"{self.pcie_data_width}_bit", + "Link_Speed" : "5.0_GT/s", + "Max_Payload_Size" : "512_bytes" if self.nlanes != 8 else "256_bytes", + "Maximum_Link_Width" : f"X{self.nlanes}", + "PCIe_Blk_Locn" : "X0Y0", + "Ref_Clk_Freq" : "100_MHz", + "Trans_Buf_Pipeline" : None, + "Trgt_Link_Speed" : "4'h2", + "User_Clk_Freq" : 125 if self.nlanes != 8 else 250, } + + # Interrupts parameters. + assert self.msi_type in ["msi", "msi-multi-vector", "msi-x"] + config.update({ + "Legacy_Interrupt" : None, + "IntX_Generation" : False, + }) + if self.msi_type == "msi": + config.update({ + "MSI_64b" : False, + "Multiple_Message_Capable" : "1_vector", + }) + if self.msi_type == "msi-multi-vector": + config.update({ + "MSI_64b" : False, + "Multiple_Message_Capable" : "1_vector", # FIXME. + }) + if self.msi_type == "msi-x": + config.update({ + "mode_selection" : "Advanced", + "MSI_Enabled" : False, + "MSIx_Enabled" : True, + "MSIx_Table_Size" : "20", # Hexa. + "MSIx_Table_Offset" : "2000", # Hexa, should match CSR_PCIE_MSI_TABLE_BASE. + "MSIx_PBA_Offset" : "1808", # Hexa, should match CSR_PCIE_MSI_PBA_ADDR. + }) + + # Extended Capabilities Registers. + if self.with_ptm: + config.update({ + "EXT_PCI_CFG_Space" : True, + "EXT_PCI_CFG_Space_Addr" : "6B", # 0x1AC. + }) + + # Tcl generation. ip_tcl = [] ip_tcl.append("create_ip -vendor xilinx.com -name pcie_7x -module_name pcie_s7") ip_tcl.append("set obj [get_ips pcie_s7]") @@ -481,6 +501,7 @@ def add_sources(self, platform, phy_path, phy_filename=None): ip_tcl.append(f"] $obj") ip_tcl.append("synth_ip $obj") platform.toolchain.pre_synthesis_commands += ip_tcl + # Reset LOC constraints on GTPE2_COMMON and BRAM36 from .xci (we only want to keep Timing constraints). if platform.device.startswith("xc7a"): platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_common.gtpe2_common_i}}]") @@ -499,6 +520,6 @@ def do_finalize(self): if not self.external_hard_ip: phy_path = "xilinx_s7_gen2" self.add_sources(self.platform, - phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), + phy_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), phy_path), ) self.specials += Instance("pcie_s7", **self.pcie_phy_params) diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py index d79975d9..43057e17 100644 --- a/litepcie/phy/uspciephy.py +++ b/litepcie/phy/uspciephy.py @@ -21,7 +21,11 @@ class USPCIEPHY(LiteXModule): endianness = "little" qword_aligned = False - def __init__(self, platform, pads, speed="gen3", data_width=64, bar0_size=1*MB, cd="sys", pcie_data_width=None): + def __init__(self, platform, pads, speed="gen3", data_width=64, cd="sys", + # PCIe hardblock parameters. + pcie_data_width = None, + bar0_size = 0x100000, + ): # Streams ---------------------------------------------------------------------------------- self.req_sink = stream.Endpoint(phy_layout(data_width)) self.cmp_sink = stream.Endpoint(phy_layout(data_width)) diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py index 5df75a7e..440c1cc7 100644 --- a/litepcie/phy/usppciephy.py +++ b/litepcie/phy/usppciephy.py @@ -21,7 +21,11 @@ class USPPCIEPHY(LiteXModule): endianness = "little" qword_aligned = False - def __init__(self, platform, pads, speed="gen3", data_width=64, bar0_size=1*MB, cd="sys", pcie_data_width=None): + def __init__(self, platform, pads, speed="gen3", data_width=64, cd="sys", + # PCIe hardblock parameters. + pcie_data_width = None, + bar0_size = 0x100000, + ): # Streams ---------------------------------------------------------------------------------- self.req_sink = stream.Endpoint(phy_layout(data_width)) self.cmp_sink = stream.Endpoint(phy_layout(data_width)) From 1e9679c244e066fdd8114a85a44e09ba0463fcd2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 8 Nov 2023 15:11:00 +0100 Subject: [PATCH 37/41] phy/xilinx_usp: Fix x8 adapters and integration in pcie_usp_support.v. --- litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v | 2 +- litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v | 2 +- litepcie/phy/xilinx_usp/pcie_usp_support.v | 28 +++++++--- litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v | 42 ++++++++------- litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v | 54 ++++++++++---------- 5 files changed, 69 insertions(+), 59 deletions(-) diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v index 7a37051a..f360de59 100644 --- a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v @@ -4,7 +4,7 @@ // SPDX-License-Identifier: BSD-2-Clause module m_axis_cq_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v index 7dd7ae72..3811870d 100644 --- a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v @@ -4,7 +4,7 @@ // SPDX-License-Identifier: BSD-2-Clause module m_axis_rc_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_usp/pcie_usp_support.v b/litepcie/phy/xilinx_usp/pcie_usp_support.v index 900531f1..b4bcc06a 100644 --- a/litepcie/phy/xilinx_usp/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp/pcie_usp_support.v @@ -314,6 +314,13 @@ module pcie_support # ( //----------------------------------------------------- RQ AXIS -------------------------------------------------// + wire s_axis_rq_tvalid_a; + wire s_axis_rq_tready_a; + wire [KEEP_WIDTH-1 :0] s_axis_rq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] s_axis_rq_tdata_a; + wire [59 :0] s_axis_rq_tuser_a; + wire s_axis_rq_tlast_a; + s_axis_rq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) @@ -373,7 +380,7 @@ module pcie_support # ( wire m_axis_cq_tready_a; wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; - wire [74 :0] m_axis_cq_tuser_a; + wire [84 :0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; m_axis_cq_adapt #( @@ -390,16 +397,23 @@ module pcie_support # ( .m_axis_cq_tuser( m_axis_cq_tuser), .m_axis_cq_tvalid(m_axis_cq_tvalid), - .m_axis_cq_tdata_a( s_axis_cq_tdata_a), - .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), - .m_axis_cq_tlast_a( s_axis_cq_tlast_a), - .m_axis_cq_tready_a(s_axis_cq_tready_a), - .m_axis_cq_tuser_a( s_axis_cq_tuser_a), - .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + .m_axis_cq_tdata_a( m_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( m_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( m_axis_cq_tlast_a), + .m_axis_cq_tready_a(m_axis_cq_tready_a), + .m_axis_cq_tuser_a( m_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(m_axis_cq_tvalid_a) ); //----------------------------------------------------- CC AXIS --------------------------------------------------// + wire s_axis_cc_tvalid_a; + wire s_axis_cc_tready_a; + wire [KEEP_WIDTH-1 :0] s_axis_cc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] s_axis_cc_tdata_a; + wire [32 :0] s_axis_cc_tuser_a; + wire s_axis_cc_tlast_a; + s_axis_cc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v index fd4906d6..a3f50cc3 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v @@ -4,26 +4,26 @@ // SPDX-License-Identifier: BSD-2-Clause module s_axis_cc_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_cc_tdata, - output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - output s_axis_cc_tlast, - input [3:0] s_axis_cc_tready, - output [3:0] s_axis_cc_tuser, - output s_axis_cc_tvalid, - - input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, - input s_axis_cc_tlast_a, - output [3:0] s_axis_cc_tready_a, - input [3:0] s_axis_cc_tuser_a, - input s_axis_cc_tvalid_a + input [DATA_WIDTH-1:0] s_axis_cc_tdata, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + input s_axis_cc_tlast, + output s_axis_cc_tready, + input [3:0] s_axis_cc_tuser, + input s_axis_cc_tvalid, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + output s_axis_cc_tlast_a, + input s_axis_cc_tready_a, + output [32:0] s_axis_cc_tuser_a, + output s_axis_cc_tvalid_a ); wire s_axis_cc_tready_ff, @@ -68,8 +68,6 @@ module s_axis_cc_adapt # ( wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - wire [3:0] s_axis_cc_tready_a; - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; wire [1:0] s_axis_cc_at = 2'b0; //address translation wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; @@ -98,12 +96,12 @@ module s_axis_cc_adapt # ( s_axis_cc_tag }; - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + assign s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [255:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [7:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + assign s_axis_cc_tready_ff = s_axis_cc_tready_a; + assign s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + assign s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + assign s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + assign s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v index 00e84c18..a21bda11 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v @@ -4,26 +4,26 @@ // SPDX-License-Identifier: BSD-2-Clause module s_axis_rq_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_rq_tdata, - output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tlast, - input [3:0] s_axis_rq_tready, - output [3:0] s_axis_rq_tuser, - output s_axis_rq_tvalid, - - input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, - input s_axis_rq_tlast_a, - output [3:0] s_axis_rq_tready_a, - input [3:0] s_axis_rq_tuser_a, - input s_axis_rq_tvalid_a + input [DATA_WIDTH-1:0] s_axis_rq_tdata, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + input s_axis_rq_tlast, + output s_axis_rq_tready, + input [3:0] s_axis_rq_tuser, + input s_axis_rq_tvalid, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + output s_axis_rq_tlast_a, + input s_axis_rq_tready_a, + output [59:0] s_axis_rq_tuser_a, + output s_axis_rq_tvalid_a ); wire s_axis_rq_tready_ff, @@ -72,26 +72,25 @@ module s_axis_rq_adapt # ( wire s_axis_rq_write = !s_axis_rq_read; reg s_axis_rq_tlast_dly_en; reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a) begin if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd5) : 1'b0; //write 5 dwords else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; end - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + assign s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + //Generate ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a && (!s_axis_rq_tlast_lat); + assign s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request @@ -141,11 +140,10 @@ module s_axis_rq_adapt # ( if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; - wire [255:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : - {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; - wire [7:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; + assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : + {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; + assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; endmodule \ No newline at end of file From 335c4f6e01672f6faac7948df06cbc35225076fb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 8 Nov 2023 15:22:56 +0100 Subject: [PATCH 38/41] phy/xilinx_usp/adapters: Update/Fix x16/x4. --- litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v | 2 +- litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v | 2 +- litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v | 43 ++++++------ litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v | 40 ++++++------ litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v | 54 ++++++++------- litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v | 65 +++++++++---------- 6 files changed, 99 insertions(+), 107 deletions(-) diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v index 8748e4d4..b343760b 100644 --- a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v @@ -4,7 +4,7 @@ // SPDX-License-Identifier: BSD-2-Clause module m_axis_cq_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 512, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v index ccc39249..8d21d865 100644 --- a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v @@ -4,7 +4,7 @@ // SPDX-License-Identifier: BSD-2-Clause module m_axis_rc_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 512, parameter KEEP_WIDTH = DATA_WIDTH/8 )( diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v index b79bb120..013027d7 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v @@ -4,26 +4,26 @@ // SPDX-License-Identifier: BSD-2-Clause module s_axis_cc_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 512, parameter KEEP_WIDTH = DATA_WIDTH/8 )( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_cc_tdata, - output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - output s_axis_cc_tlast, - input [3:0] s_axis_cc_tready, - output [3:0] s_axis_cc_tuser, - output s_axis_cc_tvalid, - - input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, - input s_axis_cc_tlast_a, - output [3:0] s_axis_cc_tready_a, - input [3:0] s_axis_cc_tuser_a, - input s_axis_cc_tvalid_a + input [DATA_WIDTH-1:0] s_axis_cc_tdata, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + input s_axis_cc_tlast, + output s_axis_cc_tready, + input [3:0] s_axis_cc_tuser, + input s_axis_cc_tvalid, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + output s_axis_cc_tlast_a, + input s_axis_cc_tready_a, + output [32:0] s_axis_cc_tuser_a, + output s_axis_cc_tvalid_a ); wire s_axis_cc_tready_ff, @@ -72,8 +72,6 @@ module s_axis_cc_adapt # ( wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - wire [3:0] s_axis_cc_tready_a; - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; wire [1:0] s_axis_cc_at = 2'b0; //address translation wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; @@ -102,13 +100,12 @@ module s_axis_cc_adapt # ( s_axis_cc_tag }; - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [511:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[511:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [15:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + assign s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + assign s_axis_cc_tready_ff = s_axis_cc_tready_a; + assign s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[511:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + assign s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + assign s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + assign s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v index 01e3d2ef..c270cb36 100644 --- a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v @@ -11,19 +11,19 @@ module s_axis_cc_adapt # ( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_cc_tdata, - output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - output s_axis_cc_tlast, - input [3:0] s_axis_cc_tready, - output [3:0] s_axis_cc_tuser, - output s_axis_cc_tvalid, - - input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, - input s_axis_cc_tlast_a, - output [3:0] s_axis_cc_tready_a, - input [3:0] s_axis_cc_tuser_a, - input s_axis_cc_tvalid_a + input [DATA_WIDTH-1:0] s_axis_cc_tdata, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + input s_axis_cc_tlast, + output s_axis_cc_tready, + input [3:0] s_axis_cc_tuser, + input s_axis_cc_tvalid, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + output s_axis_cc_tlast_a, + input s_axis_cc_tready_a, + output [32:0] s_axis_cc_tuser_a, + output s_axis_cc_tvalid_a ); wire s_axis_cc_tready_ff, @@ -66,8 +66,6 @@ module s_axis_cc_adapt # ( wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - wire [3:0] s_axis_cc_tready_a; - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; wire [1:0] s_axis_cc_at = 2'b0; //address translation wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; @@ -108,11 +106,11 @@ module s_axis_cc_adapt # ( else if (s_axis_cc_tfirst) s_axis_cc_tvalid_ff_lat <= 1'd1; end - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [127:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [3:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + assign s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + assign s_axis_cc_tready_ff = s_axis_cc_tready_a; + assign s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + assign s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + assign s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + assign s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v index 8df40829..ab4794f7 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v @@ -4,26 +4,26 @@ // SPDX-License-Identifier: BSD-2-Clause module s_axis_rq_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 512, parameter KEEP_WIDTH = DATA_WIDTH/8 )( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_rq_tdata, - output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tlast, - input [3:0] s_axis_rq_tready, - output [3:0] s_axis_rq_tuser, - output s_axis_rq_tvalid, - - input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, - input s_axis_rq_tlast_a, - output [3:0] s_axis_rq_tready_a, - input [3:0] s_axis_rq_tuser_a, - input s_axis_rq_tvalid_a + input [DATA_WIDTH-1:0] s_axis_rq_tdata, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + input s_axis_rq_tlast, + output s_axis_rq_tready, + input [3:0] s_axis_rq_tuser, + input s_axis_rq_tvalid, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + output s_axis_rq_tlast_a, + input s_axis_rq_tready_a, + output [136:0] s_axis_rq_tuser_a, + output s_axis_rq_tvalid_a ); wire s_axis_rq_tready_ff, @@ -74,26 +74,25 @@ module s_axis_rq_adapt # ( wire s_axis_rq_write = !s_axis_rq_read; reg s_axis_rq_tlast_dly_en; reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[3:0] == 5'd13); always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a) begin if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd13) : 1'b0; //write 13 dwords else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; end - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd13)) : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + assign s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd13)) : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + //Generate ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a && (!s_axis_rq_tlast_lat); + assign s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request @@ -143,11 +142,10 @@ module s_axis_rq_adapt # ( if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[511:480]; - wire [511:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[479:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : - {s_axis_rq_tdata_ff[479:0], s_axis_rq_tdata_l[31:0]}; - wire [15:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 16'h1 : {s_axis_rq_tkeep_ff[14:0], 1'b1}; - wire [136:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[36] = s_axis_rq_tuser_ff[3]; //discontinue - assign s_axis_rq_tuser_a[15:0] = {4'b0, s_axis_rq_lastbe, 4'b0, s_axis_rq_firstbe}; + assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[479:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : + {s_axis_rq_tdata_ff[479:0], s_axis_rq_tdata_l[31:0]}; + assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 16'h1 : {s_axis_rq_tkeep_ff[14:0], 1'b1}; + assign s_axis_rq_tuser_a[36] = s_axis_rq_tuser_ff[3]; //discontinue + assign s_axis_rq_tuser_a[15:0] = {4'b0, s_axis_rq_lastbe, 4'b0, s_axis_rq_firstbe}; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v index ac4261aa..3a699176 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v @@ -11,19 +11,19 @@ module s_axis_rq_adapt # ( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_rq_tdata, - output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tlast, - input [3:0] s_axis_rq_tready, - output [3:0] s_axis_rq_tuser, - output s_axis_rq_tvalid, - - input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, - input s_axis_rq_tlast_a, - output [3:0] s_axis_rq_tready_a, - input [3:0] s_axis_rq_tuser_a, - input s_axis_rq_tvalid_a + input [DATA_WIDTH-1:0] s_axis_rq_tdata, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + input s_axis_rq_tlast, + output s_axis_rq_tready, + input [3:0] s_axis_rq_tuser, + input s_axis_rq_tvalid, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + output s_axis_rq_tlast_a, + input s_axis_rq_tready_a, + output [59:0] s_axis_rq_tuser_a, + output s_axis_rq_tvalid_a ); wire s_axis_rq_tready_ff, @@ -37,8 +37,8 @@ module s_axis_rq_adapt # ( axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff ( - .clk (user_clk_out), - .rst (user_reset_out), + .clk (user_clk), + .rst (user_reset), .i_vld (s_axis_rq_tvalid), .o_rdy (s_axis_rq_tready), @@ -55,8 +55,8 @@ module s_axis_rq_adapt # ( reg [1:0] s_axis_rq_cnt; //0-2 - always @(posedge user_clk_out) - if (user_reset_out) + always @(posedge user_clk) + if (user_reset) s_axis_rq_cnt <= 2'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) begin @@ -74,15 +74,14 @@ module s_axis_rq_adapt # ( wire s_axis_rq_write = !s_axis_rq_read; reg s_axis_rq_tlast_dly_en; reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; - always @(posedge user_clk_out) - if (user_reset_out) + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); - always @(posedge user_clk_out) - if (user_reset_out) + always @(posedge user_clk) + if (user_reset) s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; @@ -94,7 +93,7 @@ module s_axis_rq_adapt # ( s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; end - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : + assign s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; // Generate ready for TLP @@ -102,8 +101,8 @@ module s_axis_rq_adapt # ( // Latch valid because it is uncontigous when coming from TLP request reg s_axis_rq_tvalid_lat; - always @(posedge user_clk_out) - if (user_reset_out) + always @(posedge user_clk) + if (user_reset) s_axis_rq_tvalid_lat <= 1'b0; else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) begin @@ -115,7 +114,7 @@ module s_axis_rq_adapt # ( else if (s_axis_rq_tvalid_ff & s_axis_rq_tfirst & s_axis_rq_write) s_axis_rq_tvalid_lat <= 1'b1; //latche input valid (required by PCIe IP) - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + assign s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = @@ -154,7 +153,7 @@ module s_axis_rq_adapt # ( reg [3:0] s_axis_rq_firstbe_l; reg [3:0] s_axis_rq_lastbe_l; - always @(posedge user_clk_out) + always @(posedge user_clk) begin if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) begin @@ -164,15 +163,15 @@ module s_axis_rq_adapt # ( end reg [31:0] s_axis_rq_tdata_l; - always @(posedge user_clk_out) + always @(posedge user_clk) if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; - wire [127:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; - wire [3:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; + assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; + assign s_axis_rq_tuser_a; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; endmodule \ No newline at end of file From 8d0d01203b570ea223fedb73b179ae3f4e6e0990 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 9 Nov 2023 17:25:02 +0100 Subject: [PATCH 39/41] phy/xilinx_usp/pcie_usp_support: Use 256-bit tuser to ensure it is large enough for all cases. --- litepcie/phy/xilinx_usp/pcie_usp_support.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litepcie/phy/xilinx_usp/pcie_usp_support.v b/litepcie/phy/xilinx_usp/pcie_usp_support.v index b4bcc06a..500ac8f5 100644 --- a/litepcie/phy/xilinx_usp/pcie_usp_support.v +++ b/litepcie/phy/xilinx_usp/pcie_usp_support.v @@ -318,7 +318,7 @@ module pcie_support # ( wire s_axis_rq_tready_a; wire [KEEP_WIDTH-1 :0] s_axis_rq_tkeep_a; wire [C_DATA_WIDTH-1 :0] s_axis_rq_tdata_a; - wire [59 :0] s_axis_rq_tuser_a; + wire [255 :0] s_axis_rq_tuser_a; wire s_axis_rq_tlast_a; s_axis_rq_adapt #( @@ -349,7 +349,7 @@ module pcie_support # ( wire m_axis_rc_tready_a; wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; - wire [74 :0] m_axis_rc_tuser_a; + wire [255 :0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; m_axis_rc_adapt #( @@ -380,7 +380,7 @@ module pcie_support # ( wire m_axis_cq_tready_a; wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; - wire [84 :0] m_axis_cq_tuser_a; + wire [255 :0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; m_axis_cq_adapt #( @@ -411,7 +411,7 @@ module pcie_support # ( wire s_axis_cc_tready_a; wire [KEEP_WIDTH-1 :0] s_axis_cc_tkeep_a; wire [C_DATA_WIDTH-1 :0] s_axis_cc_tdata_a; - wire [32 :0] s_axis_cc_tuser_a; + wire [255 :0] s_axis_cc_tuser_a; wire s_axis_cc_tlast_a; s_axis_cc_adapt #( From 796c3dd87ff847e9f28001bcb3e859fe72cb103c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 9 Nov 2023 17:59:22 +0100 Subject: [PATCH 40/41] phy/xilinx_us: Update from xilinx_usp changes. --- litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v | 50 +++---- litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v | 52 ++++--- litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v | 75 +++++----- litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v | 77 +++++----- litepcie/phy/xilinx_us/pcie_us_support.v | 32 ++-- litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v | 105 ++++++-------- litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v | 129 ++++++++--------- litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v | 153 +++++++++++--------- litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v | 128 ++++++++-------- 9 files changed, 396 insertions(+), 405 deletions(-) diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v index 384334d7..1861e7f1 100644 --- a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v @@ -64,7 +64,7 @@ module m_axis_cq_adapt # ( else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; end @@ -77,8 +77,8 @@ module m_axis_cq_adapt # ( ////keep address (low) or data (high), not header - reg [DATA_WIDTH-1:0] m_axis_cq_tdata_a1; - reg [DATA_WIDTH/8-1:0] m_axis_cq_tlast_be1; + reg [127:0] m_axis_cq_tdata_a1; + reg [15:0] m_axis_cq_tlast_be1; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin @@ -89,15 +89,15 @@ module m_axis_cq_adapt # ( //data processing wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; wire [4:0] m_axis_cq_type; wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request @@ -125,15 +125,13 @@ module m_axis_cq_adapt # ( reg [63:0] m_axis_cq_header; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = { - m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen - }; + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : @@ -144,12 +142,12 @@ module m_axis_cq_adapt # ( assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_ecrc //ECRC mapped to discontinue - }; + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_ecrc //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v index df99038d..f360de59 100644 --- a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v @@ -4,7 +4,7 @@ // SPDX-License-Identifier: BSD-2-Clause module m_axis_cq_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -60,7 +60,7 @@ module m_axis_cq_adapt # ( else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; end @@ -73,8 +73,8 @@ module m_axis_cq_adapt # ( ////keep address (low) or data (high), not header - reg [DATA_WIDTH-1:0] m_axis_cq_tdata_a1; - reg [DATA_WIDTH/8-1:0] m_axis_cq_tlast_be1; + reg [255:0] m_axis_cq_tdata_a1; + reg [31:0] m_axis_cq_tlast_be1; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin @@ -85,15 +85,15 @@ module m_axis_cq_adapt # ( //data processing wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; wire [4:0] m_axis_cq_type; wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request @@ -115,27 +115,25 @@ module m_axis_cq_adapt # ( reg [63:0] m_axis_cq_header; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = { - m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen - }; + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:32]}; assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[31:16], 12'hFFF} : m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[31:4]} : 32'hFFFF_FFFF; assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_tuser_a[41] //ECRC mapped to discontinue - }; + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_tuser_a[41] //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v index f22a94c6..fb857ef1 100644 --- a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v +++ b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v @@ -47,20 +47,20 @@ module m_axis_rc_adapt # ( m_axis_rc_poisoning_l <= m_axis_rc_poisoning; end - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; wire [4:0] m_axis_rc_type; wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; assign {m_axis_rc_fmt, @@ -69,36 +69,31 @@ module m_axis_rc_adapt # ( ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data 8'b010_01010); //Completion w/ data - wire [63:0] m_axis_rc_header0 = { - m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen - }; - wire [63:0] m_axis_rc_header1 = { - m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr - }; - - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; - assign m_axis_rc_tuser = { - 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; + assign m_axis_rc_tuser = { + 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v index 0e5e04e7..3811870d 100644 --- a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v @@ -4,7 +4,7 @@ // SPDX-License-Identifier: BSD-2-Clause module m_axis_rc_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -47,20 +47,20 @@ module m_axis_rc_adapt # ( m_axis_rc_poisoning_l <= m_axis_rc_poisoning; end - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; wire [4:0] m_axis_rc_type; wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; assign {m_axis_rc_fmt, @@ -69,35 +69,32 @@ module m_axis_rc_adapt # ( ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data 8'b010_01010); //Completion w/ data - wire [63:0] m_axis_rc_header0 = { - m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen - }; - wire [63:0] m_axis_rc_header1 = { - m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr - }; + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; + assign m_axis_rc_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; - assign m_axis_rc_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/pcie_us_support.v b/litepcie/phy/xilinx_us/pcie_us_support.v index 5bfe21b0..e9b90720 100644 --- a/litepcie/phy/xilinx_us/pcie_us_support.v +++ b/litepcie/phy/xilinx_us/pcie_us_support.v @@ -314,6 +314,13 @@ module pcie_support # ( //----------------------------------------------------- RQ AXIS -------------------------------------------------// + wire s_axis_rq_tvalid_a; + wire s_axis_rq_tready_a; + wire [KEEP_WIDTH-1 :0] s_axis_rq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] s_axis_rq_tdata_a; + wire [255 :0] s_axis_rq_tuser_a; + wire s_axis_rq_tlast_a; + s_axis_rq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) @@ -342,7 +349,7 @@ module pcie_support # ( wire m_axis_rc_tready_a; wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; - wire [74 :0] m_axis_rc_tuser_a; + wire [255 :0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; m_axis_rc_adapt #( @@ -373,7 +380,7 @@ module pcie_support # ( wire m_axis_cq_tready_a; wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; - wire [74 :0] m_axis_cq_tuser_a; + wire [255 :0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; m_axis_cq_adapt #( @@ -390,16 +397,23 @@ module pcie_support # ( .m_axis_cq_tuser( m_axis_cq_tuser), .m_axis_cq_tvalid(m_axis_cq_tvalid), - .m_axis_cq_tdata_a( s_axis_cq_tdata_a), - .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), - .m_axis_cq_tlast_a( s_axis_cq_tlast_a), - .m_axis_cq_tready_a(s_axis_cq_tready_a), - .m_axis_cq_tuser_a( s_axis_cq_tuser_a), - .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + .m_axis_cq_tdata_a( m_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( m_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( m_axis_cq_tlast_a), + .m_axis_cq_tready_a(m_axis_cq_tready_a), + .m_axis_cq_tuser_a( m_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(m_axis_cq_tvalid_a) ); //----------------------------------------------------- CC AXIS --------------------------------------------------// + wire s_axis_cc_tvalid_a; + wire s_axis_cc_tready_a; + wire [KEEP_WIDTH-1 :0] s_axis_cc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] s_axis_cc_tdata_a; + wire [255 :0] s_axis_cc_tuser_a; + wire s_axis_cc_tlast_a; + s_axis_cc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) @@ -436,7 +450,7 @@ module pcie_support # ( 3'd1 : cfg_interrupt_msi_int_enc <= 32'h0000_0002; 3'd2 : cfg_interrupt_msi_int_enc <= 32'h0000_0010; 3'd3 : cfg_interrupt_msi_int_enc <= 32'h0000_0100; - 3'd4: cfg_interrupt_msi_int_enc <= 32'h0001_0000; + 3'd4 : cfg_interrupt_msi_int_enc <= 32'h0001_0000; default: cfg_interrupt_msi_int_enc <= 32'h8000_0000; endcase diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v index b04e728c..c270cb36 100644 --- a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v @@ -11,36 +11,32 @@ module s_axis_cc_adapt # ( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_cc_tdata, - output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - output s_axis_cc_tlast, - input [3:0] s_axis_cc_tready, - output [3:0] s_axis_cc_tuser, - output s_axis_cc_tvalid, - - input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, - input s_axis_cc_tlast_a, - output [3:0] s_axis_cc_tready_a, - input [3:0] s_axis_cc_tuser_a, - input s_axis_cc_tvalid_a + input [DATA_WIDTH-1:0] s_axis_cc_tdata, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + input s_axis_cc_tlast, + output s_axis_cc_tready, + input [3:0] s_axis_cc_tuser, + input s_axis_cc_tvalid, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + output s_axis_cc_tlast_a, + input s_axis_cc_tready_a, + output [32:0] s_axis_cc_tuser_a, + output s_axis_cc_tvalid_a ); wire s_axis_cc_tready_ff, s_axis_cc_tvalid_ff, s_axis_cc_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_or = { - |s_axis_cc_tkeep[15:12], - |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], - |s_axis_cc_tkeep[3:0] - }; + wire [3:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; wire [3:0] s_axis_cc_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_ff; + wire [3:0] s_axis_cc_tkeep_ff; + wire [127:0] s_axis_cc_tdata_ff; - axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_cc_iff + axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff ( .clk (user_clk), .rst (user_reset), @@ -67,41 +63,36 @@ module s_axis_cc_adapt # ( else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; end - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = { - s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr - }; - wire [63:0] s_axis_cc_header1 = { - s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; reg [3:0] s_axis_cc_firstbe; reg [3:0] s_axis_cc_lastbe; @@ -115,11 +106,11 @@ module s_axis_cc_adapt # ( else if (s_axis_cc_tfirst) s_axis_cc_tvalid_ff_lat <= 1'd1; end - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + assign s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + assign s_axis_cc_tready_ff = s_axis_cc_tready_a; + assign s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + assign s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + assign s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + assign s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v index e401c10f..a3f50cc3 100644 --- a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v @@ -4,47 +4,41 @@ // SPDX-License-Identifier: BSD-2-Clause module s_axis_cc_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_cc_tdata, - output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - output s_axis_cc_tlast, - input [3:0] s_axis_cc_tready, - output [3:0] s_axis_cc_tuser, - output s_axis_cc_tvalid, - - input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, - input s_axis_cc_tlast_a, - output [3:0] s_axis_cc_tready_a, - input [3:0] s_axis_cc_tuser_a, - input s_axis_cc_tvalid_a + input [DATA_WIDTH-1:0] s_axis_cc_tdata, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + input s_axis_cc_tlast, + output s_axis_cc_tready, + input [3:0] s_axis_cc_tuser, + input s_axis_cc_tvalid, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + output s_axis_cc_tlast_a, + input s_axis_cc_tready_a, + output [32:0] s_axis_cc_tuser_a, + output s_axis_cc_tvalid_a ); - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_or = { - |s_axis_cc_tkeep[31:28], - |s_axis_cc_tkeep[27:24], - |s_axis_cc_tkeep[23:20], - |s_axis_cc_tkeep[19:16], - |s_axis_cc_tkeep[15:12], - |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], - |s_axis_cc_tkeep[3:0] - }; - - wire [3 :0] s_axis_cc_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_ff; - - axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_cc_iff + wire s_axis_cc_tready_ff, + s_axis_cc_tvalid_ff, + s_axis_cc_tlast_ff; + wire [7:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[31:28], |s_axis_cc_tkeep[27:24], + |s_axis_cc_tkeep[23:20], |s_axis_cc_tkeep[19:16], + |s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; + + wire [3:0] s_axis_cc_tuser_ff; + wire [7:0] s_axis_cc_tkeep_ff; + wire [255:0] s_axis_cc_tdata_ff; + + axis_iff #(.DAT_B(256+8+4)) s_axis_cc_iff ( .clk (user_clk), .rst (user_reset), @@ -71,48 +65,43 @@ module s_axis_cc_adapt # ( else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; end - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = { - s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr - }; - wire [63:0] s_axis_cc_header1 = { - s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; - - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [KEEP_WIDTH:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; + + assign s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + + assign s_axis_cc_tready_ff = s_axis_cc_tready_a; + assign s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + assign s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + assign s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + assign s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v index d204a911..3a699176 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v @@ -11,36 +11,31 @@ module s_axis_rq_adapt # ( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_rq_tdata, - output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tlast, - input [3:0] s_axis_rq_tready, - output [3:0] s_axis_rq_tuser, - output s_axis_rq_tvalid, - - input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, - input s_axis_rq_tlast_a, - output [3:0] s_axis_rq_tready_a, - input [3:0] s_axis_rq_tuser_a, - input s_axis_rq_tvalid_a + input [DATA_WIDTH-1:0] s_axis_rq_tdata, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + input s_axis_rq_tlast, + output s_axis_rq_tready, + input [3:0] s_axis_rq_tuser, + input s_axis_rq_tvalid, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + output s_axis_rq_tlast_a, + input s_axis_rq_tready_a, + output [59:0] s_axis_rq_tuser_a, + output s_axis_rq_tvalid_a ); wire s_axis_rq_tready_ff, s_axis_rq_tvalid_ff, s_axis_rq_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_or = { - |s_axis_rq_tkeep[15:12], - |s_axis_rq_tkeep[11:8], - |s_axis_rq_tkeep[7:4], - |s_axis_rq_tkeep[3:0] - }; + wire [3:0] s_axis_rq_tkeep_or = {|s_axis_rq_tkeep[15:12], |s_axis_rq_tkeep[11:8], |s_axis_rq_tkeep[7:4], |s_axis_rq_tkeep[3:0]}; - wire [3:0] s_axis_rq_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_rq_tdata_ff; + wire [3:0] s_axis_rq_tuser_ff; + wire [3:0] s_axis_rq_tkeep_ff; + wire [127:0] s_axis_rq_tdata_ff; - axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_rq_iff + axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff ( .clk (user_clk), .rst (user_reset), @@ -61,58 +56,83 @@ module s_axis_rq_adapt # ( reg [1:0] s_axis_rq_cnt; //0-2 always @(posedge user_clk) - if (user_reset) s_axis_rq_cnt <= 2'd0; + if (user_reset) + s_axis_rq_cnt <= 2'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; + if (s_axis_rq_tlast_ff) + s_axis_rq_cnt <= 2'd0; + else if (!s_axis_rq_cnt[1]) + s_axis_rq_cnt <= s_axis_rq_cnt + 1; end - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - //processing for tlast: generate new last in case write & last num of dword = 5 + i*4 - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; + // processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_write = !s_axis_rq_read; + reg s_axis_rq_tlast_dly_en; + reg s_axis_rq_tlast_lat; always @(posedge user_clk) - if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); + if (user_reset) + s_axis_rq_tlast_dly_en <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) + s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); always @(posedge user_clk) - if (user_reset) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; + if (user_reset) + s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) + s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; + if (s_axis_rq_tfirst) + s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword + else + s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; end - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; + assign s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + + // Generate ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + + // Latch valid because it is uncontigous when coming from TLP request + reg s_axis_rq_tvalid_lat; + always @(posedge user_clk) + if (user_reset) + s_axis_rq_tvalid_lat <= 1'b0; + else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) + begin + if (s_axis_rq_tlast_dly_en) + s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; + else + s_axis_rq_tvalid_lat <= !(s_axis_rq_tlast_ff && s_axis_rq_tvalid_ff); + end + else if (s_axis_rq_tvalid_ff & s_axis_rq_tfirst & s_axis_rq_write) + s_axis_rq_tvalid_lat <= 1'b1; //latche input valid (required by PCIe IP) + + assign s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [3:0] s_axis_rq_reqtype = + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request + s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request + s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request + s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 + s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 + 4'b1111; wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint + wire [15:0] s_axis_rq_completerid = 16'b0; // Applicable only to Configuration requests and messages routed by ID. + wire s_axis_rq_requester_en = 1'b0; // Must be 0 for Endpoint. wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest @@ -138,7 +158,7 @@ module s_axis_rq_adapt # ( if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) begin s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; + s_axis_rq_lastbe_l <= s_axis_rq_lastbe; end end @@ -147,10 +167,11 @@ module s_axis_rq_adapt # ( if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; - wire [DATA_WIDTH-1:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; //{s_axis_rq_tkeep_ff[2:0], 1'b1}; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; + assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; + assign s_axis_rq_tuser_a; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v index 900f23e0..a21bda11 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v @@ -4,47 +4,39 @@ // SPDX-License-Identifier: BSD-2-Clause module s_axis_rq_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_rq_tdata, - output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tlast, - input [3:0] s_axis_rq_tready, - output [3:0] s_axis_rq_tuser, - output s_axis_rq_tvalid, - - input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, - input s_axis_rq_tlast_a, - output [3:0] s_axis_rq_tready_a, - input [3:0] s_axis_rq_tuser_a, - input s_axis_rq_tvalid_a + input [DATA_WIDTH-1:0] s_axis_rq_tdata, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + input s_axis_rq_tlast, + output s_axis_rq_tready, + input [3:0] s_axis_rq_tuser, + input s_axis_rq_tvalid, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + output s_axis_rq_tlast_a, + input s_axis_rq_tready_a, + output [59:0] s_axis_rq_tuser_a, + output s_axis_rq_tvalid_a ); - wire s_axis_rq_tready_ff, + wire s_axis_rq_tready_ff, s_axis_rq_tvalid_ff, s_axis_rq_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_or = { - s_axis_rq_tkeep[28], - s_axis_rq_tkeep[24], - s_axis_rq_tkeep[20], - s_axis_rq_tkeep[16], - s_axis_rq_tkeep[12], - s_axis_rq_tkeep[8], - s_axis_rq_tkeep[4], - s_axis_rq_tkeep[0] - }; - - wire [3:0] s_axis_rq_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_rq_iff + wire [7:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], + s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; + + wire [3:0] s_axis_rq_tuser_ff; + wire [7:0] s_axis_rq_tkeep_ff; + wire [255:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(256+8+4)) s_axis_rq_iff ( .clk (user_clk), .rst (user_reset), @@ -72,34 +64,33 @@ module s_axis_rq_adapt # ( else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; end - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; //processing for tlast: generate new last in case write & last num of dword = 5 + i*8 - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request wire s_axis_rq_write = !s_axis_rq_read; reg s_axis_rq_tlast_dly_en; reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a) begin if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd5) : 1'b0; //write 5 dwords else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; end - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + assign s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + //Generate ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a && (!s_axis_rq_tlast_lat); + assign s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request @@ -112,30 +103,28 @@ module s_axis_rq_adapt # ( s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = { - s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen - }; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; always @(posedge user_clk) begin @@ -151,11 +140,10 @@ module s_axis_rq_adapt # ( if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; - wire [DATA_WIDTH-1:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : - {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; + assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : + {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; + assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; endmodule \ No newline at end of file From 9e0a01e823a58c9d0d96d71e957a54cab3fa8126 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 9 Nov 2023 18:52:32 +0100 Subject: [PATCH 41/41] phy/xilinx_us(p): Fix s_axis_rq_adapt_x4.v. --- litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v | 9 ++++----- litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v index 3a699176..df1e5d92 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v @@ -83,9 +83,9 @@ module s_axis_rq_adapt # ( always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a) begin if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword @@ -97,14 +97,14 @@ module s_axis_rq_adapt # ( s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; // Generate ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + assign s_axis_rq_tready_ff = s_axis_rq_tready_a && (!s_axis_rq_tlast_lat); // Latch valid because it is uncontigous when coming from TLP request reg s_axis_rq_tvalid_lat; always @(posedge user_clk) if (user_reset) s_axis_rq_tvalid_lat <= 1'b0; - else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a) begin if (s_axis_rq_tlast_dly_en) s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; @@ -169,7 +169,6 @@ module s_axis_rq_adapt # ( assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; - assign s_axis_rq_tuser_a; assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v index 3a699176..df1e5d92 100644 --- a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v @@ -83,9 +83,9 @@ module s_axis_rq_adapt # ( always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a) begin if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword @@ -97,14 +97,14 @@ module s_axis_rq_adapt # ( s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; // Generate ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + assign s_axis_rq_tready_ff = s_axis_rq_tready_a && (!s_axis_rq_tlast_lat); // Latch valid because it is uncontigous when coming from TLP request reg s_axis_rq_tvalid_lat; always @(posedge user_clk) if (user_reset) s_axis_rq_tvalid_lat <= 1'b0; - else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a) begin if (s_axis_rq_tlast_dly_en) s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; @@ -169,7 +169,6 @@ module s_axis_rq_adapt # ( assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; - assign s_axis_rq_tuser_a; assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l};