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Add AXI/AXILite 64 bus support ci #2698: Pull request #1851 opened by trabucayre
December 8, 2023 11:05 29m 14s trabucayre:add_64_bus_support_v2
trabucayre:add_64_bus_support_v2
December 8, 2023 11:05 29m 14s
CHANGES.md: Update. ci #2697: Commit afaeca9 pushed by enjoy-digital
December 7, 2023 15:33 27m 16s master
master
December 7, 2023 15:33 27m 16s
Merge pull request #1850 from trabucayre/efinix_serdes ci #2696: Commit 1512080 pushed by enjoy-digital
December 7, 2023 14:06 27m 47s master
master
December 7, 2023 14:06 27m 47s
Efinix PLL calc when feedback != INTERNAL ci #2695: Pull request #1850 opened by trabucayre
December 7, 2023 11:12 26m 58s trabucayre:efinix_serdes
trabucayre:efinix_serdes
December 7, 2023 11:12 26m 58s
litex/soc/integration/soc: SoCBusHandler 64bits address width support ci #2694: Commit a4ead5c pushed by trabucayre
November 30, 2023 16:47 27m 37s master
master
November 30, 2023 16:47 27m 37s
tools/litex_client: Fix csr_data_width/csr_bus_address_width is None … ci #2693: Commit cba58a0 pushed by enjoy-digital
November 23, 2023 15:30 27m 56s master
master
November 23, 2023 15:30 27m 56s
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