Assertions (and their exclusive inputs) should be guarded by `ifdefs #1942
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codegen
Related to emitting (System)Verilog.
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Related: #1048 |
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Using Yosys, assertions sometimes survive synthesis and cause problems with downstream tools. We never want assertions to get through synthesis so we use the `ASSERT_ON` define guard. The macros that guard the assertion section are configurable via the `--assert_macro_names` flag. Ref: #1942. PiperOrigin-RevId: 734314700
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Our assertions should be guarded by
`ifdefguards. This allows users to easily disable assertions without a recompile and also prevents assertions from being visible to synthesis- I believe yosys in particular can leave in stuff that causes problems for openroad if assertions aren't stripped.Ideally, we'd also guard all the wires/regs that only feed assertions (or other wires/regs that only feed assertions) in those same guards to avoid "value not read" issues.
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