DSLX formatter does not line wrap proc instantiation parametrics

[mikex-oss]

Describe the bug

If you have a long list of parametric bindings for a spawned proc, it will not line wrap at all. E.g.

import xls.examples.ram as ram_model;

const DATA_WIDTH = u32:32;
const RAM_ADDR_WIDTH = u32:7;
const RAM_DEPTH = u32:128;
const WORD_PARTITION_SIZE = DATA_WIDTH;
const INITIALIZED = false;
const ASSERT_VALID_READ = false;

type RamModelReadReq = ram_model::ReadReq<RAM_ADDR_WIDTH, 1>;
type RamModelReadResp = ram_model::ReadResp<DATA_WIDTH>;
type RamModelWriteReq = ram_model::WriteReq<RAM_ADDR_WIDTH, DATA_WIDTH, 1>;
type RamModelWriteResp = ram_model::WriteResp;

proc Foo {
    config() {
        let (ram_model_rd_req_s, ram_model_rd_req_r) = chan<RamModelReadReq>("ram_model_rd_req");
        let (ram_model_rd_resp_s, ram_model_rd_resp_r) =
            chan<RamModelReadResp>("ram_model_rd_resp");
        let (ram_model_wr_req_s, ram_model_wr_req_r) = chan<RamModelWriteReq>("ram_model_wr_req");
        let (ram_model_wr_resp_s, ram_model_wr_resp_r) =
            chan<RamModelWriteResp>("ram_model_wr_resp");

        spawn ram_model::RamModel<
            DATA_WIDTH, RAM_DEPTH, WORD_PARTITION_SIZE, ram_model::SimultaneousReadWriteBehavior::ASSERT_NO_CONFLICT, false, false>(
            ram_model_rd_req_r, ram_model_rd_resp_s, ram_model_wr_req_r, ram_model_wr_resp_s);
    }

    init { () }

    next(state: ()) {  }
}

To Reproduce
The above code is already formatted.

Expected behavior
The parametrics between < and > should be line wrapped as appropriate to fit in the line length constraint.