diff --git a/.circleci/config.yml b/.circleci/config.yml
new file mode 100644
index 0000000000..28afafb006
--- /dev/null
+++ b/.circleci/config.yml
@@ -0,0 +1,79 @@
+version: 2.1
+
+setup: true
+orbs:
+ continuation: circleci/continuation@1
+
+jobs:
+ set-matrix:
+ executor: continuation/default
+ docker:
+ - image: cimg/base:current
+ resource_class: small
+ steps:
+ - checkout
+ - run:
+ name: Set matrix
+ command: |
+ MATRIX_JSON=$(python .github/workflows/ci_set_matrix.py)
+ echo "MATRIX_JSON=$MATRIX_JSON"
+
+ BUILDSYSTEM_TOOLCHAIN=(
+ "cmake arm-clang"
+ "make aarch64-gcc"
+ "make arm-gcc"
+ "make msp430-gcc"
+ "make riscv-gcc"
+ "make rx-gcc"
+ "cmake esp-idf"
+ )
+
+ RESOURCE_LARGE='["nrf", "imxrt"]'
+
+ for e in "${BUILDSYSTEM_TOOLCHAIN[@]}"; do
+ e_arr=($e)
+ build_system="${e_arr[0]}"
+ toolchain="${e_arr[1]}"
+ FAMILY=$(echo $MATRIX_JSON | jq -r ".\"$toolchain\"")
+ echo "FAMILY_${toolchain}=$FAMILY"
+
+ # FAMILY_LARGE = FAMILY - RESOURCE_LARGE
+ # Separate large from medium+ resources
+ FAMILY_LARGE=$(jq -n --argjson family "$FAMILY" --argjson resource "$RESOURCE_LARGE" '$family | map(select(IN($resource[])))')
+ FAMILY=$(jq -n --argjson family "$FAMILY" --argjson resource "$RESOURCE_LARGE" '$family | map(select(IN($resource[]) | not))')
+
+ if [[ $toolchain == esp-idf ]]; then
+ echo " - build-vm:" >> .circleci/config2.yml
+ else
+ echo " - build:" >> .circleci/config2.yml
+ fi
+ echo " matrix:" >> .circleci/config2.yml
+ echo " parameters:" >> .circleci/config2.yml
+ echo " build-system: ['$build_system']" >> .circleci/config2.yml
+ echo " toolchain: ['$toolchain']" >> .circleci/config2.yml
+ echo " family: $FAMILY" >> .circleci/config2.yml
+ #echo " resource_class: ['medium+']" >> .circleci/config2.yml
+
+ # add large resources
+ if [ "$(echo $FAMILY_LARGE | jq 'length')" -gt 0 ]; then
+ echo " - build:" >> .circleci/config2.yml
+ echo " matrix:" >> .circleci/config2.yml
+ echo " parameters:" >> .circleci/config2.yml
+ echo " build-system: ['$build_system']" >> .circleci/config2.yml
+ echo " toolchain: ['$toolchain']" >> .circleci/config2.yml
+ echo " family: $FAMILY_LARGE" >> .circleci/config2.yml
+ echo " resource_class: ['large']" >> .circleci/config2.yml
+ fi
+ done
+
+ - continuation/continue:
+ configuration_path: .circleci/config2.yml
+
+workflows:
+ set-matrix:
+ # Only build PR here, Push will be built by github action.
+ when:
+ and:
+ - not: << pipeline.git.branch.is_default >>
+ jobs:
+ - set-matrix
diff --git a/.circleci/config2.yml b/.circleci/config2.yml
new file mode 100644
index 0000000000..5e73ab456f
--- /dev/null
+++ b/.circleci/config2.yml
@@ -0,0 +1,183 @@
+version: 2.1
+
+commands:
+ setup-toolchain:
+ parameters:
+ toolchain:
+ type: string
+
+ steps:
+ - run:
+ name: Set toolchain url and key
+ command: |
+ TOOLCHAIN_JSON='{
+ "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz",
+ "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64.tar.xz",
+ "arm-gcc": "https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v12.3.1-1.1/xpack-arm-none-eabi-gcc-12.3.1-1.1-linux-x64.tar.gz",
+ "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2",
+ "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz",
+ "rx-gcc": "https://llvm-gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run"
+ }'
+ toolchain_url=$(echo $TOOLCHAIN_JSON | jq -r '.["<< parameters.toolchain >>"]')
+
+ # only cache if not a github link
+ if [[ $toolchain_url != "https://github.com"* ]]; then
+ echo "<< parameters.toolchain >>-$toolchain_url" > toolchain_key
+ fi
+ echo "export toolchain_url=$toolchain_url" >> $BASH_ENV
+
+ - restore_cache:
+ name: Restore Toolchain Cache
+ key: deps-{{ checksum "toolchain_key" }}
+ paths:
+ - ~/cache/<< parameters.toolchain >>
+
+ - run:
+ name: Install Toolchain
+ command: |
+ # download if folder does not exist (not cached)
+ if [ ! -d ~/cache/<< parameters.toolchain >> ]; then
+ mkdir -p ~/cache/<< parameters.toolchain >>
+ wget --progress=dot:giga $toolchain_url -O toolchain.tar.gz
+ if [[ << parameters.toolchain >> == rx-gcc ]]; then
+ mv toolchain.tar.gz toolchain.run
+ chmod +x toolchain.run
+ ./toolchain.run -p ~/cache/<< parameters.toolchain >>/gnurx -y
+ else
+ tar -C ~/cache/<< parameters.toolchain >> -xaf toolchain.tar.gz
+ fi
+ fi
+
+ # Add toolchain to PATH
+ echo "export PATH=$PATH:`echo ~/cache/<< parameters.toolchain >>/*/bin`" >> $BASH_ENV
+
+ - save_cache:
+ name: Save Toolchain Cache
+ key: deps-{{ checksum "toolchain_key" }}
+ paths:
+ - ~/cache/<< parameters.toolchain >>
+
+ build:
+ parameters:
+ build-system:
+ type: string
+ toolchain:
+ type: string
+ family:
+ type: string
+
+ steps:
+ - checkout
+ - run:
+ name: Get Dependencies
+ command: |
+ python tools/get_deps.py << parameters.family >>
+
+ # Install ninja if cmake build system
+ if [ << parameters.build-system >> == "cmake" ]; then
+ NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.12.1/ninja-linux.zip
+ wget $NINJA_URL -O ninja-linux.zip
+ unzip ninja-linux.zip -d ~/bin
+ fi
+
+ # rx-gcc is 32-bit binary
+ if [[ << parameters.toolchain >> == rx-gcc ]]; then
+ sudo dpkg --add-architecture i386
+ sudo apt update
+ sudo apt install libc6:i386 libstdc++6:i386 zlib1g:i386
+ fi
+
+ # Install Pico SDK
+ if [ << parameters.family >> == "rp2040" ]; then
+ git clone --depth 1 https://github.com/raspberrypi/pico-sdk.git ~/pico-sdk
+ echo "export PICO_SDK_PATH=~/pico-sdk" >> $BASH_ENV
+ fi
+
+ - when:
+ condition:
+ not:
+ equal: [esp-idf, << parameters.toolchain >>]
+ steps:
+ - setup-toolchain:
+ toolchain: << parameters.toolchain >>
+
+ - run:
+ name: Build
+ command: |
+ if [ << parameters.toolchain >> == esp-idf ]; then
+ docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.1 python tools/build.py << parameters.family >>
+ else
+ # Toolchain option default is gcc
+ if [ << parameters.toolchain >> == arm-clang ]; then
+ TOOLCHAIN_OPTION="--toolchain clang"
+ elif [ << parameters.toolchain >> == arm-gcc ]; then
+ TOOLCHAIN_OPTION="--toolchain gcc"
+ fi
+
+ python tools/build.py -s << parameters.build-system >> $TOOLCHAIN_OPTION << parameters.family >>
+ fi
+
+jobs:
+ # Build using docker
+ build:
+ parameters:
+ resource_class:
+ type: string
+ default: medium+
+ build-system:
+ type: string
+ toolchain:
+ type: string
+ family:
+ type: string
+
+ docker:
+ - image: cimg/base:current
+ resource_class: << parameters.resource_class >>
+
+ steps:
+ - build:
+ build-system: << parameters.build-system >>
+ toolchain: << parameters.toolchain >>
+ family: << parameters.family >>
+
+ # Build using VM
+ build-vm:
+ parameters:
+ resource_class:
+ type: string
+ default: large
+ build-system:
+ type: string
+ toolchain:
+ type: string
+ family:
+ type: string
+
+ machine:
+ image: ubuntu-2404:current
+ resource_class: << parameters.resource_class >>
+
+ steps:
+ - build:
+ build-system: << parameters.build-system >>
+ toolchain: << parameters.toolchain >>
+ family: << parameters.family >>
+
+workflows:
+ build:
+ jobs:
+# - build:
+# matrix:
+# parameters:
+# toolchain: [ 'arm-gcc' ]
+# build-system: [ 'cmake' ]
+# family: [ 'nrf' ]
+# resource_class: ['large']
+# - build-vm:
+# matrix:
+# parameters:
+# toolchain: ['esp-idf']
+# build-system: ['cmake']
+# family: ['-bespressif_kaluga_1']
+# resource_class: ['large']
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000000..0fd168e5ad
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,66 @@
+# Generated from CLion C/C++ Code Style settings
+BasedOnStyle: LLVM
+AccessModifierOffset: -2
+AlignAfterOpenBracket: Align
+AlignConsecutiveAssignments: None
+AlignOperands: Align
+AllowAllArgumentsOnNextLine: false
+AllowAllConstructorInitializersOnNextLine: false
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortBlocksOnASingleLine: Always
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: All
+AllowShortIfStatementsOnASingleLine: Always
+AllowShortLambdasOnASingleLine: All
+AllowShortLoopsOnASingleLine: true
+AlwaysBreakAfterReturnType: None
+AlwaysBreakTemplateDeclarations: Yes
+BreakBeforeBraces: Custom
+BraceWrapping:
+ AfterCaseLabel: false
+ AfterClass: false
+ AfterControlStatement: Never
+ AfterEnum: false
+ AfterFunction: false
+ AfterNamespace: false
+ AfterUnion: false
+ BeforeCatch: false
+ BeforeElse: false
+ IndentBraces: false
+ SplitEmptyFunction: false
+ SplitEmptyRecord: true
+BreakBeforeBinaryOperators: None
+BreakBeforeTernaryOperators: true
+BreakConstructorInitializers: BeforeColon
+BreakInheritanceList: BeforeColon
+ColumnLimit: 0
+CompactNamespaces: false
+ContinuationIndentWidth: 4
+IndentCaseLabels: true
+IndentPPDirectives: BeforeHash
+IndentWidth: 2
+KeepEmptyLinesAtTheStartOfBlocks: true
+MaxEmptyLinesToKeep: 2
+NamespaceIndentation: All
+ObjCSpaceAfterProperty: false
+ObjCSpaceBeforeProtocolList: true
+PointerAlignment: Right
+ReflowComments: false
+SpaceAfterCStyleCast: true
+SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: false
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeParens: ControlStatements
+SpaceBeforeRangeBasedForLoopColon: false
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 0
+SpacesInAngles: false
+SpacesInCStyleCastParentheses: false
+SpacesInContainerLiterals: true
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+TabWidth: 2
+UseTab: Never
diff --git a/.github/actions/get_deps/action.yml b/.github/actions/get_deps/action.yml
new file mode 100644
index 0000000000..eea241c6cd
--- /dev/null
+++ b/.github/actions/get_deps/action.yml
@@ -0,0 +1,29 @@
+name: Get dependencies
+
+inputs:
+ arg:
+ description: 'Arguments to get_deps.py'
+ required: true
+
+runs:
+ using: "composite"
+ steps:
+ - name: Checkout pico-sdk for rp2040
+ if: contains(inputs.arg, 'rp2040') || contains(inputs.arg, 'raspberry_pi_pico')
+ uses: actions/checkout@v4
+ with:
+ repository: raspberrypi/pico-sdk
+ ref: develop
+ path: pico-sdk
+
+ - name: Linux dependencies
+ if: runner.os == 'Linux'
+ run: |
+ sudo apt install -y ninja-build
+ shell: bash
+
+ - name: Get Dependencies
+ run: |
+ python3 tools/get_deps.py ${{ inputs.arg }}
+ echo "PICO_SDK_PATH=${{ github.workspace }}/pico-sdk" >> $GITHUB_ENV
+ shell: bash
diff --git a/.github/actions/setup_toolchain/action.yml b/.github/actions/setup_toolchain/action.yml
new file mode 100644
index 0000000000..5b9bc95cec
--- /dev/null
+++ b/.github/actions/setup_toolchain/action.yml
@@ -0,0 +1,72 @@
+name: Setup Toolchain
+
+inputs:
+ toolchain:
+ description: 'Toolchain name'
+ required: true
+ toolchain_version:
+ description: 'Toolchain version'
+ required: false
+
+outputs:
+ build_option:
+ description: 'Build option for the toolchain e.g --toolchain clang'
+ value: ${{ steps.set-toolchain-option.outputs.build_option }}
+
+runs:
+ using: "composite"
+ steps:
+ - name: Install ARM GCC
+ if: inputs.toolchain == 'arm-gcc'
+ uses: carlosperate/arm-none-eabi-gcc-action@v1
+ with:
+ release: '12.3.Rel1'
+
+ - name: Pull ESP-IDF docker
+ if: inputs.toolchain == 'esp-idf'
+ uses: ./.github/actions/setup_toolchain/espressif
+ with:
+ toolchain: ${{ inputs.toolchain }}
+ toolchain_version: ${{ inputs.toolchain_version }}
+
+ - name: Get Toolchain URL
+ if: >-
+ inputs.toolchain != 'arm-gcc' &&
+ inputs.toolchain != 'arm-iar' &&
+ inputs.toolchain != 'esp-idf'
+ id: set-toolchain-url
+ run: |
+ TOOLCHAIN_JSON='{
+ "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz",
+ "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64.tar.xz",
+ "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2",
+ "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz",
+ "rx-gcc": "http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run"
+ }'
+ TOOLCHAIN_URL=$(echo $TOOLCHAIN_JSON | jq -r '.["${{ inputs.toolchain }}"]')
+ echo "toolchain_url=$TOOLCHAIN_URL"
+ echo "toolchain_url=$TOOLCHAIN_URL" >> $GITHUB_OUTPUT
+ shell: bash
+
+ - name: Download Toolchain
+ if: >-
+ inputs.toolchain != 'arm-gcc' &&
+ inputs.toolchain != 'arm-iar' &&
+ inputs.toolchain != 'esp-idf'
+ uses: ./.github/actions/setup_toolchain/download
+ with:
+ toolchain: ${{ inputs.toolchain }}
+ toolchain_url: ${{ steps.set-toolchain-url.outputs.toolchain_url }}
+
+ - name: Set toolchain option
+ id: set-toolchain-option
+ run: |
+ BUILD_OPTION=""
+ if [[ "${{ inputs.toolchain }}" == *"clang"* ]]; then
+ BUILD_OPTION="--toolchain clang"
+ elif [[ "${{ inputs.toolchain }}" == "arm-iar" ]]; then
+ BUILD_OPTION="--toolchain iar"
+ fi
+ echo "build_option=$BUILD_OPTION"
+ echo "build_option=$BUILD_OPTION" >> $GITHUB_OUTPUT
+ shell: bash
diff --git a/.github/actions/setup_toolchain/download/action.yml b/.github/actions/setup_toolchain/download/action.yml
new file mode 100644
index 0000000000..8131972082
--- /dev/null
+++ b/.github/actions/setup_toolchain/download/action.yml
@@ -0,0 +1,39 @@
+name: Download Toolchain
+
+inputs:
+ toolchain:
+ description: 'Toolchain name'
+ required: true
+ toolchain_url:
+ description: 'Toolchain URL'
+ required: true
+
+runs:
+ using: "composite"
+ steps:
+ - name: Cache Toolchain
+ if: ${{ !startsWith(inputs.toolchain_url, 'https://github.com') }}
+ uses: actions/cache@v4
+ id: cache-toolchain-download
+ with:
+ path: ~/cache/${{ inputs.toolchain }}
+ key: ${{ runner.os }}-${{ inputs.toolchain }}-${{ inputs.toolchain_url }}
+
+ - name: Install Toolchain
+ if: steps.cache-toolchain-download.outputs.cache-hit != 'true'
+ run: |
+ mkdir -p ~/cache/${{ inputs.toolchain }}
+ wget --progress=dot:giga ${{ inputs.toolchain_url }} -O toolchain.tar.gz
+ if [[ ${{ inputs.toolchain }} == rx-gcc ]]; then
+ mv toolchain.tar.gz toolchain.run
+ chmod +x toolchain.run
+ ./toolchain.run -p ~/cache/${{ inputs.toolchain }}/gnurx -y
+ else
+ tar -C ~/cache/${{ inputs.toolchain }} -xaf toolchain.tar.gz
+ fi
+ shell: bash
+
+ - name: Set Toolchain Path
+ run: |
+ echo >> $GITHUB_PATH `echo ~/cache/${{ inputs.toolchain }}/*/bin`
+ shell: bash
diff --git a/.github/actions/setup_toolchain/espressif/action.yml b/.github/actions/setup_toolchain/espressif/action.yml
new file mode 100644
index 0000000000..1e3ce18f19
--- /dev/null
+++ b/.github/actions/setup_toolchain/espressif/action.yml
@@ -0,0 +1,41 @@
+name: Setup ESP-IDF Toolchain
+
+inputs:
+ toolchain:
+ description: 'Toolchain name'
+ required: true
+ toolchain_version:
+ description: 'Toolchain version'
+ required: true
+
+runs:
+ using: "composite"
+ steps:
+ - name: Set DOCKER_ESP_IDF
+ run: |
+ DOCKER_ESP_IDF=$HOME/cache/${{ inputs.toolchain }}/docker_image.tar
+ echo "DOCKER_ESP_IDF=$DOCKER_ESP_IDF" >> $GITHUB_ENV
+ shell: bash
+
+ - name: Cache Docker Image
+ uses: actions/cache@v4
+ id: cache-toolchain-espressif
+ with:
+ path: ${{ env.DOCKER_ESP_IDF }}
+ key: ${{ inputs.toolchain }}-${{ inputs.toolchain_version }}
+
+ - name: Pull and Save Docker Image
+ if: steps.cache-toolchain-espressif.outputs.cache-hit != 'true'
+ run: |
+ docker pull espressif/idf:${{ inputs.toolchain_version }}
+ mkdir -p $(dirname $DOCKER_ESP_IDF)
+ docker save -o $DOCKER_ESP_IDF espressif/idf:${{ inputs.toolchain_version }}
+ du -sh $DOCKER_ESP_IDF
+ shell: bash
+
+ - name: Load Docker Image
+ if: steps.cache-toolchain-espressif.outputs.cache-hit == 'true'
+ run: |
+ du -sh $DOCKER_ESP_IDF
+ docker load --input $DOCKER_ESP_IDF
+ shell: bash
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 0000000000..8d5bcbc67b
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,140 @@
+name: Build
+
+on:
+ workflow_dispatch:
+ push:
+ paths:
+ - 'src/**'
+ - 'examples/**'
+ - 'lib/**'
+ - 'hw/**'
+ - 'tools/get_deps.py'
+ - 'tools/build.py'
+ - '.github/actions/**'
+ - '.github/workflows/build.yml'
+ - '.github/workflows/build_util.yml'
+ - '.github/workflows/ci_set_matrix.py'
+ pull_request:
+ branches: [ master ]
+ paths:
+ - 'src/**'
+ - 'examples/**'
+ - 'lib/**'
+ - 'hw/**'
+ - 'tools/get_deps.py'
+ - 'tools/build.py'
+ - '.github/actions/**'
+ - '.github/workflows/build.yml'
+ - '.github/workflows/build_util.yml'
+ - '.github/workflows/ci_set_matrix.py'
+concurrency:
+ group: ${{ github.workflow }}-${{ github.ref }}
+ cancel-in-progress: true
+
+jobs:
+ set-matrix:
+ runs-on: ubuntu-latest
+ outputs:
+ json: ${{ steps.set-matrix-json.outputs.matrix }}
+ steps:
+ - name: Checkout TinyUSB
+ uses: actions/checkout@v4
+
+ - name: Generate matrix json
+ id: set-matrix-json
+ run: |
+ MATRIX_JSON=$(python .github/workflows/ci_set_matrix.py)
+ echo "matrix=$MATRIX_JSON"
+ echo "matrix=$MATRIX_JSON" >> $GITHUB_OUTPUT
+
+ # ---------------------------------------
+ # Build CMake
+ # ---------------------------------------
+ cmake:
+ needs: set-matrix
+ uses: ./.github/workflows/build_util.yml
+ strategy:
+ fail-fast: false
+ matrix:
+ toolchain:
+ # - 'arm-clang' is built by circle-ci in PR
+ - 'aarch64-gcc'
+ - 'arm-gcc'
+ - 'msp430-gcc'
+ - 'riscv-gcc'
+ with:
+ build-system: 'cmake'
+ toolchain: ${{ matrix.toolchain }}
+ build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain]) }}
+ one-per-family: ${{ github.event_name == 'push' }}
+
+ # ---------------------------------------
+ # Build Make (built by circle-ci in PR, only build on push here)
+ # ---------------------------------------
+ make:
+ if: github.event_name == 'push'
+ needs: set-matrix
+ uses: ./.github/workflows/build_util.yml
+ strategy:
+ fail-fast: false
+ matrix:
+ toolchain:
+ # 'arm-clang'
+ - 'arm-gcc'
+ - 'aarch64-gcc'
+ - 'msp430-gcc'
+ - 'riscv-gcc'
+ - 'rx-gcc'
+ - 'esp-idf' # build-system is ignored
+ with:
+ build-system: 'make'
+ toolchain: ${{ matrix.toolchain }}
+ build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain]) }}
+ one-per-family: true
+
+ # ---------------------------------------
+ # Build Make on Windows/MacOS
+ # ---------------------------------------
+ make-os:
+ if: github.event_name == 'pull_request'
+ uses: ./.github/workflows/build_util.yml
+ strategy:
+ fail-fast: false
+ matrix:
+ os: [windows-latest, macos-latest]
+ with:
+ os: ${{ matrix.os }}
+ build-system: 'make'
+ toolchain: 'arm-gcc'
+ build-args: '["stm32h7"]'
+ one-per-family: true
+
+ # ---------------------------------------
+ # Build IAR on HFP self-hosted
+ # ---------------------------------------
+ arm-iar:
+ if: github.repository_owner == 'hathach'
+ needs: set-matrix
+ runs-on: [self-hosted, Linux, X64, hifiphile]
+ env:
+ BUILD_ARGS: ${{ join(fromJSON(needs.set-matrix.outputs.json)['arm-iar'], ' ') }}
+ steps:
+ - name: Clean workspace
+ run: |
+ echo "Cleaning up previous run"
+ rm -rf "${{ github.workspace }}"
+ mkdir -p "${{ github.workspace }}"
+
+ - name: Checkout TinyUSB
+ uses: actions/checkout@v4
+
+ - name: Get Dependencies
+ run: python3 tools/get_deps.py $BUILD_ARGS
+
+ - name: Build
+ run: python3 tools/build.py --one-per-family --toolchain iar $BUILD_ARGS
+
+ - name: Test on actual hardware (hardware in the loop)
+ if: github.event_name == 'pull_request'
+ run: |
+ python3 test/hil/hil_test.py hfp.json
diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
deleted file mode 100644
index 2376924989..0000000000
--- a/.github/workflows/build_aarch64.yml
+++ /dev/null
@@ -1,70 +0,0 @@
-name: Build AArch64
-
-on:
- workflow_dispatch:
- push:
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - '.github/workflows/build_aarch64.yml'
- pull_request:
- branches: [ master ]
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - '.github/workflows/build_aarch64.yml'
-
-concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
- cancel-in-progress: true
-
-jobs:
- # ---------------------------------------
- # Build AARCH64 family
- # ---------------------------------------
- build-arm:
- runs-on: ubuntu-latest
- strategy:
- fail-fast: false
- matrix:
- family:
- # Alphabetical order
- - 'broadcom_64bit'
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Set Toolchain URL
- run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
-
- - name: Cache Toolchain
- uses: actions/cache@v4
- id: cache-toolchain
- with:
- path: ~/cache/
- key: ${{ runner.os }}-21-11-02-${{ env.TOOLCHAIN_URL }}
-
- - name: Install Toolchain
- if: steps.cache-toolchain.outputs.cache-hit != 'true'
- run: |
- mkdir -p ~/cache/toolchain
- wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
- tar -C ~/cache/toolchain -xaf toolchain.tar.gz
-
- - name: Set Toolchain Path
- run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
- - name: Get Dependencies
- run: python3 tools/get_deps.py ${{ matrix.family }}
-
- - name: Build
- run: python3 tools/build_make.py ${{ matrix.family }}
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
deleted file mode 100644
index 12e6615ea9..0000000000
--- a/.github/workflows/build_arm.yml
+++ /dev/null
@@ -1,64 +0,0 @@
-name: Build ARM
-
-on:
- workflow_dispatch:
- push:
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'tools/get_deps.py'
- - '.github/workflows/build_arm.yml'
- pull_request:
- branches: [ master ]
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'tools/get_deps.py'
- - '.github/workflows/build_arm.yml'
-
-concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
- cancel-in-progress: true
-
-jobs:
- # ---------------------------------------
- # Build ARM family
- # ---------------------------------------
- build-arm:
- runs-on: ubuntu-latest
- strategy:
- fail-fast: false
- matrix:
- family:
- # Alphabetical order
- - 'broadcom_32bit'
- - 'kinetis_k32l2'
- - 'lpc11 lpc13 lpc15'
- - 'lpc51'
- - 'mm32 msp432e4'
- - 'samd11 same5x saml2x'
- - 'stm32l0 stm32wb'
- - 'tm4c123 xmc4000'
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Install ARM GCC
- uses: carlosperate/arm-none-eabi-gcc-action@v1
- with:
- release: '11.2-2022.02'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Get Dependencies
- run: python3 tools/get_deps.py ${{ matrix.family }}
-
- - name: Build
- run: python3 tools/build_make.py ${{ matrix.family }}
diff --git a/.github/workflows/build_cmake.yml b/.github/workflows/build_cmake.yml
deleted file mode 100644
index 65de47e8dd..0000000000
--- a/.github/workflows/build_cmake.yml
+++ /dev/null
@@ -1,292 +0,0 @@
-name: Build CMake
-
-on:
- workflow_dispatch:
- push:
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'test/hil/**'
- - 'tools/get_deps.py'
- - '.github/workflows/build_cmake.yml'
- pull_request:
- branches: [ master ]
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'test/hil/**'
- - 'tools/get_deps.py'
- - '.github/workflows/build_cmake.yml'
-
-concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
- cancel-in-progress: true
-
-jobs:
- # ---------------------------------------
- # Build ARM with GCC
- # ---------------------------------------
- arm-gcc:
- runs-on: ubuntu-latest
- strategy:
- fail-fast: false
- matrix:
- family:
- # Alphabetical order
- - 'imxrt'
- - 'kinetis_k kinetis_kl'
- - 'lpc17 lpc18 lpc40 lpc43'
- - 'lpc54 lpc55'
- - 'mcx'
- - 'nrf'
- - 'ra'
- - 'rp2040'
- - 'samd21'
- - 'samd51'
- - 'stm32f0'
- - 'stm32f1'
- - 'stm32f2'
- - 'stm32f3'
- - 'stm32f4'
- - 'stm32f7'
- - 'stm32g0'
- - 'stm32g4'
- - 'stm32h5'
- - 'stm32h7'
- - 'stm32l4'
- - 'stm32u5'
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Install ARM GCC
- uses: carlosperate/arm-none-eabi-gcc-action@v1
- with:
- release: '12.3.Rel1'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Checkout pico-sdk for rp2040
- if: matrix.family == 'rp2040'
- uses: actions/checkout@v4
- with:
- repository: raspberrypi/pico-sdk
- ref: develop
- path: pico-sdk
-
- - name: Get Dependencies
- run: |
- sudo apt install -y ninja-build
- python3 tools/get_deps.py ${{ matrix.family }}
-
- - name: Build
- run: python tools/build_cmake.py ${{ matrix.family }} -DCMAKE_BUILD_TYPE=MinSizeRel
- env:
- PICO_SDK_PATH: ${{ github.workspace }}/pico-sdk
-
- - name: Upload Artifacts for Hardware Testing (rp2040)
- if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
- uses: actions/upload-artifact@v4
- with:
- name: raspberry_pi_pico
- path: |
- cmake-build/cmake-build-raspberry_pi_pico/*/*/*.elf
-
- - name: Upload Artifacts for Hardware Testing (nRF)
- if: matrix.family == 'nrf' && github.repository_owner == 'hathach'
- uses: actions/upload-artifact@v4
- with:
- name: feather_nrf52840_express
- path: |
- cmake-build/cmake-build-feather_nrf52840_express/*/*/*.elf
-
- - name: Upload Artifacts for Hardware Testing (samd51)
- if: matrix.family == 'samd51' && github.repository_owner == 'hathach'
- uses: actions/upload-artifact@v4
- with:
- name: itsybitsy_m4
- path: |
- cmake-build/cmake-build-itsybitsy_m4/*/*/*.bin
-
- # ---------------------------------------
- # Build ARM with Clang
- # ---------------------------------------
- arm-clang:
- runs-on: ubuntu-latest
- strategy:
- fail-fast: false
- matrix:
- family:
- # Alphabetical order
- - 'imxrt'
- - 'kinetis_k kinetis_kl'
- - 'lpc17 lpc18 lpc40 lpc43'
- - 'lpc54 lpc55'
- #- 'mcx' not working with gcc anymore, need to fix this first
- - 'nrf'
- #- 'ra' port later
- #- 'rp2040' port later
- - 'samd21'
- - 'samd51'
- - 'stm32f0'
- - 'stm32f1'
- - 'stm32f2'
- - 'stm32f3'
- - 'stm32f4'
- - 'stm32f7'
- - 'stm32g0'
- - 'stm32g4'
- - 'stm32h5'
- - 'stm32h7'
- - 'stm32l4'
- - 'stm32u5'
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Checkout pico-sdk for rp2040
- if: matrix.family == 'rp2040'
- uses: actions/checkout@v4
- with:
- repository: raspberrypi/pico-sdk
- ref: develop
- path: pico-sdk
-
- - name: Set Toolchain URL
- run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64.tar.xz
-
- - name: Cache Toolchain
- uses: actions/cache@v4
- id: cache-toolchain
- with:
- path: ~/cache/
- key: ${{ runner.os }}-24-04-17-${{ env.TOOLCHAIN_URL }}
-
- - name: Install Toolchain
- if: steps.cache-toolchain.outputs.cache-hit != 'true'
- run: |
- mkdir -p ~/cache/toolchain
- wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.xz
- tar -C ~/cache/toolchain -xaf toolchain.tar.xz
-
- - name: Prepare to build
- run: |
- echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
- sudo apt install -y ninja-build
- python3 tools/get_deps.py ${{ matrix.family }}
-
- - name: Build
- run: python tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=clang -DCMAKE_BUILD_TYPE=MinSizeRel
- env:
- PICO_SDK_PATH: ${{ github.workspace }}/pico-sdk
-
- # ---------------------------------------
- # Build MSP430 with GCC
- # ---------------------------------------
- msp430-gcc:
- runs-on: ubuntu-latest
- strategy:
- fail-fast: false
- matrix:
- family:
- # Alphabetical order
- - 'msp430'
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Set Toolchain URL
- run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2
-
- - name: Cache Toolchain
- uses: actions/cache@v4
- id: cache-toolchain
- with:
- path: ~/cache/
- key: ${{ runner.os }}-24-04-17-${{ env.TOOLCHAIN_URL }}
-
- - name: Install Toolchain
- if: steps.cache-toolchain.outputs.cache-hit != 'true'
- run: |
- mkdir -p ~/cache/toolchain
- wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.bz2
- tar -C ~/cache/toolchain -xaf toolchain.tar.bz2
-
- - name: Prepare to build
- run: |
- echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
- sudo apt install -y ninja-build
- python3 tools/get_deps.py ${{ matrix.family }}
-
- - name: Build
- run: python tools/build_cmake.py ${{ matrix.family }} -DCMAKE_BUILD_TYPE=MinSizeRel
-
- # ---------------------------------------
- # Hardware in the loop (HIL)
- # Current self-hosted instance is running on an RPI4. For attached hardware checkout hil_pi4.json
- # ---------------------------------------
- hil-test:
- # run only with hathach's commit due to limited resource on RPI4
- if: github.repository_owner == 'hathach'
- needs: arm-gcc
- runs-on: [self-hosted, rp2040, nrf52840, hardware-in-the-loop]
- strategy:
- fail-fast: false
- matrix:
- board:
- - 'feather_nrf52840_express'
- - 'itsybitsy_m4'
- - 'raspberry_pi_pico'
- steps:
- - name: Clean workspace
- run: |
- echo "Cleaning up previous run"
- rm -rf "${{ github.workspace }}"
- mkdir -p "${{ github.workspace }}"
-
- # USB bus on rpi4 is not stable, reset it before testing
- - name: Reset USB bus
- run: |
- lsusb
- lsusb -t
- # reset VIA Labs 2.0 hub
- sudo usbreset 001/002
-
- # legacy code
- #for port in $(lspci | grep USB | cut -d' ' -f1); do
- # echo -n "0000:${port}"| sudo tee /sys/bus/pci/drivers/xhci_hcd/unbind;
- # sleep 0.1;
- # echo -n "0000:${port}" | sudo tee /sys/bus/pci/drivers/xhci_hcd/bind;
- #done
-
- - name: Checkout test/hil
- uses: actions/checkout@v4
- with:
- sparse-checkout: test/hil
-
- - name: Download Artifacts
- uses: actions/download-artifact@v4
- with:
- name: ${{ matrix.board }}
- path: cmake-build/cmake-build-${{ matrix.board }}
-
- - name: Test on actual hardware
- run: |
- python3 test/hil/hil_test.py --board ${{ matrix.board }} hil_pi4.json
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
deleted file mode 100644
index 4108a58a59..0000000000
--- a/.github/workflows/build_esp.yml
+++ /dev/null
@@ -1,114 +0,0 @@
-name: Build ESP
-
-on:
- workflow_dispatch:
- push:
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'test/hil/**'
- - '.github/workflows/build_esp.yml'
- pull_request:
- branches: [ master ]
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'test/hil/**'
- - '.github/workflows/build_esp.yml'
-
-concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
- cancel-in-progress: true
-
-jobs:
- build-esp:
- runs-on: ubuntu-latest
- strategy:
- fail-fast: false
- matrix:
- board:
- # ESP32-S2
- - 'espressif_kaluga_1'
- # ESP32-S3
- - 'espressif_s3_devkitm'
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Pull ESP-IDF docker
- run: docker pull espressif/idf:latest
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Build
- run: docker run --rm -v $PWD:/project -w /project espressif/idf:v5.1.1 python3 tools/build_esp32.py ${{ matrix.board }}
-
- - name: Upload Artifacts for Hardware Testing
- if: matrix.board == 'espressif_s3_devkitm' && github.repository_owner == 'hathach'
- uses: actions/upload-artifact@v4
- with:
- name: ${{ matrix.board }}
- path: |
- cmake-build/cmake-build-${{ matrix.board }}/*/*/bootloader/bootloader.bin
- cmake-build/cmake-build-${{ matrix.board }}/*/*/*.bin
- cmake-build/cmake-build-${{ matrix.board }}/*/*/partition_table/partition-table.bin
- cmake-build/cmake-build-${{ matrix.board }}/*/*/config.env
- cmake-build/cmake-build-${{ matrix.board }}/*/*/flash_args
-
- # ---------------------------------------
- # Hardware in the loop (HIL)
- # Current self-hosted instance is running on an RPI4. For attached hardware checkout hil_pi4.json
- # ---------------------------------------
- hil-test:
- # run only with hathach's commit due to limited resource on RPI4
- if: github.repository_owner == 'hathach'
- needs: build-esp
- runs-on: [self-hosted, esp32s3, hardware-in-the-loop]
- strategy:
- fail-fast: false
- matrix:
- board:
- - 'espressif_s3_devkitm'
- steps:
- - name: Clean workspace
- run: |
- echo "Cleaning up previous run"
- rm -rf "${{ github.workspace }}"
- mkdir -p "${{ github.workspace }}"
-
- # USB bus on rpi4 is not stable, reset it before testing
- - name: Reset USB bus
- run: |
- lsusb
- lsusb -t
- # reset VIA Labs 2.0 hub
- sudo usbreset 001/002
-
- # legacy code
- #for port in $(lspci | grep USB | cut -d' ' -f1); do
- # echo -n "0000:${port}"| sudo tee /sys/bus/pci/drivers/xhci_hcd/unbind;
- # sleep 0.1;
- # echo -n "0000:${port}" | sudo tee /sys/bus/pci/drivers/xhci_hcd/bind;
- #done
-
- - name: Checkout test/hil
- uses: actions/checkout@v4
- with:
- sparse-checkout: test/hil
-
- - name: Download Artifacts
- uses: actions/download-artifact@v4
- with:
- name: ${{ matrix.board }}
- path: cmake-build/cmake-build-${{ matrix.board }}
-
- - name: Test on actual hardware
- run: |
- python3 test/hil/hil_test.py --board ${{ matrix.board }} hil_pi4.json
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
deleted file mode 100644
index 4993499048..0000000000
--- a/.github/workflows/build_iar.yml
+++ /dev/null
@@ -1,59 +0,0 @@
-name: Build IAR
-
-on:
- workflow_dispatch:
- push:
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'tools/get_deps.py'
- - 'test/hil/**'
- - '.github/workflows/build_iar.yml'
- pull_request:
- branches: [ master ]
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'tools/get_deps.py'
- - 'test/hil/**'
- - '.github/workflows/build_iar.yml'
-
-concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
- cancel-in-progress: true
-
-jobs:
- cmake:
- if: github.repository_owner == 'hathach'
- runs-on: [self-hosted, Linux, X64, hifiphile]
- strategy:
- fail-fast: false
- matrix:
- family:
- # Alphabetical order
- # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
- # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
- - 'lpc43 stm32f0 stm32f1 stm32f7 stm32g0 stm32g4 stm32l4'
- steps:
- - name: Clean workspace
- run: |
- echo "Cleaning up previous run"
- rm -rf "${{ github.workspace }}"
- mkdir -p "${{ github.workspace }}"
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Get Dependencies
- run: python3 tools/get_deps.py ${{ matrix.family }}
-
- - name: Build
- run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iar -DCMAKE_BUILD_TYPE=MinSizeRel
-
- - name: Test on actual hardware (hardware in the loop)
- run: |
- python3 test/hil/hil_test.py hil_hfp.json
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
deleted file mode 100644
index fbc12d2858..0000000000
--- a/.github/workflows/build_renesas.yml
+++ /dev/null
@@ -1,70 +0,0 @@
-name: Build Renesas
-
-on:
- workflow_dispatch:
- push:
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'tools/get_deps.py'
- - '.github/workflows/build_renesas.yml'
- pull_request:
- branches: [ master ]
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'tools/get_deps.py'
- - '.github/workflows/build_renesas.yml'
-
-concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
- cancel-in-progress: true
-
-jobs:
- build-rx:
- runs-on: ubuntu-latest
- strategy:
- fail-fast: false
- matrix:
- family:
- # Alphabetical order
- - 'rx'
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Set Toolchain URL
- run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run
-
- - name: Cache Toolchain
- uses: actions/cache@v4
- id: cache-toolchain
- with:
- path: ~/cache/
- key: ${{ runner.os }}-21-03-30-${{ env.TOOLCHAIN_URL }}
-
- - name: Install Toolchain
- if: steps.cache-toolchain.outputs.cache-hit != 'true'
- run: |
- mkdir -p ~/cache/toolchain/gnurx
- wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.run
- chmod +x toolchain.run
- ./toolchain.run -p ~/cache/toolchain/gnurx -y
-
- - name: Set Toolchain Path
- run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
- - name: Get Dependencies
- run: python3 tools/get_deps.py ${{ matrix.family }}
-
- - name: Build
- run: python3 tools/build_make.py ${{ matrix.family }}
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
deleted file mode 100644
index 7f5031ff12..0000000000
--- a/.github/workflows/build_riscv.yml
+++ /dev/null
@@ -1,71 +0,0 @@
-name: Build RISC-V
-
-on:
- workflow_dispatch:
- push:
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'tools/get_deps.py'
- - '.github/workflows/build_riscv.yml'
- pull_request:
- branches: [ master ]
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - 'tools/get_deps.py'
- - '.github/workflows/build_riscv.yml'
-
-concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
- cancel-in-progress: true
-
-jobs:
- build-riscv:
- runs-on: ubuntu-latest
- strategy:
- fail-fast: false
- matrix:
- family:
- # Alphabetical order
- - 'ch32v307'
- - 'fomu'
- - 'gd32vf103'
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Set Toolchain URL
- run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v10.1.0-1.1/xpack-riscv-none-embed-gcc-10.1.0-1.1-linux-x64.tar.gz
-
- - name: Cache Toolchain
- uses: actions/cache@v4
- id: cache-toolchain
- with:
- path: ~/cache/
- key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
-
- - name: Install Toolchain
- if: steps.cache-toolchain.outputs.cache-hit != 'true'
- run: |
- mkdir -p ~/cache/toolchain
- wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
- tar -C ~/cache/toolchain -xaf toolchain.tar.gz
-
- - name: Set Toolchain Path
- run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
- - name: Get Dependencies
- run: python3 tools/get_deps.py ${{ matrix.family }}
-
- - name: Build
- run: python3 tools/build_make.py ${{ matrix.family }}
diff --git a/.github/workflows/build_util.yml b/.github/workflows/build_util.yml
new file mode 100644
index 0000000000..706ded1c14
--- /dev/null
+++ b/.github/workflows/build_util.yml
@@ -0,0 +1,82 @@
+name: Reusable build util
+
+on:
+ workflow_call:
+ inputs:
+ build-system:
+ required: true
+ type: string
+ toolchain:
+ required: true
+ type: string
+ build-args:
+ required: true
+ type: string
+ one-per-family:
+ required: false
+ default: false
+ type: boolean
+ upload-artifacts:
+ required: false
+ default: false
+ type: boolean
+ os:
+ required: false
+ type: string
+ default: 'ubuntu-latest'
+
+jobs:
+ family:
+ runs-on: ${{ inputs.os }}
+ strategy:
+ fail-fast: false
+ matrix:
+ arg: ${{ fromJSON(inputs.build-args) }}
+ steps:
+ - name: Checkout TinyUSB
+ uses: actions/checkout@v4
+
+ - name: Setup Toolchain
+ id: setup-toolchain
+ uses: ./.github/actions/setup_toolchain
+ with:
+ toolchain: ${{ inputs.toolchain }}
+ toolchain_version: 'v5.3.1'
+
+ - name: Get Dependencies
+ uses: ./.github/actions/get_deps
+ with:
+ arg: ${{ matrix.arg }}
+
+ - name: Set build one-per-family option
+ id: set-one-per-family
+ run: |
+ if [[ "${{ inputs.one-per-family }}" == "true" ]]; then
+ BUILD_OPTION="--one-per-family"
+ fi
+ echo "build_option=$BUILD_OPTION"
+ echo "build_option=$BUILD_OPTION" >> $GITHUB_OUTPUT
+ shell: bash
+
+ - name: Build
+ run: |
+ if [ "${{ inputs.toolchain }}" == "esp-idf" ]; then
+ docker run --rm -v $PWD:/project -w /project espressif/idf:v5.3.1 python tools/build.py ${{ matrix.arg }}
+ else
+ python tools/build.py -s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ steps.set-one-per-family.outputs.build_option }} ${{ matrix.arg }}
+ fi
+ shell: bash
+
+ - name: Upload Artifacts for Hardware Testing
+ if: ${{ inputs.upload-artifacts }}
+ uses: actions/upload-artifact@v4
+ with:
+ name: ${{ matrix.arg }}
+ path: |
+ cmake-build/cmake-build-*/*/*/*.elf
+ cmake-build/cmake-build-*/*/*/*.bin
+ cmake-build/cmake-build-*/*/*/*.bin
+ cmake-build/cmake-build-*/*/*/bootloader/bootloader.bin
+ cmake-build/cmake-build-*/*/*/partition_table/partition-table.bin
+ cmake-build/cmake-build-*/*/*/config.env
+ cmake-build/cmake-build-*/*/*/flash_args
diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
deleted file mode 100644
index b33b5b593c..0000000000
--- a/.github/workflows/build_win_mac.yml
+++ /dev/null
@@ -1,54 +0,0 @@
-name: Build Windows/MacOS
-
-on:
- workflow_dispatch:
- push:
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - '.github/workflows/build_win_mac.yml'
- pull_request:
- branches: [ master ]
- paths:
- - 'src/**'
- - 'examples/**'
- - 'lib/**'
- - 'hw/**'
- - '.github/workflows/build_win_mac.yml'
-
-concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
- cancel-in-progress: true
-
-jobs:
- # ---------------------------------------
- # Build ARM family
- # ---------------------------------------
- build-arm:
- strategy:
- fail-fast: false
- matrix:
- os: [windows-latest, macos-latest]
- runs-on: ${{ matrix.os }}
-
- steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- - name: Install ARM GCC
- uses: carlosperate/arm-none-eabi-gcc-action@v1
- with:
- release: '10.3-2021.10'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v4
-
- - name: Get Dependencies
- run: python3 tools/get_deps.py stm32f4
-
- - name: Build
- run: python3 tools/build_make.py stm32f4 stm32f411disco
diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py
new file mode 100755
index 0000000000..705dcac94c
--- /dev/null
+++ b/.github/workflows/ci_set_matrix.py
@@ -0,0 +1,72 @@
+#!/usr/bin/env python3
+import json
+
+# toolchain, url
+toolchain_list = [
+ "aarch64-gcc",
+ "arm-clang",
+ "arm-iar",
+ "arm-gcc",
+ "esp-idf",
+ "msp430-gcc",
+ "riscv-gcc",
+ "rx-gcc"
+]
+
+# family: [supported toolchain]
+family_list = {
+ "broadcom_32bit": ["arm-gcc"],
+ "broadcom_64bit": ["aarch64-gcc"],
+ "ch32v10x ch32v20x ch32v307 fomu gd32vf103": ["riscv-gcc"],
+ "da1469x": ["arm-gcc"],
+ "imxrt": ["arm-gcc", "arm-clang"],
+ "kinetis_k kinetis_kl kinetis_k32l2": ["arm-gcc", "arm-clang"],
+ "lpc11 lpc13 lpc15": ["arm-gcc", "arm-clang"],
+ "lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"],
+ "lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"],
+ "max32650 max32666 max32690 max78002": ["arm-gcc"],
+ "mcx": ["arm-gcc"],
+ "mm32": ["arm-gcc"],
+ "msp430": ["msp430-gcc"],
+ "msp432e4 tm4c": ["arm-gcc"],
+ "nrf": ["arm-gcc", "arm-clang"],
+ "ra": ["arm-gcc"],
+ "rp2040": ["arm-gcc"],
+ "rx": ["rx-gcc"],
+ "samd11 saml2x": ["arm-gcc", "arm-clang"],
+ "samd21": ["arm-gcc", "arm-clang"],
+ "samd5x_e5x samg": ["arm-gcc", "arm-clang"],
+ "stm32f0 stm32f1 stm32f2 stm32f3": ["arm-gcc", "arm-clang", "arm-iar"],
+ "stm32f4": ["arm-gcc", "arm-clang", "arm-iar"],
+ "stm32f7": ["arm-gcc", "arm-clang", "arm-iar"],
+ "stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"],
+ "stm32h7": ["arm-gcc", "arm-clang", "arm-iar"],
+ "stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"],
+ "stm32u5 stm32wb": ["arm-gcc", "arm-clang", "arm-iar"],
+ "xmc4000": ["arm-gcc"],
+ "-bespressif_kaluga_1": ["esp-idf"],
+ "-bespressif_s3_devkitm": ["esp-idf"],
+ "-bespressif_p4_function_ev": ["esp-idf"],
+}
+
+
+def set_matrix_json():
+ matrix = {}
+ for toolchain in toolchain_list:
+ filtered_families = [family for family, supported_toolchain in family_list.items() if
+ toolchain in supported_toolchain]
+
+ # always add board in hfp.json for arm-iar
+ if toolchain == 'arm-iar':
+ with open('test/hil/hfp.json') as f:
+ hfp_data = json.load(f)
+ hfp_boards = [f"-b{board['name']}" for board in hfp_data['boards']]
+ filtered_families = filtered_families + hfp_boards
+
+ matrix[toolchain] = filtered_families
+
+ print(json.dumps(matrix))
+
+
+if __name__ == '__main__':
+ set_matrix_json()
diff --git a/.github/workflows/cifuzz.yml b/.github/workflows/cifuzz.yml
index 5dc0f27644..d7f1fc0667 100644
--- a/.github/workflows/cifuzz.yml
+++ b/.github/workflows/cifuzz.yml
@@ -20,12 +20,14 @@ jobs:
with:
oss-fuzz-project-name: 'tinyusb'
language: c++
+
- name: Run Fuzzers
uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master
with:
oss-fuzz-project-name: 'tinyusb'
language: c++
- fuzz-seconds: 600
+ fuzz-seconds: 400
+
- name: Upload Crash
uses: actions/upload-artifact@v4
if: failure() && steps.build.outcome == 'success'
diff --git a/.github/workflows/codeql-buildscript.sh b/.github/workflows/codeql-buildscript.sh
index 35e0299227..272b55d228 100644
--- a/.github/workflows/codeql-buildscript.sh
+++ b/.github/workflows/codeql-buildscript.sh
@@ -1,5 +1,6 @@
#!/usr/bin/env bash
FAMILY=stm32l4
+pip install click
python3 tools/get_deps.py $FAMILY
-python3 tools/build_make.py $FAMILY
+python3 tools/build.py -s make $FAMILY
diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml
index 1f7b60b9c1..be4c2dd872 100644
--- a/.github/workflows/codeql.yml
+++ b/.github/workflows/codeql.yml
@@ -59,10 +59,10 @@ jobs:
- name: Checkout repository
uses: actions/checkout@v4
- - name: Install ARM GCC
- uses: carlosperate/arm-none-eabi-gcc-action@v1
+ - name: Setup Toolchain
+ uses: ./.github/actions/setup_toolchain
with:
- release: '11.2-2022.02'
+ toolchain: 'arm-gcc'
# Initializes the CodeQL tools for scanning.
- name: Initialize CodeQL
diff --git a/.github/workflows/hil_test.yml b/.github/workflows/hil_test.yml
new file mode 100644
index 0000000000..c6e7f33b0b
--- /dev/null
+++ b/.github/workflows/hil_test.yml
@@ -0,0 +1,88 @@
+name: Hardware Test
+
+on:
+ workflow_dispatch:
+ pull_request:
+ branches: [ master ]
+ paths:
+ - 'src/**'
+ - 'examples/**'
+ - 'lib/**'
+ - 'hw/**'
+ - 'test/hil/**'
+ - 'tools/get_deps.py'
+ - '.github/actions/**'
+ - '.github/workflows/hil_test.yml'
+concurrency:
+ group: ${{ github.workflow }}-${{ github.ref }}
+ cancel-in-progress: true
+
+env:
+ HIL_JSON: test/hil/tinyusb.json
+
+jobs:
+ set-matrix:
+ runs-on: ubuntu-latest
+ outputs:
+ json: ${{ steps.set-matrix-json.outputs.matrix }}
+ steps:
+ - name: Checkout TinyUSB
+ uses: actions/checkout@v4
+
+ - name: Generate matrix json
+ id: set-matrix-json
+ run: |
+ MATRIX_JSON=$(python test/hil/hil_ci_set_matrix.py ${{ env.HIL_JSON }})
+ echo "matrix=$MATRIX_JSON"
+ echo "matrix=$MATRIX_JSON" >> $GITHUB_OUTPUT
+
+ # ---------------------------------------
+ # Build arm-gcc
+ # ---------------------------------------
+ build:
+ if: github.repository_owner == 'hathach'
+ needs: set-matrix
+ uses: ./.github/workflows/build_util.yml
+ strategy:
+ fail-fast: false
+ matrix:
+ toolchain:
+ - 'arm-gcc'
+ - 'esp-idf'
+ with:
+ build-system: 'cmake'
+ toolchain: ${{ matrix.toolchain }}
+ build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain]) }}
+ one-per-family: true
+ upload-artifacts: true
+
+ # ---------------------------------------
+ # Hardware in the loop (HIL)
+ # self-hosted running on an VM. For attached hardware checkout HIL_JSON
+ # ---------------------------------------
+ hil-tinyusb:
+ if: github.repository_owner == 'hathach'
+ needs: build
+ runs-on: [self-hosted, X64, hathach, hardware-in-the-loop]
+ steps:
+ - name: Clean workspace
+ run: |
+ echo "Cleaning up previous run"
+ rm -rf "${{ github.workspace }}"
+ mkdir -p "${{ github.workspace }}"
+
+ - name: Checkout TinyUSB
+ uses: actions/checkout@v4
+ with:
+ sparse-checkout: test/hil
+
+ - name: Download Artifacts
+ uses: actions/download-artifact@v4
+ with:
+ path: cmake-build
+ merge-multiple: true
+
+ - name: Test on actual hardware
+ run: |
+ ls cmake-build/
+ python3 test/hil/hil_test.py ${{ env.HIL_JSON }}
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index e36259daae..530484079e 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -7,18 +7,13 @@ on:
branches: [ master ]
concurrency:
- group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+ group: ${{ github.workflow }}-${{ github.ref }}
cancel-in-progress: true
jobs:
pre-commit:
runs-on: ubuntu-latest
steps:
- - name: Setup Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.x'
-
- name: Setup Ruby
uses: ruby/setup-ruby@v1
with:
@@ -34,7 +29,7 @@ jobs:
#ceedling test:all
- name: Run pre-commit
- uses: pre-commit/action@v3.0.0
+ uses: pre-commit/action@v3.0.1
- name: Build Fuzzer
run: |
diff --git a/.gitignore b/.gitignore
index e6ccec736e..309d7466af 100644
--- a/.gitignore
+++ b/.gitignore
@@ -31,59 +31,6 @@ cov-int
__pycache__
cmake-build-*
sdkconfig
-
-# submodules
-hw/mcu/allwinner
-hw/mcu/bridgetek/ft9xx/ft90x-sdk
-hw/mcu/broadcom
-hw/mcu/gd/nuclei-sdk
-hw/mcu/infineon/mtb-xmclib-cat3
-hw/mcu/microchip
-hw/mcu/mindmotion/mm32sdk
-hw/mcu/nordic/nrfx
-hw/mcu/nuvoton
-hw/mcu/nxp/lpcopen
-hw/mcu/nxp/mcux-sdk
-hw/mcu/nxp/nxp_sdk
-hw/mcu/raspberry_pi/Pico-PIO-USB
-hw/mcu/renesas/rx
-hw/mcu/silabs/cmsis-dfp-efm32gg12b
-hw/mcu/sony/cxd56/spresense-exported-sdk
-hw/mcu/st/cmsis_device_f0
-hw/mcu/st/cmsis_device_f1
-hw/mcu/st/cmsis_device_f2
-hw/mcu/st/cmsis_device_f3
-hw/mcu/st/cmsis_device_f4
-hw/mcu/st/cmsis_device_f7
-hw/mcu/st/cmsis_device_g0
-hw/mcu/st/cmsis_device_g4
-hw/mcu/st/cmsis_device_h7
-hw/mcu/st/cmsis_device_l0
-hw/mcu/st/cmsis_device_l1
-hw/mcu/st/cmsis_device_l4
-hw/mcu/st/cmsis_device_l5
-hw/mcu/st/cmsis_device_u5
-hw/mcu/st/cmsis_device_wb
-hw/mcu/st/stm32f0xx_hal_driver
-hw/mcu/st/stm32f1xx_hal_driver
-hw/mcu/st/stm32f2xx_hal_driver
-hw/mcu/st/stm32f3xx_hal_driver
-hw/mcu/st/stm32f4xx_hal_driver
-hw/mcu/st/stm32f7xx_hal_driver
-hw/mcu/st/stm32g0xx_hal_driver
-hw/mcu/st/stm32g4xx_hal_driver
-hw/mcu/st/stm32h7xx_hal_driver
-hw/mcu/st/stm32l0xx_hal_driver
-hw/mcu/st/stm32l1xx_hal_driver
-hw/mcu/st/stm32l4xx_hal_driver
-hw/mcu/st/stm32l5xx_hal_driver
-hw/mcu/st/stm32u5xx_hal_driver
-hw/mcu/st/stm32wbxx_hal_driver
-hw/mcu/ti
-hw/mcu/wch/ch32v307
-hw/mcu/wch/ch32f20x
-lib/CMSIS_5
-lib/FreeRTOS-Kernel
-lib/lwip
-lib/sct_neopixel
-tools/uf2
+.PVS-Studio
+.vscode/
+build/
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 22199b103e..05dceda5a5 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,93 +2,153 @@
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
-
+
-
+
-
+
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/k64f.xml b/.idea/runConfigurations/k64f.xml
new file mode 100644
index 0000000000..80ca22d400
--- /dev/null
+++ b/.idea/runConfigurations/k64f.xml
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra2a1.xml b/.idea/runConfigurations/ra2a1.xml
new file mode 100644
index 0000000000..cb87de5bd3
--- /dev/null
+++ b/.idea/runConfigurations/ra2a1.xml
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/rp2040.xml b/.idea/runConfigurations/rp2040.xml
index 51ab7b5ccd..da5a8f1ee8 100644
--- a/.idea/runConfigurations/rp2040.xml
+++ b/.idea/runConfigurations/rp2040.xml
@@ -1,5 +1,5 @@
-
+
diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml
index 628f7910de..2d94e66d65 100644
--- a/.idea/runConfigurations/stlink.xml
+++ b/.idea/runConfigurations/stlink.xml
@@ -1,6 +1,6 @@
-
-
+
+
diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml
index 6d65e83c78..c3b5c9953d 100644
--- a/.idea/runConfigurations/stm32g474.xml
+++ b/.idea/runConfigurations/stm32g474.xml
@@ -1,7 +1,8 @@
-
-
+
+
+
diff --git a/.idea/runConfigurations/stm32h563.xml b/.idea/runConfigurations/stm32h563.xml
new file mode 100644
index 0000000000..7a72e53cb0
--- /dev/null
+++ b/.idea/runConfigurations/stm32h563.xml
@@ -0,0 +1,11 @@
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/stm32h743.xml b/.idea/runConfigurations/stm32h743.xml
index aeaf9fb533..618f136b34 100644
--- a/.idea/runConfigurations/stm32h743.xml
+++ b/.idea/runConfigurations/stm32h743.xml
@@ -1,7 +1,8 @@
-
-
+
+
+
diff --git a/.idea/runConfigurations/stm32u5a5.xml b/.idea/runConfigurations/stm32u5a5.xml
new file mode 100644
index 0000000000..a53a65308f
--- /dev/null
+++ b/.idea/runConfigurations/stm32u5a5.xml
@@ -0,0 +1,11 @@
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index bba217cc99..9cd4a5ed1c 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -42,3 +42,18 @@ repos:
pass_filenames: false
types_or: [c, header]
language: system
+
+# - id: build-fuzzer
+# name: build-fuzzer
+# files: ^(src/|test/fuzz/)
+# language: system
+# types_or: [c, header]
+# entry: |
+# bash -c 'export CC=clang
+# export CXX=clang++
+# fuzz_harness=$(ls -d test/fuzz/device/*/)
+# for h in $fuzz_harness
+# do
+# make -C $h get-deps
+# make -C $h all
+# done'
diff --git a/README.rst b/README.rst
index 8c3145d333..502115c259 100644
--- a/README.rst
+++ b/README.rst
@@ -1,4 +1,4 @@
-|Build Status| |Documentation Status| |Fuzzing Status| |License|
+|Build Status| |CircleCI Status| |Documentation Status| |Fuzzing Status| |License|
Sponsors
========
@@ -77,7 +77,7 @@ Host Stack
- Human Interface Device (HID): Keyboard, Mouse, Generic
- Mass Storage Class (MSC)
- Communication Device Class: CDC-ACM
-- Vendor serial over USB: FTDI, CP210x
+- Vendor serial over USB: FTDI, CP210x, CH34x
- Hub with multiple-level support
Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack.
@@ -109,7 +109,9 @@ Following CPUs are supported, check out `Supported Devices`_ for comprehensive l
+==============+============================================================+
| Allwinner | F1C100s/F1C200s |
+--------------+------------------------------------------------------------+
-| Analog | MAX3421E (usb host shield) |
+| Analog | max32: 650, 666, 690. max78002 |
+| | |
+| | max3421e (spi host) |
+--------------+------------------------------------------------------------+
| Brigetek | FT90x |
+--------------+------------------------------------------------------------+
@@ -122,42 +124,46 @@ Following CPUs are supported, check out `Supported Devices`_ for comprehensive l
| GigaDevice | GD32VF103 |
+--------------+------------------------------------------------------------+
| Infineon | XMC4500 |
-+--------------+-----+------------------------------------------------------+
-| MicroChip | SAM | D11, D21, D51, E5x, G55, L2x, E7x, S7x, V7x |
-| +-----+------------------------------------------------------+
-| | PIC | 24, 32mm, 32mk, 32mx, 32mz, dsPIC33 |
-+--------------+-----+------------------------------------------------------+
++--------------+------------------------------------------------------------+
+| | SAM: D11, D21, D51, E5x, G55, L2x, E7x, S7x, V7x |
+| MicroChip | |
+| | PIC: 24, 32mm, 32mk, 32mx, 32mz, dsPIC33 |
++--------------+------------------------------------------------------------+
| Mind Montion | mm32 |
+--------------+------------------------------------------------------------+
| NordicSemi | nRF52833, nRF52840, nRF5340 |
+--------------+------------------------------------------------------------+
| Nuvoton | NUC 120, 121, 125, 126, 505 |
-+--------------+---------+--------------------------------------------------+
-| NXP | iMXRT | RT10xx, RT11xx |
-| +---------+--------------------------------------------------+
-| | Kinetis | KL, K32L2 |
-| +---------+--------------------------------------------------+
-| | LPC | 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55 |
-| +---------+--------------------------------------------------+
-| | MCX | A15, N9 |
-+--------------+---------+--------------------------------------------------+
-| Raspberry Pi | RP2040 |
-+--------------+-----+------------------------------------------------------+
-| Renesas | RX | 63N, 65N, 72N |
++--------------+------------------------------------------------------------+
+| NXP | iMXRT: RT10xx, RT11xx |
+| | |
+| | Kinetis: KL, K32L2 |
+| | |
+| | LPC: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55 |
+| | |
+| | MCX: A15, N9 |
++--------------+------------------------------------------------------------+
+| Raspberry Pi | RP2040, RP2350 |
+--------------+-----+------------------------------------------------------+
-| | RA | 4M1, 4M3, 6M1, 6M5 |
+| Renesas | RA: 4M1, 4M3, 6M1, 6M5 |
+| | |
+| | RX: 63N, 65N, 72N |
+--------------+-----+------------------------------------------------------+
| Silabs | EFM32GG12 |
+--------------+------------------------------------------------------------+
| Sony | CXD56 |
+--------------+------------------------------------------------------------+
-| ST STM32 | F0, F1, F2, F3, F4, F7, H7, G0, G4, L0, L1, L4, L4+ U5, WB |
+| ST STM32 | F0, F1, F2, F3, F4, F7, G0, G4, H5, H7, |
+| | |
+| | L0, L1, L4, L4+, L5, U5, WB |
+--------------+------------------------------------------------------------+
| TI | MSP430, MSP432E4, TM4C123 |
+--------------+------------------------------------------------------------+
| ValentyUSB | eptri |
+--------------+------------------------------------------------------------+
-| WCH | CH32F20x, CH32V307, |
+| WCH | CH32F: F20x |
+| | |
+| | CH32V: V20x, V307 |
+--------------+------------------------------------------------------------+
License
@@ -191,8 +197,10 @@ Docs
- `Structure`_
- `Porting`_
-.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/cmake_arm.yml/badge.svg
+.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/build.yml/badge.svg
:target: https://github.com/hathach/tinyusb/actions
+.. |CircleCI Status| image:: https://dl.circleci.com/status-badge/img/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master.svg?style=svg
+ :target: https://dl.circleci.com/status-badge/redirect/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master
.. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
:target: https://docs.tinyusb.org/en/latest/?badge=latest
.. |Fuzzing Status| image:: https://oss-fuzz-build-logs.storage.googleapis.com/badges/tinyusb.svg
diff --git a/docs/conf.py b/docs/conf.py
old mode 100644
new mode 100755
index 878b29645e..af44b73391
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
# Configuration file for the Sphinx documentation builder.
#
# This file only contains a selection of the most common options. For a full
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index b359ebb448..d11e1134a0 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -2,6 +2,166 @@
Changelog
*********
+0.17.0
+======
+
+General
+-------
+
+- Improved CI: build both cmake and make. Make use of CircleCI for part of build process to speed up CI
+- Add CodeQL Workflow for Code Security Analysis
+- Add Clang compiler support
+- Add default implementation for weak callbacks functions for better Keil compatibility
+- Upgrade hardware-in-the-loop (HIL) testing with more boards and examples: including dual stack example
+
+Controller Driver (DCD & HCD)
+-----------------------------
+
+- Chipidea
+
+ - Support MCXA
+
+- DWC2
+
+ - Fix tickless issue with stm32f7: disable ULPI clock during sleep when using internal phy
+ - Fix SOF interrupt handling
+ - Fix fifo level half/empty issue
+ - Add DWC2 Test Mode support.
+ - for esp32 force disconnect/connect using USB_WRAP otg pad override
+
+- FSDEV
+
+ - Rewrite and Generalize driver to support non-stm32 mcu such as wch
+ - Simplify PMA, HW FIFO access and bit manipulation for different access scheme 1x16, 2x16 and 32 bit
+ - Add support for ch32 usbd e.g ch32v203
+ - Add support for STM32G4 and STM32U5 microcontrollers.
+ - Fix h5 (32-bit) errata 2.15.1: Buffer description table update completes after CTR interrupt triggers
+ - ISO EP buffer allocation improvements, implement dcd_edpt_close_all()
+
+ - Fix ch32v203 race condition and stability issue with
+
+ - fix ch32v203 seems to unconditionally accept ZLP on EP0 OUT.
+ - fix v203 race condition between rx bufsize and RX_STAT which cause PMAOVR, occurs with WRITE10
+ - correctly handle setup prepare at dcd_edpt0_status_complete(), which fixes the race condition with windows where we could miss setup packet (setup bit set, but count = 0)
+
+- MAX3421E
+
+ - Add support for rp2040, esp32 (c3, c6, h2, etc..)
+ - Add hcd_deinit() for max3421
+ - Retry NAK handling next frame to reduce CPU and SPI bus usage
+ - add cpuctl and pinctl to tuh_configure() option for max3421
+ - Implement hcd abort transfer for Max3421
+ - Properly Handle NAK Response in MAX3421E driver: correctly switch and skip writing to 2 FIFOs when NAK received. Otherwise, the driver may hang in certain conditions.
+
+- MSP430: support non-bus-powered
+
+- MUSB
+
+ - Add support for Analoog devices: max32650, max32666, max32690, max3278002
+
+- nRF
+
+ - Fix dcd_edpt_open for iso endpoint
+ - Handle ISOOUT CRC errors
+ - Add compile support with old nordic sdk
+ - Fix a few race conditions
+
+- OHCI
+
+ - Allow more than 16 devices
+
+- RP2040
+
+ - Correctly abort control transfer when new setup arrived. Due to RP2040-E2 only able to fix B2 or later
+ - Implement hcd abort transfer for rp2040
+ - Add support for rp2350
+
+- RUSB2
+
+ - Support ra2a1 pipe number scheme
+
+- WCH CH32
+
+ - Added support for USB OTG/FS and FSDev Driver. Update CH32V307 to allow manual select FS or HS driver.
+ - Fixed various bugs in CH32v307 usbhs driver: endpoint handling and data transfer management.
+
+Device Stack
+------------
+
+- Add tud_deinit() and class driver deinit() to deinitialize TinyUSB device stack.
+- Add support for generic SOF callback.
+- Add set address recovery time 2ms per USB spec.
+
+- Audio
+
+ - Add audio_test_freertos & audio_4_channel_mic_freertos
+ - Improved support for Audio Class 2.0 (UAC2) with various bug fixes.
+ - Add feedback by fifo counting.
+
+- Bluetooth HCI
+
+ - Issue ZLP on ACL IN ep when transfer is multiple of endpoint max packet size
+
+- CDC
+
+ - Add tud_cdc_configure_fifo() to make RX/TX buffer persistent (not clear when disconnected)
+ - Add missing capability bit for CDC ACM serial break support
+ - Enhanced CDC class with better handling of large data transmissions.
+ - Add missing capability bit for CDC ACM serial break support
+
+- HID
+
+ - Added missing key codes for keypad
+ - Added HID Lighting and Illumination functionality
+ - Fixed issues in the HID class for more reliable device enumeration.
+ - Support HID Mouse with absolute positioning
+ - Use separate buffer for control SET_REPORT, fix conflict with interrupt endpoint out
+
+- MSC: Added support for SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL
+
+- Net
+
+ - Rewrite of NCM device driver to improve throughput
+ - removed obsolete tud_network_link_state_cb()
+
+- USBTMC Added notification support
+
+- Vendor
+
+ - Migrate to new endpoint stream API, support non-buffered TX/RX
+ - Add ZLP for write() when needed
+
+- Video
+
+ - Enhance UVC descriptors and example
+ - Video Added support for USB Video Class (UVC) with MJPEG.
+ - Fix multiple interfaces, add an example of 2ch video capture.
+ - Fix race for tud_video_n_streaming check
+
+Host Stack
+----------
+
+- Added tuh_deinit() to de-initialize TinyUSB host stack.
+- Added support for new USB mass storage class APIs.
+- Improved error handling and retry mechanisms for unstable devices.
+
+- CDC Serial
+
+ - Add support for ch34x
+ - Allow to overwrite CFG_TUH_CDC_FTDI/CP210X/CH32X_VID_PID_LIST
+ - Enhanced stability of CDC-ACM devices during enumeration.
+
+- HID
+
+ - Add tuh_hid_receive_abort()
+ - Add tuh_hid_get_report()
+
+- Hub
+
+ - Prevent status request to invalid ep_num
+ - Fix double status xfer
+ - unroll hub removal
+
0.16.0
======
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
index 6ba6692e93..65ee31f227 100644
--- a/docs/reference/dependencies.rst
+++ b/docs/reference/dependencies.rst
@@ -4,21 +4,22 @@ Dependencies
MCU low-level peripheral driver and external libraries for building TinyUSB examples
-======================================== ============================================================== ======================================== =======================================================================================================================================================================================================
+======================================== ============================================================== ======================================== ==========================================================================================================================================================================================================================================================================================================================
Local Path Repo Commit Required by
-======================================== ============================================================== ======================================== =======================================================================================================================================================================================================
+======================================== ============================================================== ======================================== ==========================================================================================================================================================================================================================================================================================================================
hw/mcu/allwinner https://github.com/hathach/allwinner_driver.git 8e5e89e8e132c0fd90e72d5422e5d3d68232b756 fc100s
+hw/mcu/analog/max32 https://github.com/analogdevicesinc/msdk.git b20b398d3e5e2007594e54a74ba3d2a2e50ddd75 max32650 max32666 max32690 max78002
hw/mcu/bridgetek/ft9xx/ft90x-sdk https://github.com/BRTSG-FOSS/ft90x-sdk.git 91060164afe239fcb394122e8bf9eb24d3194eb1 brtmm90x
hw/mcu/broadcom https://github.com/adafruit/broadcom-peripherals.git 08370086080759ed54ac1136d62d2ad24c6fa267 broadcom_32bit broadcom_64bit
hw/mcu/gd/nuclei-sdk https://github.com/Nuclei-Software/nuclei-sdk.git 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7 gd32vf103
hw/mcu/infineon/mtb-xmclib-cat3 https://github.com/Infineon/mtb-xmclib-cat3.git daf5500d03cba23e68c2f241c30af79cd9d63880 xmc4000
-hw/mcu/microchip https://github.com/hathach/microchip_driver.git 9e8b37e307d8404033bb881623a113931e1edf27 sam3x samd11 samd21 samd51 same5x same7x saml2x samg
-hw/mcu/mindmotion/mm32sdk https://github.com/hathach/mm32sdk.git 0b79559eb411149d36e073c1635c620e576308d4 mm32
-hw/mcu/nordic/nrfx https://github.com/NordicSemiconductor/nrfx.git 2527e3c8449cfd38aee41598e8af8492f410ed15 nrf
+hw/mcu/microchip https://github.com/hathach/microchip_driver.git 9e8b37e307d8404033bb881623a113931e1edf27 sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg
+hw/mcu/mindmotion/mm32sdk https://github.com/hathach/mm32sdk.git b93e856211060ae825216c6a1d6aa347ec758843 mm32
+hw/mcu/nordic/nrfx https://github.com/NordicSemiconductor/nrfx.git 7c47cc0a56ce44658e6da2458e86cd8783ccc4a2 nrf
hw/mcu/nuvoton https://github.com/majbthrd/nuc_driver.git 2204191ec76283371419fbcec207da02e1bc22fa nuc
-hw/mcu/nxp/lpcopen https://github.com/hathach/nxp_lpcopen.git 84e0bd3e43910aaf71eefd62075cf57495418312 lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43
-hw/mcu/nxp/mcux-sdk https://github.com/hathach/mcux-sdk.git 950819b7de9b32f92c3edf396bc5ffb8d66e7009 kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt
-hw/mcu/raspberry_pi/Pico-PIO-USB https://github.com/sekigon-gonnoc/Pico-PIO-USB.git d00a10a8c425d0d40f81b87169102944b01f3bb3 rp2040
+hw/mcu/nxp/lpcopen https://github.com/hathach/nxp_lpcopen.git b41cf930e65c734d8ec6de04f1d57d46787c76ae lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43
+hw/mcu/nxp/mcux-sdk https://github.com/hathach/mcux-sdk.git 144f1eb7ea8c06512e12f12b27383601c0272410 kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt
+hw/mcu/raspberry_pi/Pico-PIO-USB https://github.com/sekigon-gonnoc/Pico-PIO-USB.git fe9133fc513b82cc3dc62c67cb51f2339cf29ef7 rp2040
hw/mcu/renesas/fsp https://github.com/renesas/fsp.git d52e5a6a59b7c638da860c2bb309b6e78e752ff8 ra
hw/mcu/renesas/rx https://github.com/kkitayam/rx_device.git 706b4e0cf485605c32351e2f90f5698267996023 rx
hw/mcu/silabs/cmsis-dfp-efm32gg12b https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git f1c31b7887669cb230b3ea63f9b56769078960bc efm32
@@ -28,15 +29,16 @@ hw/mcu/st/cmsis_device_f1 https://github.com/STMicroelectronics/
hw/mcu/st/cmsis_device_f2 https://github.com/STMicroelectronics/cmsis_device_f2.git 182fcb3681ce116816feb41b7764f1b019ce796f stm32f2
hw/mcu/st/cmsis_device_f3 https://github.com/STMicroelectronics/cmsis_device_f3.git 5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b stm32f3
hw/mcu/st/cmsis_device_f4 https://github.com/STMicroelectronics/cmsis_device_f4.git 2615e866fa48fe1ff1af9e31c348813f2b19e7ec stm32f4
-hw/mcu/st/cmsis_device_f7 https://github.com/STMicroelectronics/cmsis_device_f7.git fc676ef1ad177eb874eaa06444d3d75395fc51f4 stm32f7
+hw/mcu/st/cmsis_device_f7 https://github.com/STMicroelectronics/cmsis_device_f7.git 25b0463439303b7a38f0d27b161f7d2f3c096e79 stm32f7
hw/mcu/st/cmsis_device_g0 https://github.com/STMicroelectronics/cmsis_device_g0.git 3a23e1224417f3f2d00300ecd620495e363f2094 stm32g0
hw/mcu/st/cmsis_device_g4 https://github.com/STMicroelectronics/cmsis_device_g4.git ce822adb1dc552b3aedd13621edbc7fdae124878 stm32g4
+hw/mcu/st/cmsis_device_h5 https://github.com/STMicroelectronics/cmsis_device_h5.git cd2d1d579743de57b88ccaf61a968b9c05848ffc stm32h5
hw/mcu/st/cmsis_device_h7 https://github.com/STMicroelectronics/cmsis_device_h7.git 60dc2c913203dc8629dc233d4384dcc41c91e77f stm32h7
-hw/mcu/st/cmsis_device_l0 https://github.com/STMicroelectronics/cmsis_device_l0.git 06748ca1f93827befdb8b794402320d94d02004f stm32l0
+hw/mcu/st/cmsis_device_l0 https://github.com/STMicroelectronics/cmsis_device_l0.git 69cd5999fd40ae6e546d4905b21635c6ca1bcb92 stm32l0
hw/mcu/st/cmsis_device_l1 https://github.com/STMicroelectronics/cmsis_device_l1.git 7f16ec0a1c4c063f84160b4cc6bf88ad554a823e stm32l1
hw/mcu/st/cmsis_device_l4 https://github.com/STMicroelectronics/cmsis_device_l4.git 6ca7312fa6a5a460b5a5a63d66da527fdd8359a6 stm32l4
hw/mcu/st/cmsis_device_l5 https://github.com/STMicroelectronics/cmsis_device_l5.git d922865fc0326a102c26211c44b8e42f52c1e53d stm32l5
-hw/mcu/st/cmsis_device_u5 https://github.com/STMicroelectronics/cmsis_device_u5.git 06d7edade7167b0eafdd550bf77cfc4fa98eae2e stm32u5
+hw/mcu/st/cmsis_device_u5 https://github.com/STMicroelectronics/cmsis_device_u5.git 5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309 stm32u5
hw/mcu/st/cmsis_device_wb https://github.com/STMicroelectronics/cmsis_device_wb.git 9c5d1920dd9fabbe2548e10561d63db829bb744f stm32wb
hw/mcu/st/stm32f0xx_hal_driver https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git 0e95cd88657030f640a11e690a8a5186c7712ea5 stm32f0
hw/mcu/st/stm32f1xx_hal_driver https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git 1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29 stm32f1
@@ -46,6 +48,7 @@ hw/mcu/st/stm32f4xx_hal_driver https://github.com/STMicroelectronics/
hw/mcu/st/stm32f7xx_hal_driver https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git f7ffdf6bf72110e58b42c632b0a051df5997e4ee stm32f7
hw/mcu/st/stm32g0xx_hal_driver https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git e911b12c7f67084d7f6b76157a4c0d4e2ec3779c stm32g0
hw/mcu/st/stm32g4xx_hal_driver https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git 8b4518417706d42eef5c14e56a650005abf478a8 stm32g4
+hw/mcu/st/stm32h5xx_hal_driver https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git 2cf77de584196d619cec1b4586c3b9e2820a254e stm32h5
hw/mcu/st/stm32h7xx_hal_driver https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04 stm32h7
hw/mcu/st/stm32l0xx_hal_driver https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b stm32l0
hw/mcu/st/stm32l1xx_hal_driver https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git 44efc446fa69ed8344e7fd966e68ed11043b35d9 stm32l1
@@ -53,12 +56,14 @@ hw/mcu/st/stm32l4xx_hal_driver https://github.com/STMicroelectronics/
hw/mcu/st/stm32l5xx_hal_driver https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git 675c32a75df37f39d50d61f51cb0dcf53f07e1cb stm32l5
hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git 4d93097a67928e9377e655ddd14622adc31b9770 stm32u5
hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8 stm32wb
-hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5 msp430 msp432e4 tm4c123
+hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5 msp430 msp432e4 tm4c
hw/mcu/wch/ch32f20x https://github.com/openwch/ch32f20x.git 77c4095087e5ed2c548ec9058e655d0b8757663b ch32f20x
-hw/mcu/wch/ch32v307 https://github.com/openwch/ch32v307.git 17761f5cf9dbbf2dcf665b7c04934188add20082 ch32v307
-lib/CMSIS_5 https://github.com/ARM-software/CMSIS_5.git 20285262657d1b482d132d20d755c8c330d55c1f imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2xstm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb
-lib/FreeRTOS-Kernel https://github.com/FreeRTOS/FreeRTOS-Kernel.git 4ff01a7a4a51f53b44496aefee1e3c0071b7b173 all
+hw/mcu/wch/ch32v103 https://github.com/openwch/ch32v103.git 7578cae0b21f86dd053a1f781b2fc6ab99d0ec17 ch32v10x
+hw/mcu/wch/ch32v20x https://github.com/openwch/ch32v20x.git c4c38f507e258a4e69b059ccc2dc27dde33cea1b ch32v20x
+hw/mcu/wch/ch32v307 https://github.com/openwch/ch32v307.git 184f21b852cb95eed58e86e901837bc9fff68775 ch32v307
+lib/CMSIS_5 https://github.com/ARM-software/CMSIS_5.git 20285262657d1b482d132d20d755c8c330d55c1f imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2xlpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wbsam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samgtm4c
+lib/FreeRTOS-Kernel https://github.com/FreeRTOS/FreeRTOS-Kernel.git cc0e0707c0c748713485b870bb980852b210877f all
lib/lwip https://github.com/lwip-tcpip/lwip.git 159e31b689577dbf69cf0683bbaffbd71fa5ee10 all
lib/sct_neopixel https://github.com/gsteiert/sct_neopixel.git e73e04ca63495672d955f9268e003cffe168fcd8 lpc55
-tools/uf2 https://github.com/microsoft/uf2.git 19615407727073e36d81bf239c52108ba92e7660 all
-======================================== ============================================================== ======================================== =======================================================================================================================================================================================================
+tools/uf2 https://github.com/microsoft/uf2.git c594542b2faa01cc33a2b97c9fbebc38549df80a all
+======================================== ============================================================== ======================================== ==========================================================================================================================================================================================================================================================================================================================
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 3db3fa2064..ac4ab63926 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -12,22 +12,19 @@ It is relatively simple to incorporate tinyusb to your project
* Add *your_project/tinyusb/src* to your include path. Also make sure your current include path also contains the configuration file tusb_config.h.
* Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all boards).
* If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud descriptor** callbacks for the stack to work.
-* Add tusb_init() call to your reset initialization code.
-* Call ``tud_int_handler()`` (device) and/or ``tuh_int_handler()`` (host) in your USB IRQ Handler
+* Add tusb_init(rhport, role) call to your reset initialization code.
+* Call ``tusb_int_handler(rhport, in_isr)`` in your USB IRQ Handler
* Implement all enabled classes's callbacks.
* If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. All of the callbacks and functionality are handled and invoked within the call of that task runner.
.. code-block::
- int main(void)
- {
+ int main(void) {
your_init_code();
- tusb_init(); // initialize tinyusb stack
+ tusb_init(0, TUSB_ROLE_DEVICE); // initialize device stack on roothub port 0
- while(1) // the mainloop
- {
+ while(1) { // the mainloop
your_application_code();
-
tud_task(); // device task
tuh_task(); // host task
}
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 7e7be25a43..b871490dcf 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -5,143 +5,143 @@ Supported Devices
Supported MCUs
==============
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Manufacturer | Family | Device | Host | Highspeed | Driver | Note |
-+==============+=======================+========+======+===========+===================+==============+
-| Allwinner | F1C100s/F1C200s | ✔ | | ✔ | sunxi | musb variant |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Analog | MAX3421E | | ✔ | ✖ | max3421 | via SPI |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Brigetek | FT90x | ✔ | | ✔ | ft9xx | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Broadcom | BCM2711, BCM2837 | ✔ | | ✔ | dwc2 | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Dialog | DA1469x | ✔ | ✖ | ✖ | da146xx | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Espressif | ESP32 S2, S3 | ✔ | | ✖ | dwc2 or esp32sx | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| GigaDevice | GD32VF103 | ✔ | | ✖ | dwc2 | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Infineon | XMC4500 | ✔ | | ✖ | dwc2 | |
-+--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
-| MicroChip | SAM | D11, D21 | ✔ | | ✖ | samd | |
-| | +-----------------+--------+------+-----------+-------------------+--------------+
-| | | D51, E5x | ✔ | | ✖ | samd | |
-| | +-----------------+--------+------+-----------+-------------------+--------------+
-| | | G55 | ✔ | | ✖ | samg | |
-| | +-----------------+--------+------+-----------+-------------------+--------------+
-| | | L21, L22 | ✔ | | ✖ | samd | |
-| | +-----------------+--------+------+-----------+-------------------+--------------+
-| | | E70,S70,V70,V71 | ✔ | | ✔ | samx7x | |
-| +-----+-----------------+--------+------+-----------+-------------------+--------------+
-| | PIC | 24 | ✔ | | | pic | ci_fs variant|
-| | +-----------------+--------+------+-----------+-------------------+--------------+
-| | | 32 mm, mk, mx | ✔ | | | pic | ci_fs variant|
-| | +-----------------+--------+------+-----------+-------------------+--------------+
-| | | dsPIC33 | ✔ | | | pic | ci_fs variant|
-| | +-----------------+--------+------+-----------+-------------------+--------------+
-| | | 32mz | ✔ | | | pic32mz | musb variant |
-+--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
-| Mind Montion | mm32 | ✔ | | ✖ | mm32f327x_otg | ci_fs variant|
-+--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
-| NordicSemi | nRF52833, nRF52840 | ✔ | ✖ | ✖ | nrf5x | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | nRF5340 | ✔ | ✖ | ✖ | nrf5x | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Nuvoton | NUC120 | ✔ | ✖ | ✖ | nuc120 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | NUC121/NUC125 | ✔ | ✖ | ✖ | nuc121 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | NUC126 | ✔ | ✖ | ✖ | nuc121 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | NUC505 | ✔ | | ✔ | nuc505 | |
-+--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
-| NXP | iMXRT | RT10xx | ✔ | ✔ | ✔ | ci_hs | |
-| | +-------------+--------+------+-----------+-------------------+--------------+
-| | | RT11xx | ✔ | ✔ | ✔ | ci_hs | |
-| +---------+-------------+--------+------+-----------+-------------------+--------------+
-| | Kinetis | KL | ✔ | ⚠| ✖ | ci_fs, khci | |
-| | +-------------+--------+------+-----------+-------------------+--------------+
-| | | K32L2 | ✔ | | ✖ | khci | ci_fs variant|
-| +---------+-------------+--------+------+-----------+-------------------+--------------+
-| | LPC | 11u, 13, 15 | ✔ | ✖ | ✖ | lpc_ip3511 | |
-| | +-------------+--------+------+-----------+-------------------+--------------+
-| | | 17, 40 | ✔ | ⚠| ✖ | lpc17_40 | |
-| | +-------------+--------+------+-----------+-------------------+--------------+
-| | | 18, 43 | ✔ | ✔ | ✔ | ci_hs | |
-| | +-------------+--------+------+-----------+-------------------+--------------+
-| | | 51u | ✔ | ✖ | ✖ | lpc_ip3511 | |
-| | +-------------+--------+------+-----------+-------------------+--------------+
-| | | 54 | ✔ | | ✔ | lpc_ip3511 | |
-| | +-------------+--------+------+-----------+-------------------+--------------+
-| | | 55 | ✔ | | ✔ | lpc_ip3511 | |
-| +---------+-------------+--------+------+-----------+-------------------+--------------+
-| | MCX | N9 | ✔ | | ✔ | ci_fs, ci_hs | |
-+--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
-| Raspberry Pi | RP2040 | ✔ | ✔ | ✖ | rp2040, pio_usb | |
-+--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
-| Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | rusb2 | |
-| +-----+-----------------+--------+------+-----------+-------------------+--------------+
-| | RA | 4M1, 4M3, 6M1 | ✔ | ✔ | ✖ | rusb2 | |
-| | +-----------------+--------+------+-----------+-------------------+--------------+
-| | | 6M5 | ✔ | ✔ | ✔ | rusb2 | |
-+--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
-| Silabs | EFM32GG12 | ✔ | | ✖ | dwc2 | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Sony | CXD56 | ✔ | ✖ | ✔ | cxd56 | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| ST STM32 | F0 | ✔ | ✖ | ✖ | stm32_fsdev | |
-| +----+------------------+--------+------+-----------+-------------------+--------------+
-| | F1 | 102, 103 | ✔ | ✖ | ✖ | stm32_fsdev | |
-| | +------------------+--------+------+-----------+-------------------+--------------+
-| | | 105, 107 | ✔ | | ✖ | dwc2 | |
-| +----+------------------+--------+------+-----------+-------------------+--------------+
-| | F2 | ✔ | | ✔ | dwc2 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | F3 | ✔ | ✖ | ✖ | stm32_fsdev | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | F4 | ✔ | | ✔ | dwc2 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | F7 | ✔ | | ✔ | dwc2 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | H7 | ✔ | | ✔ | dwc2 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | G4 | ✔ | ✖ | ✖ | stm32_fsdev | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | L0, L1 | ✔ | ✖ | ✖ | stm32_fsdev | |
-| +----+------------------+--------+------+-----------+-------------------+--------------+
-| | L4 | 4x2, 4x3 | ✔ | ✖ | ✖ | stm32_fsdev | |
-| | +------------------+--------+------+-----------+-------------------+--------------+
-| | | 4x5, 4x6 | ✔ | | | dwc2 | |
-| +----+------------------+--------+------+-----------+-------------------+--------------+
-| | L4+ | ✔ | | | dwc2 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | U5 | ✔ | | ✔ | dwc2 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | WBx5 | ✔ | | | stm32_fsdev | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| TI | MSP430 | ✔ | ✖ | ✖ | msp430x5xx | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | MSP432E4 | ✔ | | ✖ | musb | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | TM4C123 | ✔ | | ✖ | musb | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| ValentyUSB | eptri | ✔ | ✖ | ✖ | eptri | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| WCH | CH32V307 | ✔ | | ✔ | ch32v307 | |
-| +-----------------------+--------+------+-----------+-------------------+--------------+
-| | CH32F20x | ✔ | | ✔ | ch32f205 | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Manufacturer | Family | Device | Host | Highspeed | Driver | Note |
++==============+=============================+========+======+===========+========================+===================+
+| Allwinner | F1C100s/F1C200s | ✔ | | ✔ | sunxi | musb variant |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Analog | MAX3421E | | ✔ | ✖ | max3421 | via SPI |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | MAX32 650, 666, 690, | ✔ | | ✔ | musb | 1-dir ep |
+| | MAX78002 | | | | | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Brigetek | FT90x | ✔ | | ✔ | ft9xx | 1-dir ep |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Broadcom | BCM2711, BCM2837 | ✔ | | ✔ | dwc2 | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Dialog | DA1469x | ✔ | ✖ | ✖ | da146xx | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Espressif | ESP32 S2, S3 | ✔ | | ✖ | dwc2 or esp32sx | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| GigaDevice | GD32VF103 | ✔ | | ✖ | dwc2 | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Infineon | XMC4500 | ✔ | | ✖ | dwc2 | |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| MicroChip | SAM | D11, D21, L21, L22 | ✔ | | ✖ | samd | |
+| | +-----------------------+--------+------+-----------+------------------------+-------------------+
+| | | D51, E5x | ✔ | | ✖ | samd | |
+| | +-----------------------+--------+------+-----------+------------------------+-------------------+
+| | | G55 | ✔ | | ✖ | samg | 1-dir ep |
+| | +-----------------------+--------+------+-----------+------------------------+-------------------+
+| | | E70,S70,V70,V71 | ✔ | | ✔ | samx7x | 1-dir ep |
+| +-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| | PIC | 24 | ✔ | | | pic | ci_fs variant |
+| | +-----------------------+--------+------+-----------+------------------------+-------------------+
+| | | 32 mm, mk, mx | ✔ | | | pic | ci_fs variant |
+| | +-----------------------+--------+------+-----------+------------------------+-------------------+
+| | | dsPIC33 | ✔ | | | pic | ci_fs variant |
+| | +-----------------------+--------+------+-----------+------------------------+-------------------+
+| | | 32mz | ✔ | | | pic32mz | musb variant |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| Mind Montion | mm32 | ✔ | | ✖ | mm32f327x_otg | ci_fs variant |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| NordicSemi | nRF 52833, 52840, 5340 | ✔ | ✖ | ✖ | nrf5x | only ep8 is ISO |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Nuvoton | NUC120 | ✔ | ✖ | ✖ | nuc120 | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | NUC121/NUC125 | ✔ | ✖ | ✖ | nuc121 | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | NUC126 | ✔ | ✖ | ✖ | nuc121 | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | NUC505 | ✔ | | ✔ | nuc505 | |
++--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+
+| NXP | iMXRT | RT 10xx, 11xx | ✔ | ✔ | ✔ | ci_hs | |
+| +---------+-------------------+--------+------+-----------+------------------------+-------------------+
+| | Kinetis | KL | ✔ | ⚠| ✖ | ci_fs, khci | |
+| | +-------------------+--------+------+-----------+------------------------+-------------------+
+| | | K32L2 | ✔ | | ✖ | khci | ci_fs variant |
+| +---------+-------------------+--------+------+-----------+------------------------+-------------------+
+| | LPC | 11u, 13, 15 | ✔ | ✖ | ✖ | lpc_ip3511 | |
+| | +-------------------+--------+------+-----------+------------------------+-------------------+
+| | | 17, 40 | ✔ | ⚠| ✖ | lpc17_40 | |
+| | +-------------------+--------+------+-----------+------------------------+-------------------+
+| | | 18, 43 | ✔ | ✔ | ✔ | ci_hs | |
+| | +-------------------+--------+------+-----------+------------------------+-------------------+
+| | | 51u | ✔ | ✖ | ✖ | lpc_ip3511 | |
+| | +-------------------+--------+------+-----------+------------------------+-------------------+
+| | | 54, 55 | ✔ | | ✔ | lpc_ip3511 | |
+| +---------+-------------------+--------+------+-----------+------------------------+-------------------+
+| | MCX | N9, A15 | ✔ | | ✔ | ci_fs, ci_hs | |
++--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+
+| Raspberry Pi | RP2040, RP2350 | ✔ | ✔ | ✖ | rp2040, pio_usb | |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | rusb2 | |
+| +-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| | RA | 4M1, 4M3, 6M1 | ✔ | ✔ | ✖ | rusb2 | |
+| | +-----------------------+--------+------+-----------+------------------------+-------------------+
+| | | 6M5 | ✔ | ✔ | ✔ | rusb2 | |
++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+
+| Silabs | EFM32GG12 | ✔ | | ✖ | dwc2 | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Sony | CXD56 | ✔ | ✖ | ✔ | cxd56 | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| ST STM32 | F0 | ✔ | ✖ | ✖ | stm32_fsdev | |
+| +----+------------------------+--------+------+-----------+------------------------+-------------------+
+| | F1 | 102, 103 | ✔ | ✖ | ✖ | stm32_fsdev | |
+| | +------------------------+--------+------+-----------+------------------------+-------------------+
+| | | 105, 107 | ✔ | | ✖ | dwc2 | |
+| +----+------------------------+--------+------+-----------+------------------------+-------------------+
+| | F2, F4, F7, H7 | ✔ | | ✔ | dwc2 | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | F3 | ✔ | ✖ | ✖ | stm32_fsdev | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | G0, H5 | ✔ | | ✖ | stm32_fsdev | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | G4 | ✔ | ✖ | ✖ | stm32_fsdev | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | L0, L1 | ✔ | ✖ | ✖ | stm32_fsdev | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | L4 | 4x2, 4x3 | ✔ | ✖ | ✖ | stm32_fsdev | |
+| | +------------------------+--------+------+-----------+------------------------+-------------------+
+| | | 4x5, 4x6 | ✔ | | ✖ | dwc2 | |
+| +----+------------------------+--------+------+-----------+------------------------+-------------------+
+| | L4+ | ✔ | | ✖ | dwc2 | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | L5 | ✔ | ✖ | ✖ | stm32_fsdev | |
+| +----+------------------------+--------+------+-----------+------------------------+-------------------+
+| | U5 | 535, 545 | ✔ | | ✖ | stm32_fsdev | |
+| | +------------------------+--------+------+-----------+------------------------+-------------------+
+| | | 575, 585 | ✔ | | ✖ | dwc2 | |
+| | +------------------------+--------+------+-----------+------------------------+-------------------+
+| | | 59x,5Ax,5Fx,5Gx | ✔ | | ✔ | dwc2 | |
+| +----+------------------------+--------+------+-----------+------------------------+-------------------+
+| | WBx5 | ✔ | ✖ | ✖ | stm32_fsdev | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| TI | MSP430 | ✔ | ✖ | ✖ | msp430x5xx | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | MSP432E4 | ✔ | | ✖ | musb | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | TM4C123 | ✔ | | ✖ | musb | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| ValentyUSB | eptri | ✔ | ✖ | ✖ | eptri | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| WCH | CH32F20x | ✔ | | ✔ | ch32_usbhs | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | CH32V20x | ✔ | | ✖ | stm32_fsdev/ch32_usbfs | |
+| +-----------------------------+--------+------+-----------+------------------------+-------------------+
+| | CH32V307 | ✔ | | ✔ | ch32_usbfs/hs | |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
Table Legend
------------
-= ===================
-✔ Supported
-âš WIP/partial support
-✖ Not supported
-= ===================
+========= =========================
+✔ Supported
+âš Partial support
+✖ Not supported by hardware
+\[empty\] Unknown
+========= =========================
Supported Boards
================
diff --git a/examples/build_system/cmake/cpu/arm1176jzf-s.cmake b/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
new file mode 100644
index 0000000000..8029e39876
--- /dev/null
+++ b/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
@@ -0,0 +1,21 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -mcpu=arm1176jzf-s
+ -ffreestanding
+ )
+ # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --target=arm-none-eabi
+ -mcpu=arm1176jzf-s
+ -mfpu=none
+ -mfloat-abi=soft
+ -ffreestanding
+ )
+ #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/arm926ej-s.cmake b/examples/build_system/cmake/cpu/arm926ej-s.cmake
new file mode 100644
index 0000000000..c19b9f8a87
--- /dev/null
+++ b/examples/build_system/cmake/cpu/arm926ej-s.cmake
@@ -0,0 +1,21 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -mcpu=arm926ej-s
+ -ffreestanding
+ )
+ # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --target=arm-none-eabi
+ -mcpu=arm926ej-s
+ -mfpu=none
+ -mfloat-abi=soft
+ -ffreestanding
+ )
+ #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-a53.cmake b/examples/build_system/cmake/cpu/cortex-a53.cmake
new file mode 100644
index 0000000000..dde8c0a0c4
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-a53.cmake
@@ -0,0 +1,17 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -mcpu=cortex-a53
+ )
+ # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --target=arm-none-eabi
+ -mcpu=cortex-a53
+ )
+ #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-a72.cmake b/examples/build_system/cmake/cpu/cortex-a72.cmake
new file mode 100644
index 0000000000..a443242346
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-a72.cmake
@@ -0,0 +1,17 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -mcpu=cortex-a72
+ )
+ # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --target=arm-none-eabi
+ -mcpu=cortex-a72
+ )
+ #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m33-nodsp.cmake b/examples/build_system/cmake/cpu/cortex-m33-nodsp.cmake
new file mode 100644
index 0000000000..b3cd743fdf
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m33-nodsp.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -mthumb
+ -mcpu=cortex-m33+nodsp
+ -mfloat-abi=hard
+ -mfpu=fpv5-sp-d16
+ )
+ set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --target=arm-none-eabi
+ -mcpu=cortex-m33+nodsp
+ -mfpu=fpv5-sp-d16
+ )
+ set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --cpu cortex-m33+nodsp
+ --fpu VFPv5-SP
+ )
+ set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m7-fpsp.cmake b/examples/build_system/cmake/cpu/cortex-m7-fpsp.cmake
new file mode 100644
index 0000000000..b10f00fc29
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m7-fpsp.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -mthumb
+ -mcpu=cortex-m7
+ -mfloat-abi=hard
+ -mfpu=fpv5-sp-d16
+ )
+ set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --target=arm-none-eabi
+ -mcpu=cortex-m7
+ -mfpu=fpv5-sp-d16
+ )
+ set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --cpu cortex-m7
+ --fpu VFPv5_sp
+ )
+ set(FREERTOS_PORT IAR_ARM_CM7 CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/rv32i-ilp32.cmake b/examples/build_system/cmake/cpu/rv32i-ilp32.cmake
new file mode 100644
index 0000000000..605c40ba18
--- /dev/null
+++ b/examples/build_system/cmake/cpu/rv32i-ilp32.cmake
@@ -0,0 +1,19 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -march=rv32i_zicsr
+ -mabi=ilp32
+ )
+ set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -march=rv32i_zicsr
+ -mabi=ilp32
+ )
+ set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ message(FATAL_ERROR "IAR not supported")
+ set(FREERTOS_PORT IAR_RISC_V CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake b/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
new file mode 100644
index 0000000000..584d905193
--- /dev/null
+++ b/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
@@ -0,0 +1,18 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -march=rv32imac_zicsr
+ -mabi=ilp32
+ )
+ set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -march=rv32imac_zicsr
+ -mabi=ilp32
+ )
+ set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ message(FATAL_ERROR "IAR not supported")
+ set(FREERTOS_PORT IAR_RISC_V CACHE INTERNAL "")
+endif ()
diff --git a/examples/build_system/cmake/toolchain/aarch64_gcc.cmake b/examples/build_system/cmake/toolchain/aarch64_gcc.cmake
new file mode 100644
index 0000000000..2d30a0b71d
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/aarch64_gcc.cmake
@@ -0,0 +1,21 @@
+if (NOT DEFINED CMAKE_C_COMPILER)
+ set(CMAKE_C_COMPILER "aarch64-none-elf-gcc")
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+ set(CMAKE_CXX_COMPILER "aarch64-none-elf-g++")
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+set(CMAKE_SIZE "aarch64-none-elf-size" CACHE FILEPATH "")
+set(CMAKE_OBJCOPY "aarch64-none-elf-objcopy" CACHE FILEPATH "")
+set(CMAKE_OBJDUMP "aarch64-none-elf-objdump" CACHE FILEPATH "")
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
+
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if (IS_IN_TRY_COMPILE)
+ set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+ set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+ cmake_print_variables(CMAKE_C_LINK_FLAGS)
+endif ()
diff --git a/examples/build_system/cmake/toolchain/riscv_gcc.cmake b/examples/build_system/cmake/toolchain/riscv_gcc.cmake
new file mode 100644
index 0000000000..d788df0232
--- /dev/null
+++ b/examples/build_system/cmake/toolchain/riscv_gcc.cmake
@@ -0,0 +1,30 @@
+# default Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+if (NOT DEFINED CROSS_COMPILE)
+ set(CROSS_COMPILE "riscv-none-elf-")
+endif ()
+
+if (NOT DEFINED CMAKE_C_COMPILER)
+ set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+endif ()
+
+if (NOT DEFINED CMAKE_C_COMPILER)
+ set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+ set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+set(CMAKE_SIZE ${CROSS_COMPILE}size CACHE FILEPATH "")
+set(CMAKE_OBJCOPY ${CROSS_COMPILE}objcopy CACHE FILEPATH "")
+set(CMAKE_OBJDUMP ${CROSS_COMPILE}objdump CACHE FILEPATH "")
+
+include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)
+
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if (IS_IN_TRY_COMPILE)
+ set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+ set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+ cmake_print_variables(CMAKE_C_LINK_FLAGS)
+endif ()
diff --git a/examples/build_system/make/cpu/arm1176.mk b/examples/build_system/make/cpu/arm1176jzf-s.mk
similarity index 100%
rename from examples/build_system/make/cpu/arm1176.mk
rename to examples/build_system/make/cpu/arm1176jzf-s.mk
diff --git a/examples/build_system/make/cpu/arm926ej-s.mk b/examples/build_system/make/cpu/arm926ej-s.mk
new file mode 100644
index 0000000000..5b84f514f4
--- /dev/null
+++ b/examples/build_system/make/cpu/arm926ej-s.mk
@@ -0,0 +1,9 @@
+ifeq ($(TOOLCHAIN),gcc)
+ CFLAGS += \
+ -mcpu=arm926ej-s \
+
+else ifeq ($(TOOLCHAIN),iar)
+ #CFLAGS += --cpu cortex-a53
+ #ASFLAGS += --cpu cortex-a53
+
+endif
diff --git a/examples/build_system/make/cpu/cortex-m7-fpsp.mk b/examples/build_system/make/cpu/cortex-m7-fpsp.mk
new file mode 100644
index 0000000000..cd42c6fb8b
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m7-fpsp.mk
@@ -0,0 +1,27 @@
+ifeq ($(TOOLCHAIN),gcc)
+ CFLAGS += \
+ -mthumb \
+ -mcpu=cortex-m7 \
+ -mfloat-abi=hard \
+ -mfpu=fpv5-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+ CFLAGS += \
+ --target=arm-none-eabi \
+ -mcpu=cortex-m7 \
+ -mfpu=fpv5-sp-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+ CFLAGS += \
+ --cpu cortex-m7 \
+ --fpu VFPv5_sp \
+
+ ASFLAGS += \
+ --cpu cortex-m7 \
+ --fpu VFPv5_sp \
+
+else
+ $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/examples/build_system/make/cpu/rv32i-ilp32.mk b/examples/build_system/make/cpu/rv32i-ilp32.mk
new file mode 100644
index 0000000000..af764afc51
--- /dev/null
+++ b/examples/build_system/make/cpu/rv32i-ilp32.mk
@@ -0,0 +1,16 @@
+ifeq ($(TOOLCHAIN),gcc)
+ CFLAGS += \
+ -march=rv32i_zicsr \
+ -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),clang)
+ CFLAGS += \
+ -march=rv32i_zicsr \
+ -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),iar)
+ $(error not support)
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
diff --git a/examples/build_system/make/cpu/rv32imac-ilp32.mk b/examples/build_system/make/cpu/rv32imac-ilp32.mk
new file mode 100644
index 0000000000..19c322ebca
--- /dev/null
+++ b/examples/build_system/make/cpu/rv32imac-ilp32.mk
@@ -0,0 +1,17 @@
+ifeq ($(TOOLCHAIN),gcc)
+ CFLAGS += \
+ -march=rv32imac_zicsr \
+ -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),clang)
+ CFLAGS += \
+ -march=rv32imac_zicsr \
+ -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),iar)
+ $(error not support)
+
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
diff --git a/examples/build_system/make/make.mk b/examples/build_system/make/make.mk
index a78f4130d7..1500a51e00 100644
--- a/examples/build_system/make/make.mk
+++ b/examples/build_system/make/make.mk
@@ -109,6 +109,10 @@ INC += \
BOARD_UPPER = $(subst a,A,$(subst b,B,$(subst c,C,$(subst d,D,$(subst e,E,$(subst f,F,$(subst g,G,$(subst h,H,$(subst i,I,$(subst j,J,$(subst k,K,$(subst l,L,$(subst m,M,$(subst n,N,$(subst o,O,$(subst p,P,$(subst q,Q,$(subst r,R,$(subst s,S,$(subst t,T,$(subst u,U,$(subst v,V,$(subst w,W,$(subst x,X,$(subst y,Y,$(subst z,Z,$(subst -,_,$(BOARD))))))))))))))))))))))))))))
CFLAGS += -DBOARD_$(BOARD_UPPER)
+ifdef CFLAGS_CLI
+ CFLAGS += $(CFLAGS_CLI)
+endif
+
# use max3421 as host controller
ifeq (${MAX3421_HOST},1)
SRC_C += src/portable/analog/max3421/hcd_max3421.c
diff --git a/examples/build_system/make/rules.mk b/examples/build_system/make/rules.mk
index 7b6b339edc..86de17b6ce 100644
--- a/examples/build_system/make/rules.mk
+++ b/examples/build_system/make/rules.mk
@@ -134,6 +134,23 @@ OPENOCD_OPTION ?=
flash-openocd: $(BUILD)/$(PROJECT).elf
openocd $(OPENOCD_OPTION) -c "program $< verify reset exit"
+# --------------- openocd-wch -----------------
+# wch-linke is not supported yet in official openOCD yet. We need to either use
+# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
+# 2. compiled from https://github.com/hathach/riscv-openocd-wch or
+# https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
+# with ./configure --disable-werror --enable-wlinke --enable-ch347=no
+OPENOCD_WCH ?= /home/${USER}/app/riscv-openocd-wch/src/openocd
+OPENOCD_WCH_OPTION ?=
+flash-openocd-wch: $(BUILD)/$(PROJECT).elf
+ $(OPENOCD_WCH) $(OPENOCD_WCH_OPTION) -c init -c halt -c "flash write_image $<" -c reset -c exit
+
+# --------------- wlink-rs -----------------
+# flash with https://github.com/ch32-rs/wlink
+WLINK_RS ?= wlink
+flash-wlink-rs: $(BUILD)/$(PROJECT).elf
+ $(WLINK_RS) flash $<
+
# --------------- dfu-util -----------------
DFU_UTIL_OPTION ?= -a 0
flash-dfu-util: $(BUILD)/$(PROJECT).bin
@@ -149,6 +166,11 @@ flash-bmp: $(BUILD)/$(PROJECT).elf
debug-bmp: $(BUILD)/$(PROJECT).elf
$(GDB) -ex 'target extended-remote $(BMP)' -ex 'monitor swdp_scan' -ex 'attach 1' $<
+# --------------- TI Uniflash -----------------
+DSLITE ?= dslite.sh
+flash-uniflash: $(BUILD)/$(PROJECT).hex
+ ${DSLITE} ${UNIFLASH_OPTION} -f $<
+
#-------------- Artifacts --------------
# Create binary directory
diff --git a/examples/build_system/make/toolchain/riscv_gcc.mk b/examples/build_system/make/toolchain/riscv_gcc.mk
new file mode 100644
index 0000000000..843aff38c2
--- /dev/null
+++ b/examples/build_system/make/toolchain/riscv_gcc.mk
@@ -0,0 +1,20 @@
+# makefile for arm gcc toolchain
+
+# Can be set by family, default to ARM GCC
+CROSS_COMPILE ?= riscv-none-embed-
+
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CC) -x assembler-with-cpp
+LD = $(CC)
+
+GDB = $(CROSS_COMPILE)gdb
+OBJCOPY = $(CROSS_COMPILE)objcopy
+SIZE = $(CROSS_COMPILE)size
+
+CFLAGS += \
+ -fsingle-precision-constant \
+
+LIBS += -lgcc -lm -lnosys
+
+include ${TOP}/examples/build_system/make/toolchain/gcc_common.mk
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index c3671da698..26a808a217 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -8,6 +8,8 @@ family_initialize_project(tinyusb_device_examples ${CMAKE_CURRENT_LIST_DIR})
# family_add_subdirectory will filter what to actually add based on selected FAMILY
family_add_subdirectory(audio_4_channel_mic)
family_add_subdirectory(audio_test)
+family_add_subdirectory(audio_4_channel_mic_freertos)
+family_add_subdirectory(audio_test_freertos)
family_add_subdirectory(audio_test_multi_rate)
family_add_subdirectory(board_test)
family_add_subdirectory(cdc_dual_ports)
@@ -26,6 +28,7 @@ family_add_subdirectory(midi_test)
family_add_subdirectory(msc_dual_lun)
family_add_subdirectory(net_lwip_webserver)
family_add_subdirectory(uac2_headset)
+family_add_subdirectory(uac2_speaker_fb)
family_add_subdirectory(usbtmc)
family_add_subdirectory(video_capture)
family_add_subdirectory(video_capture_2ch)
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 10e6fe88a4..e8c40309ed 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -86,7 +86,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
old mode 100644
new mode 100755
index d17a908b6b..4d61e7f5e5
--- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
+++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
import sounddevice as sd
import matplotlib.pyplot as plt
import numpy as np
diff --git a/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt b/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt
new file mode 100644
index 0000000000..e8ca3751df
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt
@@ -0,0 +1,39 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Add libm for GCC
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_libraries(${PROJECT} PUBLIC m)
+endif()
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/audio_4_channel_mic_freertos/Makefile b/examples/device/audio_4_channel_mic_freertos/Makefile
new file mode 100644
index 0000000000..df2cdef4e8
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/Makefile
@@ -0,0 +1,38 @@
+include ../../build_system/make/make.mk
+
+FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORTABLE_PATH = $(FREERTOS_SRC)/portable/$(if $(findstring iar,$(TOOLCHAIN)),IAR,GCC)
+
+INC += \
+ src \
+ src/FreeRTOSConfig \
+ $(TOP)/hw \
+ $(TOP)/$(FREERTOS_SRC)/include \
+ $(TOP)/$(FREERTOS_PORTABLE_SRC) \
+
+# Example source
+EXAMPLE_SOURCE = \
+ src/freertos_hook.c \
+ src/main.c \
+ src/usb_descriptors.c
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+# FreeRTOS source, all files in port folder
+SRC_C += \
+ $(FREERTOS_SRC)/list.c \
+ $(FREERTOS_SRC)/queue.c \
+ $(FREERTOS_SRC)/tasks.c \
+ $(FREERTOS_SRC)/timers.c \
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
+
+SRC_S += \
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
+
+# Suppress FreeRTOS warnings
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+
+# FreeRTOS (lto + Os) linker issue
+LDFLAGS += -Wl,--undefined=vTaskSwitchContext
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_4_channel_mic_freertos/README.md b/examples/device/audio_4_channel_mic_freertos/README.md
new file mode 100644
index 0000000000..a99f28bc31
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/README.md
@@ -0,0 +1,19 @@
+# How to build example for Esp32s3
+1. Load idf environment variables (eg. using the esp-idf alias `get_idf` if configured)
+
+2. cd into examples directory
+```
+$ cd /tinyusb/examples/device/audio_4_channel_mic_freertos
+```
+
+3. Run cmake in project directory specifying the board
+```
+$ cmake -DBOARD=espressif_s3_devkitc -B build -G Ninja .
+$ ninja.exe -C build
+```
+
+4. Flash the binary onto the esp32-s3 by copy-paste of the full command output by the esp-idf build system replacing **(PORT)** with eg. /dev/ttyUSB0
+
+eg.
+
+> /home/kaspernyhus/.espressif/python_env/idf4.4_py3.8_env/bin/python ../../../../esp-idf/components/esptool_py/esptool/esptool.py -p /dev/ttyUSB0 -b 460800 --before default_reset --after hard_reset --chip esp32s3 write_flash --flash_mode dio --flash_size detect --flash_freq 80m 0x0 _build/espressif_s3_devkitc/bootloader/bootloader.bin 0x8000 _build/espressif_s3_devkitc/partition_table/partition-table.bin 0x10000 _build/espressif_s3_devkitc/audio_4_channel_mic_freertos.bin
diff --git a/examples/device/audio_4_channel_mic_freertos/sdkconfig.defaults b/examples/device/audio_4_channel_mic_freertos/sdkconfig.defaults
new file mode 100644
index 0000000000..eaa9fb9021
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/sdkconfig.defaults
@@ -0,0 +1,4 @@
+CONFIG_IDF_CMAKE=y
+CONFIG_FREERTOS_HZ=1000
+CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
diff --git a/examples/device/audio_4_channel_mic_freertos/skip.txt b/examples/device/audio_4_channel_mic_freertos/skip.txt
new file mode 100644
index 0000000000..30cd46e7e1
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/skip.txt
@@ -0,0 +1,19 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:CH32V307
+mcu:CXD56
+mcu:F1C100S
+mcu:GD32VF103
+mcu:MCXA15
+mcu:MKL25ZXX
+mcu:MSP430x5xx
+mcu:RP2040
+mcu:SAMD11
+mcu:SAMX7X
+mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
+mcu:STM32L0
+board:lpcxpresso11u37
+board:lpcxpresso1347
+family:broadcom_32bit
+family:broadcom_64bit
diff --git a/examples/device/audio_4_channel_mic_freertos/src/CMakeLists.txt b/examples/device/audio_4_channel_mic_freertos/src/CMakeLists.txt
new file mode 100644
index 0000000000..cef2b46ee7
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+ INCLUDE_DIRS "."
+ REQUIRES boards tinyusb_src)
diff --git a/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..869500ad2a
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,191 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+
+// Include MCU header
+#include "bsp/board_mcu.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+ #error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
+#endif
+
+// TODO fix later
+#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
+ extern u32 SystemCoreClock;
+#else
+ // FIXME cause redundant-decls warnings
+ extern uint32_t SystemCoreClock;
+#endif
+
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
+#define configRUN_FREERTOS_SECURE_ONLY 1
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 0
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR INT_Excep_ICU_SWINT
+#define vTickISR INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY 1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
+
+#else
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+#if defined(__NVIC_PRIO_BITS)
+ // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
+ #define configPRIO_BITS __NVIC_PRIO_BITS
+
+#elif defined(__ECLIC_INTCTLBITS)
+ // RISC-V Bumblebee core from nuclei
+ #define configPRIO_BITS __ECLIC_INTCTLBITS
+
+#elif defined(__IASMARM__)
+ // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+ // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+ // IAR user must update this to correct value of the target MCU
+ #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+ #define configPRIO_BITS 2
+
+#else
+ #error "FreeRTOS configPRIO_BITS to be defined"
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<
+#include
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if TUP_MCU_ESPRESSIF
+ // ESP-IDF need "freertos/" prefix in include path.
+ // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+ #include "freertos/FreeRTOS.h"
+ #include "freertos/semphr.h"
+ #include "freertos/queue.h"
+ #include "freertos/task.h"
+ #include "freertos/timers.h"
+
+ #define USBD_STACK_SIZE 4096
+#else
+
+ #include "FreeRTOS.h"
+ #include "semphr.h"
+ #include "queue.h"
+ #include "task.h"
+ #include "timers.h"
+
+ // Increase stack size when debug log is enabled
+ #define USBD_STACK_SIZE (4*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE
+#define AUDIO_STACK_SIZE configMINIMAL_STACK_SIZE
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+#define AUDIO_SAMPLE_RATE CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE
+
+/* Blink pattern
+ * - 250 ms : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum {
+ BLINK_NOT_MOUNTED = 250,
+ BLINK_MOUNTED = 1000,
+ BLINK_SUSPENDED = 2500,
+};
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+
+StackType_t audio_stack[AUDIO_STACK_SIZE];
+StaticTask_t audio_taskdef;
+#endif
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+bool mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
+uint16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
+uint32_t sampFreq;
+uint8_t clkValid;
+
+// Range states
+audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state
+audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
+#else
+// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000];
+#endif
+
+void led_blinking_task(void* param);
+void usb_device_task(void* param);
+void audio_task(void* param);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+ board_init();
+
+ // Init values
+ sampFreq = AUDIO_SAMPLE_RATE;
+ clkValid = 1;
+
+ sampleFreqRng.wNumSubRanges = 1;
+ sampleFreqRng.subrange[0].bMin = AUDIO_SAMPLE_RATE;
+ sampleFreqRng.subrange[0].bMax = AUDIO_SAMPLE_RATE;
+ sampleFreqRng.subrange[0].bRes = 0;
+
+ // Generate dummy data
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+ uint16_t * p_buff = i2s_dummy_buffer[0];
+ uint16_t dataVal = 0;
+ for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+ {
+ // CH0 saw wave
+ *p_buff++ = dataVal;
+ // CH1 inverted saw wave
+ *p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+ dataVal+= 32;
+ }
+ p_buff = i2s_dummy_buffer[1];
+ for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+ {
+ // CH3 square wave
+ *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000;
+ // CH4 sinus wave
+ float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+ *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
+ }
+#else
+ uint16_t * p_buff = i2s_dummy_buffer;
+ uint16_t dataVal = 0;
+ for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+ {
+ // CH0 saw wave
+ *p_buff++ = dataVal;
+ // CH1 inverted saw wave
+ *p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+ dataVal+= 32;
+ // CH3 square wave
+ *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000;
+ // CH4 sinus wave
+ float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+ *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
+ }
+#endif
+
+#if configSUPPORT_STATIC_ALLOCATION
+ // blinky task
+ xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+
+ // Create a task for tinyusb device stack
+ xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+
+ // Create a task for audio
+ xTaskCreateStatic(audio_task, "audio", AUDIO_STACK_SIZE, NULL, configMAX_PRIORITIES-1, audio_stack, &audio_taskdef);
+#else
+ xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+ xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+ xTaskCreate(audio_task, "audio", AUDIO_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+#endif
+
+ // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+ #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ vTaskStartScheduler();
+ #endif
+
+ return 0;
+}
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+void app_main(void)
+{
+ main();
+}
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void* param)
+{
+ (void) param;
+
+ // init device stack on configured roothub port
+ // This should be called after scheduler/kernel is started.
+ // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
+ // RTOS forever loop
+ while (1)
+ {
+ // tinyusb device task
+ tud_task();
+ }
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+ blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+ blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+ (void) remote_wakeup_en;
+ blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void* param)
+{
+ (void) param;
+ // Yet to be filled - e.g. read audio from I2S buffer.
+ // Here we simulate a I2S receive callback every 1ms.
+ while (1) {
+ vTaskDelay(1);
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+ // Write I2S buffer into FIFO
+ for (uint8_t cnt=0; cnt < 2; cnt++)
+ {
+ tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
+ }
+#else
+ tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
+#endif
+ }
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when audio class specific set request received for an EP
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+ (void) pBuff;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) ep;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an interface
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+ (void) pBuff;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) itf;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+ uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+ (void) itf;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // If request is for our feature unit
+ if ( entityID == 2 )
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_FU_CTRL_MUTE:
+ // Request uses format layout 1
+ TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_1_t));
+
+ mute[channelNum] = ((audio_control_cur_1_t*) pBuff)->bCur;
+
+ TU_LOG2(" Set Mute: %d of channel: %u\r\n", mute[channelNum], channelNum);
+ return true;
+
+ case AUDIO_FU_CTRL_VOLUME:
+ // Request uses format layout 2
+ TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
+
+ volume[channelNum] = ((audio_control_cur_2_t*) pBuff)->bCur;
+
+ TU_LOG2(" Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
+ return true;
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an EP
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) ep;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an interface
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) itf;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ // uint8_t itf = TU_U16_LOW(p_request->wIndex); // Since we have only one audio function implemented, we do not need the itf value
+ uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+ // Input terminal (Microphone input)
+ if (entityID == 1)
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_TE_CTRL_CONNECTOR:
+ {
+ // The terminal connector control only has a get request with only the CUR attribute.
+ audio_desc_channel_cluster_t ret;
+
+ // Those are dummy values for now
+ ret.bNrChannels = 1;
+ ret.bmChannelConfig = 0;
+ ret.iChannelNames = 0;
+
+ TU_LOG2(" Get terminal connector\r\n");
+
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+ }
+ break;
+
+ // Unknown/Unsupported control selector
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ // Feature unit
+ if (entityID == 2)
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_FU_CTRL_MUTE:
+ // Audio control mute cur parameter block consists of only one byte - we thus can send it right away
+ // There does not exist a range parameter block for mute
+ TU_LOG2(" Get Mute of channel: %u\r\n", channelNum);
+ return tud_control_xfer(rhport, p_request, &mute[channelNum], 1);
+
+ case AUDIO_FU_CTRL_VOLUME:
+ switch ( p_request->bRequest )
+ {
+ case AUDIO_CS_REQ_CUR:
+ TU_LOG2(" Get Volume of channel: %u\r\n", channelNum);
+ return tud_control_xfer(rhport, p_request, &volume[channelNum], sizeof(volume[channelNum]));
+
+ case AUDIO_CS_REQ_RANGE:
+ TU_LOG2(" Get Volume range of channel: %u\r\n", channelNum);
+
+ // Copy values - only for testing - better is version below
+ audio_control_range_2_n_t(1)
+ ret;
+
+ ret.wNumSubRanges = 1;
+ ret.subrange[0].bMin = -90; // -90 dB
+ ret.subrange[0].bMax = 90; // +90 dB
+ ret.subrange[0].bRes = 1; // 1 dB steps
+
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ break;
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ // Clock Source unit
+ if ( entityID == 4 )
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_CS_CTRL_SAM_FREQ:
+ // channelNum is always zero in this case
+ switch ( p_request->bRequest )
+ {
+ case AUDIO_CS_REQ_CUR:
+ TU_LOG2(" Get Sample Freq.\r\n");
+ // Buffered control transfer is needed for IN flow control to work
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+
+ case AUDIO_CS_REQ_RANGE:
+ TU_LOG2(" Get Sample Freq. range\r\n");
+ return tud_control_xfer(rhport, p_request, &sampleFreqRng, sizeof(sampleFreqRng));
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ break;
+
+ case AUDIO_CS_CTRL_CLK_VALID:
+ // Only cur attribute exists for this request
+ TU_LOG2(" Get Sample Freq. valid\r\n");
+ return tud_control_xfer(rhport, p_request, &clkValid, sizeof(clkValid));
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ TU_LOG2(" Unsupported entity: %d\r\n", entityID);
+ return false; // Yet not implemented
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+ (void) rhport;
+ (void) itf;
+ (void) ep_in;
+ (void) cur_alt_setting;
+
+
+ // In read world application data flow is driven by I2S clock,
+ // both tud_audio_tx_done_pre_load_cb() & tud_audio_tx_done_post_load_cb() are hardly used.
+ // For example in your I2S receive callback:
+ // void I2S_Rx_Callback(int channel, const void* data, uint16_t samples)
+ // {
+ // tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO);
+ // }
+
+ return true;
+}
+
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+ (void) rhport;
+ (void) n_bytes_copied;
+ (void) itf;
+ (void) ep_in;
+ (void) cur_alt_setting;
+
+ return true;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+ (void) p_request;
+
+ return true;
+}
+
+///--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void* param) {
+ (void) param;
+ static uint32_t start_ms = 0;
+ static bool led_state = false;
+
+ while (1) {
+ // Blink every interval ms
+ vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+ start_ms += blink_interval_ms;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state; // toggle
+ }
+}
diff --git a/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py
new file mode 100755
index 0000000000..4d5ca28d65
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py
@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+import sounddevice as sd
+import matplotlib.pyplot as plt
+import numpy as np
+import platform
+
+if __name__ == '__main__':
+
+ # If you got "ValueError: No input device matching", that is because your PC name example device
+ # differently from tested list below. Uncomment the next line to see full list and try to pick correct one
+ # print(sd.query_devices())
+
+ fs = 48000 # Sample rate
+ duration = 100e-3 # Duration of recording
+
+ if platform.system() == 'Windows':
+ # WDM-KS is needed since there are more than one MicNode device APIs (at least in Windows)
+ device = 'Microphone (MicNode_4_Ch), Windows WDM-KS'
+ elif platform.system() == 'Darwin':
+ device = 'MicNode_4_Ch'
+ else:
+ device ='default'
+
+ myrecording = sd.rec(int(duration * fs), samplerate=fs, channels=4, dtype='int16', device=device)
+ print('Waiting...')
+ sd.wait() # Wait until recording is finished
+ print('Done!')
+
+ time = np.arange(0, duration, 1 / fs) # time vector
+ plt.plot(time, myrecording)
+ plt.xlabel('Time [s]')
+ plt.ylabel('Amplitude')
+ plt.title('MicNode 4 Channel')
+ plt.show()
diff --git a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h
new file mode 100644
index 0000000000..88f20278b5
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h
@@ -0,0 +1,148 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+// This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_FREERTOS
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUP_MCU_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED 1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO 1
+#define CFG_TUD_CDC 0
+#define CFG_TUD_MSC 0
+#define CFG_TUD_HID 0
+#define CFG_TUD_MIDI 0
+#define CFG_TUD_VENDOR 0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+// Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE 48000
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN TUD_AUDIO_MIC_FOUR_CH_DESC_LEN
+
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 1
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ 64
+
+#define CFG_TUD_AUDIO_ENABLE_EP_IN 1
+#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX 2 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 4 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
+#define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_ENABLE_ENCODING 1
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL 1
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN
+
+#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1
+#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
+#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device
+
+#else
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/audio_4_channel_mic_freertos/src/usb_descriptors.c b/examples/device/audio_4_channel_mic_freertos/src/usb_descriptors.c
new file mode 100644
index 0000000000..728a5f9cec
--- /dev/null
+++ b/examples/device/audio_4_channel_mic_freertos/src/usb_descriptors.c
@@ -0,0 +1,179 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ * [MSB] AUDIO | MIDI | HID | MSC | CDC [LSB]
+ */
+#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) )
+#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+ _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = 0x0200,
+
+ // Use Interface Association Descriptor (IAD) for Audio
+ // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+ .idVendor = 0xCafe,
+ .idProduct = USB_PID,
+ .bcdDevice = 0x0100,
+
+ .iManufacturer = 0x01,
+ .iProduct = 0x02,
+ .iSerialNumber = 0x03,
+
+ .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+ return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+enum
+{
+ ITF_NUM_AUDIO_CONTROL = 0,
+ ITF_NUM_AUDIO_STREAMING,
+ ITF_NUM_TOTAL
+};
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_FOUR_CH_DESC_LEN)
+
+#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
+ // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+ // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+ #define EPNUM_AUDIO 0x03
+
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
+ // nRF5x ISO can only be endpoint 8
+ #define EPNUM_AUDIO 0x08
+
+#else
+ #define EPNUM_AUDIO 0x01
+#endif
+
+uint8_t const desc_configuration[] =
+{
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+ // Interface number, string index, EP Out & EP In address, EP size
+ TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+ (void) index; // for multiple configurations
+ return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] = {
+ (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+ "PaniRCorp", // 1: Manufacturer
+ "MicNode_4_Ch", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "UAC2", // 4: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+ (void) langid;
+ size_t chr_count;
+
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
+
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
+
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+ const char *str = string_desc_arr[index];
+
+ // Cap at max char
+ chr_count = strlen(str);
+ size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+ if ( chr_count > max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
+ }
+
+ // first byte is length (including header), second byte is string type
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+ return _desc_str;
+}
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index 06783ccfb1..018c48994d 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -42,10 +42,6 @@
// MACRO CONSTANT TYPEDEF PROTYPES
//--------------------------------------------------------------------+
-#ifndef AUDIO_SAMPLE_RATE
-#define AUDIO_SAMPLE_RATE 48000
-#endif
-
/* Blink pattern
* - 250 ms : device not mounted
* - 1000 ms : device mounted
@@ -83,19 +79,23 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
}
// Init values
- sampFreq = AUDIO_SAMPLE_RATE;
+ sampFreq = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
clkValid = 1;
sampleFreqRng.wNumSubRanges = 1;
- sampleFreqRng.subrange[0].bMin = AUDIO_SAMPLE_RATE;
- sampleFreqRng.subrange[0].bMax = AUDIO_SAMPLE_RATE;
+ sampleFreqRng.subrange[0].bMin = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
+ sampleFreqRng.subrange[0].bMax = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
sampleFreqRng.subrange[0].bRes = 0;
while (1)
diff --git a/examples/device/audio_test/src/plot_audio_samples.py b/examples/device/audio_test/src/plot_audio_samples.py
old mode 100644
new mode 100755
index 1504684a64..ea6aa661e3
--- a/examples/device/audio_test/src/plot_audio_samples.py
+++ b/examples/device/audio_test/src/plot_audio_samples.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
import sounddevice as sd
import matplotlib.pyplot as plt
import numpy as np
diff --git a/examples/device/audio_test/src/tusb_config.h b/examples/device/audio_test/src/tusb_config.h
index 9f38612a9c..8c021e23ca 100644
--- a/examples/device/audio_test/src/tusb_config.h
+++ b/examples/device/audio_test/src/tusb_config.h
@@ -106,6 +106,7 @@ extern "C" {
//--------------------------------------------------------------------
// Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE 48000
#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN TUD_AUDIO_MIC_ONE_CH_DESC_LEN
#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 1 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
@@ -114,9 +115,9 @@ extern "C" {
#define CFG_TUD_AUDIO_ENABLE_EP_IN 1
#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX 2 // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below
#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 1 // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
-#define CFG_TUD_AUDIO_EP_SZ_IN (48 + 1) * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX // 48 Samples (48 kHz) x 2 Bytes/Sample x CFG_TUD_AUDIO_N_CHANNELS_TX Channels - One extra sample is needed for asynchronous transfer adjustment, see feedback EP
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN // Maximum EP IN size for all AS alternate settings used
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN + 1
+#define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 8 : 1) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
#ifdef __cplusplus
}
diff --git a/examples/device/audio_test_freertos/CMakeLists.txt b/examples/device/audio_test_freertos/CMakeLists.txt
new file mode 100644
index 0000000000..eb22014fbc
--- /dev/null
+++ b/examples/device/audio_test_freertos/CMakeLists.txt
@@ -0,0 +1,34 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/audio_test_freertos/Makefile b/examples/device/audio_test_freertos/Makefile
new file mode 100644
index 0000000000..df2cdef4e8
--- /dev/null
+++ b/examples/device/audio_test_freertos/Makefile
@@ -0,0 +1,38 @@
+include ../../build_system/make/make.mk
+
+FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORTABLE_PATH = $(FREERTOS_SRC)/portable/$(if $(findstring iar,$(TOOLCHAIN)),IAR,GCC)
+
+INC += \
+ src \
+ src/FreeRTOSConfig \
+ $(TOP)/hw \
+ $(TOP)/$(FREERTOS_SRC)/include \
+ $(TOP)/$(FREERTOS_PORTABLE_SRC) \
+
+# Example source
+EXAMPLE_SOURCE = \
+ src/freertos_hook.c \
+ src/main.c \
+ src/usb_descriptors.c
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+# FreeRTOS source, all files in port folder
+SRC_C += \
+ $(FREERTOS_SRC)/list.c \
+ $(FREERTOS_SRC)/queue.c \
+ $(FREERTOS_SRC)/tasks.c \
+ $(FREERTOS_SRC)/timers.c \
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
+
+SRC_S += \
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
+
+# Suppress FreeRTOS warnings
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+
+# FreeRTOS (lto + Os) linker issue
+LDFLAGS += -Wl,--undefined=vTaskSwitchContext
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/audio_test_freertos/README.md b/examples/device/audio_test_freertos/README.md
new file mode 100644
index 0000000000..9477fcd78f
--- /dev/null
+++ b/examples/device/audio_test_freertos/README.md
@@ -0,0 +1,19 @@
+# How to build example for Esp32s3
+1. Load idf environment variables (eg. using the esp-idf alias `get_idf` if configured)
+
+2. cd into examples directory
+```
+$ cd /tinyusb/examples/device/audio_test_freertos
+```
+
+3. Run cmake in project directory specifying the board
+```
+$ cmake -DBOARD=espressif_s3_devkitc -B build -G Ninja .
+$ ninja.exe -C build
+```
+
+4. Flash the binary onto the esp32-s3 by copy-paste of the full command output by the esp-idf build system replacing **(PORT)** with eg. /dev/ttyUSB0
+
+eg.
+
+> /home/kaspernyhus/.espressif/python_env/idf4.4_py3.8_env/bin/python ../../../../esp-idf/components/esptool_py/esptool/esptool.py -p /dev/ttyUSB0 -b 460800 --before default_reset --after hard_reset --chip esp32s3 write_flash --flash_mode dio --flash_size detect --flash_freq 80m 0x0 _build/espressif_s3_devkitc/bootloader/bootloader.bin 0x8000 _build/espressif_s3_devkitc/partition_table/partition-table.bin 0x10000 _build/espressif_s3_devkitc/audio_test_freertos.bin
diff --git a/examples/device/audio_test_freertos/sdkconfig.defaults b/examples/device/audio_test_freertos/sdkconfig.defaults
new file mode 100644
index 0000000000..83871619e6
--- /dev/null
+++ b/examples/device/audio_test_freertos/sdkconfig.defaults
@@ -0,0 +1,3 @@
+CONFIG_IDF_CMAKE=y
+CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
diff --git a/examples/device/audio_test_freertos/skip.txt b/examples/device/audio_test_freertos/skip.txt
new file mode 100644
index 0000000000..650bf355b2
--- /dev/null
+++ b/examples/device/audio_test_freertos/skip.txt
@@ -0,0 +1,16 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:CH32V307
+mcu:CXD56
+mcu:F1C100S
+mcu:GD32VF103
+mcu:MCXA15
+mcu:MKL25ZXX
+mcu:MSP430x5xx
+mcu:RP2040
+mcu:SAMD11
+mcu:SAMX7X
+mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
+family:broadcom_32bit
+family:broadcom_64bit
diff --git a/examples/device/audio_test_freertos/src/CMakeLists.txt b/examples/device/audio_test_freertos/src/CMakeLists.txt
new file mode 100644
index 0000000000..cef2b46ee7
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+ INCLUDE_DIRS "."
+ REQUIRES boards tinyusb_src)
diff --git a/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..869500ad2a
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,191 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+
+// Include MCU header
+#include "bsp/board_mcu.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+ #error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
+#endif
+
+// TODO fix later
+#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
+ extern u32 SystemCoreClock;
+#else
+ // FIXME cause redundant-decls warnings
+ extern uint32_t SystemCoreClock;
+#endif
+
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
+#define configRUN_FREERTOS_SECURE_ONLY 1
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 0
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR INT_Excep_ICU_SWINT
+#define vTickISR INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY 1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
+
+#else
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+#if defined(__NVIC_PRIO_BITS)
+ // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
+ #define configPRIO_BITS __NVIC_PRIO_BITS
+
+#elif defined(__ECLIC_INTCTLBITS)
+ // RISC-V Bumblebee core from nuclei
+ #define configPRIO_BITS __ECLIC_INTCTLBITS
+
+#elif defined(__IASMARM__)
+ // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+ // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+ // IAR user must update this to correct value of the target MCU
+ #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+ #define configPRIO_BITS 2
+
+#else
+ #error "FreeRTOS configPRIO_BITS to be defined"
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if TUP_MCU_ESPRESSIF
+ // ESP-IDF need "freertos/" prefix in include path.
+ // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+ #include "freertos/FreeRTOS.h"
+ #include "freertos/semphr.h"
+ #include "freertos/queue.h"
+ #include "freertos/task.h"
+ #include "freertos/timers.h"
+
+ #define USBD_STACK_SIZE 4096
+#else
+
+ #include "FreeRTOS.h"
+ #include "semphr.h"
+ #include "queue.h"
+ #include "task.h"
+ #include "timers.h"
+
+ // Increase stack size when debug log is enabled
+ #define USBD_STACK_SIZE (4*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum {
+ BLINK_NOT_MOUNTED = 250,
+ BLINK_MOUNTED = 1000,
+ BLINK_SUSPENDED = 2500,
+};
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+#endif
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+bool mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
+uint16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
+uint32_t sampFreq;
+uint8_t clkValid;
+
+// Range states
+audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state
+audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state
+
+// Audio test data
+uint16_t test_buffer_audio[(CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2];
+uint16_t startVal = 0;
+
+void led_blinking_task(void* param);
+void usb_device_task(void* param);
+void audio_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+ board_init();
+
+ // Init values
+ sampFreq = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
+ clkValid = 1;
+
+ sampleFreqRng.wNumSubRanges = 1;
+ sampleFreqRng.subrange[0].bMin = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
+ sampleFreqRng.subrange[0].bMax = CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE;
+ sampleFreqRng.subrange[0].bRes = 0;
+
+#if configSUPPORT_STATIC_ALLOCATION
+ // blinky task
+ xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+
+ // Create a task for tinyusb device stack
+ xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+#else
+ xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+ xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+#endif
+
+ // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+ #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ vTaskStartScheduler();
+ #endif
+
+ return 0;
+}
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+void app_main(void)
+{
+ main();
+}
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void* param)
+{
+ (void) param;
+
+ // init device stack on configured roothub port
+ // This should be called after scheduler/kernel is started.
+ // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
+ // RTOS forever loop
+ while (1)
+ {
+ // tinyusb device task
+ tud_task();
+ }
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void) {
+ blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+ blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en) {
+ (void) remote_wakeup_en;
+ blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void) {
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void)
+{
+ // Yet to be filled - e.g. put meas data into TX FIFOs etc.
+ // asm("nop");
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when audio class specific set request received for an EP
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+ (void) pBuff;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) ep;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an interface
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+ (void) pBuff;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) itf;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+ uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+ (void) itf;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // If request is for our feature unit
+ if ( entityID == 2 )
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_FU_CTRL_MUTE:
+ // Request uses format layout 1
+ TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_1_t));
+
+ mute[channelNum] = ((audio_control_cur_1_t*) pBuff)->bCur;
+
+ TU_LOG2(" Set Mute: %d of channel: %u\r\n", mute[channelNum], channelNum);
+ return true;
+
+ case AUDIO_FU_CTRL_VOLUME:
+ // Request uses format layout 2
+ TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
+
+ volume[channelNum] = (uint16_t) ((audio_control_cur_2_t*) pBuff)->bCur;
+
+ TU_LOG2(" Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
+ return true;
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an EP
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) ep;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an interface
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) itf;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ // uint8_t itf = TU_U16_LOW(p_request->wIndex); // Since we have only one audio function implemented, we do not need the itf value
+ uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+ // Input terminal (Microphone input)
+ if (entityID == 1)
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_TE_CTRL_CONNECTOR:
+ {
+ // The terminal connector control only has a get request with only the CUR attribute.
+ audio_desc_channel_cluster_t ret;
+
+ // Those are dummy values for now
+ ret.bNrChannels = 1;
+ ret.bmChannelConfig = (audio_channel_config_t) 0;
+ ret.iChannelNames = 0;
+
+ TU_LOG2(" Get terminal connector\r\n");
+
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+ }
+ break;
+
+ // Unknown/Unsupported control selector
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ // Feature unit
+ if (entityID == 2)
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_FU_CTRL_MUTE:
+ // Audio control mute cur parameter block consists of only one byte - we thus can send it right away
+ // There does not exist a range parameter block for mute
+ TU_LOG2(" Get Mute of channel: %u\r\n", channelNum);
+ return tud_control_xfer(rhport, p_request, &mute[channelNum], 1);
+
+ case AUDIO_FU_CTRL_VOLUME:
+ switch ( p_request->bRequest )
+ {
+ case AUDIO_CS_REQ_CUR:
+ TU_LOG2(" Get Volume of channel: %u\r\n", channelNum);
+ return tud_control_xfer(rhport, p_request, &volume[channelNum], sizeof(volume[channelNum]));
+
+ case AUDIO_CS_REQ_RANGE:
+ TU_LOG2(" Get Volume range of channel: %u\r\n", channelNum);
+
+ // Copy values - only for testing - better is version below
+ audio_control_range_2_n_t(1)
+ ret;
+
+ ret.wNumSubRanges = 1;
+ ret.subrange[0].bMin = -90; // -90 dB
+ ret.subrange[0].bMax = 90; // +90 dB
+ ret.subrange[0].bRes = 1; // 1 dB steps
+
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ break;
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ // Clock Source unit
+ if ( entityID == 4 )
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_CS_CTRL_SAM_FREQ:
+ // channelNum is always zero in this case
+ switch ( p_request->bRequest )
+ {
+ case AUDIO_CS_REQ_CUR:
+ TU_LOG2(" Get Sample Freq.\r\n");
+ return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+
+ case AUDIO_CS_REQ_RANGE:
+ TU_LOG2(" Get Sample Freq. range\r\n");
+ return tud_control_xfer(rhport, p_request, &sampleFreqRng, sizeof(sampleFreqRng));
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ break;
+
+ case AUDIO_CS_CTRL_CLK_VALID:
+ // Only cur attribute exists for this request
+ TU_LOG2(" Get Sample Freq. valid\r\n");
+ return tud_control_xfer(rhport, p_request, &clkValid, sizeof(clkValid));
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ TU_LOG2(" Unsupported entity: %d\r\n", entityID);
+ return false; // Yet not implemented
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+ (void) rhport;
+ (void) itf;
+ (void) ep_in;
+ (void) cur_alt_setting;
+
+ tud_audio_write ((uint8_t *)test_buffer_audio, CFG_TUD_AUDIO_EP_SZ_IN - 2);
+
+ return true;
+}
+
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+ (void) rhport;
+ (void) n_bytes_copied;
+ (void) itf;
+ (void) ep_in;
+ (void) cur_alt_setting;
+
+ for (size_t cnt = 0; cnt < (CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2; cnt++)
+ {
+ test_buffer_audio[cnt] = startVal++;
+ }
+
+ return true;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+ (void) p_request;
+ startVal = 0;
+
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void* param) {
+ (void) param;
+ static uint32_t start_ms = 0;
+ static bool led_state = false;
+
+ while (1) {
+ // Blink every interval ms
+ vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+ start_ms += blink_interval_ms;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state; // toggle
+ }
+}
diff --git a/examples/device/audio_test_freertos/src/plot_audio_samples.py b/examples/device/audio_test_freertos/src/plot_audio_samples.py
new file mode 100755
index 0000000000..46738eb3f8
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/plot_audio_samples.py
@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+import sounddevice as sd
+import matplotlib.pyplot as plt
+import numpy as np
+import platform
+
+if __name__ == '__main__':
+
+ # If you got "ValueError: No input device matching", that is because your PC name example device
+ # differently from tested list below. Uncomment the next line to see full list and try to pick correct one
+ # print(sd.query_devices())
+
+ fs = 48000 # Sample rate
+ duration = 1000e-3 # Duration of recording
+
+ if platform.system() == 'Windows':
+ # MME is needed since there are more than one MicNode device APIs (at least in Windows)
+ device = 'Microphone (MicNode) MME'
+ elif platform.system() == 'Darwin':
+ device = 'MicNode'
+ else:
+ device ='default'
+
+ myrecording = sd.rec(int(duration * fs), samplerate=fs, channels=1, dtype='int16', device=device)
+ print('Waiting...')
+ sd.wait() # Wait until recording is finished
+ print('Done!')
+
+ time = np.arange(0, duration, 1 / fs) # time vector
+ plt.plot(time, myrecording)
+ plt.xlabel('Time [s]')
+ plt.ylabel('Amplitude')
+ plt.title('MicNode')
+ plt.show()
diff --git a/examples/device/audio_test_freertos/src/tusb_config.h b/examples/device/audio_test_freertos/src/tusb_config.h
new file mode 100644
index 0000000000..8b376a4c3c
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/tusb_config.h
@@ -0,0 +1,132 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+// This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_FREERTOS
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TUP_MCU_ESPRESSIF
+#define CFG_TUSB_OS_INC_PATH freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED 1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG 0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO 1
+#define CFG_TUD_CDC 0
+#define CFG_TUD_MSC 0
+#define CFG_TUD_HID 0
+#define CFG_TUD_MIDI 0
+#define CFG_TUD_VENDOR 0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+// Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE 48000
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN TUD_AUDIO_MIC_ONE_CH_DESC_LEN
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 1 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ 64 // Size of control request buffer
+
+#define CFG_TUD_AUDIO_ENABLE_EP_IN 1
+#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX 2 // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 1 // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
+#define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 8 : 1) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/audio_test_freertos/src/usb_descriptors.c b/examples/device/audio_test_freertos/src/usb_descriptors.c
new file mode 100644
index 0000000000..9864377f60
--- /dev/null
+++ b/examples/device/audio_test_freertos/src/usb_descriptors.c
@@ -0,0 +1,181 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ * [MSB] AUDIO | MIDI | HID | MSC | CDC [LSB]
+ */
+#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) )
+#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+ _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = 0x0200,
+
+ // Use Interface Association Descriptor (IAD) for Audio
+ // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+ .idVendor = 0xCafe,
+ .idProduct = USB_PID,
+ .bcdDevice = 0x0100,
+
+ .iManufacturer = 0x01,
+ .iProduct = 0x02,
+ .iSerialNumber = 0x03,
+
+ .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+ return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+enum
+{
+ ITF_NUM_AUDIO_CONTROL = 0,
+ ITF_NUM_AUDIO_STREAMING,
+ ITF_NUM_TOTAL
+};
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_ONE_CH_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+ // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+ // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+ #define EPNUM_AUDIO 0x03
+
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
+ // nRF5x ISO can only be endpoint 8
+ #define EPNUM_AUDIO 0x08
+
+#else
+ #define EPNUM_AUDIO 0x01
+#endif
+
+uint8_t const desc_configuration[] =
+{
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+ // Interface number, string index, EP Out & EP In address, EP size
+ TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+ (void) index; // for multiple configurations
+ return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+ (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+ "PaniRCorp", // 1: Manufacturer
+ "MicNode", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "UAC2", // 4: Audio Interface
+
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+ (void) langid;
+ size_t chr_count;
+
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
+
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
+
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+ const char *str = string_desc_arr[index];
+
+ // Cap at max char
+ chr_count = strlen(str);
+ size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+ if ( chr_count > max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
+ }
+
+ // first byte is length (including header), second byte is string type
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+ return _desc_str;
+}
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index 2ff7f10bd0..f9dcd1b8a4 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -97,7 +97,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
old mode 100644
new mode 100755
index c92e49957a..1f33a003ee
--- a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
+++ b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
import sounddevice as sd
import matplotlib.pyplot as plt
import numpy as np
diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h
index 1a27cc87f2..89c27d1c0f 100644
--- a/examples/device/board_test/src/tusb_config.h
+++ b/examples/device/board_test/src/tusb_config.h
@@ -30,11 +30,6 @@
extern "C" {
#endif
-// board_test example is special example that doesn't enable device or host stack
-// This can cause some TinyUSB API missing, this define hack to allow us to fill those API
-// to pass the compilation process
-#define tud_int_handler(x)
-
//--------------------------------------------------------------------
// COMMON CONFIGURATION
//--------------------------------------------------------------------
@@ -49,7 +44,7 @@
#endif
// Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
#define CFG_TUSB_OS_INC_PATH freertos/
#endif
diff --git a/examples/device/cdc_dual_ports/skip.txt b/examples/device/cdc_dual_ports/skip.txt
new file mode 100644
index 0000000000..75184e5e50
--- /dev/null
+++ b/examples/device/cdc_dual_ports/skip.txt
@@ -0,0 +1,2 @@
+board:stm32f407disco
+board:stm32f411disco
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 2190b984ac..e5432eb236 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -52,7 +52,11 @@ int main(void) {
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
@@ -128,6 +132,26 @@ static void cdc_task(void) {
}
}
+// Invoked when cdc when line state changed e.g connected/disconnected
+// Use to reset to DFU when disconnect with 1200 bps
+void tud_cdc_line_state_cb(uint8_t instance, bool dtr, bool rts) {
+ (void)rts;
+
+ // DTR = false is counted as disconnected
+ if (!dtr) {
+ // touch1200 only with first CDC instance (Serial)
+ if (instance == 0) {
+ cdc_line_coding_t coding;
+ tud_cdc_get_line_coding(&coding);
+ if (coding.bit_rate == 1200) {
+ if (board_reset_to_bootloader) {
+ board_reset_to_bootloader();
+ }
+ }
+ }
+ }
+}
+
//--------------------------------------------------------------------+
// BLINKING TASK
//--------------------------------------------------------------------+
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index 76907de096..68eedd964c 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -98,19 +98,19 @@ enum
#define EPNUM_CDC_1_OUT 0x05
#define EPNUM_CDC_1_IN 0x85
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
- // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
- // e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_CDC_0_NOTIF 0x81
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+ // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+ // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+ #define EPNUM_CDC_0_NOTIF 0x83
#define EPNUM_CDC_0_OUT 0x02
- #define EPNUM_CDC_0_IN 0x83
+ #define EPNUM_CDC_0_IN 0x81
- #define EPNUM_CDC_1_NOTIF 0x84
+ #define EPNUM_CDC_1_NOTIF 0x86
#define EPNUM_CDC_1_OUT 0x05
- #define EPNUM_CDC_1_IN 0x86
+ #define EPNUM_CDC_1_IN 0x84
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_CDC_0_NOTIF 0x81
#define EPNUM_CDC_0_OUT 0x02
diff --git a/examples/device/cdc_msc/skip.txt b/examples/device/cdc_msc/skip.txt
index 833fd072c0..b6252e4050 100644
--- a/examples/device/cdc_msc/skip.txt
+++ b/examples/device/cdc_msc/skip.txt
@@ -1,2 +1,3 @@
mcu:SAMD11
family:espressif
+board:ch32v203g_r0_1v0
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index 4581a3babe..f36c910d7a 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -51,7 +51,11 @@ int main(void) {
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 2afa249037..4b6b88041e 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -93,19 +93,7 @@ enum {
#define EPNUM_MSC_OUT 0x05
#define EPNUM_MSC_IN 0x85
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
- // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
- // e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_CDC_NOTIF 0x81
- #define EPNUM_CDC_OUT 0x02
- #define EPNUM_CDC_IN 0x83
-
- #define EPNUM_MSC_OUT 0x04
- #define EPNUM_MSC_IN 0x85
-
#elif CFG_TUSB_MCU == OPT_MCU_CXD56
- // CXD56 doesn't support a same endpoint number with different direction IN and OUT
- // e.g EP1 OUT & EP1 IN cannot exist together
// CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
// 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
#define EPNUM_CDC_NOTIF 0x83
@@ -115,8 +103,8 @@ enum {
#define EPNUM_MSC_OUT 0x05
#define EPNUM_MSC_IN 0x84
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_CDC_NOTIF 0x81
#define EPNUM_CDC_OUT 0x02
diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
index a6f96b2885..b73a6d8dd6 100644
--- a/examples/device/cdc_msc_freertos/skip.txt
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -1,7 +1,10 @@
+mcu:CH32V103
+mcu:CH32V20X
mcu:CH32V307
mcu:CXD56
mcu:F1C100S
mcu:GD32VF103
+mcu:MCXA15
mcu:MKL25ZXX
mcu:MSP430x5xx
mcu:RP2040
@@ -9,5 +12,6 @@ mcu:SAMD11
mcu:SAMX7X
mcu:VALENTYUSB_EPTRI
mcu:RAXXX
+mcu:STM32L0
family:broadcom_32bit
family:broadcom_64bit
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 6cc7a6577c..869500ad2a 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -67,6 +67,7 @@
#define configENABLE_FPU 1
#define configENABLE_TRUSTZONE 0
#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
+#define configRUN_FREERTOS_SECURE_ONLY 1
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index e94e8eaec4..f70267e335 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -30,7 +30,7 @@
#include "bsp/board_api.h"
#include "tusb.h"
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
@@ -111,14 +111,14 @@ int main(void) {
#endif
// skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if !TUP_MCU_ESPRESSIF
vTaskStartScheduler();
#endif
return 0;
}
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
void app_main(void) {
main();
}
@@ -132,7 +132,11 @@ static void usb_device_task(void *param) {
// init device stack on configured roothub port
// This should be called after scheduler/kernel is started.
// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index c8a04bb745..d2f8628f13 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -28,6 +28,9 @@
#if CFG_TUD_MSC
+// whether host does safe-eject
+static bool ejected = false;
+
// Some MCU doesn't have enough 8KB SRAM to store the whole disk
// We will use Flash as read-only disk with board that has
// CFG_EXAMPLE_MSC_READONLY defined
@@ -137,7 +140,14 @@ bool tud_msc_test_unit_ready_cb(uint8_t lun)
{
(void) lun;
- return true; // RAM disk is always ready
+ // RAM disk is ready until ejected
+ if (ejected) {
+ // Additional Sense 3A-00 is NOT_FOUND
+ tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3a, 0x00);
+ return false;
+ }
+
+ return true;
}
// Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size
@@ -166,6 +176,7 @@ bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, boo
}else
{
// unload disk storage
+ ejected = true;
}
}
@@ -187,6 +198,17 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
return (int32_t) bufsize;
}
+bool tud_msc_is_writable_cb (uint8_t lun)
+{
+ (void) lun;
+
+#ifdef CFG_EXAMPLE_MSC_READONLY
+ return false;
+#else
+ return true;
+#endif
+}
+
// Callback invoked when received WRITE10 command.
// Process data in buffer to disk's storage and return number of written bytes
int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize)
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index 91efe7d40c..e743c91484 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -59,7 +59,7 @@
#endif
// Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
#define CFG_TUSB_OS_INC_PATH freertos/
#endif
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index 9c29701c72..405a57fe45 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -42,8 +42,7 @@
//--------------------------------------------------------------------+
// Device Descriptors
//--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
+tusb_desc_device_t const desc_device = {
.bLength = sizeof(tusb_desc_device_t),
.bDescriptorType = TUSB_DESC_DEVICE,
.bcdUSB = USB_BCD,
@@ -69,8 +68,7 @@ tusb_desc_device_t const desc_device =
// Invoked when received GET DEVICE DESCRIPTOR
// Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
+uint8_t const *tud_descriptor_device_cb(void) {
return (uint8_t const *) &desc_device;
}
@@ -78,8 +76,7 @@ uint8_t const * tud_descriptor_device_cb(void)
// Configuration Descriptor
//--------------------------------------------------------------------+
-enum
-{
+enum {
ITF_NUM_CDC = 0,
ITF_NUM_CDC_DATA,
ITF_NUM_MSC,
@@ -96,8 +93,18 @@ enum
#define EPNUM_MSC_OUT 0x05
#define EPNUM_MSC_IN 0x85
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
- // SAMG doesn't support a same endpoint number with different direction IN and OUT
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+ // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+ // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+ #define EPNUM_CDC_NOTIF 0x83
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x81
+
+ #define EPNUM_MSC_OUT 0x05
+ #define EPNUM_MSC_IN 0x84
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_CDC_NOTIF 0x81
#define EPNUM_CDC_OUT 0x02
diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c
index 25b2cd9a52..b148593dab 100644
--- a/examples/device/cdc_uac2/src/main.c
+++ b/examples/device/cdc_uac2/src/main.c
@@ -46,7 +46,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
stdio_init_all();
diff --git a/examples/device/cdc_uac2/src/uac2_app.c b/examples/device/cdc_uac2/src/uac2_app.c
index c57d98a1a7..70b0949a9e 100644
--- a/examples/device/cdc_uac2/src/uac2_app.c
+++ b/examples/device/cdc_uac2/src/uac2_app.c
@@ -141,7 +141,7 @@ static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_req
TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
}
- else if (UAC2_ENTITY_SPK_FEATURE_UNIT && request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+ else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
{
if (request->bRequest == AUDIO_CS_REQ_RANGE)
{
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c
index 72a695622e..9f7255d8a3 100644
--- a/examples/device/cdc_uac2/src/usb_descriptors.c
+++ b/examples/device/cdc_uac2/src/usb_descriptors.c
@@ -97,18 +97,8 @@ uint8_t const * tud_descriptor_device_cb(void)
#define EPNUM_CDC_OUT 0x02
#define EPNUM_CDC_IN 0x82
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
- // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
- // e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_AUDIO_IN 0x01
- #define EPNUM_AUDIO_OUT 0x02
-
- #define EPNUM_CDC_NOTIF 0x83
- #define EPNUM_CDC_OUT 0x04
- #define EPNUM_CDC_IN 0x85
-
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_AUDIO_IN 0x01
#define EPNUM_AUDIO_OUT 0x02
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 81fc0a62c2..af9e998579 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -75,7 +75,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 170dde9323..4740c18c42 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -70,7 +70,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/dynamic_configuration/skip.txt b/examples/device/dynamic_configuration/skip.txt
index 833fd072c0..b6252e4050 100644
--- a/examples/device/dynamic_configuration/skip.txt
+++ b/examples/device/dynamic_configuration/skip.txt
@@ -1,2 +1,3 @@
mcu:SAMD11
family:espressif
+board:ch32v203g_r0_1v0
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index b6409c8e1e..32ff58232d 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -57,7 +57,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 7f35b4b22e..0a20492883 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -132,21 +132,8 @@ enum
#define EPNUM_1_MSC_OUT 0x02
#define EPNUM_1_MSC_IN 0x82
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
- // SAMG doesn't support a same endpoint number with different direction IN and OUT
- // e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_0_CDC_NOTIF 0x81
- #define EPNUM_0_CDC_OUT 0x02
- #define EPNUM_0_CDC_IN 0x83
-
- #define EPNUM_0_MIDI_OUT 0x04
- #define EPNUM_0_MIDI_IN 0x85
-
- #define EPNUM_1_MSC_OUT 0x01
- #define EPNUM_1_MSC_IN 0x82
-
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_0_CDC_NOTIF 0x81
#define EPNUM_0_CDC_OUT 0x02
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 7ad5c53c21..570e4e8010 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -57,7 +57,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
@@ -161,8 +165,8 @@ void hid_task(void)
{
uint8_t const report_id = 0;
uint8_t const button_mask = 0;
- uint8_t const vertical = 0;
- uint8_t const horizontal = 0;
+ int8_t const vertical = 0;
+ int8_t const horizontal = 0;
int8_t const delta = 5;
tud_hid_n_mouse_report(ITF_NUM_MOUSE, report_id, button_mask, delta, delta, vertical, horizontal);
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index dcf13079f3..5302af3b8c 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -58,7 +58,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
index a6f96b2885..650bf355b2 100644
--- a/examples/device/hid_composite_freertos/skip.txt
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -1,7 +1,10 @@
+mcu:CH32V103
+mcu:CH32V20X
mcu:CH32V307
mcu:CXD56
mcu:F1C100S
mcu:GD32VF103
+mcu:MCXA15
mcu:MKL25ZXX
mcu:MSP430x5xx
mcu:RP2040
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 6cc7a6577c..869500ad2a 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -67,6 +67,7 @@
#define configENABLE_FPU 1
#define configENABLE_TRUSTZONE 0
#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
+#define configRUN_FREERTOS_SECURE_ONLY 1
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index ff2cb635ee..ae091571e0 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -31,7 +31,7 @@
#include "tusb.h"
#include "usb_descriptors.h"
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
@@ -113,14 +113,14 @@ int main(void)
xTimerStart(blinky_tm, 0);
// skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if !TUP_MCU_ESPRESSIF
vTaskStartScheduler();
#endif
return 0;
}
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
void app_main(void)
{
main();
@@ -136,7 +136,11 @@ void usb_device_task(void* param)
// init device stack on configured roothub port
// This should be called after scheduler/kernel is started.
// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 3ba9bf3116..0689e0f230 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -59,7 +59,7 @@
#endif
// Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
#define CFG_TUSB_OS_INC_PATH freertos/
#endif
diff --git a/examples/device/hid_generic_inout/hid_test.py b/examples/device/hid_generic_inout/hid_test.py
old mode 100644
new mode 100755
index 5bdba9db06..3aaca9d2c2
--- a/examples/device/hid_generic_inout/hid_test.py
+++ b/examples/device/hid_generic_inout/hid_test.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
# Install python3 HID package https://pypi.org/project/hid/
import hid
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index cfa9f62831..73f51002d8 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -81,7 +81,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 30b4ae0552..92c7e8332c 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -62,7 +62,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index b1d51598fe..d7849a2c4b 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -63,7 +63,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c
index 9781d3d6fd..3870eaaf0e 100644
--- a/examples/device/midi_test/src/usb_descriptors.c
+++ b/examples/device/midi_test/src/usb_descriptors.c
@@ -84,15 +84,24 @@ enum
#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
- #define EPNUM_MIDI_OUT 0x02
- #define EPNUM_MIDI_IN 0x02
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // On Bridgetek FT9xx endpoint numbers must be unique...
- #define EPNUM_MIDI_OUT 0x02
- #define EPNUM_MIDI_IN 0x03
+ #define EPNUM_MIDI_OUT 0x02
+ #define EPNUM_MIDI_IN 0x82
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+ // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+ // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+ #define EPNUM_MIDI_OUT 0x02
+ #define EPNUM_MIDI_IN 0x81
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
+ // e.g EP1 OUT & EP1 IN cannot exist together
+ #define EPNUM_MIDI_OUT 0x01
+ #define EPNUM_MIDI_IN 0x82
+
#else
- #define EPNUM_MIDI_OUT 0x01
- #define EPNUM_MIDI_IN 0x01
+ #define EPNUM_MIDI_OUT 0x01
+ #define EPNUM_MIDI_IN 0x81
#endif
uint8_t const desc_fs_configuration[] =
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index aabd0bf8ac..012095dcaa 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -54,7 +54,11 @@ int main(void) {
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index 4f0f6410f1..b44b77c6cf 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -34,9 +34,13 @@
// Some MCU doesn't have enough 8KB SRAM to store the whole disk
// We will use Flash as read-only disk with board that has
// CFG_EXAMPLE_MSC_READONLY defined
+#if defined(CFG_EXAMPLE_MSC_READONLY) || defined(CFG_EXAMPLE_MSC_DUAL_READONLY)
+ #define MSC_CONST const
+#else
+ #define MSC_CONST
+#endif
-enum
-{
+enum {
DISK_BLOCK_NUM = 16, // 8KB is the smallest size that windows allow to mount
DISK_BLOCK_SIZE = 512
};
@@ -51,10 +55,7 @@ If you find any bugs or get any questions, feel free to file an\r\n\
issue at github.com/hathach/tinyusb"
-#ifdef CFG_EXAMPLE_MSC_READONLY
-const
-#endif
-uint8_t msc_disk0[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
+MSC_CONST uint8_t msc_disk0[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
{
//------------- Block0: Boot Sector -------------//
// byte_per_sector = DISK_BLOCK_SIZE; fat12_sector_num_16 = DISK_BLOCK_NUM;
@@ -132,10 +133,7 @@ uint8_t msc_disk0[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
If you find any bugs or get any questions, feel free to file an\r\n\
issue at github.com/hathach/tinyusb"
-#ifdef CFG_EXAMPLE_MSC_READONLY
-const
-#endif
-uint8_t msc_disk1[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
+MSC_CONST uint8_t msc_disk1[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
{
//------------- Block0: Boot Sector -------------//
// byte_per_sector = DISK_BLOCK_SIZE; fat12_sector_num_16 = DISK_BLOCK_NUM;
@@ -206,15 +204,13 @@ uint8_t msc_disk1[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
};
// Invoked to determine max LUN
-uint8_t tud_msc_get_maxlun_cb(void)
-{
+uint8_t tud_msc_get_maxlun_cb(void) {
return 2; // dual LUN
}
// Invoked when received SCSI_CMD_INQUIRY
// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively
-void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4])
-{
+void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) {
(void) lun; // use same ID for both LUNs
const char vid[] = "TinyUSB";
@@ -228,8 +224,7 @@ void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16
// Invoked when received Test Unit Ready command.
// return true allowing host to read/write this LUN e.g SD card inserted
-bool tud_msc_test_unit_ready_cb(uint8_t lun)
-{
+bool tud_msc_test_unit_ready_cb(uint8_t lun) {
if ( lun == 1 && board_button_read() ) return false;
return true; // RAM disk is always ready
@@ -237,8 +232,7 @@ bool tud_msc_test_unit_ready_cb(uint8_t lun)
// Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size
// Application update block count and block size
-void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_size)
-{
+void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_size) {
(void) lun;
*block_count = DISK_BLOCK_NUM;
@@ -248,18 +242,14 @@ void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_siz
// Invoked when received Start Stop Unit command
// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage
// - Start = 1 : active mode, if load_eject = 1 : load disk storage
-bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject)
-{
+bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject) {
(void) lun;
(void) power_condition;
- if ( load_eject )
- {
- if (start)
- {
+ if (load_eject) {
+ if (start) {
// load disk storage
- }else
- {
+ } else {
// unload disk storage
}
}
@@ -269,10 +259,9 @@ bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, boo
// Callback invoked when received READ10 command.
// Copy disk's data to buffer (up to bufsize) and return number of copied bytes.
-int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize)
-{
+int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize) {
// out of ramdisk
- if ( lba >= DISK_BLOCK_NUM ) return -1;
+ if (lba >= DISK_BLOCK_NUM) return -1;
uint8_t const* addr = (lun ? msc_disk1[lba] : msc_disk0[lba]) + offset;
memcpy(buffer, addr, bufsize);
@@ -280,11 +269,10 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
return (int32_t) bufsize;
}
-bool tud_msc_is_writable_cb (uint8_t lun)
-{
+bool tud_msc_is_writable_cb(uint8_t lun) {
(void) lun;
-#ifdef CFG_EXAMPLE_MSC_READONLY
+#if defined(CFG_EXAMPLE_MSC_READONLY) || defined(CFG_EXAMPLE_MSC_DUAL_READONLY)
return false;
#else
return true;
@@ -293,16 +281,18 @@ bool tud_msc_is_writable_cb (uint8_t lun)
// Callback invoked when received WRITE10 command.
// Process data in buffer to disk's storage and return number of written bytes
-int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize)
-{
+int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize) {
// out of ramdisk
- if ( lba >= DISK_BLOCK_NUM ) return -1;
+ if (lba >= DISK_BLOCK_NUM) return -1;
-#ifndef CFG_EXAMPLE_MSC_READONLY
+#if defined(CFG_EXAMPLE_MSC_READONLY) || defined(CFG_EXAMPLE_MSC_DUAL_READONLY)
+ (void) lun;
+ (void) lba;
+ (void) offset;
+ (void) buffer;
+#else
uint8_t* addr = (lun ? msc_disk1[lba] : msc_disk0[lba]) + offset;
memcpy(addr, buffer, bufsize);
-#else
- (void) lun; (void) lba; (void) offset; (void) buffer;
#endif
return (int32_t) bufsize;
@@ -310,38 +300,30 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
// Callback invoked when received an SCSI command not in built-in list below
// - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE
-// - READ10 and WRITE10 has their own callbacks
-int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize)
-{
- // read10 & write10 has their own callback and MUST not be handled here
-
+// - READ10 and WRITE10 has their own callbacks (MUST not be handled here)
+int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize) {
void const* response = NULL;
int32_t resplen = 0;
// most scsi handled is input
bool in_xfer = true;
- switch (scsi_cmd[0])
- {
+ switch (scsi_cmd[0]) {
default:
// Set Sense = Invalid Command Operation
tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
// negative means error -> tinyusb could stall and/or response with failed status
- resplen = -1;
- break;
+ return -1;
}
// return resplen must not larger than bufsize
- if ( resplen > bufsize ) resplen = bufsize;
+ if (resplen > bufsize) resplen = bufsize;
- if ( response && (resplen > 0) )
- {
- if(in_xfer)
- {
+ if (response && (resplen > 0)) {
+ if (in_xfer) {
memcpy(buffer, response, (size_t) resplen);
- }else
- {
+ } else {
// SCSI output
}
}
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index c0610945f9..efb9a966d4 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -85,17 +85,17 @@ enum
#define EPNUM_MSC_OUT 0x02
#define EPNUM_MSC_IN 0x82
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
- // SAMG doesn't support a same endpoint number with different direction IN and OUT
- // e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_MSC_OUT 0x01
- #define EPNUM_MSC_IN 0x82
-
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+ // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+ // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+ #define EPNUM_MSC_OUT 0x02
+ #define EPNUM_MSC_IN 0x81
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_MSC_OUT 0x01
- #define EPNUM_MSC_IN 0x82
+ #define EPNUM_MSC_OUT 0x01
+ #define EPNUM_MSC_IN 0x82
#else
#define EPNUM_MSC_OUT 0x01
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index a16b8bd71d..13923b5837 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -5,7 +5,14 @@ include(${CMAKE_CURRENT_LIST_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+# Prefer the tinyusb lwip
set(LWIP ${TOP}/lib/lwip)
+
+# If we can't find one from tinyusb then check cmake var before giving up
+if (NOT EXISTS ${LWIP}/src)
+ set(LWIP ${TINYUSB_LWIP_PATH})
+endif()
+
if (NOT EXISTS ${LWIP}/src)
family_example_missing_dependency(${PROJECT} "lib/lwip")
return()
@@ -74,6 +81,7 @@ target_sources(${PROJECT} PUBLIC
${LWIP}/src/netif/slipif.c
${LWIP}/src/apps/http/httpd.c
${LWIP}/src/apps/http/fs.c
+ ${LWIP}/src/apps/lwiperf/lwiperf.c
)
# due to warnings from other net source, we need to prevent error from some of the warnings options
diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index 22426ba0de..141532466f 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -63,6 +63,7 @@ SRC_C += \
lib/lwip/src/netif/slipif.c \
lib/lwip/src/apps/http/httpd.c \
lib/lwip/src/apps/http/fs.c \
+ lib/lwip/src/apps/lwiperf/lwiperf.c \
lib/networking/dhserver.c \
lib/networking/dnserver.c \
lib/networking/rndis_reports.c
diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt
index 75aa2ef145..5ebe716121 100644
--- a/examples/device/net_lwip_webserver/skip.txt
+++ b/examples/device/net_lwip_webserver/skip.txt
@@ -1,12 +1,19 @@
+mcu:CH32V103
+mcu:CH32V20X
mcu:LPC11UXX
mcu:LPC13XX
+mcu:LPC15XX
+mcu:MCXA15
mcu:MSP430x5xx
mcu:NUC121
mcu:SAMD11
mcu:STM32L0
+mcu:STM32F0
mcu:KINETIS_KL
family:broadcom_64bit
family:broadcom_32bit
+family:espressif
board:curiosity_nano
board:frdm_kl25z
-family:espressif
+# lpc55 has weird error 'ncm_interface' causes a section type conflict with 'ntb_parameters'
+family:lpc55
diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h
index 336c9243dd..41e8f0d677 100644
--- a/examples/device/net_lwip_webserver/src/lwipopts.h
+++ b/examples/device/net_lwip_webserver/src/lwipopts.h
@@ -48,8 +48,8 @@
#define LWIP_IP_ACCEPT_UDP_PORT(p) ((p) == PP_NTOHS(67))
#define TCP_MSS (1500 /*mtu*/ - 20 /*iphdr*/ - 20 /*tcphhr*/)
-#define TCP_SND_BUF (2 * TCP_MSS)
-#define TCP_WND (TCP_MSS)
+#define TCP_SND_BUF (4 * TCP_MSS)
+#define TCP_WND (4 * TCP_MSS)
#define ETHARP_SUPPORT_STATIC_ENTRIES 1
@@ -59,7 +59,7 @@
#define LWIP_SINGLE_NETIF 1
-#define PBUF_POOL_SIZE 2
+#define PBUF_POOL_SIZE 4
#define HTTPD_USE_CUSTOM_FSDATA 0
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 7d98aacbc9..8af7a9de6a 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -48,12 +48,17 @@ try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00
#include "dhserver.h"
#include "dnserver.h"
+#include "httpd.h"
+#include "lwip/ethip6.h"
#include "lwip/init.h"
#include "lwip/timeouts.h"
-#include "lwip/ethip6.h"
-#include "httpd.h"
-#define INIT_IP4(a,b,c,d) { PP_HTONL(LWIP_MAKEU32(a,b,c,d)) }
+#ifdef INCLUDE_IPERF
+ #include "lwip/apps/lwiperf.h"
+#endif
+
+#define INIT_IP4(a, b, c, d) \
+ { PP_HTONL(LWIP_MAKEU32(a, b, c, d)) }
/* lwip context */
static struct netif netif_data;
@@ -64,44 +69,40 @@ static struct pbuf *received_frame;
/* this is used by this code, ./class/net/net_driver.c, and usb_descriptors.c */
/* ideally speaking, this should be generated from the hardware's unique ID (if available) */
/* it is suggested that the first byte is 0x02 to indicate a link-local address */
-uint8_t tud_network_mac_address[6] = {0x02,0x02,0x84,0x6A,0x96,0x00};
+uint8_t tud_network_mac_address[6] = {0x02, 0x02, 0x84, 0x6A, 0x96, 0x00};
/* network parameters of this MCU */
-static const ip4_addr_t ipaddr = INIT_IP4(192, 168, 7, 1);
+static const ip4_addr_t ipaddr = INIT_IP4(192, 168, 7, 1);
static const ip4_addr_t netmask = INIT_IP4(255, 255, 255, 0);
static const ip4_addr_t gateway = INIT_IP4(0, 0, 0, 0);
/* database IP addresses that can be offered to the host; this must be in RAM to store assigned MAC addresses */
-static dhcp_entry_t entries[] =
-{
- /* mac ip address lease time */
- { {0}, INIT_IP4(192, 168, 7, 2), 24 * 60 * 60 },
- { {0}, INIT_IP4(192, 168, 7, 3), 24 * 60 * 60 },
- { {0}, INIT_IP4(192, 168, 7, 4), 24 * 60 * 60 },
+static dhcp_entry_t entries[] = {
+ /* mac ip address lease time */
+ {{0}, INIT_IP4(192, 168, 7, 2), 24 * 60 * 60},
+ {{0}, INIT_IP4(192, 168, 7, 3), 24 * 60 * 60},
+ {{0}, INIT_IP4(192, 168, 7, 4), 24 * 60 * 60},
};
-static const dhcp_config_t dhcp_config =
-{
- .router = INIT_IP4(0, 0, 0, 0), /* router address (if any) */
- .port = 67, /* listen port */
- .dns = INIT_IP4(192, 168, 7, 1), /* dns server (if any) */
- "usb", /* dns suffix */
- TU_ARRAY_SIZE(entries), /* num entry */
- entries /* entries */
+static const dhcp_config_t dhcp_config = {
+ .router = INIT_IP4(0, 0, 0, 0), /* router address (if any) */
+ .port = 67, /* listen port */
+ .dns = INIT_IP4(192, 168, 7, 1), /* dns server (if any) */
+ "usb", /* dns suffix */
+ TU_ARRAY_SIZE(entries), /* num entry */
+ entries /* entries */
};
-static err_t linkoutput_fn(struct netif *netif, struct pbuf *p)
-{
- (void)netif;
- for (;;)
- {
+static err_t linkoutput_fn(struct netif *netif, struct pbuf *p) {
+ (void) netif;
+
+ for (;;) {
/* if TinyUSB isn't ready, we must signal back to lwip that there is nothing we can do */
if (!tud_ready())
return ERR_USE;
/* if the network driver can accept another packet, we make it happen */
- if (tud_network_can_xmit(p->tot_len))
- {
+ if (tud_network_can_xmit(p->tot_len)) {
tud_network_xmit(p, 0 /* unused for this example */);
return ERR_OK;
}
@@ -111,20 +112,17 @@ static err_t linkoutput_fn(struct netif *netif, struct pbuf *p)
}
}
-static err_t ip4_output_fn(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr)
-{
+static err_t ip4_output_fn(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr) {
return etharp_output(netif, p, addr);
}
#if LWIP_IPV6
-static err_t ip6_output_fn(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr)
-{
+static err_t ip6_output_fn(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr) {
return ethip6_output(netif, p, addr);
}
#endif
-static err_t netif_init_cb(struct netif *netif)
-{
+static err_t netif_init_cb(struct netif *netif) {
LWIP_ASSERT("netif != NULL", (netif != NULL));
netif->mtu = CFG_TUD_NET_MTU;
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP;
@@ -139,8 +137,7 @@ static err_t netif_init_cb(struct netif *netif)
return ERR_OK;
}
-static void init_lwip(void)
-{
+static void init_lwip(void) {
struct netif *netif = &netif_data;
lwip_init();
@@ -158,28 +155,23 @@ static void init_lwip(void)
}
/* handle any DNS requests from dns-server */
-bool dns_query_proc(const char *name, ip4_addr_t *addr)
-{
- if (0 == strcmp(name, "tiny.usb"))
- {
+bool dns_query_proc(const char *name, ip4_addr_t *addr) {
+ if (0 == strcmp(name, "tiny.usb")) {
*addr = ipaddr;
return true;
}
return false;
}
-bool tud_network_recv_cb(const uint8_t *src, uint16_t size)
-{
+bool tud_network_recv_cb(const uint8_t *src, uint16_t size) {
/* this shouldn't happen, but if we get another packet before
parsing the previous, we must signal our inability to accept it */
if (received_frame) return false;
- if (size)
- {
+ if (size) {
struct pbuf *p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL);
- if (p)
- {
+ if (p) {
/* pbuf_alloc() has already initialized struct; all we need to do is copy the data */
memcpy(p->payload, src, size);
@@ -191,20 +183,17 @@ bool tud_network_recv_cb(const uint8_t *src, uint16_t size)
return true;
}
-uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg)
-{
- struct pbuf *p = (struct pbuf *)ref;
+uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) {
+ struct pbuf *p = (struct pbuf *) ref;
- (void)arg; /* unused for this example */
+ (void) arg; /* unused for this example */
return pbuf_copy_partial(p, dst, p->tot_len, 0);
}
-static void service_traffic(void)
-{
+static void service_traffic(void) {
/* handle any packet received by tud_network_recv_cb() */
- if (received_frame)
- {
+ if (received_frame) {
ethernet_input(received_frame, &netif_data);
pbuf_free(received_frame);
received_frame = NULL;
@@ -214,23 +203,24 @@ static void service_traffic(void)
sys_check_timeouts();
}
-void tud_network_init_cb(void)
-{
+void tud_network_init_cb(void) {
/* if the network is re-initializing and we have a leftover packet, we must do a cleanup */
- if (received_frame)
- {
+ if (received_frame) {
pbuf_free(received_frame);
received_frame = NULL;
}
}
-int main(void)
-{
+int main(void) {
/* initialize TinyUSB */
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
@@ -243,8 +233,12 @@ int main(void)
while (dnserv_init(IP_ADDR_ANY, 53, dns_query_proc) != ERR_OK);
httpd_init();
- while (1)
- {
+#ifdef INCLUDE_IPERF
+ // test with: iperf -c 192.168.7.1 -e -i 1 -M 5000 -l 8192 -r
+ lwiperf_start_tcp_server_default(NULL, NULL);
+#endif
+
+ while (1) {
tud_task();
service_traffic();
}
@@ -253,17 +247,14 @@ int main(void)
}
/* lwip has provision for using a mutex, when applicable */
-sys_prot_t sys_arch_protect(void)
-{
+sys_prot_t sys_arch_protect(void) {
return 0;
}
-void sys_arch_unprotect(sys_prot_t pval)
-{
- (void)pval;
+void sys_arch_unprotect(sys_prot_t pval) {
+ (void) pval;
}
/* lwip needs a millisecond time source, and the TinyUSB board support code has one available */
-uint32_t sys_now(void)
-{
+uint32_t sys_now(void) {
return board_millis();
}
diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h
index fe72ecdfe7..22082fc818 100644
--- a/examples/device/net_lwip_webserver/src/tusb_config.h
+++ b/examples/device/net_lwip_webserver/src/tusb_config.h
@@ -27,21 +27,23 @@
#define _TUSB_CONFIG_H_
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
+#include "lwipopts.h"
+
//--------------------------------------------------------------------+
// Board Specific Configuration
//--------------------------------------------------------------------+
// RHPort number used for device can be defined by board.mk, default to port 0
#ifndef BOARD_TUD_RHPORT
-#define BOARD_TUD_RHPORT 0
+ #define BOARD_TUD_RHPORT 0
#endif
// RHPort max operational speed can defined by board.mk
#ifndef BOARD_TUD_MAX_SPEED
-#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+ #define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
#endif
//--------------------------------------------------------------------
@@ -50,22 +52,22 @@
// defined by compiler flags for flexibility
#ifndef CFG_TUSB_MCU
-#error CFG_TUSB_MCU must be defined
+ #error CFG_TUSB_MCU must be defined
#endif
#ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS OPT_OS_NONE
+ #define CFG_TUSB_OS OPT_OS_NONE
#endif
#ifndef CFG_TUSB_DEBUG
-#define CFG_TUSB_DEBUG 0
+ #define CFG_TUSB_DEBUG 0
#endif
// Enable Device stack
-#define CFG_TUD_ENABLED 1
+#define CFG_TUD_ENABLED 1
// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
* Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -75,11 +77,47 @@
* - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
*/
#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+ #define CFG_TUSB_MEM_SECTION
#endif
#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+ #define CFG_TUSB_MEM_ALIGN __attribute__((aligned(4)))
+#endif
+
+// Use different configurations to test all net devices (also due to resource limitations)
+#if TU_CHECK_MCU(OPT_MCU_LPC15XX, OPT_MCU_LPC40XX, OPT_MCU_LPC51UXX, OPT_MCU_LPC54)
+ #define USE_ECM 1
+#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAML21, OPT_MCU_SAML22)
+ #define USE_ECM 1
+#elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1)
+ #define USE_ECM 1
+#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002)
+ #define USE_ECM 1
+#else
+ #define USE_ECM 0
+ #define INCLUDE_IPERF
+#endif
+
+//--------------------------------------------------------------------
+// NCM CLASS CONFIGURATION, SEE "ncm.h" FOR PERFORMANCE TUNING
+//--------------------------------------------------------------------
+
+// Must be >> MTU
+// Can be set to 2048 without impact
+#define CFG_TUD_NCM_IN_NTB_MAX_SIZE (2 * TCP_MSS + 100)
+
+// Must be >> MTU
+// Can be set to smaller values if wNtbOutMaxDatagrams==1
+#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE (2 * TCP_MSS + 100)
+
+// Number of NCM transfer blocks for reception side
+#ifndef CFG_TUD_NCM_OUT_NTB_N
+ #define CFG_TUD_NCM_OUT_NTB_N 1
+#endif
+
+// Number of NCM transfer blocks for transmission side
+#ifndef CFG_TUD_NCM_IN_NTB_N
+ #define CFG_TUD_NCM_IN_NTB_N 1
#endif
//--------------------------------------------------------------------
@@ -87,18 +125,18 @@
//--------------------------------------------------------------------
#ifndef CFG_TUD_ENDPOINT0_SIZE
-#define CFG_TUD_ENDPOINT0_SIZE 64
+ #define CFG_TUD_ENDPOINT0_SIZE 64
#endif
//------------- CLASS -------------//
// Network class has 2 drivers: ECM/RNDIS and NCM.
// Only one of the drivers can be enabled
-#define CFG_TUD_ECM_RNDIS 1
-#define CFG_TUD_NCM (1-CFG_TUD_ECM_RNDIS)
+#define CFG_TUD_ECM_RNDIS USE_ECM
+#define CFG_TUD_NCM (1 - CFG_TUD_ECM_RNDIS)
#ifdef __cplusplus
- }
+}
#endif
#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index da628c8bea..d061f50763 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -113,8 +113,15 @@ uint8_t const * tud_descriptor_device_cb(void)
#define EPNUM_NET_OUT 0x02
#define EPNUM_NET_IN 0x82
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
- // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+ // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+ // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+ #define EPNUM_NET_NOTIF 0x83
+ #define EPNUM_NET_OUT 0x02
+ #define EPNUM_NET_IN 0x81
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_NET_NOTIF 0x81
#define EPNUM_NET_OUT 0x02
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 0ea6e70258..6b2ab09738 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -100,7 +100,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
@@ -229,7 +233,7 @@ static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_req
TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
}
- else if (UAC2_ENTITY_SPK_FEATURE_UNIT && request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+ else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
{
if (request->bRequest == AUDIO_CS_REQ_RANGE)
{
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index ff4dc2acc9..bc9160d5e0 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -84,21 +84,21 @@ uint8_t const * tud_descriptor_device_cb(void)
#define EPNUM_AUDIO_OUT 0x03
#define EPNUM_AUDIO_INT 0x01
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+ // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+ // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+ // #define EPNUM_AUDIO_IN 0x01
+ // #define EPNUM_AUDIO_OUT 0x02
+ // #define EPNUM_AUDIO_INT 0x03
+
#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
// ISO endpoints for NRF5x are fixed to 0x08 (0x88)
#define EPNUM_AUDIO_IN 0x08
#define EPNUM_AUDIO_OUT 0x08
#define EPNUM_AUDIO_INT 0x01
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
- // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
- // e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_AUDIO_IN 0x01
- #define EPNUM_AUDIO_OUT 0x02
- #define EPNUM_AUDIO_INT 0x03
-
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_AUDIO_IN 0x01
#define EPNUM_AUDIO_OUT 0x02
diff --git a/examples/device/uac2_speaker_fb/CMakeLists.txt b/examples/device/uac2_speaker_fb/CMakeLists.txt
new file mode 100644
index 0000000000..f40ca87166
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/CMakeLists.txt
@@ -0,0 +1,34 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/quirk_os_guessing.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/uac2_speaker_fb/Makefile b/examples/device/uac2_speaker_fb/Makefile
new file mode 100644
index 0000000000..7fa475da55
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/Makefile
@@ -0,0 +1,11 @@
+include ../../build_system/make/make.mk
+
+INC += \
+ src \
+ $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/device/uac2_speaker_fb/skip.txt b/examples/device/uac2_speaker_fb/skip.txt
new file mode 100644
index 0000000000..234f1ebedf
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/skip.txt
@@ -0,0 +1,8 @@
+mcu:LPC11UXX
+mcu:LPC13XX
+mcu:NUC121
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
+board:stm32l052dap52
+family:broadcom_64bit
diff --git a/examples/device/uac2_speaker_fb/src/audio_debug.py b/examples/device/uac2_speaker_fb/src/audio_debug.py
new file mode 100755
index 0000000000..05b49baf6a
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/audio_debug.py
@@ -0,0 +1,70 @@
+#!/usr/bin/env python3
+# Install python3 HID package https://pypi.org/project/hid/
+# Install python3 matplotlib package https://pypi.org/project/matplotlib/
+
+from ctypes import *
+try:
+ import hid
+ import matplotlib.pyplot as plt
+ import matplotlib.animation as animation
+except:
+ print("Missing import, please try 'pip install hid matplotlib' or consult your OS's python package manager.")
+
+# Example must be compiled with CFG_AUDIO_DEBUG=1
+VID = 0xcafe
+PID = 0x4014
+
+CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX = 2
+
+class audio_debug_info_t (Structure):
+ _fields_ = [("sample_rate", c_uint32),
+ ("alt_settings", c_uint8),
+ ("mute", (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1) * c_int8),
+ ("volume", (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1) * c_int16),
+ ("fifo_size", c_uint16),
+ ("fifo_count", c_uint16),
+ ("fifo_count_avg", c_uint16)
+ ]
+
+dev = hid.Device(VID, PID)
+
+if dev:
+ # Create figure for plotting
+ fig = plt.figure()
+ ax = fig.add_subplot(1, 1, 1)
+ fifo_avg = []
+ fifo_cnt = []
+ # This function is called periodically from FuncAnimation
+ def animate(i):
+ info = None
+ for i in range(30):
+ try:
+ str_in = dev.read(64, 50)
+ info = audio_debug_info_t.from_buffer_copy(str_in)
+
+ global fifo_avg
+ global fifo_cnt
+ fifo_avg.append(info.fifo_count_avg)
+ fifo_cnt.append(info.fifo_count)
+ except:
+ exit(1)
+ # Limit to 1000 items
+ fifo_avg = fifo_avg[-1000:]
+ fifo_cnt = fifo_cnt[-1000:]
+
+ if info is not None:
+ # Draw x and y lists
+ ax.clear()
+ ax.plot(fifo_cnt, label='FIFO count')
+ ax.plot(fifo_avg, label='FIFO average')
+ ax.legend()
+ ax.set_ylim(bottom=0, top=info.fifo_size)
+
+ # Format plot
+ plt.title('FIFO information')
+ plt.grid()
+
+ print(f'Sample rate:{info.sample_rate} | Alt settings:{info.alt_settings} | Volume:{info.volume[:]}')
+
+ ani = animation.FuncAnimation(fig, animate, interval=10)
+ plt.show()
diff --git a/examples/device/uac2_speaker_fb/src/common_types.h b/examples/device/uac2_speaker_fb/src/common_types.h
new file mode 100644
index 0000000000..174e266714
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/common_types.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _COMMON_TYPES_H_
+#define _COMMON_TYPES_H_
+
+enum
+{
+ ITF_NUM_AUDIO_CONTROL = 0,
+ ITF_NUM_AUDIO_STREAMING,
+#if CFG_AUDIO_DEBUG
+ ITF_NUM_DEBUG,
+#endif
+ ITF_NUM_TOTAL
+};
+
+#if CFG_AUDIO_DEBUG
+typedef struct
+ {
+ uint32_t sample_rate;
+ uint8_t alt_settings;
+ int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];
+ int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];
+ uint16_t fifo_size;
+ uint16_t fifo_count;
+ uint16_t fifo_count_avg;
+ } audio_debug_info_t;
+#endif
+
+#endif
diff --git a/examples/device/uac2_speaker_fb/src/main.c b/examples/device/uac2_speaker_fb/src/main.c
new file mode 100644
index 0000000000..ea5a2941d5
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/main.c
@@ -0,0 +1,509 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+#include "common_types.h"
+
+#ifdef CFG_QUIRK_OS_GUESSING
+#include "quirk_os_guessing.h"
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+// List of supported sample rates
+#if defined(__RX__)
+ const uint32_t sample_rates[] = {44100, 48000};
+#else
+ const uint32_t sample_rates[] = {44100, 48000, 88200, 96000};
+#endif
+
+uint32_t current_sample_rate = 44100;
+
+#define N_SAMPLE_RATES TU_ARRAY_SIZE(sample_rates)
+
+/* Blink pattern
+ * - 25 ms : streaming data
+ * - 250 ms : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum
+{
+ BLINK_STREAMING = 25,
+ BLINK_NOT_MOUNTED = 250,
+ BLINK_MOUNTED = 1000,
+ BLINK_SUSPENDED = 2500,
+};
+
+enum
+{
+ VOLUME_CTRL_0_DB = 0,
+ VOLUME_CTRL_10_DB = 2560,
+ VOLUME_CTRL_20_DB = 5120,
+ VOLUME_CTRL_30_DB = 7680,
+ VOLUME_CTRL_40_DB = 10240,
+ VOLUME_CTRL_50_DB = 12800,
+ VOLUME_CTRL_60_DB = 15360,
+ VOLUME_CTRL_70_DB = 17920,
+ VOLUME_CTRL_80_DB = 20480,
+ VOLUME_CTRL_90_DB = 23040,
+ VOLUME_CTRL_100_DB = 25600,
+ VOLUME_CTRL_SILENCE = 0x8000,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1]; // +1 for master channel 0
+int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1]; // +1 for master channel 0
+
+// Buffer for speaker data
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ/2];
+
+void led_blinking_task(void);
+void audio_task(void);
+
+#if CFG_AUDIO_DEBUG
+void audio_debug_task(void);
+uint8_t current_alt_settings;
+uint16_t fifo_count;
+uint32_t fifo_count_avg;
+#endif
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+ board_init();
+
+ // init device stack on configured roothub port
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
+ TU_LOG1("Speaker running\r\n");
+
+ while (1)
+ {
+ tud_task(); // TinyUSB device task
+ led_blinking_task();
+#if CFG_AUDIO_DEBUG
+ audio_debug_task();
+#endif
+ audio_task();
+ }
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+ blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+ blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+ (void)remote_wakeup_en;
+ blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Helper for clock get requests
+static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+ TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+
+ if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+ {
+ if (request->bRequest == AUDIO_CS_REQ_CUR)
+ {
+ TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
+
+ audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
+ }
+ else if (request->bRequest == AUDIO_CS_REQ_RANGE)
+ {
+ audio_control_range_4_n_t(N_SAMPLE_RATES) rangef =
+ {
+ .wNumSubRanges = tu_htole16(N_SAMPLE_RATES)
+ };
+ TU_LOG1("Clock get %d freq ranges\r\n", N_SAMPLE_RATES);
+ for(uint8_t i = 0; i < N_SAMPLE_RATES; i++)
+ {
+ rangef.subrange[i].bMin = (int32_t) sample_rates[i];
+ rangef.subrange[i].bMax = (int32_t) sample_rates[i];
+ rangef.subrange[i].bRes = 0;
+ TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+ }
+
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
+ }
+ }
+ else if (request->bControlSelector == AUDIO_CS_CTRL_CLK_VALID &&
+ request->bRequest == AUDIO_CS_REQ_CUR)
+ {
+ audio_control_cur_1_t cur_valid = { .bCur = 1 };
+ TU_LOG1("Clock get is valid %u\r\n", cur_valid.bCur);
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_valid, sizeof(cur_valid));
+ }
+ TU_LOG1("Clock get request not supported, entity = %u, selector = %u, request = %u\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+ return false;
+}
+
+// Helper for clock set requests
+static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+ (void)rhport;
+
+ TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+ TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+ if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+ {
+ TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
+
+ current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
+
+ TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
+
+ return true;
+ }
+ else
+ {
+ TU_LOG1("Clock set request not supported, entity = %u, selector = %u, request = %u\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+ return false;
+ }
+}
+
+// Helper for feature unit get requests
+static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+ TU_ASSERT(request->bEntityID == UAC2_ENTITY_FEATURE_UNIT);
+
+ if (request->bControlSelector == AUDIO_FU_CTRL_MUTE && request->bRequest == AUDIO_CS_REQ_CUR)
+ {
+ audio_control_cur_1_t mute1 = { .bCur = mute[request->bChannelNumber] };
+ TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
+ }
+ else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+ {
+ if (request->bRequest == AUDIO_CS_REQ_RANGE)
+ {
+ audio_control_range_2_n_t(1) range_vol = {
+ .wNumSubRanges = tu_htole16(1),
+ .subrange[0] = { .bMin = tu_htole16(-VOLUME_CTRL_50_DB), tu_htole16(VOLUME_CTRL_0_DB), tu_htole16(256) }
+ };
+ TU_LOG1("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
+ range_vol.subrange[0].bMin / 256, range_vol.subrange[0].bMax / 256, range_vol.subrange[0].bRes / 256);
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &range_vol, sizeof(range_vol));
+ }
+ else if (request->bRequest == AUDIO_CS_REQ_CUR)
+ {
+ audio_control_cur_2_t cur_vol = { .bCur = tu_htole16(volume[request->bChannelNumber]) };
+ TU_LOG1("Get channel %u volume %d dB\r\n", request->bChannelNumber, cur_vol.bCur / 256);
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_vol, sizeof(cur_vol));
+ }
+ }
+ TU_LOG1("Feature unit get request not supported, entity = %u, selector = %u, request = %u\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+
+ return false;
+}
+
+// Helper for feature unit set requests
+static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+ (void)rhport;
+
+ TU_ASSERT(request->bEntityID == UAC2_ENTITY_FEATURE_UNIT);
+ TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+ if (request->bControlSelector == AUDIO_FU_CTRL_MUTE)
+ {
+ TU_VERIFY(request->wLength == sizeof(audio_control_cur_1_t));
+
+ mute[request->bChannelNumber] = ((audio_control_cur_1_t const *)buf)->bCur;
+
+ TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
+
+ return true;
+ }
+ else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+ {
+ TU_VERIFY(request->wLength == sizeof(audio_control_cur_2_t));
+
+ volume[request->bChannelNumber] = ((audio_control_cur_2_t const *)buf)->bCur;
+
+ TU_LOG1("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
+
+ return true;
+ }
+ else
+ {
+ TU_LOG1("Feature unit set request not supported, entity = %u, selector = %u, request = %u\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+ return false;
+ }
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request)
+{
+ audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+ if (request->bEntityID == UAC2_ENTITY_CLOCK)
+ return tud_audio_clock_get_request(rhport, request);
+ if (request->bEntityID == UAC2_ENTITY_FEATURE_UNIT)
+ return tud_audio_feature_unit_get_request(rhport, request);
+ else
+ {
+ TU_LOG1("Get request not handled, entity = %d, selector = %d, request = %d\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+ }
+ return false;
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request, uint8_t *buf)
+{
+ audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+ if (request->bEntityID == UAC2_ENTITY_FEATURE_UNIT)
+ return tud_audio_feature_unit_set_request(rhport, request, buf);
+ if (request->bEntityID == UAC2_ENTITY_CLOCK)
+ return tud_audio_clock_set_request(rhport, request, buf);
+ TU_LOG1("Set request not handled, entity = %d, selector = %d, request = %d\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+
+ return false;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void)rhport;
+
+ uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+ uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+ if (ITF_NUM_AUDIO_STREAMING == itf && alt == 0)
+ blink_interval_ms = BLINK_MOUNTED;
+
+ return true;
+}
+
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void)rhport;
+ uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+ uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+ TU_LOG2("Set interface %d alt %d\r\n", itf, alt);
+ if (ITF_NUM_AUDIO_STREAMING == itf && alt != 0)
+ blink_interval_ms = BLINK_STREAMING;
+
+#if CFG_AUDIO_DEBUG
+ current_alt_settings = alt;
+#endif
+
+ return true;
+}
+
+void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param)
+{
+ (void)func_id;
+ (void)alt_itf;
+ // Set feedback method to fifo counting
+ feedback_param->method = AUDIO_FEEDBACK_METHOD_FIFO_COUNT;
+ feedback_param->sample_freq = current_sample_rate;
+}
+
+#if CFG_AUDIO_DEBUG
+bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting)
+{
+ (void)rhport;
+ (void)n_bytes_received;
+ (void)func_id;
+ (void)ep_out;
+ (void)cur_alt_setting;
+
+ fifo_count = tud_audio_available();
+ // Same averaging method used in UAC2 class
+ fifo_count_avg = (uint32_t)(((uint64_t)fifo_count_avg * 63 + ((uint32_t)fifo_count << 16)) >> 6);
+
+ return true;
+}
+#endif
+
+#if CFG_QUIRK_OS_GUESSING
+bool tud_audio_feedback_format_correction_cb(uint8_t func_id)
+{
+ (void)func_id;
+ if(tud_speed_get() == TUSB_SPEED_FULL && quirk_os_guessing_get() == QUIRK_OS_GUESSING_OSX) {
+ return true;
+ } else {
+ return false;
+ }
+}
+#endif
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void)
+{
+ // Replace audio_task() with your I2S transmit callback.
+ // Here we simulate a callback called every 1ms.
+ static uint32_t start_ms = 0;
+ uint32_t curr_ms = board_millis();
+ if ( start_ms == curr_ms ) return; // not enough time
+ start_ms = curr_ms;
+
+ uint16_t length = (uint16_t) (current_sample_rate/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX);
+
+ if (current_sample_rate == 44100 && (curr_ms % 10 == 0))
+ {
+ // Take one more sample every 10 cycles, to have a average reading speed of 44.1
+ // This correction is not needed in real world cases
+ length += CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX;
+ } else
+ if (current_sample_rate == 88200 && (curr_ms % 5 == 0))
+ {
+ // Take one more sample every 5 cycles, to have a average reading speed of 88.2
+ // This correction is not needed in real world cases
+ length += CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX;
+ }
+
+ tud_audio_read(i2s_dummy_buffer, length);
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+ static uint32_t start_ms = 0;
+ static bool led_state = false;
+
+ // Blink every interval ms
+ if (board_millis() - start_ms < blink_interval_ms) return;
+ start_ms += blink_interval_ms;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state;
+}
+
+#if CFG_AUDIO_DEBUG
+//--------------------------------------------------------------------+
+// HID interface for audio debug
+//--------------------------------------------------------------------+
+// Every 1ms, we will sent 1 debug information report
+void audio_debug_task(void)
+{
+ static uint32_t start_ms = 0;
+ uint32_t curr_ms = board_millis();
+ if ( start_ms == curr_ms ) return; // not enough time
+ start_ms = curr_ms;
+
+ audio_debug_info_t debug_info;
+ debug_info.sample_rate = current_sample_rate;
+ debug_info.alt_settings = current_alt_settings;
+ debug_info.fifo_size = CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ;
+ debug_info.fifo_count = fifo_count;
+ debug_info.fifo_count_avg = (uint16_t) (fifo_count_avg >> 16);
+ for (int i = 0; i < CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1; i++)
+ {
+ debug_info.mute[i] = mute[i];
+ debug_info.volume[i] = volume[i];
+ }
+
+ if(tud_hid_ready())
+ tud_hid_report(0, &debug_info, sizeof(debug_info));
+}
+
+// Invoked when received GET_REPORT control request
+// Unused here
+uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen)
+{
+ // TODO not Implemented
+ (void) itf;
+ (void) report_id;
+ (void) report_type;
+ (void) buffer;
+ (void) reqlen;
+
+ return 0;
+}
+
+// Invoked when received SET_REPORT control request or
+// Unused here
+void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
+{
+ // This example doesn't use multiple report and report ID
+ (void) itf;
+ (void) report_id;
+ (void) report_type;
+ (void) buffer;
+ (void) bufsize;
+}
+
+#endif
diff --git a/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c
new file mode 100644
index 0000000000..965bbd6cf0
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c
@@ -0,0 +1,90 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "quirk_os_guessing.h"
+
+static tusb_desc_type_t desc_req_buf[2];
+static int desc_req_idx = 0;
+
+// Place at the start of tud_descriptor_device_cb()
+void quirk_os_guessing_desc_device_cb() {
+ desc_req_idx = 0;
+}
+
+// Place at the start of tud_descriptor_configuration_cb()
+void quirk_os_guessing_desc_configuration_cb() {
+ // Skip redundant request
+ if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_CONFIGURATION)) {
+ desc_req_buf[desc_req_idx++] = TUSB_DESC_CONFIGURATION;
+ }
+}
+
+// Place at the start of tud_descriptor_bos_cb()
+void quirk_os_guessing_desc_bos_cb() {
+ // Skip redundant request
+ if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_BOS)) {
+ desc_req_buf[desc_req_idx++] = TUSB_DESC_BOS;
+ }
+}
+
+// Place at the start of tud_descriptor_string_cb()
+void quirk_os_guessing_desc_string_cb() {
+ // Skip redundant request
+ if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_STRING)) {
+ desc_req_buf[desc_req_idx++] = TUSB_DESC_STRING;
+ }
+}
+
+// Each OS request descriptors differently:
+// Windows 10 - 11
+// Device Desc
+// Config Desc
+// BOS Desc
+// String Desc
+// Linux 3.16 - 6.8
+// Device Desc
+// BOS Desc
+// Config Desc
+// String Desc
+// OS X Ventura - Sonoma
+// Device Desc
+// String Desc
+// Config Desc || BOS Desc
+// BOS Desc || Config Desc
+quirk_os_guessing_t quirk_os_guessing_get(void) {
+ if (desc_req_idx < 2) {
+ return QUIRK_OS_GUESSING_UNKNOWN;
+ }
+
+ if (desc_req_buf[0] == TUSB_DESC_BOS && desc_req_buf[1] == TUSB_DESC_CONFIGURATION) {
+ return QUIRK_OS_GUESSING_LINUX;
+ } else if (desc_req_buf[0] == TUSB_DESC_CONFIGURATION && desc_req_buf[1] == TUSB_DESC_BOS) {
+ return QUIRK_OS_GUESSING_WINDOWS;
+ } else if (desc_req_buf[0] == TUSB_DESC_STRING && (desc_req_buf[1] == TUSB_DESC_BOS || desc_req_buf[1] == TUSB_DESC_CONFIGURATION)) {
+ return QUIRK_OS_GUESSING_OSX;
+ }
+
+ return QUIRK_OS_GUESSING_UNKNOWN;
+}
diff --git a/examples/device/uac2_speaker_fb/src/quirk_os_guessing.h b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.h
new file mode 100644
index 0000000000..1120355c9e
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.h
@@ -0,0 +1,75 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _QUIRK_OS_GUESSING_H_
+#define _QUIRK_OS_GUESSING_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "tusb.h"
+
+//================================== !!! WARNING !!! ====================================
+// This quirk operate out of USB specification in order to workaround specific issues.
+// It may not work on your platform.
+//=======================================================================================
+//
+// Prerequisites:
+// - Set USB version to at least 2.01 in Device Descriptor
+// - Has a valid BOS Descriptor, refer to webusb_serial example
+//
+// Attention:
+// Windows detection result comes out after Configuration Descriptor request,
+// meaning it will be too late to do descriptor adjustment. It's advised to make
+// Windows as default configuration and adjust to other OS accordingly.
+
+typedef enum {
+ QUIRK_OS_GUESSING_UNKNOWN,
+ QUIRK_OS_GUESSING_LINUX,
+ QUIRK_OS_GUESSING_OSX,
+ QUIRK_OS_GUESSING_WINDOWS,
+} quirk_os_guessing_t;
+
+// Get Host OS type
+quirk_os_guessing_t quirk_os_guessing_get(void);
+
+// Place at the start of tud_descriptor_device_cb()
+void quirk_os_guessing_desc_device_cb(void);
+
+// Place at the start of tud_descriptor_configuration_cb()
+void quirk_os_guessing_desc_configuration_cb(void);
+
+// Place at the start of tud_descriptor_bos_cb()
+void quirk_os_guessing_desc_bos_cb(void);
+
+// Place at the start of tud_descriptor_string_cb()
+void quirk_os_guessing_desc_string_cb(void);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _QUIRK_OS_GUESSING_H_ */
diff --git a/examples/device/uac2_speaker_fb/src/tusb_config.h b/examples/device/uac2_speaker_fb/src/tusb_config.h
new file mode 100644
index 0000000000..fd4925c7f3
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/tusb_config.h
@@ -0,0 +1,168 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+// It's recommended to disable debug unless for control requests debugging,
+// as the extra time needed will impact data stream !
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED 1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+/* (Needed for Full-Speed only)
+ * Enable host OS guessing to workaround UAC2 compatibility issues between Windows and OS X
+ * The default configuration only support Windows and Linux, enable this option for OS X
+ * support. Otherwise if you don't need Windows support you can make OS X's configuration as
+ * default.
+ */
+#define CFG_QUIRK_OS_GUESSING 1
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+// Expose audio class debug information via HID interface
+#ifndef CFG_AUDIO_DEBUG
+#define CFG_AUDIO_DEBUG 1
+#endif
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+#define CFG_TUD_HID_EP_BUFSIZE 64
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO 1
+
+#if CFG_AUDIO_DEBUG
+#define CFG_TUD_HID 1
+#else
+#define CFG_TUD_HID 0
+#endif
+
+#define CFG_TUD_CDC 0
+#define CFG_TUD_MSC 0
+#define CFG_TUD_MIDI 0
+#define CFG_TUD_VENDOR 0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN TUD_AUDIO_SPEAKER_STEREO_FB_DESC_LEN
+
+// Enable if Full-Speed on OSX, also set feedback EP size to 3
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION 0
+
+// Audio format type I specifications
+#if defined(__RX__)
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE 48000
+#else
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE 96000
+#endif
+
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX 2
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX 2
+#define CFG_TUD_AUDIO_FUNC_1_RESOLUTION_RX 16
+
+// EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
+#define CFG_TUD_AUDIO_ENABLE_EP_OUT 1
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX // Example read FIFO every 1ms, so it should be 8 times larger for HS device
+
+// Enable feedback EP
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP 1
+
+// Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 1
+
+// Size of control request buffer
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ 64
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/uac2_speaker_fb/src/usb_descriptors.c b/examples/device/uac2_speaker_fb/src/usb_descriptors.c
new file mode 100644
index 0000000000..ee1b92225a
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/usb_descriptors.c
@@ -0,0 +1,288 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+#include "common_types.h"
+
+#ifdef CFG_QUIRK_OS_GUESSING
+#include "quirk_os_guessing.h"
+#endif
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ * [MSB] AUDIO | MIDI | HID | MSC | CDC [LSB]
+ */
+#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) )
+#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+ _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = 0x0201,
+
+ // Use Interface Association Descriptor (IAD) for Audio
+ // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+ .idVendor = 0xCafe,
+ .idProduct = USB_PID,
+ .bcdDevice = 0x0100,
+
+ .iManufacturer = 0x01,
+ .iProduct = 0x02,
+ .iSerialNumber = 0x03,
+
+ .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+#if CFG_QUIRK_OS_GUESSING
+ quirk_os_guessing_desc_device_cb();
+#endif
+ return (uint8_t const *)&desc_device;
+}
+
+#if CFG_AUDIO_DEBUG
+//--------------------------------------------------------------------+
+// HID Report Descriptor
+//--------------------------------------------------------------------+
+
+uint8_t const desc_hid_report[] =
+{
+ HID_USAGE_PAGE_N ( HID_USAGE_PAGE_VENDOR, 2 ),\
+ HID_USAGE ( 0x01 ),\
+ HID_COLLECTION ( HID_COLLECTION_APPLICATION ),\
+ HID_USAGE ( 0x02 ),\
+ HID_LOGICAL_MIN ( 0x00 ),\
+ HID_LOGICAL_MAX_N ( 0xff, 2 ),\
+ HID_REPORT_SIZE ( 8 ),\
+ HID_REPORT_COUNT( sizeof(audio_debug_info_t) ),\
+ HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_COLLECTION_END
+};
+
+// Invoked when received GET HID REPORT DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_hid_descriptor_report_cb(uint8_t itf)
+{
+ (void) itf;
+ return desc_hid_report;
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+#if CFG_AUDIO_DEBUG
+ #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_AUDIO_SPEAKER_STEREO_FB_DESC_LEN + TUD_HID_DESC_LEN)
+#else
+ #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_AUDIO_SPEAKER_STEREO_FB_DESC_LEN)
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+ // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+ // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+ #define EPNUM_AUDIO_FB 0x03
+ #define EPNUM_AUDIO_OUT 0x03
+ #define EPNUM_DEBUG 0x04
+
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+ // ISO endpoints for NRF5x are fixed to 0x08 (0x88)
+ #define EPNUM_AUDIO_FB 0x08
+ #define EPNUM_AUDIO_OUT 0x08
+ #define EPNUM_DEBUG 0x01
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
+ // e.g EP1 OUT & EP1 IN cannot exist together
+ #define EPNUM_AUDIO_FB 0x01
+ #define EPNUM_AUDIO_OUT 0x02
+ #define EPNUM_DEBUG 0x03
+
+#else
+ #define EPNUM_AUDIO_FB 0x01
+ #define EPNUM_AUDIO_OUT 0x01
+ #define EPNUM_DEBUG 0x02
+#endif
+
+uint8_t const desc_configuration_default[] =
+{
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+ // Interface number, string index, byte per sample, bit per sample, EP Out, EP size, EP feedback, feedback EP size,
+ TUD_AUDIO_SPEAKER_STEREO_FB_DESCRIPTOR(0, 4, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_RESOLUTION_RX, EPNUM_AUDIO_OUT, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX, EPNUM_AUDIO_FB | 0x80, 4),
+
+#if CFG_AUDIO_DEBUG
+ // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval
+ TUD_HID_DESCRIPTOR(ITF_NUM_DEBUG, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_DEBUG | 0x80, CFG_TUD_HID_EP_BUFSIZE, 7)
+#endif
+};
+
+#if CFG_QUIRK_OS_GUESSING
+// OS X needs 3 bytes feedback endpoint on FS
+uint8_t const desc_configuration_osx_fs[] =
+{
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+ // Interface number, string index, byte per sample, bit per sample, EP Out, EP size, EP feedback, feedback EP size,
+ TUD_AUDIO_SPEAKER_STEREO_FB_DESCRIPTOR(0, 4, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_RESOLUTION_RX, EPNUM_AUDIO_OUT, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX, EPNUM_AUDIO_FB | 0x80, 3),
+
+#if CFG_AUDIO_DEBUG
+ // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval
+ TUD_HID_DESCRIPTOR(ITF_NUM_DEBUG, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_DEBUG | 0x80, CFG_TUD_HID_EP_BUFSIZE, 7)
+#endif
+};
+#endif
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+ (void)index; // for multiple configurations
+
+#if CFG_QUIRK_OS_GUESSING
+ quirk_os_guessing_desc_configuration_cb();
+ if(tud_speed_get() == TUSB_SPEED_FULL && quirk_os_guessing_get() == QUIRK_OS_GUESSING_OSX) {
+ return desc_configuration_osx_fs;
+ }
+#endif
+ return desc_configuration_default;
+}
+
+//--------------------------------------------------------------------+
+// BOS Descriptor, required for OS guessing quirk
+//--------------------------------------------------------------------+
+
+#define TUD_BOS_USB20_EXT_DESC_LEN 7
+
+#define BOS_TOTAL_LEN (TUD_BOS_DESC_LEN + TUD_BOS_USB20_EXT_DESC_LEN)
+
+// BOS Descriptor is required for webUSB
+uint8_t const desc_bos[] =
+{
+ // total length, number of device caps
+ TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 1),
+
+ // USB 2.0 Extension Descriptor
+ 0x07, TUSB_DESC_DEVICE_CAPABILITY, DEVICE_CAPABILITY_USB20_EXTENSION, 0x00, 0x00, 0x00,0x00
+};
+
+uint8_t const * tud_descriptor_bos_cb(void)
+{
+#if CFG_QUIRK_OS_GUESSING
+ quirk_os_guessing_desc_bos_cb();
+#endif
+ return desc_bos;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] =
+{
+ (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+ "TinyUSB", // 1: Manufacturer
+ "TinyUSB Speaker", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "UAC2 Speaker", // 4: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+ (void) langid;
+ size_t chr_count;
+
+#if CFG_QUIRK_OS_GUESSING
+ quirk_os_guessing_desc_string_cb();
+#endif
+
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
+
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
+
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+ const char *str = string_desc_arr[index];
+
+ // Cap at max char
+ chr_count = strlen(str);
+ size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+ if ( chr_count > max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
+ }
+
+ // first byte is length (including header), second byte is string type
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+ return _desc_str;
+}
diff --git a/examples/device/uac2_speaker_fb/src/usb_descriptors.h b/examples/device/uac2_speaker_fb/src/usb_descriptors.h
new file mode 100644
index 0000000000..9511bf797d
--- /dev/null
+++ b/examples/device/uac2_speaker_fb/src/usb_descriptors.h
@@ -0,0 +1,82 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+// Defined in TUD_AUDIO_SPEAKER_STEREO_FB_DESCRIPTOR
+#define UAC2_ENTITY_CLOCK 0x04
+#define UAC2_ENTITY_INPUT_TERMINAL 0x01
+#define UAC2_ENTITY_FEATURE_UNIT 0x02
+#define UAC2_ENTITY_OUTPUT_TERMINAL 0x03
+
+#define TUD_AUDIO_SPEAKER_STEREO_FB_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+ + TUD_AUDIO_DESC_STD_AC_LEN\
+ + TUD_AUDIO_DESC_CS_AC_LEN\
+ + TUD_AUDIO_DESC_CLK_SRC_LEN\
+ + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN)
+
+#define TUD_AUDIO_SPEAKER_STEREO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epoutsize, _epfb, _epfbsize) \
+ /* Standard Interface Association Descriptor (IAD) */\
+ TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+ /* Standard AC Interface Descriptor(4.7.1) */\
+ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+ TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_DESKTOP_SPEAKER, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+ /* Clock Source Descriptor(4.7.2.1) */\
+ TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_PRO_CLK, /*_ctrl*/ (AUDIO_CTRL_RW << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00),\
+ /* Input Terminal Descriptor(4.7.2.4) */\
+ TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+ /* Output Terminal Descriptor(4.7.2.5) */\
+ TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_OUT_DESKTOP_SPEAKER, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+ /* Feature Unit Descriptor(4.7.2.8) */\
+ TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch2*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS,/*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x01, /*_nEPs*/ 0x02, /*_stridx*/ 0x00),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x01, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+ /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_epsize*/ _epfbsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 4 : 1)\
+
+#endif
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 9d8f0783d2..aa7902a15a 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -55,7 +55,11 @@ int main(void)
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/device/usbtmc/src/usb_descriptors.c b/examples/device/usbtmc/src/usb_descriptors.c
index 54948291ed..85acd990a8 100644
--- a/examples/device/usbtmc/src/usb_descriptors.c
+++ b/examples/device/usbtmc/src/usb_descriptors.c
@@ -38,7 +38,7 @@
#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
_PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
-#define USB_VID 0xCafe
+#define USB_VID 0xcafe
#define USB_BCD 0x0200
//--------------------------------------------------------------------+
@@ -48,8 +48,8 @@ tusb_desc_device_t const desc_device =
{
.bLength = sizeof(tusb_desc_device_t),
.bDescriptorType = TUSB_DESC_DEVICE,
- .bcdUSB = 0x0200,
- .bDeviceClass = 0x00,
+ .bcdUSB = USB_BCD,
+ .bDeviceClass = TUSB_CLASS_UNSPECIFIED,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
@@ -57,7 +57,7 @@ tusb_desc_device_t const desc_device =
.idVendor = USB_VID,
.idProduct = USB_PID,
- .bcdDevice = USB_BCD,
+ .bcdDevice = 0x0100,
.iManufacturer = 0x01,
.iProduct = 0x02,
@@ -112,17 +112,6 @@ enum
#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_USBTMC_DESC_LEN)
-#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
- // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
- // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
- // Note: since CDC EP ( 1 & 2), HID (4) are spot-on, thus we only need to force
- // endpoint number for MSC to 5
- #define EPNUM_MSC 0x05
-#else
- #define EPNUM_MSC 0x03
-#endif
-
-
uint8_t const desc_fs_configuration[] =
{
// Config number, interface count, string index, total length, attribute, power in mA
@@ -151,7 +140,7 @@ tusb_desc_device_qualifier_t const desc_device_qualifier =
.bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
.bcdUSB = USB_BCD,
- .bDeviceClass = 0x00,
+ .bDeviceClass = TUSB_CLASS_UNSPECIFIED,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py
old mode 100644
new mode 100755
diff --git a/examples/device/video_capture/skip.txt b/examples/device/video_capture/skip.txt
index db64cc6398..50302c5447 100644
--- a/examples/device/video_capture/skip.txt
+++ b/examples/device/video_capture/skip.txt
@@ -1,4 +1,6 @@
+mcu:CH32V103
+mcu:CH32V20X
+mcu:MCXA15
mcu:MSP430x5xx
mcu:NUC121
mcu:SAMD11
-family:espressif
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 2a2b0961f0..aeeeb89308 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -68,7 +68,11 @@ int main(void) {
freertos_init_task();
#else
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
@@ -288,7 +292,7 @@ void led_blinking_task(void* param) {
#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE
#define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4)
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
#define USBD_STACK_SIZE 4096
int main(void);
void app_main(void) {
@@ -319,7 +323,11 @@ void usb_device_task(void *param) {
// init device stack on configured roothub port
// This should be called after scheduler/kernel is started.
// Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API.
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
@@ -344,7 +352,7 @@ void freertos_init_task(void) {
#endif
// skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
- #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ #if !TUP_MCU_ESPRESSIF
vTaskStartScheduler();
#endif
}
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index bdfc37d872..3a6daa3d31 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -58,7 +58,7 @@
#endif
// Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
#define CFG_TUSB_OS_INC_PATH freertos/
#endif
@@ -106,7 +106,7 @@
#define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE 256
// use bulk endpoint for streaming interface
-#define CFG_TUD_VIDEO_STREAMING_BULK 1
+ #define CFG_TUD_VIDEO_STREAMING_BULK 0
//#define CFG_EXAMPLE_VIDEO_READONLY
//#define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 5011bee183..b3e19b0f05 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -118,6 +118,8 @@ enum {
#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
// nRF5x ISO can only be endpoint 8
#define EPNUM_VIDEO_IN (CFG_TUD_VIDEO_STREAMING_BULK ? 0x81 : 0x88)
+#elif TU_CHECK_MCU(OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX32690, OPT_MCU_MAX78002)
+ #define EPNUM_VIDEO_IN 0x81
#else
#define EPNUM_VIDEO_IN 0x81
#endif
diff --git a/examples/device/video_capture_2ch/skip.txt b/examples/device/video_capture_2ch/skip.txt
index b36abf721f..0f65082265 100644
--- a/examples/device/video_capture_2ch/skip.txt
+++ b/examples/device/video_capture_2ch/skip.txt
@@ -2,7 +2,11 @@ mcu:MSP430x5xx
mcu:NUC121
mcu:SAMD11
mcu:GD32VF103
+mcu:CH32V103
+mcu:CH32V20X
mcu:CH32V307
+mcu:STM32L0
+mcu:MCXA15
family:espressif
board:curiosity_nano
board:kuiic
@@ -11,3 +15,5 @@ board:lpcxpresso11u68
board:stm32f303disco
board:stm32l412nucleo
board:ek_tm4c123gxl
+board:uno_r4
+board:ra4m1_ek
diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c
index eb1cf25808..dd69837666 100644
--- a/examples/device/video_capture_2ch/src/main.c
+++ b/examples/device/video_capture_2ch/src/main.c
@@ -68,7 +68,11 @@ int main(void) {
freertos_init_task();
#else
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
@@ -296,7 +300,7 @@ void led_blinking_task(void* param) {
#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE
#define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4)
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
#define USBD_STACK_SIZE 4096
int main(void);
void app_main(void) {
@@ -327,7 +331,11 @@ void usb_device_task(void *param) {
// init device stack on configured roothub port
// This should be called after scheduler/kernel is started.
// Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API.
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
@@ -352,7 +360,7 @@ void freertos_init_task(void) {
#endif
// skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
- #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ #if !TUP_MCU_ESPRESSIF
vTaskStartScheduler();
#endif
}
diff --git a/examples/device/video_capture_2ch/src/tusb_config.h b/examples/device/video_capture_2ch/src/tusb_config.h
index fe66d63b5c..43c7dfc903 100644
--- a/examples/device/video_capture_2ch/src/tusb_config.h
+++ b/examples/device/video_capture_2ch/src/tusb_config.h
@@ -58,7 +58,7 @@
#endif
// Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
#define CFG_TUSB_OS_INC_PATH freertos/
#endif
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 800d435b8a..d189af91fb 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -73,8 +73,7 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
#define URL "example.tinyusb.org/webusb-serial/index.html"
-const tusb_desc_webusb_url_t desc_url =
-{
+const tusb_desc_webusb_url_t desc_url = {
.bLength = 3 + sizeof(URL) - 1,
.bDescriptorType = 3, // WEBUSB URL type
.bScheme = 1, // 0: http, 1: https
@@ -86,47 +85,44 @@ static bool web_serial_connected = false;
//------------- prototypes -------------//
void led_blinking_task(void);
void cdc_task(void);
-void webserial_task(void);
/*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
board_init();
// init device stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
if (board_init_after_tusb) {
board_init_after_tusb();
}
- while (1)
- {
+ while (1) {
tud_task(); // tinyusb device task
cdc_task();
- webserial_task();
led_blinking_task();
}
}
// send characters to both CDC and WebUSB
-void echo_all(uint8_t buf[], uint32_t count)
-{
+void echo_all(const uint8_t buf[], uint32_t count) {
// echo to web serial
- if ( web_serial_connected )
- {
+ if (web_serial_connected) {
tud_vendor_write(buf, count);
tud_vendor_write_flush();
}
// echo to cdc
- if ( tud_cdc_connected() )
- {
- for(uint32_t i=0; ibmRequestType_bit.type)
- {
+ switch (request->bmRequestType_bit.type) {
case TUSB_REQ_TYPE_VENDOR:
- switch (request->bRequest)
- {
+ switch (request->bRequest) {
case VENDOR_REQUEST_WEBUSB:
// match vendor request in BOS descriptor
// Get landing page url
- return tud_control_xfer(rhport, request, (void*)(uintptr_t) &desc_url, desc_url.bLength);
+ return tud_control_xfer(rhport, request, (void*)(uintptr_t)&desc_url, desc_url.bLength);
case VENDOR_REQUEST_MICROSOFT:
- if ( request->wIndex == 7 )
- {
+ if (request->wIndex == 7) {
// Get Microsoft OS 2.0 compatible descriptor
uint16_t total_len;
- memcpy(&total_len, desc_ms_os_20+8, 2);
+ memcpy(&total_len, desc_ms_os_20 + 8, 2);
- return tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_ms_os_20, total_len);
- }else
- {
+ return tud_control_xfer(rhport, request, (void*)(uintptr_t)desc_ms_os_20, total_len);
+ } else {
return false;
}
default: break;
}
- break;
+ break;
case TUSB_REQ_TYPE_CLASS:
- if (request->bRequest == 0x22)
- {
+ if (request->bRequest == 0x22) {
// Webserial simulate the CDC_REQUEST_SET_CONTROL_LINE_STATE (0x22) to connect and disconnect.
web_serial_connected = (request->wValue != 0);
// Always lit LED if connected
- if ( web_serial_connected )
- {
+ if (web_serial_connected) {
board_led_write(true);
blink_interval_ms = BLINK_ALWAYS_ON;
tud_vendor_write_str("\r\nWebUSB interface connected\r\n");
tud_vendor_write_flush();
- }else
- {
+ } else {
blink_interval_ms = BLINK_MOUNTED;
}
// response with status OK
return tud_control_status(rhport, request);
}
- break;
+ break;
default: break;
}
@@ -233,32 +217,24 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
return false;
}
-void webserial_task(void)
-{
- if ( web_serial_connected )
- {
- if ( tud_vendor_available() )
- {
- uint8_t buf[64];
- uint32_t count = tud_vendor_read(buf, sizeof(buf));
+void tud_vendor_rx_cb(uint8_t itf, uint8_t const* buffer, uint16_t bufsize) {
+ (void) itf;
- // echo back to both web serial and cdc
- echo_all(buf, count);
- }
- }
-}
+ echo_all(buffer, bufsize);
+ // if using RX buffered is enabled, we need to flush the buffer to make room for new data
+ #if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+ tud_vendor_read_flush();
+ #endif
+}
//--------------------------------------------------------------------+
// USB CDC
//--------------------------------------------------------------------+
-void cdc_task(void)
-{
- if ( tud_cdc_connected() )
- {
+void cdc_task(void) {
+ if (tud_cdc_connected()) {
// connected and there are data available
- if ( tud_cdc_available() )
- {
+ if (tud_cdc_available()) {
uint8_t buf[64];
uint32_t count = tud_cdc_read(buf, sizeof(buf));
@@ -270,34 +246,30 @@ void cdc_task(void)
}
// Invoked when cdc when line state changed e.g connected/disconnected
-void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
-{
- (void) itf;
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
+ (void)itf;
// connected
- if ( dtr && rts )
- {
+ if (dtr && rts) {
// print initial message when connected
tud_cdc_write_str("\r\nTinyUSB WebUSB device example\r\n");
}
}
// Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
- (void) itf;
+void tud_cdc_rx_cb(uint8_t itf) {
+ (void)itf;
}
//--------------------------------------------------------------------+
// BLINKING TASK
//--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
static uint32_t start_ms = 0;
static bool led_state = false;
// Blink every interval ms
- if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+ if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
start_ms += blink_interval_ms;
board_led_write(led_state);
diff --git a/examples/device/webusb_serial/src/tusb_config.h b/examples/device/webusb_serial/src/tusb_config.h
index fde732b9ec..b86ad37525 100644
--- a/examples/device/webusb_serial/src/tusb_config.h
+++ b/examples/device/webusb_serial/src/tusb_config.h
@@ -102,7 +102,7 @@
#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
// Vendor FIFO size of TX and RX
-// If not configured vendor endpoints will not be buffered
+// If zero: vendor endpoints will not be buffered
#define CFG_TUD_VENDOR_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_VENDOR_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index b01fae8e3e..2b69a5b560 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -87,29 +87,40 @@ enum
#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
- #define EPNUM_CDC_IN 2
- #define EPNUM_CDC_OUT 2
- #define EPNUM_VENDOR_IN 5
- #define EPNUM_VENDOR_OUT 5
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
- // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
- // e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_CDC_IN 2
- #define EPNUM_CDC_OUT 3
- #define EPNUM_VENDOR_IN 4
- #define EPNUM_VENDOR_OUT 5
-#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+ #define EPNUM_CDC_NOTIF 0x81
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x82
+
+ #define EPNUM_VENDOR_OUT 0x05
+ #define EPNUM_VENDOR_IN 0x85
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+ // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+ // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+ #define EPNUM_CDC_NOTIF 0x83
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x81
+
+ #define EPNUM_VENDOR_OUT 0x05
+ #define EPNUM_VENDOR_IN 0x84
+
+#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY)
+ // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h
// e.g EP1 OUT & EP1 IN cannot exist together
- #define EPNUM_CDC_IN 2
- #define EPNUM_CDC_OUT 3
- #define EPNUM_VENDOR_IN 4
- #define EPNUM_VENDOR_OUT 5
+ #define EPNUM_CDC_NOTIF 0x81
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x83
+
+ #define EPNUM_VENDOR_OUT 0x04
+ #define EPNUM_VENDOR_IN 0x85
+
#else
- #define EPNUM_CDC_IN 2
- #define EPNUM_CDC_OUT 2
- #define EPNUM_VENDOR_IN 3
- #define EPNUM_VENDOR_OUT 3
+ #define EPNUM_CDC_NOTIF 0x81
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x82
+
+ #define EPNUM_VENDOR_OUT 0x03
+ #define EPNUM_VENDOR_IN 0x83
#endif
uint8_t const desc_configuration[] =
@@ -118,7 +129,7 @@ uint8_t const desc_configuration[] =
TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
// Interface number, string index, EP notification address and size, EP data address (out, in) and size.
- TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, 0x81, 8, EPNUM_CDC_OUT, 0x80 | EPNUM_CDC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),
+ TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, 0x80 | EPNUM_CDC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),
// Interface number, string index, EP Out & IN address, EP size
TUD_VENDOR_DESCRIPTOR(ITF_NUM_VENDOR, 5, EPNUM_VENDOR_OUT, 0x80 | EPNUM_VENDOR_IN, TUD_OPT_HIGH_SPEED ? 512 : 64)
diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt
index 15081cf26b..f11074e936 100644
--- a/examples/dual/CMakeLists.txt
+++ b/examples/dual/CMakeLists.txt
@@ -10,4 +10,5 @@ if (FAMILY STREQUAL "rp2040" AND NOT TARGET tinyusb_pico_pio_usb)
else ()
# family_add_subdirectory will filter what to actually add based on selected FAMILY
family_add_subdirectory(host_hid_to_device_cdc)
+ family_add_subdirectory(host_info_to_device_cdc)
endif ()
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 96a2beff53..633f7a6acf 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -55,14 +55,14 @@ const uint8_t colemak[128] = {
};
#endif
-static uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII };
+static uint8_t const keycode2ascii[128][2] = {HID_KEYCODE_TO_ASCII};
/* Blink pattern
* - 250 ms : device not mounted
* - 1000 ms : device mounted
* - 2500 ms : device is suspended
*/
-enum {
+enum {
BLINK_NOT_MOUNTED = 250,
BLINK_MOUNTED = 1000,
BLINK_SUSPENDED = 2500,
@@ -73,22 +73,29 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
void led_blinking_task(void);
/*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
board_init();
printf("TinyUSB Host HID <-> Device CDC Example\r\n");
// init device and host stack on configured roothub port
- tud_init(BOARD_TUD_RHPORT);
- tuh_init(BOARD_TUH_RHPORT);
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+ tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUH_RHPORT, &host_init);
if (board_init_after_tusb) {
board_init_after_tusb();
}
- while (1)
- {
+ while (1) {
tud_task(); // tinyusb device task
tuh_task(); // tinyusb host task
led_blinking_task();
@@ -102,35 +109,30 @@ int main(void)
//--------------------------------------------------------------------+
// Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
blink_interval_ms = BLINK_MOUNTED;
}
// Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
blink_interval_ms = BLINK_NOT_MOUNTED;
}
// Invoked when usb bus is suspended
// remote_wakeup_en : if host allow us to perform remote wakeup
// Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
(void) remote_wakeup_en;
blink_interval_ms = BLINK_SUSPENDED;
}
// Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
+void tud_resume_cb(void) {
blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
// Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
+void tud_cdc_rx_cb(uint8_t itf) {
(void) itf;
char buf[64];
@@ -149,38 +151,36 @@ void tud_cdc_rx_cb(uint8_t itf)
// can be used to parse common/simple enough descriptor.
// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
// therefore report_desc = NULL, desc_len = 0
-void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
-{
- (void)desc_report;
- (void)desc_len;
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len) {
+ (void) desc_report;
+ (void) desc_len;
// Interface protocol (hid_interface_protocol_enum_t)
- const char* protocol_str[] = { "None", "Keyboard", "Mouse" };
+ const char* protocol_str[] = {"None", "Keyboard", "Mouse"};
uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
uint16_t vid, pid;
tuh_vid_pid_get(dev_addr, &vid, &pid);
char tempbuf[256];
- int count = sprintf(tempbuf, "[%04x:%04x][%u] HID Interface%u, Protocol = %s\r\n", vid, pid, dev_addr, instance, protocol_str[itf_protocol]);
+ int count = sprintf(
+ tempbuf, "[%04x:%04x][%u] HID Interface%u, Protocol = %s\r\n", vid, pid, dev_addr, instance,
+ protocol_str[itf_protocol]);
tud_cdc_write(tempbuf, (uint32_t) count);
tud_cdc_write_flush();
// Receive report from boot keyboard & mouse only
// tuh_hid_report_received_cb() will be invoked when report is available
- if (itf_protocol == HID_ITF_PROTOCOL_KEYBOARD || itf_protocol == HID_ITF_PROTOCOL_MOUSE)
- {
- if ( !tuh_hid_receive_report(dev_addr, instance) )
- {
+ if (itf_protocol == HID_ITF_PROTOCOL_KEYBOARD || itf_protocol == HID_ITF_PROTOCOL_MOUSE) {
+ if (!tuh_hid_receive_report(dev_addr, instance)) {
tud_cdc_write_str("Error: cannot request report\r\n");
}
}
}
// Invoked when device with hid interface is un-mounted
-void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
-{
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) {
char tempbuf[256];
int count = sprintf(tempbuf, "[%u] HID Interface%u is unmounted\r\n", dev_addr, instance);
tud_cdc_write(tempbuf, (uint32_t) count);
@@ -188,11 +188,9 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
}
// look up new key in previous keys
-static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode)
-{
- for(uint8_t i=0; i<6; i++)
- {
- if (report->keycode[i] == keycode) return true;
+static inline bool find_key_in_report(hid_keyboard_report_t const* report, uint8_t keycode) {
+ for (uint8_t i = 0; i < 6; i++) {
+ if (report->keycode[i] == keycode) return true;
}
return false;
@@ -200,22 +198,17 @@ static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8
// convert hid keycode to ascii and print via usb device CDC (ignore non-printable)
-static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const *report)
-{
+static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const* report) {
(void) dev_addr;
- static hid_keyboard_report_t prev_report = { 0, 0, {0} }; // previous report to check key released
+ static hid_keyboard_report_t prev_report = {0, 0, {0}}; // previous report to check key released
bool flush = false;
- for(uint8_t i=0; i<6; i++)
- {
+ for (uint8_t i = 0; i < 6; i++) {
uint8_t keycode = report->keycode[i];
- if ( keycode )
- {
- if ( find_key_in_report(&prev_report, keycode) )
- {
+ if (keycode) {
+ if (find_key_in_report(&prev_report, keycode)) {
// exist in previous report means the current key is holding
- }else
- {
+ } else {
// not existed in previous report means the current key is pressed
// remap the key code for Colemak layout
@@ -227,8 +220,7 @@ static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const *re
bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
uint8_t ch = keycode2ascii[keycode][is_shift ? 1 : 0];
- if (ch)
- {
+ if (ch) {
if (ch == '\n') tud_cdc_write("\r", 1);
tud_cdc_write(&ch, 1);
flush = true;
@@ -244,13 +236,12 @@ static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const *re
}
// send mouse report to usb device CDC
-static void process_mouse_report(uint8_t dev_addr, hid_mouse_report_t const * report)
-{
+static void process_mouse_report(uint8_t dev_addr, hid_mouse_report_t const* report) {
//------------- button state -------------//
//uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
- char l = report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-';
+ char l = report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-';
char m = report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-';
- char r = report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-';
+ char r = report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-';
char tempbuf[32];
int count = sprintf(tempbuf, "[%u] %c%c%c %d %d %d\r\n", dev_addr, l, m, r, report->x, report->y, report->wheel);
@@ -260,27 +251,25 @@ static void process_mouse_report(uint8_t dev_addr, hid_mouse_report_t const * re
}
// Invoked when received report from device via interrupt endpoint
-void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
-{
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len) {
(void) len;
uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
- switch(itf_protocol)
- {
+ switch (itf_protocol) {
case HID_ITF_PROTOCOL_KEYBOARD:
- process_kbd_report(dev_addr, (hid_keyboard_report_t const*) report );
- break;
+ process_kbd_report(dev_addr, (hid_keyboard_report_t const*) report);
+ break;
case HID_ITF_PROTOCOL_MOUSE:
- process_mouse_report(dev_addr, (hid_mouse_report_t const*) report );
- break;
+ process_mouse_report(dev_addr, (hid_mouse_report_t const*) report);
+ break;
- default: break;
+ default:
+ break;
}
// continue to request to receive report
- if ( !tuh_hid_receive_report(dev_addr, instance) )
- {
+ if (!tuh_hid_receive_report(dev_addr, instance)) {
tud_cdc_write_str("Error: cannot request report\r\n");
}
}
@@ -288,13 +277,12 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons
//--------------------------------------------------------------------+
// Blinking Task
//--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
static uint32_t start_ms = 0;
static bool led_state = false;
// Blink every interval ms
- if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+ if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
start_ms += blink_interval_ms;
board_led_write(led_state);
diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index 8133ed4187..2843e0b83c 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -23,8 +23,8 @@
*
*/
-#ifndef _TUSB_CONFIG_H_
-#define _TUSB_CONFIG_H_
+#ifndef TUSB_CONFIG_H_
+#define TUSB_CONFIG_H_
#ifdef __cplusplus
extern "C" {
@@ -144,4 +144,4 @@
}
#endif
-#endif /* _TUSB_CONFIG_H_ */
+#endif
diff --git a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
index 2936200425..9d57737fb9 100644
--- a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
+++ b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
@@ -42,44 +42,41 @@
//--------------------------------------------------------------------+
// Device Descriptors
//--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
- .bLength = sizeof(tusb_desc_device_t),
- .bDescriptorType = TUSB_DESC_DEVICE,
- .bcdUSB = USB_BCD,
+tusb_desc_device_t const desc_device = {
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = USB_BCD,
- // Use Interface Association Descriptor (IAD) for CDC
- // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
- .bDeviceClass = TUSB_CLASS_MISC,
- .bDeviceSubClass = MISC_SUBCLASS_COMMON,
- .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ // Use Interface Association Descriptor (IAD) for CDC
+ // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
- .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
- .idVendor = USB_VID,
- .idProduct = USB_PID,
- .bcdDevice = 0x0100,
+ .idVendor = USB_VID,
+ .idProduct = USB_PID,
+ .bcdDevice = 0x0100,
- .iManufacturer = 0x01,
- .iProduct = 0x02,
- .iSerialNumber = 0x03,
+ .iManufacturer = 0x01,
+ .iProduct = 0x02,
+ .iSerialNumber = 0x03,
- .bNumConfigurations = 0x01
+ .bNumConfigurations = 0x01
};
// Invoked when received GET DEVICE DESCRIPTOR
// Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
- return (uint8_t const *) &desc_device;
+uint8_t const* tud_descriptor_device_cb(void) {
+ return (uint8_t const*) &desc_device;
}
//--------------------------------------------------------------------+
// Configuration Descriptor
//--------------------------------------------------------------------+
-enum
-{
+enum {
ITF_NUM_CDC = 0,
ITF_NUM_CDC_DATA,
ITF_NUM_TOTAL
@@ -92,7 +89,7 @@ enum
#define EPNUM_CDC_OUT 0x02
#define EPNUM_CDC_IN 0x82
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
// SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_CDC_NOTIF 0x81
@@ -109,7 +106,7 @@ enum
#define EPNUM_CDC_IN 0x81
#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
- // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+// FT9XX doesn't support a same endpoint number with different direction IN and OUT
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_CDC_NOTIF 0x81
#define EPNUM_CDC_OUT 0x02
@@ -125,21 +122,19 @@ enum
#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
// full speed configuration
-uint8_t const desc_fs_configuration[] =
-{
- // Config number, interface count, string index, total length, attribute, power in mA
- TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+uint8_t const desc_fs_configuration[] = {
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
- // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
- TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+ // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+ TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
};
#if TUD_OPT_HIGH_SPEED
// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
// high speed configuration
-uint8_t const desc_hs_configuration[] =
-{
+uint8_t const desc_hs_configuration[] = {
// Config number, interface count, string index, total length, attribute, power in mA
TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
@@ -151,8 +146,7 @@ uint8_t const desc_hs_configuration[] =
uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
-tusb_desc_device_qualifier_t const desc_device_qualifier =
-{
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
.bLength = sizeof(tusb_desc_device_qualifier_t),
.bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
.bcdUSB = USB_BCD,
@@ -170,16 +164,14 @@ tusb_desc_device_qualifier_t const desc_device_qualifier =
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
// device_qualifier descriptor describes information about a high-speed capable device that would
// change if the device were operating at the other speed. If not highspeed capable stall this request.
-uint8_t const* tud_descriptor_device_qualifier_cb(void)
-{
+uint8_t const* tud_descriptor_device_qualifier_cb(void) {
return (uint8_t const*) &desc_device_qualifier;
}
// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
-uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
-{
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
(void) index; // for multiple configurations
// if link speed is high return fullspeed config, and vice versa
@@ -199,8 +191,7 @@ uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
// Invoked when received GET CONFIGURATION DESCRIPTOR
// Application return pointer to descriptor
// Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
(void) index; // for multiple configurations
#if TUD_OPT_HIGH_SPEED
@@ -224,24 +215,23 @@ enum {
};
// array of pointer to string descriptors
-char const *string_desc_arr[] =
-{
- (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
- "TinyUSB", // 1: Manufacturer
- "TinyUSB Device", // 2: Product
- NULL, // 3: Serials will use unique ID if possible
- "TinyUSB CDC", // 4: CDC Interface
+char const* string_desc_arr[] = {
+ (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
+ "TinyUSB", // 1: Manufacturer
+ "TinyUSB Device", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "TinyUSB CDC", // 4: CDC Interface
};
static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
size_t chr_count;
- switch ( index ) {
+ switch (index) {
case STRID_LANGID:
memcpy(&_desc_str[1], string_desc_arr[0], 2);
chr_count = 1;
@@ -255,17 +245,17 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
// Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
// https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+ if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) return NULL;
- const char *str = string_desc_arr[index];
+ const char* str = string_desc_arr[index];
// Cap at max char
chr_count = strlen(str);
size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
- if ( chr_count > max_count ) chr_count = max_count;
+ if (chr_count > max_count) chr_count = max_count;
// Convert ASCII string into UTF-16
- for ( size_t i = 0; i < chr_count; i++ ) {
+ for (size_t i = 0; i < chr_count; i++) {
_desc_str[1 + i] = str[i];
}
break;
diff --git a/examples/dual/host_info_to_device_cdc/CMakeLists.txt b/examples/dual/host_info_to_device_cdc/CMakeLists.txt
new file mode 100644
index 0000000000..a6557c2d05
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/CMakeLists.txt
@@ -0,0 +1,40 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_dual_usb_example(${PROJECT} noos)
+
+# due to warnings from Pico-PIO-USB
+target_compile_options(${PROJECT} PUBLIC
+ -Wno-error=shadow
+ -Wno-error=cast-align
+ -Wno-error=cast-qual
+ -Wno-error=redundant-decls
+ -Wno-error=sign-conversion
+ -Wno-error=conversion
+ -Wno-error=sign-compare
+ -Wno-error=unused-function
+ )
diff --git a/examples/dual/host_info_to_device_cdc/Makefile b/examples/dual/host_info_to_device_cdc/Makefile
new file mode 100644
index 0000000000..0ede79c176
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/Makefile
@@ -0,0 +1,17 @@
+include ../../build_system/make/make.mk
+
+INC += \
+ src \
+ $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
+
+SRC_C += \
+ src/host/hub.c \
+ src/host/usbh.c
+
+include ../../build_system/make/rules.mk
diff --git a/examples/dual/host_info_to_device_cdc/only.txt b/examples/dual/host_info_to_device_cdc/only.txt
new file mode 100644
index 0000000000..cfc87eb4ec
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/only.txt
@@ -0,0 +1,6 @@
+board:mimxrt1060_evk
+board:mimxrt1064_evk
+board:mcb1800
+mcu:RP2040
+mcu:ra6m5
+mcu:MAX3421
diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c
new file mode 100644
index 0000000000..668808db25
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/src/main.c
@@ -0,0 +1,302 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* Host example will get device descriptors of attached devices and print it out via device cdc as follows:
+ * Device 1: ID 046d:c52f SN 11223344
+ Device Descriptor:
+ bLength 18
+ bDescriptorType 1
+ bcdUSB 0200
+ bDeviceClass 0
+ bDeviceSubClass 0
+ bDeviceProtocol 0
+ bMaxPacketSize0 8
+ idVendor 0x046d
+ idProduct 0xc52f
+ bcdDevice 2200
+ iManufacturer 1 Logitech
+ iProduct 2 USB Receiver
+ iSerialNumber 0
+ bNumConfigurations 1
+ *
+ */
+
+#include
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+// Language ID: English
+#define LANGUAGE_ID 0x0409
+
+/* Blink pattern
+ * - 250 ms : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum {
+ BLINK_NOT_MOUNTED = 250,
+ BLINK_MOUNTED = 1000,
+ BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+static bool is_print[CFG_TUH_DEVICE_MAX+1] = { 0 };
+
+static void print_utf16(uint16_t *temp_buf, size_t buf_len);
+void led_blinking_task(void);
+void cdc_task(void);
+
+/*------------- MAIN -------------*/
+int main(void) {
+ board_init();
+
+ printf("TinyUSB Host Information -> Device CDC Example\r\n");
+
+ // init device and host stack on configured roothub port
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUD_RHPORT, &dev_init);
+
+ tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUH_RHPORT, &host_init);
+
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
+ while (1) {
+ tud_task(); // tinyusb device task
+ tuh_task(); // tinyusb host task
+ cdc_task();
+ led_blinking_task();
+ }
+
+ return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device CDC
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void) {
+ blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+ blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en) {
+ (void) remote_wakeup_en;
+ blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void) {
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+#if 1
+#define cdc_printf(...) \
+ do { \
+ char _tempbuf[256]; \
+ int count = sprintf(_tempbuf, __VA_ARGS__); \
+ tud_cdc_write(_tempbuf, (uint32_t) count); \
+ tud_cdc_write_flush(); \
+ tud_task(); \
+ } while(0)
+#endif
+
+//#define cdc_printf printf
+
+void print_device_info(uint8_t daddr) {
+ tusb_desc_device_t desc_device;
+ uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc_device, 18);
+ if (XFER_RESULT_SUCCESS != xfer_result) {
+ tud_cdc_write_str("Failed to get device descriptor\r\n");
+ return;
+ }
+
+ // Get String descriptor using Sync API
+ uint16_t serial[64];
+ uint16_t buf[128];
+
+ cdc_printf("Device %u: ID %04x:%04x SN ", daddr, desc_device.idVendor, desc_device.idProduct);
+ xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, serial, sizeof(serial));
+ if (XFER_RESULT_SUCCESS != xfer_result) {
+ serial[0] = 'n';
+ serial[1] = '/';
+ serial[2] = 'a';
+ serial[3] = 0;
+ }
+ print_utf16(serial, TU_ARRAY_SIZE(serial));
+ tud_cdc_write_str("\r\n");
+
+ cdc_printf("Device Descriptor:\r\n");
+ cdc_printf(" bLength %u\r\n" , desc_device.bLength);
+ cdc_printf(" bDescriptorType %u\r\n" , desc_device.bDescriptorType);
+ cdc_printf(" bcdUSB %04x\r\n" , desc_device.bcdUSB);
+ cdc_printf(" bDeviceClass %u\r\n" , desc_device.bDeviceClass);
+ cdc_printf(" bDeviceSubClass %u\r\n" , desc_device.bDeviceSubClass);
+ cdc_printf(" bDeviceProtocol %u\r\n" , desc_device.bDeviceProtocol);
+ cdc_printf(" bMaxPacketSize0 %u\r\n" , desc_device.bMaxPacketSize0);
+ cdc_printf(" idVendor 0x%04x\r\n" , desc_device.idVendor);
+ cdc_printf(" idProduct 0x%04x\r\n" , desc_device.idProduct);
+ cdc_printf(" bcdDevice %04x\r\n" , desc_device.bcdDevice);
+
+ cdc_printf(" iManufacturer %u " , desc_device.iManufacturer);
+ xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
+ if (XFER_RESULT_SUCCESS == xfer_result ) {
+ print_utf16(buf, TU_ARRAY_SIZE(buf));
+ }
+ tud_cdc_write_str("\r\n");
+
+ cdc_printf(" iProduct %u " , desc_device.iProduct);
+ xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
+ if (XFER_RESULT_SUCCESS == xfer_result) {
+ print_utf16(buf, TU_ARRAY_SIZE(buf));
+ }
+ tud_cdc_write_str("\r\n");
+
+ cdc_printf(" iSerialNumber %u " , desc_device.iSerialNumber);
+ tud_cdc_write_str((char*)serial); // serial is already to UTF-8
+ tud_cdc_write_str("\r\n");
+
+ cdc_printf(" bNumConfigurations %u\r\n" , desc_device.bNumConfigurations);
+}
+
+void cdc_task(void) {
+ if (tud_cdc_connected()) {
+ for (uint8_t daddr = 1; daddr <= CFG_TUH_DEVICE_MAX; daddr++) {
+ if (tuh_mounted(daddr)) {
+ if (is_print[daddr]) {
+ is_print[daddr] = false;
+ print_device_info(daddr);
+ tud_cdc_write_flush();
+ }
+ }
+ }
+ }
+}
+
+//--------------------------------------------------------------------+
+// Host Get device information
+//--------------------------------------------------------------------+
+void tuh_mount_cb(uint8_t daddr) {
+ printf("mounted device %u\r\n", daddr);
+ is_print[daddr] = true;
+}
+
+void tuh_umount_cb(uint8_t daddr) {
+ printf("unmounted device %u\r\n", daddr);
+ is_print[daddr] = false;
+}
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void) {
+ static uint32_t start_ms = 0;
+ static bool led_state = false;
+
+ // Blink every interval ms
+ if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+ start_ms += blink_interval_ms;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state; // toggle
+}
+
+//--------------------------------------------------------------------+
+// String Descriptor Helper
+//--------------------------------------------------------------------+
+
+static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {
+ // TODO: Check for runover.
+ (void)utf8_len;
+ // Get the UTF-16 length out of the data itself.
+
+ for (size_t i = 0; i < utf16_len; i++) {
+ uint16_t chr = utf16[i];
+ if (chr < 0x80) {
+ *utf8++ = chr & 0xffu;
+ } else if (chr < 0x800) {
+ *utf8++ = (uint8_t)(0xC0 | (chr >> 6 & 0x1F));
+ *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
+ } else {
+ // TODO: Verify surrogate.
+ *utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F));
+ *utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F));
+ *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
+ }
+ // TODO: Handle UTF-16 code points that take two entries.
+ }
+}
+
+// Count how many bytes a utf-16-le encoded string will take in utf-8.
+static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
+ size_t total_bytes = 0;
+ for (size_t i = 0; i < len; i++) {
+ uint16_t chr = buf[i];
+ if (chr < 0x80) {
+ total_bytes += 1;
+ } else if (chr < 0x800) {
+ total_bytes += 2;
+ } else {
+ total_bytes += 3;
+ }
+ // TODO: Handle UTF-16 code points that take two entries.
+ }
+ return (int) total_bytes;
+}
+
+static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
+ if ((temp_buf[0] & 0xff) == 0) return; // empty
+ size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
+ size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
+ _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
+ ((uint8_t*) temp_buf)[utf8_len] = '\0';
+
+ tud_cdc_write(temp_buf, utf8_len);
+ tud_cdc_write_flush();
+ tud_task();
+}
diff --git a/examples/dual/host_info_to_device_cdc/src/tusb_config.h b/examples/dual/host_info_to_device_cdc/src/tusb_config.h
new file mode 100644
index 0000000000..bb47fbf4a8
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/src/tusb_config.h
@@ -0,0 +1,143 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef TUSB_CONFIG_H_
+#define TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+// RHPort number used for host can be defined by board.mk, default to port 1
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT 1
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Device stack, Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_ENABLED 1
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
+
+// Enable Host stack, Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_ENABLED 1
+#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+// Use pico-pio-usb as host controller for raspberry rp2040
+#define CFG_TUH_RPI_PIO_USB 1
+#endif
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUD_MEM_SECTION
+#define CFG_TUD_MEM_SECTION
+#endif
+
+#ifndef CFG_TUD_MEM_ALIGN
+#define CFG_TUD_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC 1
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+//--------------------------------------------------------------------
+// HOST CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+#define CFG_TUH_HUB 1
+// max device support (excluding hub device)
+#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/examples/dual/host_info_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_info_to_device_cdc/src/usb_descriptors.c
new file mode 100644
index 0000000000..9d57737fb9
--- /dev/null
+++ b/examples/dual/host_info_to_device_cdc/src/usb_descriptors.c
@@ -0,0 +1,268 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ * [MSB] HID | MSC | CDC [LSB]
+ */
+#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) )
+#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+ _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
+
+#define USB_VID 0xCafe
+#define USB_BCD 0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device = {
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = USB_BCD,
+
+ // Use Interface Association Descriptor (IAD) for CDC
+ // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+ .idVendor = USB_VID,
+ .idProduct = USB_PID,
+ .bcdDevice = 0x0100,
+
+ .iManufacturer = 0x01,
+ .iProduct = 0x02,
+ .iSerialNumber = 0x03,
+
+ .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const* tud_descriptor_device_cb(void) {
+ return (uint8_t const*) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum {
+ ITF_NUM_CDC = 0,
+ ITF_NUM_CDC_DATA,
+ ITF_NUM_TOTAL
+};
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+ // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+ // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
+ #define EPNUM_CDC_NOTIF 0x81
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x82
+
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
+ // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+ // e.g EP1 OUT & EP1 IN cannot exist together
+ #define EPNUM_CDC_NOTIF 0x81
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x83
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+ // CXD56 doesn't support a same endpoint number with different direction IN and OUT
+ // e.g EP1 OUT & EP1 IN cannot exist together
+ // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+ // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+ #define EPNUM_CDC_NOTIF 0x83
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x81
+
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+// FT9XX doesn't support a same endpoint number with different direction IN and OUT
+ // e.g EP1 OUT & EP1 IN cannot exist together
+ #define EPNUM_CDC_NOTIF 0x81
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x83
+
+#else
+ #define EPNUM_CDC_NOTIF 0x81
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x82
+
+#endif
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] = {
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+ // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+ TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] = {
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+ // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+ TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+ .bLength = sizeof(tusb_desc_device_qualifier_t),
+ .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
+ .bcdUSB = USB_BCD,
+
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+ .bNumConfigurations = 0x01,
+ .bReserved = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void) {
+ return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+ (void) index; // for multiple configurations
+
+ // if link speed is high return fullspeed config, and vice versa
+ // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+ memcpy(desc_other_speed_config,
+ (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration,
+ CONFIG_TOTAL_LEN);
+
+ desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+ return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
+ (void) index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+ // Although we are highspeed, host may be fullspeed.
+ return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration;
+#else
+ return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr[] = {
+ (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
+ "TinyUSB", // 1: Manufacturer
+ "TinyUSB Device", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "TinyUSB CDC", // 4: CDC Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+ (void) langid;
+ size_t chr_count;
+
+ switch (index) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
+
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
+
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+ if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) return NULL;
+
+ const char* str = string_desc_arr[index];
+
+ // Cap at max char
+ chr_count = strlen(str);
+ size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+ if (chr_count > max_count) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for (size_t i = 0; i < chr_count; i++) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
+ }
+
+ // first byte is length (including header), second byte is string type
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+ return _desc_str;
+}
diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index e6a2ece149..793f6ab08d 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -9,5 +9,6 @@ family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
family_add_subdirectory(bare_api)
family_add_subdirectory(cdc_msc_hid)
family_add_subdirectory(cdc_msc_hid_freertos)
+family_add_subdirectory(device_info)
family_add_subdirectory(hid_controller)
family_add_subdirectory(msc_file_explorer)
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 940840a30a..f582f4f5ae 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -23,10 +23,6 @@
*
*/
-/* This example current worked and tested with following controller
- * - Sony DualShock 4 [CUH-ZCT2x] VID = 0x054c, PID = 0x09cc
- */
-
#include
#include
@@ -34,6 +30,7 @@
#include "bsp/board_api.h"
#include "tusb.h"
+#include "class/hid/hid.h"
// English
#define LANGUAGE_ID 0x0409
@@ -65,7 +62,11 @@ int main(void)
printf("TinyUSB Bare API Example\r\n");
// init host stack on configured roothub port
- tuh_init(BOARD_TUH_RHPORT);
+ tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUH_RHPORT, &host_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index 432446e947..fab233be02 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -23,8 +23,8 @@
*
*/
-#ifndef _TUSB_CONFIG_H_
-#define _TUSB_CONFIG_H_
+#ifndef TUSB_CONFIG_H_
+#define TUSB_CONFIG_H_
#ifdef __cplusplus
extern "C" {
@@ -118,4 +118,4 @@
}
#endif
-#endif /* _TUSB_CONFIG_H_ */
+#endif
diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index f0d42a08f0..6bb3a2072d 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -235,6 +235,7 @@ static void process_mouse_report(hid_mouse_report_t const * report)
static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
{
(void) dev_addr;
+ (void) len;
uint8_t const rpt_count = hid_info[instance].report_count;
tuh_hid_report_info_t* rpt_info_arr = hid_info[instance].report_info;
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index a3b80e030b..71257c0fed 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -50,7 +50,11 @@ int main(void) {
printf("TinyUSB Host CDC MSC HID Example\r\n");
// init host stack on configured roothub port
- tuh_init(BOARD_TUH_RHPORT);
+ tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUH_RHPORT, &host_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt
index 81d993ffa9..1e0e600754 100644
--- a/examples/host/cdc_msc_hid_freertos/only.txt
+++ b/examples/host/cdc_msc_hid_freertos/only.txt
@@ -8,5 +8,4 @@ mcu:MIMXRT10XX
mcu:MIMXRT11XX
mcu:MSP432E4
mcu:RX65X
-mcu:RAXXX
mcu:MAX3421
diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
index 7d246af67b..f3495ab284 100644
--- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -27,7 +27,7 @@
#include "tusb.h"
#include "bsp/board_api.h"
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index 069cbdc908..7fb84a40f2 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -30,7 +30,7 @@
#include "bsp/board_api.h"
#include "tusb.h"
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
@@ -107,14 +107,14 @@ int main(void) {
xTimerStart(blinky_tm, 0);
// skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if !TUP_MCU_ESPRESSIF
vTaskStartScheduler();
#endif
return 0;
}
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
void app_main(void) {
main();
}
@@ -126,7 +126,15 @@ static void usb_host_task(void *param) {
(void) param;
// init host stack on configured roothub port
- tuh_init(BOARD_TUH_RHPORT);
+ tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUSB_SPEED_AUTO
+ };
+
+ if (!tusb_init(BOARD_TUH_RHPORT, &host_init)) {
+ printf("Failed to init USB Host Stack\r\n");
+ vTaskSuspend(NULL);
+ }
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index 35de5ee502..0aab2cd2fd 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -44,7 +44,7 @@
#endif
// Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
#define CFG_TUSB_OS_INC_PATH freertos/
#endif
diff --git a/examples/host/device_info/CMakeLists.txt b/examples/host/device_info/CMakeLists.txt
new file mode 100644
index 0000000000..6a16155ec7
--- /dev/null
+++ b/examples/host/device_info/CMakeLists.txt
@@ -0,0 +1,32 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/device_info/Makefile b/examples/host/device_info/Makefile
new file mode 100644
index 0000000000..0235e08c37
--- /dev/null
+++ b/examples/host/device_info/Makefile
@@ -0,0 +1,13 @@
+include ../../build_system/make/make.mk
+
+INC += \
+ src \
+ $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+ src/main.c
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../build_system/make/rules.mk
diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt
new file mode 100644
index 0000000000..b3f4468bbc
--- /dev/null
+++ b/examples/host/device_info/only.txt
@@ -0,0 +1,14 @@
+mcu:KINETIS_KL
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MAX3421
+mcu:MIMXRT1XXX
+mcu:MIMXRT10XX
+mcu:MIMXRT11XX
+mcu:MSP432E4
+mcu:RP2040
+mcu:RX65X
+mcu:RAXXX
diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c
new file mode 100644
index 0000000000..0ff4f32e99
--- /dev/null
+++ b/examples/host/device_info/src/main.c
@@ -0,0 +1,214 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* Host example will get device descriptors of attached devices and print it out via uart/rtt (logger) as follows:
+ * Device 1: ID 046d:c52f
+ Device Descriptor:
+ bLength 18
+ bDescriptorType 1
+ bcdUSB 0200
+ bDeviceClass 0
+ bDeviceSubClass 0
+ bDeviceProtocol 0
+ bMaxPacketSize0 8
+ idVendor 0x046d
+ idProduct 0xc52f
+ bcdDevice 2200
+ iManufacturer 1 Logitech
+ iProduct 2 USB Receiver
+ iSerialNumber 0
+ bNumConfigurations 1
+ *
+ */
+
+#include
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+// English
+#define LANGUAGE_ID 0x0409
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+void led_blinking_task(void);
+static void print_utf16(uint16_t* temp_buf, size_t buf_len);
+
+/*------------- MAIN -------------*/
+int main(void) {
+ board_init();
+
+ printf("TinyUSB Device Info Example\r\n");
+
+ // init host stack on configured roothub port
+ tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUH_RHPORT, &host_init);
+
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
+ while (1) {
+ // tinyusb host task
+ tuh_task();
+ led_blinking_task();
+ }
+
+ return 0;
+}
+
+/*------------- TinyUSB Callbacks -------------*/
+
+// Invoked when device is mounted (configured)
+void tuh_mount_cb(uint8_t daddr) {
+ // Get Device Descriptor
+ tusb_desc_device_t desc_device;
+ uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc_device, 18);
+ if (XFER_RESULT_SUCCESS != xfer_result) {
+ printf("Failed to get device descriptor\r\n");
+ return;
+ }
+
+ uint16_t buf[256];
+
+ printf("Device %u: ID %04x:%04x\r\n", daddr, desc_device.idVendor, desc_device.idProduct);
+ printf("Device Descriptor:\r\n");
+ printf(" bLength %u\r\n", desc_device.bLength);
+ printf(" bDescriptorType %u\r\n", desc_device.bDescriptorType);
+ printf(" bcdUSB %04x\r\n", desc_device.bcdUSB);
+ printf(" bDeviceClass %u\r\n", desc_device.bDeviceClass);
+ printf(" bDeviceSubClass %u\r\n", desc_device.bDeviceSubClass);
+ printf(" bDeviceProtocol %u\r\n", desc_device.bDeviceProtocol);
+ printf(" bMaxPacketSize0 %u\r\n", desc_device.bMaxPacketSize0);
+ printf(" idVendor 0x%04x\r\n", desc_device.idVendor);
+ printf(" idProduct 0x%04x\r\n", desc_device.idProduct);
+ printf(" bcdDevice %04x\r\n", desc_device.bcdDevice);
+
+ // Get String descriptor using Sync API
+
+ printf(" iManufacturer %u ", desc_device.iManufacturer);
+ xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
+ if (XFER_RESULT_SUCCESS == xfer_result) {
+ print_utf16(buf, TU_ARRAY_SIZE(buf));
+ }
+ printf("\r\n");
+
+ printf(" iProduct %u ", desc_device.iProduct);
+ xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
+ if (XFER_RESULT_SUCCESS == xfer_result) {
+ print_utf16(buf, TU_ARRAY_SIZE(buf));
+ }
+ printf("\r\n");
+
+ printf(" iSerialNumber %u ", desc_device.iSerialNumber);
+ xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
+ if (XFER_RESULT_SUCCESS == xfer_result) {
+ print_utf16(buf, TU_ARRAY_SIZE(buf));
+ }
+ printf("\r\n");
+
+ printf(" bNumConfigurations %u\r\n", desc_device.bNumConfigurations);
+}
+
+/// Invoked when device is unmounted (bus reset/unplugged)
+void tuh_umount_cb(uint8_t daddr) {
+ printf("Device removed, address = %d\r\n", daddr);
+}
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void) {
+ const uint32_t interval_ms = 1000;
+ static uint32_t start_ms = 0;
+
+ static bool led_state = false;
+
+ // Blink every interval ms
+ if (board_millis() - start_ms < interval_ms) return; // not enough time
+ start_ms += interval_ms;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state; // toggle
+}
+
+//--------------------------------------------------------------------+
+// String Descriptor Helper
+//--------------------------------------------------------------------+
+
+static void _convert_utf16le_to_utf8(const uint16_t* utf16, size_t utf16_len, uint8_t* utf8, size_t utf8_len) {
+ // TODO: Check for runover.
+ (void) utf8_len;
+ // Get the UTF-16 length out of the data itself.
+
+ for (size_t i = 0; i < utf16_len; i++) {
+ uint16_t chr = utf16[i];
+ if (chr < 0x80) {
+ *utf8++ = chr & 0xffu;
+ } else if (chr < 0x800) {
+ *utf8++ = (uint8_t) (0xC0 | (chr >> 6 & 0x1F));
+ *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F));
+ } else {
+ // TODO: Verify surrogate.
+ *utf8++ = (uint8_t) (0xE0 | (chr >> 12 & 0x0F));
+ *utf8++ = (uint8_t) (0x80 | (chr >> 6 & 0x3F));
+ *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F));
+ }
+ // TODO: Handle UTF-16 code points that take two entries.
+ }
+}
+
+// Count how many bytes a utf-16-le encoded string will take in utf-8.
+static int _count_utf8_bytes(const uint16_t* buf, size_t len) {
+ size_t total_bytes = 0;
+ for (size_t i = 0; i < len; i++) {
+ uint16_t chr = buf[i];
+ if (chr < 0x80) {
+ total_bytes += 1;
+ } else if (chr < 0x800) {
+ total_bytes += 2;
+ } else {
+ total_bytes += 3;
+ }
+ // TODO: Handle UTF-16 code points that take two entries.
+ }
+ return (int) total_bytes;
+}
+
+static void print_utf16(uint16_t* temp_buf, size_t buf_len) {
+ if ((temp_buf[0] & 0xff) == 0) return; // empty
+ size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
+ size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
+ _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t*) temp_buf, sizeof(uint16_t) * buf_len);
+ ((uint8_t*) temp_buf)[utf8_len] = '\0';
+
+ printf("%s", (char*) temp_buf);
+}
diff --git a/examples/host/device_info/src/tusb_config.h b/examples/host/device_info/src/tusb_config.h
new file mode 100644
index 0000000000..2e9731eaf7
--- /dev/null
+++ b/examples/host/device_info/src/tusb_config.h
@@ -0,0 +1,115 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef TUSB_CONFIG_H_
+#define TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED 1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+ // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller
+ // #define CFG_TUH_MAX3421 1 // use max3421 as host controller
+
+ // host roothub port is 1 if using either pio-usb or max3421
+ #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+ #define BOARD_TUH_RHPORT 1
+ #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Driver Configuration
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+// only hub class is enabled
+#define CFG_TUH_HUB 1
+
+// max device support (excluding hub device)
+// 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index bff830ca29..6ffe0b6d40 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -253,6 +253,7 @@ bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2)
void process_sony_ds4(uint8_t const* report, uint16_t len)
{
+ (void)len;
const char* dpad_str[] = { "N", "NE", "E", "SE", "S", "SW", "W", "NW", "none" };
// previous report used to compare for changes
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index 05a5ae1761..ba12774bdc 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -52,7 +52,11 @@ int main(void)
printf("Note: Events only displayed for explicit supported controllers\r\n");
// init host stack on configured roothub port
- tuh_init(BOARD_TUH_RHPORT);
+ tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUH_RHPORT, &host_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index f6b6810f5f..9509035b4a 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -78,7 +78,11 @@ int main(void) {
printf("TinyUSB Host MassStorage Explorer Example\r\n");
// init host stack on configured roothub port
- tuh_init(BOARD_TUH_RHPORT);
+ tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUSB_SPEED_AUTO
+ };
+ tusb_init(BOARD_TUH_RHPORT, &host_init);
if (board_init_after_tusb) {
board_init_after_tusb();
diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
index 489d01aa18..a8214f34e6 100644
--- a/examples/typec/power_delivery/src/main.c
+++ b/examples/typec/power_delivery/src/main.c
@@ -98,7 +98,7 @@ bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t
pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo;
uint32_t const voltage_mv = fixed->voltage_50mv*50;
uint32_t const current_ma = fixed->current_max_10ma*10;
- printf("[Fixed] %lu mV %lu mA\r\n", voltage_mv, current_ma);
+ printf("[Fixed] %"PRIu32" mV %"PRIu32" mA\r\n", voltage_mv, current_ma);
if (voltage_mv <= VOLTAGE_MAX_MV && current_ma >= CURRENT_MAX_MA) {
// Found a suitable PDO
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index f21a323715..a458a3fdcc 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -24,8 +24,8 @@
* This file is part of the TinyUSB stack.
*/
-#ifndef _BOARD_API_H_
-#define _BOARD_API_H_
+#ifndef BOARD_API_H_
+#define BOARD_API_H_
#ifdef __cplusplus
extern "C" {
@@ -39,7 +39,7 @@ extern "C" {
#include "tusb.h"
#if CFG_TUSB_OS == OPT_OS_FREERTOS
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
@@ -72,6 +72,9 @@ void board_init(void);
// Init board after tinyusb is initialized
void board_init_after_tusb(void) TU_ATTR_WEAK;
+// Jump to bootloader
+void board_reset_to_bootloader(void) TU_ATTR_WEAK;
+
// Turn LED on or off
void board_led_write(bool state);
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 013eb1c834..d3a33cf36d 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -170,6 +170,18 @@
#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
// no header needed
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32690
+ #include "max32690.h"
+
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32650
+ #include "max32650.h"
+
+#elif CFG_TUSB_MCU == OPT_MCU_MAX32666
+ #include "max32665.h"
+
+#elif CFG_TUSB_MCU == OPT_MCU_MAX78002
+ #include "max78002.h"
+
#else
#error "Missing MCU header"
#endif
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake
new file mode 100644
index 0000000000..2b8cc19e0d
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake
@@ -0,0 +1,8 @@
+set(CMAKE_SYSTEM_PROCESSOR arm1176jzf-s CACHE INTERNAL "System Processor")
+#set(SUFFIX "")
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ BCM_VERSION=2835
+ )
+endfunction()
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h
similarity index 100%
rename from hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
rename to hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk
similarity index 77%
rename from hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
rename to hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk
index 0520332302..7a248ed24b 100644
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk
@@ -1,4 +1,4 @@
-CPU_CORE = arm1176
+CPU_CORE = arm1176jzf-s
CFLAGS += -DBCM_VERSION=2835 \
-DCFG_TUSB_MCU=OPT_MCU_BCM2835
diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c
index 664b4dcaf0..0062e2e839 100644
--- a/hw/bsp/broadcom_32bit/family.c
+++ b/hw/bsp/broadcom_32bit/family.c
@@ -27,6 +27,13 @@
#include "bsp/board_api.h"
#include "board.h"
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
#include "broadcom/cpu.h"
#include "broadcom/gpio.h"
#include "broadcom/interrupts.h"
@@ -34,6 +41,10 @@
#include "broadcom/caches.h"
#include "broadcom/vcmailbox.h"
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
// LED
#define LED_PIN 18
#define LED_STATE_ON 1
@@ -44,8 +55,7 @@
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
tud_int_handler(0);
}
@@ -56,8 +66,7 @@ void USB_IRQHandler(void)
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
-void board_init(void)
-{
+void board_init(void) {
setup_mmu_flat_map();
init_caches();
@@ -97,24 +106,21 @@ void board_init(void)
BP_EnableIRQs();
}
-void board_led_write(bool state)
-{
- gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+ gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
return 0;
}
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+ (void) buf;
+ (void) len;
return 0;
}
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
for (int i = 0; i < len; i++) {
const char* cbuf = buf;
while (!UART1->STAT_b.TX_READY) {}
@@ -127,30 +133,27 @@ int board_uart_write(void const * buf, int len)
return len;
}
-#if CFG_TUSB_OS == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void TIMER_1_IRQHandler(void)
-{
+void TIMER_1_IRQHandler(void) {
system_ticks++;
SYSTMR->C1 += 977;
SYSTMR->CS_b.M1 = 1;
}
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
+
#endif
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
// asm("bkpt");
}
// Required by __libc_init_array in startup code if we are compiling using
// -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
}
diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake
new file mode 100644
index 0000000000..6205d4e1bf
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/family.cmake
@@ -0,0 +1,108 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/broadcom)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS BCM2835 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${SDK_DIR}/broadcom/link.ld)
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ set(STARTUP_FILE_GNU ${SDK_DIR}/broadcom/boot.s)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/broadcom/gen/interrupt_handlers.c
+ ${SDK_DIR}/broadcom/gpio.c
+ ${SDK_DIR}/broadcom/interrupts.c
+ ${SDK_DIR}/broadcom/mmu.c
+ ${SDK_DIR}/broadcom/caches.c
+ ${SDK_DIR}/broadcom/vcmailbox.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -O0
+ -ffreestanding
+ -mgeneral-regs-only
+ -fno-exceptions
+ -std=c17
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ "LINKER:--entry=_start"
+ --specs=nosys.specs
+ -nostartfiles
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ "LINKER:--entry=_start"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_BCM2835 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk
index cf68e21ee1..e15bd93f70 100644
--- a/hw/bsp/broadcom_32bit/family.mk
+++ b/hw/bsp/broadcom_32bit/family.mk
@@ -1,5 +1,4 @@
MCU_DIR = hw/mcu/broadcom
-DEPS_SUBMODULES += $(MCU_DIR)
include $(TOP)/$(BOARD_PATH)/board.mk
@@ -27,15 +26,13 @@ SRC_C += \
$(MCU_DIR)/broadcom/caches.c \
$(MCU_DIR)/broadcom/vcmailbox.c
-SKIP_NANOLIB = 1
-
LD_FILE = $(MCU_DIR)/broadcom/link$(SUFFIX).ld
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/$(MCU_DIR)
-SRC_S += $(MCU_DIR)/broadcom/boot$(SUFFIX).S
+SRC_S += $(MCU_DIR)/broadcom/boot$(SUFFIX).s
$(BUILD)/kernel$(SUFFIX).img: $(BUILD)/$(PROJECT).elf
$(OBJCOPY) -O binary $^ $@
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake
new file mode 100644
index 0000000000..919068f1d9
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake
@@ -0,0 +1,5 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-a72 CACHE INTERNAL "System Processor")
+set(BCM_VERSION 2711)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake
new file mode 100644
index 0000000000..85f84e9477
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake
@@ -0,0 +1,5 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-a53 CACHE INTERNAL "System Processor")
+set(BCM_VERSION 2837)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h
similarity index 100%
rename from hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
rename to hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.mk
similarity index 100%
rename from hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
rename to hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.mk
diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c
index 664b4dcaf0..0062e2e839 100644
--- a/hw/bsp/broadcom_64bit/family.c
+++ b/hw/bsp/broadcom_64bit/family.c
@@ -27,6 +27,13 @@
#include "bsp/board_api.h"
#include "board.h"
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
#include "broadcom/cpu.h"
#include "broadcom/gpio.h"
#include "broadcom/interrupts.h"
@@ -34,6 +41,10 @@
#include "broadcom/caches.h"
#include "broadcom/vcmailbox.h"
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
// LED
#define LED_PIN 18
#define LED_STATE_ON 1
@@ -44,8 +55,7 @@
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
tud_int_handler(0);
}
@@ -56,8 +66,7 @@ void USB_IRQHandler(void)
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
-void board_init(void)
-{
+void board_init(void) {
setup_mmu_flat_map();
init_caches();
@@ -97,24 +106,21 @@ void board_init(void)
BP_EnableIRQs();
}
-void board_led_write(bool state)
-{
- gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+ gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
return 0;
}
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+ (void) buf;
+ (void) len;
return 0;
}
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
for (int i = 0; i < len; i++) {
const char* cbuf = buf;
while (!UART1->STAT_b.TX_READY) {}
@@ -127,30 +133,27 @@ int board_uart_write(void const * buf, int len)
return len;
}
-#if CFG_TUSB_OS == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void TIMER_1_IRQHandler(void)
-{
+void TIMER_1_IRQHandler(void) {
system_ticks++;
SYSTMR->C1 += 977;
SYSTMR->CS_b.M1 = 1;
}
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
+
#endif
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
// asm("bkpt");
}
// Required by __libc_init_array in startup code if we are compiling using
// -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
}
diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake
new file mode 100644
index 0000000000..f373dc6335
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/family.cmake
@@ -0,0 +1,115 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/broadcom)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/aarch64_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS BCM2711 BCM2835 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${SDK_DIR}/broadcom/link8.ld)
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ set(STARTUP_FILE_GNU ${SDK_DIR}/broadcom/boot8.s)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/broadcom/gen/interrupt_handlers.c
+ ${SDK_DIR}/broadcom/gpio.c
+ ${SDK_DIR}/broadcom/interrupts.c
+ ${SDK_DIR}/broadcom/mmu.c
+ ${SDK_DIR}/broadcom/caches.c
+ ${SDK_DIR}/broadcom/vcmailbox.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -O0
+ -ffreestanding
+ -mgeneral-regs-only
+ -fno-exceptions
+ -std=c17
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ BCM_VERSION=${BCM_VERSION}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}
+ ${CMSIS_5}/CMSIS/Core_A/Include
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+# target_compile_options(${BOARD_TARGET} PUBLIC
+# )
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ "LINKER:--entry=_start"
+ --specs=nosys.specs
+ -nostartfiles
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ "LINKER:--entry=_start"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION} ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk
index 97af6d64a5..89f798f196 100644
--- a/hw/bsp/broadcom_64bit/family.mk
+++ b/hw/bsp/broadcom_64bit/family.mk
@@ -1,6 +1,4 @@
MCU_DIR = hw/mcu/broadcom
-DEPS_SUBMODULES += $(MCU_DIR)
-
include $(TOP)/$(BOARD_PATH)/board.mk
CFLAGS += \
@@ -9,6 +7,7 @@ CFLAGS += \
-ffreestanding \
-nostdlib \
-nostartfiles \
+ --specs=nosys.specs \
-mgeneral-regs-only \
-std=c17
@@ -26,8 +25,6 @@ SRC_C += \
$(MCU_DIR)/broadcom/caches.c \
$(MCU_DIR)/broadcom/vcmailbox.c
-SKIP_NANOLIB = 1
-
LD_FILE = $(MCU_DIR)/broadcom/link8.ld
INC += \
@@ -35,7 +32,7 @@ INC += \
$(TOP)/$(MCU_DIR) \
$(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
-SRC_S += $(MCU_DIR)/broadcom/boot8.S
+SRC_S += $(MCU_DIR)/broadcom/boot8.s
$(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
$(OBJCOPY) -O binary $^ $@
diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake
new file mode 100644
index 0000000000..f6e47ba300
--- /dev/null
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.cmake
@@ -0,0 +1,8 @@
+set(LD_FLASH_SIZE 64K)
+set(LD_RAM_SIZE 20K)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ CFG_EXAMPLE_MSC_DUAL_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h
new file mode 100644
index 0000000000..3b1187c3a7
--- /dev/null
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h
@@ -0,0 +1,20 @@
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_Pin_10
+#define LED_STATE_ON 0
+
+#define BUTTON_PORT GPIOA
+#define BUTTON_PIN GPIO_Pin_1
+#define BUTTON_STATE_ACTIVE 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk
new file mode 100644
index 0000000000..e594f42a75
--- /dev/null
+++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.mk
@@ -0,0 +1,5 @@
+CFLAGS += -DCFG_EXAMPLE_MSC_DUAL_READONLY
+
+LDFLAGS += \
+ -Wl,--defsym=__FLASH_SIZE=64K \
+ -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v10x/ch32v10x_conf.h b/hw/bsp/ch32v10x/ch32v10x_conf.h
new file mode 100644
index 0000000000..939c0fbde4
--- /dev/null
+++ b/hw/bsp/ch32v10x/ch32v10x_conf.h
@@ -0,0 +1,37 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : ch32v10x_conf.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2020/04/30
+ * Description : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V10x_CONF_H
+#define __CH32V10x_CONF_H
+
+#include "ch32v10x_adc.h"
+#include "ch32v10x_bkp.h"
+#include "ch32v10x_crc.h"
+#include "ch32v10x_dbgmcu.h"
+#include "ch32v10x_dma.h"
+#include "ch32v10x_exti.h"
+#include "ch32v10x_flash.h"
+#include "ch32v10x_gpio.h"
+#include "ch32v10x_i2c.h"
+#include "ch32v10x_iwdg.h"
+#include "ch32v10x_pwr.h"
+#include "ch32v10x_rcc.h"
+#include "ch32v10x_rtc.h"
+#include "ch32v10x_spi.h"
+#include "ch32v10x_tim.h"
+#include "ch32v10x_usart.h"
+#include "ch32v10x_wwdg.h"
+#include "ch32v10x_usb.h"
+#include "ch32v10x_usb_host.h"
+#include "ch32v10x_it.h"
+#include "ch32v10x_misc.h"
+
+#endif /* __CH32V10x_CONF_H */
diff --git a/hw/bsp/ch32v10x/ch32v10x_it.h b/hw/bsp/ch32v10x/ch32v10x_it.h
new file mode 100644
index 0000000000..13afc2412a
--- /dev/null
+++ b/hw/bsp/ch32v10x/ch32v10x_it.h
@@ -0,0 +1,15 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : ch32v10x_it.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2022/08/20
+ * Description : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V10x_IT_H
+#define __CH32V10x_IT_H
+
+#endif /* __CH32V10x_IT_H */
diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c
new file mode 100644
index 0000000000..15f754e110
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.c
@@ -0,0 +1,148 @@
+#include
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include "ch32v10x.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+__attribute__((interrupt)) __attribute__((used))
+void USBHD_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_USBFS
+ tud_int_handler(0);
+ #endif
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USBWakeUp_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_USBFS
+ tud_int_handler(0);
+ #endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+__attribute__((interrupt)) __attribute__((used))
+void SysTick_Handler(void) {
+ SysTick->CNTL0 = SysTick->CNTL1 = SysTick->CNTL2 = SysTick->CNTL3 = 0;
+ SysTick->CNTH0 = SysTick->CNTH1 = SysTick->CNTH2 = SysTick->CNTH3 = 0;
+ system_ticks++;
+}
+
+uint32_t SysTick_Config(uint32_t ticks) {
+ NVIC_EnableIRQ(SysTicK_IRQn);
+ SysTick->CTLR = 0;
+ SysTick->CNTL0 = SysTick->CNTL1 = SysTick->CNTL2 = SysTick->CNTL3 = 0;
+ SysTick->CNTH0 = SysTick->CNTH1 = SysTick->CNTH2 = SysTick->CNTH3 = 0;
+
+ SysTick->CMPLR0 = (u8)(ticks & 0xFF);
+ SysTick->CMPLR1 = (u8)(ticks >> 8);
+ SysTick->CMPLR2 = (u8)(ticks >> 16);
+ SysTick->CMPLR3 = (u8)(ticks >> 24);
+
+ SysTick->CMPHR0 = SysTick->CMPHR1 = SysTick->CMPHR2 = SysTick->CMPHR3 = 0;
+ SysTick->CTLR = 1;
+ return 0;
+}
+
+uint32_t board_millis(void) {
+ return system_ticks;
+}
+#endif
+
+void board_init(void) {
+ __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+ SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+ EXTEN->EXTEN_CTR |= EXTEN_USBFS_IO_EN;
+ uint8_t usb_div;
+ switch (SystemCoreClock) {
+ case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
+ case 72000000: usb_div = RCC_USBCLKSource_PLLCLK_1Div5; break;
+ default: TU_ASSERT(0,); break;
+ }
+ RCC_USBCLKConfig(usb_div);
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBFS, ENABLE);
+
+ #ifdef LED_PIN
+ GPIO_InitTypeDef led_init = {
+ .GPIO_Pin = LED_PIN,
+ .GPIO_Mode = GPIO_Mode_Out_OD,
+ .GPIO_Speed = GPIO_Speed_50MHz,
+ };
+ GPIO_Init(LED_PORT, &led_init);
+ #endif
+
+ #ifdef BUTTON_PIN
+ GPIO_InitTypeDef button_init = {
+ .GPIO_Pin = BUTTON_PIN,
+ .GPIO_Mode = GPIO_Mode_IPU,
+ .GPIO_Speed = GPIO_Speed_50MHz,
+ };
+ GPIO_Init(BUTTON_PORT, &button_init);
+ #endif
+
+ // UART TX is PA9
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+ GPIO_InitTypeDef usart_init = {
+ .GPIO_Pin = GPIO_Pin_9,
+ .GPIO_Speed = GPIO_Speed_50MHz,
+ .GPIO_Mode = GPIO_Mode_AF_PP,
+ };
+ GPIO_Init(GPIOA, &usart_init);
+
+ USART_InitTypeDef usart = {
+ .USART_BaudRate = 115200,
+ .USART_WordLength = USART_WordLength_8b,
+ .USART_StopBits = USART_StopBits_1,
+ .USART_Parity = USART_Parity_No,
+ .USART_Mode = USART_Mode_Tx,
+ .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
+ };
+ USART_Init(USART1, &usart);
+ USART_Cmd(USART1, ENABLE);
+
+ __enable_irq();
+
+ board_led_write(true);
+}
+
+void board_led_write(bool state) {
+ GPIO_WriteBit(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+ return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+ const char *bufc = (const char *) buf;
+ for (int i = 0; i < len; i++) {
+ while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+ USART_SendData(USART1, *bufc++);
+ }
+
+ return len;
+}
diff --git a/hw/bsp/ch32v10x/family.cmake b/hw/bsp/ch32v10x/family.cmake
new file mode 100644
index 0000000000..c0af0ef44c
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.cmake
@@ -0,0 +1,117 @@
+include_guard()
+
+#set(UF2_FAMILY_ID 0x699b62ec)
+set(CH32_FAMILY ch32v10x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v103)
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V103 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${CH32_FAMILY}.ld)
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ if (NOT DEFINED STARTUP_FILE_GNU)
+ set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}.S)
+ endif ()
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_SRC_DIR}/Core/core_riscv.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_SRC_DIR}/Core
+ ${SDK_SRC_DIR}/Peripheral/inc
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -mcmodel=medany
+ )
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE}
+ -Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE}
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ message(FATAL_ERROR "Clang is not supported for MSP432E4")
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_CH32V103 ${RTOS})
+
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_add_bin_hex(${TARGET})
+ family_flash_openocd_wch(${TARGET})
+
+ #family_add_uf2(${TARGET} ${UF2_FAMILY_ID})
+ #family_flash_uf2(${TARGET} ${UF2_FAMILY_ID})
+endfunction()
diff --git a/hw/bsp/ch32v10x/family.mk b/hw/bsp/ch32v10x/family.mk
new file mode 100644
index 0000000000..d96d5012ef
--- /dev/null
+++ b/hw/bsp/ch32v10x/family.mk
@@ -0,0 +1,53 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
+
+CH32_FAMILY = ch32v10x
+SDK_DIR = hw/mcu/wch/ch32v103
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32
+
+# Port0 use FSDev, Port1 use USBFS
+PORT ?= 0
+
+CFLAGS += \
+ -mcmodel=medany \
+ -ffat-lto-objects \
+ -flto \
+ -DCFG_TUSB_MCU=OPT_MCU_CH32V103
+
+# https://github.com/openwch/ch32v20x/pull/12
+CFLAGS += -Wno-error=strict-prototypes
+
+LDFLAGS_GCC += \
+ -nostdlib -nostartfiles \
+ --specs=nosys.specs --specs=nano.specs \
+
+LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld
+
+SRC_C += \
+ src/portable/wch/dcd_ch32_usbfs.c \
+ $(SDK_SRC_DIR)/Core/core_riscv.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c \
+
+SRC_S += $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}.S
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(SDK_SRC_DIR)/Core \
+ $(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
+
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
+
+OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
+flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v10x/linker/ch32v10x.ld b/hw/bsp/ch32v10x/linker/ch32v10x.ld
new file mode 100644
index 0000000000..cd5c8dc179
--- /dev/null
+++ b/hw/bsp/ch32v10x/linker/ch32v10x.ld
@@ -0,0 +1,165 @@
+/* Define default values if not already defined */
+__FLASH_SIZE = DEFINED(__flash_size) ? __flash_size : 64K;
+__RAM_SIZE = DEFINED(__ram_size) ? __ram_size : 20K;
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __FLASH_SIZE
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __RAM_SIZE
+}
+
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+SECTIONS
+{
+ .init :
+ {
+ _sinit = .;
+ . = ALIGN(4);
+ KEEP(*(SORT_NONE(.init)))
+ . = ALIGN(4);
+ _einit = .;
+ } >FLASH AT>FLASH
+
+ .vector :
+ {
+ *(.vector);
+ . = ALIGN(64);
+ } >FLASH AT>FLASH
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata*)
+ *(.gnu.linkonce.t.*)
+ . = ALIGN(4);
+ } >FLASH AT>FLASH
+
+ .fini :
+ {
+ KEEP(*(SORT_NONE(.fini)))
+ . = ALIGN(4);
+ } >FLASH AT>FLASH
+
+ PROVIDE( _etext = . );
+ PROVIDE( _eitcm = . );
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH AT>FLASH
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH AT>FLASH
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH AT>FLASH
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >FLASH AT>FLASH
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >FLASH AT>FLASH
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_vma = .);
+ } >RAM AT>FLASH
+
+ .dlalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_lma = .);
+ } >FLASH AT>FLASH
+
+ .data :
+ {
+ *(.gnu.linkonce.r.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ . = ALIGN(4);
+ PROVIDE( _edata = .);
+ } >RAM AT>FLASH
+
+ .bss :
+ {
+ . = ALIGN(4);
+ PROVIDE( _sbss = .);
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON*)
+ . = ALIGN(4);
+ PROVIDE( _ebss = .);
+ } >RAM AT>FLASH
+
+ PROVIDE( _end = _ebss);
+ PROVIDE( end = . );
+
+ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = ALIGN(4);
+ PROVIDE(_susrstack = . );
+ . = . + __stack_size;
+ PROVIDE( _eusrstack = .);
+ } >RAM
+
+}
diff --git a/hw/bsp/ch32v10x/system_ch32v10x.c b/hw/bsp/ch32v10x/system_ch32v10x.c
new file mode 100644
index 0000000000..b083b83b4c
--- /dev/null
+++ b/hw/bsp/ch32v10x/system_ch32v10x.c
@@ -0,0 +1,600 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : system_ch32v10x.c
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2020/04/30
+ * Description : CH32V10x Device Peripheral Access Layer System Source File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v10x.h"
+
+/*
+ * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+ * reset the HSI is used as SYSCLK source).
+ * If none of the define below is enabled, the HSI is used as System clock source.
+ */
+//#define SYSCLK_FREQ_HSE HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE 48000000
+//#define SYSCLK_FREQ_56MHz_HSE 56000000
+#define SYSCLK_FREQ_72MHz_HSE 72000000
+//#define SYSCLK_FREQ_HSI HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI 48000000
+//#define SYSCLK_FREQ_56MHz_HSI 56000000
+//#define SYSCLK_FREQ_72MHz_HSI 72000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* ch32v10x_system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn SystemInit
+ *
+ * @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
+ * the PLL and update the SystemCoreClock variable.
+ *
+ * @return none
+ */
+void SystemInit(void)
+{
+ RCC->CTLR |= (uint32_t)0x00000001;
+ RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+ RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+ RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+ RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+ RCC->INTR = 0x009F0000;
+ SetSysClock();
+}
+
+/*********************************************************************
+ * @fn SystemCoreClockUpdate
+ *
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return none
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+ tmp = RCC->CFGR0 & RCC_SWS;
+
+ switch(tmp)
+ {
+ case 0x00:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04:
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08:
+ pllmull = RCC->CFGR0 & RCC_PLLMULL;
+ pllsource = RCC->CFGR0 & RCC_PLLSRC;
+ pllmull = (pllmull >> 18) + 2;
+ if(pllsource == 0x00)
+ {
+ if( EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE )
+ {
+ SystemCoreClock = ( HSI_VALUE ) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull;
+ }
+ }
+ else
+ {
+ if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+ {
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ }
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+ SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn SetSysClock
+ *
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClock(void)
+{
+ //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+ SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+ SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+ SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+ SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+ SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+ SetSysClockTo72_HSI();
+
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ * source (default after reset)
+ */
+}
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn SetSysClockToHSE
+ *
+ * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if(HSEStatus == (uint32_t)0x01)
+ {
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+ /* Flash 0 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+ /* Select HSE as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo48_HSE
+ *
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if(HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo56_HSE
+ *
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if(HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo72_HSE
+ *
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if(HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo48_HSI
+ *
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo56_HSI
+ *
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo72_HSI
+ *
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+#endif
diff --git a/hw/bsp/ch32v10x/system_ch32v10x.h b/hw/bsp/ch32v10x/system_ch32v10x.h
new file mode 100644
index 0000000000..d156245209
--- /dev/null
+++ b/hw/bsp/ch32v10x/system_ch32v10x.h
@@ -0,0 +1,29 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : system_ch32v10x.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2020/04/30
+ * Description : CH32V10x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V10x_H
+#define __SYSTEM_CH32V10x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_SYSTEM_H */
diff --git a/hw/bsp/ch32v10x/wch-riscv.cfg b/hw/bsp/ch32v10x/wch-riscv.cfg
new file mode 100644
index 0000000000..aa35aa9c56
--- /dev/null
+++ b/hw/bsp/ch32v10x/wch-riscv.cfg
@@ -0,0 +1,17 @@
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake
new file mode 100644
index 0000000000..4aae6bdc2f
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT D6)
+
+# 64KB zero-wait, 224KB total flash
+#set(LD_FLASH_SIZE 64K)
+set(LD_FLASH_SIZE 224K)
+set(LD_RAM_SIZE 20K)
+
+# set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${CH32_FAMILY}_tinyuf2.ld)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ SYSCLK_FREQ_144MHz_HSE=144000000
+ CFG_EXAMPLE_MSC_DUAL_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
new file mode 100644
index 0000000000..692cf11bf1
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h
@@ -0,0 +1,21 @@
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_Pin_0
+#define LED_STATE_ON 0
+
+#define UART_DEV USART1
+#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+#define UART_TX_PIN GPIO_Pin_9
+#define UART_RX_PIN GPIO_Pin_10
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk
new file mode 100644
index 0000000000..bdd15f737d
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = D6
+
+CFLAGS += \
+ -DSYSCLK_FREQ_144MHz_HSE=144000000 \
+ -DCH32_FLASH_ENHANCE_READ_MODE=1 \
+ -DCFG_EXAMPLE_MSC_DUAL_READONLY \
+
+# 64KB zero-wait, 224KB total flash
+LDFLAGS += \
+ -Wl,--defsym=__FLASH_SIZE=224K \
+ -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake
new file mode 100644
index 0000000000..ecb8b378fb
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT D6)
+
+# 32KB zero-wait, 224KB total flash
+#set(LD_FLASH_SIZE 32K)
+set(LD_FLASH_SIZE 224K)
+set(LD_RAM_SIZE 10K)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ SYSCLK_FREQ_144MHz_HSI=144000000
+ CFG_EXAMPLE_MSC_DUAL_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
new file mode 100644
index 0000000000..783831edd6
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h
@@ -0,0 +1,21 @@
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_Pin_0
+#define LED_STATE_ON 0
+
+#define UART_DEV USART2
+#define UART_CLOCK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE)
+#define UART_TX_PIN GPIO_Pin_2
+#define UART_RX_PIN GPIO_Pin_3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk
new file mode 100644
index 0000000000..f71f53478e
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = D6
+
+CFLAGS += \
+ -DSYSCLK_FREQ_144MHz_HSI=144000000 \
+ -DCH32_FLASH_ENHANCE_READ_MODE=1 \
+ -DCFG_EXAMPLE_MSC_DUAL_READONLY \
+
+# 32KB zero-wait, 224KB total flash
+LDFLAGS += \
+ -Wl,--defsym=__FLASH_SIZE=224K \
+ -Wl,--defsym=__RAM_SIZE=10K \
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
new file mode 100644
index 0000000000..6c7712cdd5
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT D6)
+
+# 64KB zero-wait, 224KB total flash
+set(LD_FLASH_SIZE 64K)
+#set(LD_FLASH_SIZE 224K)
+set(LD_RAM_SIZE 20K)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ SYSCLK_FREQ_144MHz_HSE=144000000
+ CFG_EXAMPLE_MSC_DUAL_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
new file mode 100644
index 0000000000..64eaf931eb
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h
@@ -0,0 +1,21 @@
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_Pin_15
+#define LED_STATE_ON 0
+
+#define UART_DEV USART1
+#define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+#define UART_TX_PIN GPIO_Pin_9
+#define UART_RX_PIN GPIO_Pin_10
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk b/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
new file mode 100644
index 0000000000..362aace477
--- /dev/null
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = D6
+
+CFLAGS += \
+ -DSYSCLK_FREQ_144MHz_HSE=144000000 \
+ -DCH32_FLASH_ENHANCE_READ_MODE=1 \
+ -DCFG_EXAMPLE_MSC_DUAL_READONLY \
+
+# 64KB zero-wait , 224KB total flash
+LDFLAGS += \
+ -Wl,--defsym=__FLASH_SIZE=224K \
+ -Wl,--defsym=__RAM_SIZE=20K \
diff --git a/hw/bsp/ch32v20x/ch32v20x_conf.h b/hw/bsp/ch32v20x/ch32v20x_conf.h
new file mode 100644
index 0000000000..949297fe63
--- /dev/null
+++ b/hw/bsp/ch32v20x/ch32v20x_conf.h
@@ -0,0 +1,36 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : ch32v20x_conf.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/06/06
+ * Description : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+#endif /* __CH32V20x_CONF_H */
diff --git a/hw/bsp/ch32v20x/ch32v20x_it.h b/hw/bsp/ch32v20x/ch32v20x_it.h
new file mode 100644
index 0000000000..e49c61ae25
--- /dev/null
+++ b/hw/bsp/ch32v20x/ch32v20x_it.h
@@ -0,0 +1,15 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : ch32v20x_it.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/06/06
+ * Description : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#endif /* __CH32V20x_IT_H */
diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c
new file mode 100644
index 0000000000..43dd7e0322
--- /dev/null
+++ b/hw/bsp/ch32v20x/family.c
@@ -0,0 +1,209 @@
+#include
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include "ch32v20x.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+/* CH32v203 depending on variants can support 2 USB IPs: FSDEV and USBFS.
+ * By default, we use FSDEV, but you can explicitly select by define:
+ * - CFG_TUD_WCH_USBIP_FSDEV
+ * - CFG_TUD_WCH_USBIP_USBFS
+ */
+
+// USBFS
+__attribute__((interrupt)) __attribute__((used))
+void USBHD_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_USBFS
+ tud_int_handler(0);
+ #endif
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USBHDWakeUp_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_USBFS
+ tud_int_handler(0);
+ #endif
+}
+
+// USBD (fsdev)
+__attribute__((interrupt)) __attribute__((used))
+void USB_LP_CAN1_RX0_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_FSDEV
+ tud_int_handler(0);
+ #endif
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USB_HP_CAN1_TX_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_FSDEV
+ tud_int_handler(0);
+ #endif
+
+}
+
+__attribute__((interrupt)) __attribute__((used))
+void USBWakeUp_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_FSDEV
+ tud_int_handler(0);
+ #endif
+}
+
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+__attribute__((interrupt))
+void SysTick_Handler(void) {
+ SysTick->SR = 0;
+ system_ticks++;
+}
+
+uint32_t SysTick_Config(uint32_t ticks) {
+ NVIC_EnableIRQ(SysTicK_IRQn);
+ SysTick->CTLR = 0;
+ SysTick->SR = 0;
+ SysTick->CNT = 0;
+ SysTick->CMP = ticks - 1;
+ SysTick->CTLR = 0xF;
+ return 0;
+}
+
+uint32_t board_millis(void) {
+ return system_ticks;
+}
+#endif
+
+void board_init(void) {
+ __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+ SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+ GPIO_InitTypeDef GPIO_InitStructure = {
+ .GPIO_Pin = LED_PIN,
+ .GPIO_Mode = GPIO_Mode_Out_OD,
+ .GPIO_Speed = GPIO_Speed_10MHz,
+ };
+ GPIO_Init(LED_PORT, &GPIO_InitStructure);
+
+#ifdef UART_DEV
+ UART_CLOCK_EN();
+ GPIO_InitTypeDef usart_init = {
+ .GPIO_Pin = UART_TX_PIN,
+ .GPIO_Speed = GPIO_Speed_50MHz,
+ .GPIO_Mode = GPIO_Mode_AF_PP,
+ };
+ GPIO_Init(GPIOA, &usart_init);
+
+ USART_InitTypeDef usart = {
+ .USART_BaudRate = 115200,
+ .USART_WordLength = USART_WordLength_8b,
+ .USART_StopBits = USART_StopBits_1,
+ .USART_Parity = USART_Parity_No,
+ .USART_Mode = USART_Mode_Tx,
+ .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
+ };
+ USART_Init(UART_DEV, &usart);
+ USART_Cmd(UART_DEV, ENABLE);
+#endif
+
+ // USB init
+ uint8_t usb_div;
+ switch (SystemCoreClock) {
+ case 48000000: usb_div = RCC_USBCLKSource_PLLCLK_Div1; break;
+ case 96000000: usb_div = RCC_USBCLKSource_PLLCLK_Div2; break;
+ case 144000000: usb_div = RCC_USBCLKSource_PLLCLK_Div3; break;
+ default: TU_ASSERT(0,); break;
+ }
+ RCC_USBCLKConfig(usb_div);
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); // FSDEV
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); // USB FS
+
+ __enable_irq();
+}
+
+void board_reset_to_bootloader(void) {
+// board_led_write(true);
+//
+// __disable_irq();
+//
+// #if CFG_TUD_ENABLED
+// tud_deinit(0);
+// RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, ENABLE);
+// RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, DISABLE);
+// #endif
+//
+// SysTick->CTLR = 0;
+// for (int i = WWDG_IRQn; i< DMA1_Channel8_IRQn; i++) {
+// NVIC_DisableIRQ(i);
+// }
+//
+// __enable_irq();
+//
+// // define function pointer to BOOT ROM address
+// void (*bootloader_entry)(void) = (void (*)(void))0x1FFF8000;
+//
+// bootloader_entry();
+//
+// board_led_write(false);
+
+ // while(1) { }
+}
+
+void board_led_write(bool state) {
+ GPIO_WriteBit(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+ return false;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ (void) max_len;
+ volatile uint32_t* ch32_uuid = ((volatile uint32_t*) 0x1FFFF7E8UL);
+ uint32_t* serial_32 = (uint32_t*) (uintptr_t) id;
+ serial_32[0] = ch32_uuid[0];
+ serial_32[1] = ch32_uuid[1];
+ serial_32[2] = ch32_uuid[2];
+
+ return 12;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
+ const char *bufc = (const char *) buf;
+ for (int i = 0; i < len; i++) {
+ while (USART_GetFlagStatus(UART_DEV, USART_FLAG_TC) == RESET);
+ USART_SendData(UART_DEV, *bufc++);
+ }
+#else
+ (void) buf; (void) len;
+#endif
+
+ return len;
+}
+
+//--------------------------------------------------------------------
+// Neopixel
+//--------------------------------------------------------------------
diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake
new file mode 100644
index 0000000000..380ef190d5
--- /dev/null
+++ b/hw/bsp/ch32v20x/family.cmake
@@ -0,0 +1,144 @@
+include_guard()
+
+set(UF2_FAMILY_ID 0x699b62ec)
+set(CH32_FAMILY ch32v20x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/${CH32_FAMILY})
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V20X CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+# Port0 use FSDev, Port1 use USBFS
+if (NOT DEFINED PORT)
+ set(PORT 0)
+endif()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${CH32_FAMILY}.ld)
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ if (NOT DEFINED STARTUP_FILE_GNU)
+ set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S)
+ endif ()
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_SRC_DIR}/Core/core_riscv.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_flash.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_SRC_DIR}/Core
+ ${SDK_SRC_DIR}/Peripheral/inc
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CH32V20x_${MCU_VARIANT}
+ )
+
+ if (PORT EQUAL 0)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CFG_TUD_WCH_USBIP_FSDEV=1
+ )
+ elseif (PORT EQUAL 1)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CFG_TUD_WCH_USBIP_USBFS=1
+ )
+ else()
+ message(FATAL_ERROR "Invalid PORT ${PORT}")
+ endif()
+
+ update_board(${BOARD_TARGET})
+
+ if (LD_FLASH_SIZE STREQUAL 224K)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CH32_FLASH_ENHANCE_READ_MODE=1
+ )
+ endif()
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -mcmodel=medany
+ )
+ target_link_options(${BOARD_TARGET} PUBLIC
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ -Wl,--defsym=__FLASH_SIZE=${LD_FLASH_SIZE}
+ -Wl,--defsym=__RAM_SIZE=${LD_RAM_SIZE}
+ "LINKER:--script=${LD_FILE_GNU}"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ message(FATAL_ERROR "Clang is not supported for CH32v")
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X ${RTOS})
+
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+ ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_add_bin_hex(${TARGET})
+ family_flash_openocd_wch(${TARGET})
+ family_flash_wlink_rs(${TARGET})
+
+ #family_add_uf2(${TARGET} ${UF2_FAMILY_ID})
+ #family_flash_uf2(${TARGET} ${UF2_FAMILY_ID})
+endfunction()
diff --git a/hw/bsp/ch32v20x/family.mk b/hw/bsp/ch32v20x/family.mk
new file mode 100644
index 0000000000..08761dc0d2
--- /dev/null
+++ b/hw/bsp/ch32v20x/family.mk
@@ -0,0 +1,64 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
+
+CH32_FAMILY = ch32v20x
+SDK_DIR = hw/mcu/wch/ch32v20x
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32
+
+# Port0 use FSDev, Port1 use USBFS
+PORT ?= 0
+
+CFLAGS += \
+ -mcmodel=medany \
+ -ffat-lto-objects \
+ -flto \
+ -DCH32V20x_${MCU_VARIANT} \
+ -DCFG_TUSB_MCU=OPT_MCU_CH32V20X
+
+# https://github.com/openwch/ch32v20x/pull/12
+CFLAGS += -Wno-error=strict-prototypes
+
+ifeq ($(PORT),0)
+ $(info "Using FSDEV driver")
+ CFLAGS += -DCFG_TUD_WCH_USBIP_FSDEV=1
+else
+ $(info "Using USBFS driver")
+ CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1
+endif
+
+LDFLAGS_GCC += \
+ -nostdlib -nostartfiles \
+ --specs=nosys.specs --specs=nano.specs \
+
+LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld
+
+SRC_C += \
+ src/portable/wch/dcd_ch32_usbfs.c \
+ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+ $(SDK_SRC_DIR)/Core/core_riscv.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c \
+
+SRC_S += $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(SDK_SRC_DIR)/Core \
+ $(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
+
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
+
+OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
+flash: flash-wlink-rs
+#flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v20x/linker/ch32v20x.ld b/hw/bsp/ch32v20x/linker/ch32v20x.ld
new file mode 100644
index 0000000000..f84808b0d3
--- /dev/null
+++ b/hw/bsp/ch32v20x/linker/ch32v20x.ld
@@ -0,0 +1,164 @@
+/* Define default values if not already defined */
+__flash_size = DEFINED(__FLASH_SIZE) ? __FLASH_SIZE : 64K;
+__ram_size = DEFINED(__RAM_SIZE) ? __RAM_SIZE : 20K;
+__stack_size = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2048;
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __flash_size
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __ram_size
+}
+
+ENTRY( _start )
+
+PROVIDE( _stack_size = __stack_size );
+
+SECTIONS
+{
+ .init :
+ {
+ _sinit = .;
+ . = ALIGN(4);
+ KEEP(*(SORT_NONE(.init)))
+ . = ALIGN(4);
+ _einit = .;
+ } >FLASH AT>FLASH
+
+ .vector :
+ {
+ *(.vector);
+ . = ALIGN(64);
+ } >FLASH AT>FLASH
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata*)
+ *(.gnu.linkonce.t.*)
+ . = ALIGN(4);
+ } >FLASH AT>FLASH
+
+ .fini :
+ {
+ KEEP(*(SORT_NONE(.fini)))
+ . = ALIGN(4);
+ } >FLASH AT>FLASH
+
+ PROVIDE( _etext = . );
+ PROVIDE( _eitcm = . );
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH AT>FLASH
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH AT>FLASH
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH AT>FLASH
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >FLASH AT>FLASH
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >FLASH AT>FLASH
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_vma = .);
+ } >RAM AT>FLASH
+
+ .dlalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_lma = .);
+ } >FLASH AT>FLASH
+
+ .data :
+ {
+ *(.gnu.linkonce.r.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ . = ALIGN(4);
+ PROVIDE( _edata = .);
+ } >RAM AT>FLASH
+
+ .bss :
+ {
+ . = ALIGN(4);
+ PROVIDE( _sbss = .);
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON*)
+ . = ALIGN(4);
+ PROVIDE( _ebss = .);
+ } >RAM AT>FLASH
+
+ PROVIDE( _end = _ebss);
+ PROVIDE( end = . );
+
+ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = ALIGN(4);
+ PROVIDE(_susrstack = . );
+ . = . + __stack_size;
+ PROVIDE( _eusrstack = .);
+ } >RAM
+
+}
diff --git a/hw/bsp/ch32v20x/system_ch32v20x.c b/hw/bsp/ch32v20x/system_ch32v20x.c
new file mode 100644
index 0000000000..d32ee8d172
--- /dev/null
+++ b/hw/bsp/ch32v20x/system_ch32v20x.c
@@ -0,0 +1,986 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : system_ch32v20x.c
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/06/06
+ * Description : CH32V20x Device Peripheral Access Layer System Source File.
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 8Mhz (other CH32V203x)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+//#define SYSCLK_FREQ_HSE HSE_VALUE
+// #define SYSCLK_FREQ_48MHz_HSE 48000000
+//#define SYSCLK_FREQ_56MHz_HSE 56000000
+// #define SYSCLK_FREQ_72MHz_HSE 72000000
+// #define SYSCLK_FREQ_96MHz_HSE 96000000
+//#define SYSCLK_FREQ_120MHz_HSE 120000000
+//#define SYSCLK_FREQ_144MHz_HSE 144000000
+//#define SYSCLK_FREQ_HSI HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI 48000000
+//#define SYSCLK_FREQ_56MHz_HSI 56000000
+//#define SYSCLK_FREQ_72MHz_HSI 72000000
+//#define SYSCLK_FREQ_96MHz_HSI 96000000
+//#define SYSCLK_FREQ_120MHz_HSI 120000000
+//#define SYSCLK_FREQ_144MHz_HSI 144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn SystemInit
+ *
+ * @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
+ * the PLL and update the SystemCoreClock variable.
+ *
+ * @return none
+ */
+void SystemInit (void)
+{
+ // Enable Flash enhance read mode for full 224KB
+#if defined(CH32_FLASH_ENHANCE_READ_MODE) && CH32_FLASH_ENHANCE_READ_MODE == 1
+ FLASH->KEYR = 0x45670123; // FLASH_Unlock_Fast();
+ FLASH->KEYR = 0xCDEF89AB;
+
+ FLASH->CTLR |= (1 << 24); // Enhanced Read Mode
+
+ FLASH->CTLR |= (1 << 15); // FLASH_Lock_Fast();
+#endif
+
+ RCC->CTLR |= (uint32_t)0x00000001;
+ RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+ RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+ RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+ RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+ RCC->INTR = 0x009F0000;
+ SetSysClock();
+}
+
+/*********************************************************************
+ * @fn SystemCoreClockUpdate
+ *
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return none
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+ tmp = RCC->CFGR0 & RCC_SWS;
+
+ switch (tmp)
+ {
+ case 0x00:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04:
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08:
+ pllmull = RCC->CFGR0 & RCC_PLLMULL;
+ pllsource = RCC->CFGR0 & RCC_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if(pllmull == 17) pllmull = 18;
+
+ if (pllsource == 0x00)
+ {
+ if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+ SystemCoreClock = HSI_VALUE * pllmull;
+ }
+ else{
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ }
+ else
+ {
+#if defined (CH32V20x_D8W)
+ if((RCC->CFGR0 & (3<<22)) == (3<<22))
+ {
+ SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+ }
+ else
+#endif
+ if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+ {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+ SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+ }
+ else
+ {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+ SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+ SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+ }
+ }
+
+ if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+ SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn SetSysClock
+ *
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+ SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+ SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+ SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+ SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+ SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+ SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+ SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+ SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+ SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+ SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+ SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+ SetSysClockTo144_HSI();
+
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ * source (default after reset)
+ */
+}
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn SetSysClockToHSE
+ *
+ * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+ /* Select HSE as system clock source
+ * CH32V20x_D6 (HSE=8MHZ)
+ * CH32V20x_D8 (HSE=32MHZ)
+ * CH32V20x_D8W (HSE=32MHZ)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo48_HSE
+ *
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+ * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+ * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo56_HSE
+ *
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+ * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+ * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo72_HSE
+ *
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+ * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+ * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo96_HSE
+ *
+ * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+ * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+ * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo120_HSE
+ *
+ * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if(HSEStatus == (uint32_t)0x01)
+ {
+#if defined (CH32V20x_D8W)
+ RCC->CFGR0 |= (uint32_t)(3<<22);
+ /* HCLK = SYSCLK/2 */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+ * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+ * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo144_HSE
+ *
+ * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+ * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+ * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo48_HSI
+ *
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo56_HSI
+ *
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo72_HSI
+ *
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo96_HSI
+ *
+ * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo120_HSI
+ *
+ * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo144_HSI
+ *
+ * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+#endif
diff --git a/hw/bsp/ch32v20x/system_ch32v20x.h b/hw/bsp/ch32v20x/system_ch32v20x.h
new file mode 100644
index 0000000000..eec7ccb156
--- /dev/null
+++ b/hw/bsp/ch32v20x/system_ch32v20x.h
@@ -0,0 +1,29 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : system_ch32v20x.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/06/06
+ * Description : CH32V20x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
diff --git a/hw/bsp/ch32v20x/wch-riscv.cfg b/hw/bsp/ch32v20x/wch-riscv.cfg
new file mode 100644
index 0000000000..aa35aa9c56
--- /dev/null
+++ b/hw/bsp/ch32v20x/wch-riscv.cfg
@@ -0,0 +1,17 @@
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake
new file mode 100644
index 0000000000..9f56820422
--- /dev/null
+++ b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake
@@ -0,0 +1,4 @@
+function(update_board TARGET)
+# target_compile_definitions(${TARGET} PUBLIC
+# )
+endfunction()
diff --git a/hw/bsp/ch32v307/core_riscv.h b/hw/bsp/ch32v307/core_riscv.h
deleted file mode 100644
index a7ce10a001..0000000000
--- a/hw/bsp/ch32v307/core_riscv.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name : core_riscv.h
-* Author : WCH
-* Version : V1.0.0
-* Date : 2021/06/06
-* Description : RISC-V Core Peripheral Access Layer Header File for CH32V30x
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* SPDX-License-Identifier: Apache-2.0
-*******************************************************************************/
-#ifndef __CORE_RISCV_H__
-#define __CORE_RISCV_H__
-
-/* IO definitions */
-#ifdef __cplusplus
- #define __I volatile /* defines 'read only' permissions */
-#else
- #define __I volatile const /* defines 'read only' permissions */
-#endif
-#define __O volatile /* defines 'write only' permissions */
-#define __IO volatile /* defines 'read / write' permissions */
-
-/* Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef __I uint64_t vuc64; /* Read Only */
-typedef __I uint32_t vuc32; /* Read Only */
-typedef __I uint16_t vuc16; /* Read Only */
-typedef __I uint8_t vuc8; /* Read Only */
-
-typedef const uint64_t uc64; /* Read Only */
-typedef const uint32_t uc32; /* Read Only */
-typedef const uint16_t uc16; /* Read Only */
-typedef const uint8_t uc8; /* Read Only */
-
-typedef __I int64_t vsc64; /* Read Only */
-typedef __I int32_t vsc32; /* Read Only */
-typedef __I int16_t vsc16; /* Read Only */
-typedef __I int8_t vsc8; /* Read Only */
-
-typedef const int64_t sc64; /* Read Only */
-typedef const int32_t sc32; /* Read Only */
-typedef const int16_t sc16; /* Read Only */
-typedef const int8_t sc8; /* Read Only */
-
-typedef __IO uint64_t vu64;
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef uint64_t u64;
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef __IO int64_t vs64;
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef int64_t s64;
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-#define RV_STATIC_INLINE static inline
-
-/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
-typedef struct{
- __I uint32_t ISR[8];
- __I uint32_t IPR[8];
- __IO uint32_t ITHRESDR;
- __IO uint32_t RESERVED;
- __IO uint32_t CFGR;
- __I uint32_t GISR;
- uint8_t VTFIDR[4];
- uint8_t RESERVED0[12];
- __IO uint32_t VTFADDR[4];
- uint8_t RESERVED1[0x90];
- __O uint32_t IENR[8];
- uint8_t RESERVED2[0x60];
- __O uint32_t IRER[8];
- uint8_t RESERVED3[0x60];
- __O uint32_t IPSR[8];
- uint8_t RESERVED4[0x60];
- __O uint32_t IPRR[8];
- uint8_t RESERVED5[0x60];
- __IO uint32_t IACTR[8];
- uint8_t RESERVED6[0xE0];
- __IO uint8_t IPRIOR[256];
- uint8_t RESERVED7[0x810];
- __IO uint32_t SCTLR;
-}PFIC_Type;
-
-/* memory mapped structure for SysTick */
-typedef struct
-{
- __IO u32 CTLR;
- __IO u32 SR;
- __IO u64 CNT;
- __IO u64 CMP;
-}SysTick_Type;
-
-
-#define PFIC ((PFIC_Type *) 0xE000E000 )
-#define NVIC PFIC
-#define NVIC_KEY1 ((uint32_t)0xFA050000)
-#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
-#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
-
-#define SysTick ((SysTick_Type *) 0xE000F000)
-
-
-/*********************************************************************
- * @fn __enable_irq
- *
- * @brief Enable Global Interrupt
- *
- * @return none
- */
-RV_STATIC_INLINE void __enable_irq(void)
-{
- __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
-}
-
-/*********************************************************************
- * @fn __disable_irq
- *
- * @brief Disable Global Interrupt
- *
- * @return none
- */
-RV_STATIC_INLINE void __disable_irq(void)
-{
- __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
-}
-
-/*********************************************************************
- * @fn __NOP
- *
- * @brief nop
- *
- * @return none
- */
-RV_STATIC_INLINE void __NOP(void)
-{
- __asm volatile ("nop");
-}
-
-/*********************************************************************
- * @fn NVIC_EnableIRQ
- *
- * @brief Enable Interrupt
- *
- * @param IRQn: Interrupt Numbers
- *
- * @return none
- */
-RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn NVIC_DisableIRQ
- *
- * @brief Disable Interrupt
- *
- * @param IRQn: Interrupt Numbers
- *
- * @return none
- */
-RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn NVIC_GetStatusIRQ
- *
- * @brief Get Interrupt Enable State
- *
- * @param IRQn: Interrupt Numbers
- *
- * @return 1 - Interrupt Enable
- * 0 - Interrupt Disable
- */
-RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn NVIC_GetPendingIRQ
- *
- * @brief Get Interrupt Pending State
- *
- * @param IRQn: Interrupt Numbers
- *
- * @return 1 - Interrupt Pending Enable
- * 0 - Interrupt Pending Disable
- */
-RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn NVIC_SetPendingIRQ
- *
- * @brief Set Interrupt Pending
- *
- * @param IRQn: Interrupt Numbers
- *
- * @return None
- */
-RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn NVIC_ClearPendingIRQ
- *
- * @brief Clear Interrupt Pending
- *
- * @param IRQn: Interrupt Numbers
- *
- * @return None
- */
-RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn NVIC_GetActive
- *
- * @brief Get Interrupt Active State
- *
- * @param IRQn: Interrupt Numbers
- *
- * @return 1 - Interrupt Active
- * 0 - Interrupt No Active
- */
-RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn NVIC_SetPriority
- *
- * @brief Set Interrupt Priority
- *
- * @param IRQn - Interrupt Numbers
- * priority -
- * bit7 - pre-emption priority
- * bit6~bit4 - subpriority
- * @return None
- */
-RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
-{
- NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
-}
-
-/*********************************************************************
- * @fn __WFI
- *
- * @brief Wait for Interrupt
- *
- * @return None
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
-{
- NVIC->SCTLR &= ~(1<<3); // wfi
- asm volatile ("wfi");
-}
-
-/*********************************************************************
- * @fn __WFE
- *
- * @brief Wait for Events
- *
- * @return None
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
-{
- uint32_t t;
-
- t = NVIC->SCTLR;
- NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
- NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
- asm volatile ("wfi");
- asm volatile ("wfi");
-}
-
-/*********************************************************************
- * @fn SetVTFIRQ
- *
- * @brief Set VTF Interrupt
- *
- * @param add - VTF interrupt service function base address.
- * IRQn -Interrupt Numbers
- * num - VTF Interrupt Numbers
- * NewState - DISABLE or ENABLE
- * @return None
- */
-RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
- if(num > 3) return ;
-
- if (NewState != DISABLE)
- {
- NVIC->VTFIDR[num] = IRQn;
- NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
- }
- else{
- NVIC->VTFIDR[num] = IRQn;
- NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
- }
-}
-
-/*********************************************************************
- * @fn NVIC_SystemReset
- *
- * @brief Initiate a system reset request
- *
- * @return None
- */
-RV_STATIC_INLINE void NVIC_SystemReset(void)
-{
- NVIC->CFGR = NVIC_KEY3|(1<<7);
-}
-
-
-/* Core_Exported_Functions */
-extern uint32_t __get_FFLAGS(void);
-extern void __set_FFLAGS(uint32_t value);
-extern uint32_t __get_FRM(void);
-extern void __set_FRM(uint32_t value);
-extern uint32_t __get_FCSR(void);
-extern void __set_FCSR(uint32_t value);
-extern uint32_t __get_MSTATUS(void);
-extern void __set_MSTATUS(uint32_t value);
-extern uint32_t __get_MISA(void);
-extern void __set_MISA(uint32_t value);
-extern uint32_t __get_MIE(void);
-extern void __set_MIE(uint32_t value);
-extern uint32_t __get_MTVEC(void);
-extern void __set_MTVEC(uint32_t value);
-extern uint32_t __get_MSCRATCH(void);
-extern void __set_MSCRATCH(uint32_t value);
-extern uint32_t __get_MEPC(void);
-extern void __set_MEPC(uint32_t value);
-extern uint32_t __get_MCAUSE(void);
-extern void __set_MCAUSE(uint32_t value);
-extern uint32_t __get_MTVAL(void);
-extern void __set_MTVAL(uint32_t value);
-extern uint32_t __get_MIP(void);
-extern void __set_MIP(uint32_t value);
-extern uint32_t __get_MCYCLE(void);
-extern void __set_MCYCLE(uint32_t value);
-extern uint32_t __get_MCYCLEH(void);
-extern void __set_MCYCLEH(uint32_t value);
-extern uint32_t __get_MINSTRET(void);
-extern void __set_MINSTRET(uint32_t value);
-extern uint32_t __get_MINSTRETH(void);
-extern void __set_MINSTRETH(uint32_t value);
-extern uint32_t __get_MVENDORID(void);
-extern uint32_t __get_MARCHID(void);
-extern uint32_t __get_MIMPID(void);
-extern uint32_t __get_MHARTID(void);
-extern uint32_t __get_SP(void);
-
-
-#endif
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.c b/hw/bsp/ch32v307/debug_uart.c
similarity index 94%
rename from hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.c
rename to hw/bsp/ch32v307/debug_uart.c
index db3551ca78..2fd3a9d64d 100644
--- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.c
+++ b/hw/bsp/ch32v307/debug_uart.c
@@ -25,10 +25,19 @@
*/
#include "debug_uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
#include
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
-#define UART_RINGBUFFER_SIZE_TX 64
+#define UART_RINGBUFFER_SIZE_TX 128
#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
static char tx_buf[UART_RINGBUFFER_SIZE_TX];
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.h b/hw/bsp/ch32v307/debug_uart.h
similarity index 100%
rename from hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.h
rename to hw/bsp/ch32v307/debug_uart.h
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
index 245fa5674d..adf2dbea5d 100644
--- a/hw/bsp/ch32v307/family.c
+++ b/hw/bsp/ch32v307/family.c
@@ -25,9 +25,22 @@
*/
#include "stdio.h"
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
#include "debug_uart.h"
#include "ch32v30x.h"
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
#include "bsp/board_api.h"
#include "board.h"
@@ -35,29 +48,31 @@
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USBHS_IRQHandler (void) __attribute__((naked));
-void USBHS_IRQHandler (void)
-{
- __asm volatile ("call USBHS_IRQHandler_impl; mret");
+// TODO maybe having FS as port0, HS as port1
+
+__attribute__((interrupt)) void USBHS_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_USBHS
+ tud_int_handler(0);
+ #endif
}
-__attribute__ ((used)) void USBHS_IRQHandler_impl (void)
-{
+__attribute__((interrupt)) void OTG_FS_IRQHandler(void) {
+ #if CFG_TUD_WCH_USBIP_USBFS
tud_int_handler(0);
+ #endif
}
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
-uint32_t SysTick_Config(uint32_t ticks)
-{
+uint32_t SysTick_Config(uint32_t ticks) {
NVIC_EnableIRQ(SysTicK_IRQn);
- SysTick->CTLR=0;
- SysTick->SR=0;
- SysTick->CNT=0;
- SysTick->CMP=ticks-1;
- SysTick->CTLR=0xF;
+ SysTick->CTLR = 0;
+ SysTick->SR = 0;
+ SysTick->CNT = 0;
+ SysTick->CMP = ticks - 1;
+ SysTick->CTLR = 0xF;
return 0;
}
@@ -70,14 +85,28 @@ void board_init(void) {
SysTick_Config(SystemCoreClock / 1000);
#endif
- usart_printf_init(115200);
+ usart_printf_init(CFG_BOARD_UART_BAUDRATE);
+#ifdef CH32V30x_D8C
+ // v305/v307: Highspeed USB
RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
RCC_USBHSConfig(RCC_USBPLL_Div2);
RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
RCC_USBHSPHYPLLALIVEcmd(ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
+#endif
+
+ // Fullspeed USB
+ uint8_t otg_div;
+ switch (SystemCoreClock) {
+ case 48000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div1; break;
+ case 96000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div2; break;
+ case 144000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div3; break;
+ default: TU_ASSERT(0,); break;
+ }
+ RCC_OTGFSCLKConfig(otg_div);
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE);
GPIO_InitTypeDef GPIO_InitStructure = {0};
@@ -102,24 +131,14 @@ void board_init(void) {
}
#if CFG_TUSB_OS == OPT_OS_NONE
-
volatile uint32_t system_ticks = 0;
-/* Small workaround to support HW stack save/restore */
-void SysTick_Handler (void) __attribute__((naked));
-void SysTick_Handler (void)
-{
- __asm volatile ("call SysTick_Handler_impl; mret");
-}
-
-__attribute__((used)) void SysTick_Handler_impl (void)
-{
+__attribute__((interrupt)) void SysTick_Handler(void) {
SysTick->SR = 0;
system_ticks++;
}
-uint32_t board_millis (void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
@@ -129,36 +148,30 @@ uint32_t board_millis (void)
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write (bool state)
-{
+void board_led_write(bool state) {
GPIO_WriteBit(LED_PORT, LED_PIN, state);
}
-uint32_t board_button_read (void)
-{
+uint32_t board_button_read(void) {
return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
}
-int board_uart_read (uint8_t *buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
(void) buf;
(void) len;
return 0;
}
-int board_uart_write (void const *buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
int txsize = len;
- while ( txsize-- )
- {
- uart_write(*(uint8_t const*) buf);
- buf++;
+ const char* bufc = (const char*) buf;
+ while (txsize--) {
+ uart_write(*bufc++);
}
+ uart_sync();
return len;
}
-
-
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake
new file mode 100644
index 0000000000..d603af62d4
--- /dev/null
+++ b/hw/bsp/ch32v307/family.cmake
@@ -0,0 +1,129 @@
+include_guard()
+
+set(CH32_FAMILY ch32v30x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v307)
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V307 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+# default to highspeed, used to select USBFS / USBHS driver
+if (NOT DEFINED SPEED)
+ set(SPEED high)
+endif()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/ch32v307.ld)
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ if (NOT DEFINED STARTUP_FILE_GNU)
+ set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_D8C.S)
+ endif ()
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_SRC_DIR}/Core/core_riscv.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+ ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${CH32_FAMILY}_it.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_SRC_DIR}/Core
+ ${SDK_SRC_DIR}/Peripheral/inc
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ )
+ if (SPEED STREQUAL high)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CFG_TUD_WCH_USBIP_USBHS=1
+# BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ )
+ else ()
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CFG_TUD_WCH_USBIP_USBFS=1
+ )
+ endif ()
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -msmall-data-limit=8
+ -mno-save-restore
+ -fmessage-length=0
+ -fsigned-char
+ )
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ message(FATAL_ERROR "Clang is not supported for MSP432E4")
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/debug_uart.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_CH32V307 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/wch/dcd_ch32_usbhs.c
+ ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_add_bin_hex(${TARGET})
+ family_flash_openocd_wch(${TARGET})
+endfunction()
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 07e57f04c4..bf2732106d 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -1,66 +1,64 @@
# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
#CROSS_COMPILE ?= riscv32-unknown-elf-
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE ?= riscv-none-embed-
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
-# Submodules
-CH32V307_SDK = hw/mcu/wch/ch32v307
-DEPS_SUBMODULES += $(CH32V307_SDK)
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
-# WCH-SDK paths
-CH32V307_SDK_SRC = $(CH32V307_SDK)/EVT/EXAM/SRC
+CH32_FAMILY = ch32v30x
+SDK_DIR = hw/mcu/wch/ch32v307
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32
+
+# default to use high speed port, unless specified in board.mk or command line
+SPEED ?= high
CFLAGS += \
-flto \
- -march=rv32imac \
- -mabi=ilp32 \
-msmall-data-limit=8 \
- -mno-save-restore -Os \
+ -mno-save-restore \
-fmessage-length=0 \
-fsigned-char \
- -ffunction-sections \
- -fdata-sections \
- -nostdlib -nostartfiles \
-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
- -Xlinker --gc-sections \
- -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+# https://github.com/openwch/ch32v307/pull/90
+CFLAGS += -Wno-error=strict-prototypes
+
+ifeq ($(SPEED),high)
+ $(info "Using USBHS driver for HighSpeed mode")
+ CFLAGS += -DCFG_TUD_WCH_USBIP_USBHS=1
+else
+ $(info "Using USBFS driver for FullSpeed mode")
+ CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1
+endif
+
+LDFLAGS_GCC += \
+ -nostdlib -nostartfiles \
+ --specs=nosys.specs --specs=nano.specs \
SRC_C += \
src/portable/wch/dcd_ch32_usbhs.c \
- $(CH32V307_SDK_SRC)/Core/core_riscv.c \
- $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_gpio.c \
- $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_misc.c \
- $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_rcc.c \
- $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_usart.c
+ src/portable/wch/dcd_ch32_usbfs.c \
+ $(SDK_SRC_DIR)/Core/core_riscv.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c
SRC_S += \
- $(CH32V307_SDK_SRC)/Startup/startup_ch32v30x_D8C.S
+ $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_D8C.S
INC += \
$(TOP)/$(BOARD_PATH) \
- $(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc
+ $(TOP)/$(SDK_SRC_DIR)/Core \
+ $(TOP)/$(SDK_SRC_DIR)/Peripheral/inc
# For freeRTOS port source
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
-# wch-link is not supported yet in official openOCD yet. We need to either use
-# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
-# 2. compiled from modified source https://github.com/kprasadvnsi/riscv-openocd-wch
-#
-# Note: For Linux, somehow openocd in mounriver studio does not seem to have wch-link enable,
-# therefore we need to compile it from source as follows:
-# git clone https://github.com/kprasadvnsi/riscv-openocd-wch
-# cd riscv-openocd-wch
-# ./bootstrap
-# ./configure CFLAGS="-Wno-error" --enable-wlink
-# make
-# openocd binaries will be generated in riscv-openocd-wch/src
-
-# flash target ROM bootloader
-flash: $(BUILD)/$(PROJECT).elf
- openocd -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "program $<" -c wlink_reset_resume -c exit
+OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
+flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v307/wch-riscv.cfg b/hw/bsp/ch32v307/wch-riscv.cfg
index 0d24d16ca2..aa35aa9c56 100644
--- a/hw/bsp/ch32v307/wch-riscv.cfg
+++ b/hw/bsp/ch32v307/wch-riscv.cfg
@@ -1,13 +1,15 @@
-#interface wlink
-adapter driver wlink
-wlink_set
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
diff --git a/hw/bsp/da14695_dk_usb/board.mk b/hw/bsp/da14695_dk_usb/board.mk
deleted file mode 100644
index 980b1a3615..0000000000
--- a/hw/bsp/da14695_dk_usb/board.mk
+++ /dev/null
@@ -1,56 +0,0 @@
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
-
-CFLAGS += \
- -flto \
- -mthumb \
- -mthumb-interwork \
- -mabi=aapcs \
- -mcpu=cortex-m33+nodsp \
- -mfloat-abi=hard \
- -mfpu=fpv5-sp-d16 \
- -nostdlib \
- -DCORE_M33 \
- -DCFG_TUSB_MCU=OPT_MCU_DA1469X \
- -DCFG_TUD_ENDPOINT0_SIZE=8\
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
-
-# While this is for da1469x chip, there is chance that da1468x chip family will also work
-SRC_C += \
- src/portable/dialog/da146xx/dcd_da146xx.c \
- $(MCU_FAMILY_DIR)/src/system_da1469x.c \
- $(MCU_FAMILY_DIR)/src/da1469x_clock.c \
- $(MCU_FAMILY_DIR)/src/hal_gpio.c \
-
-SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
-
-INC += \
- $(TOP)/hw/bsp/$(BOARD) \
- $(TOP)/$(MCU_FAMILY_DIR)/include \
- $(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
-
-# For flash-jlink target
-JLINK_DEVICE = DA14695
-
-# flash using jlink but with some twists
-flash: flash-dialog
-
-flash-dialog: $(BUILD)/$(PROJECT).bin
- @echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
- @echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >>$(BUILD)/version.h
- mkimage da1469x $(BUILD)/$(PROJECT).bin $(BUILD)/version.h $^.img
- cp $(TOP)/hw/bsp/$(BOARD)/product_header.dump $(BUILD)/$(BOARD)-image.bin
- cat $^.img >> $(BUILD)/$(BOARD)-image.bin
- @echo r > $(BUILD)/$(BOARD).jlink
- @echo halt >> $(BUILD)/$(BOARD).jlink
- @echo loadfile $(BUILD)/$(BOARD)-image.bin 0x16000000 >> $(BUILD)/$(BOARD).jlink
- @echo r >> $(BUILD)/$(BOARD).jlink
- @echo go >> $(BUILD)/$(BOARD).jlink
- @echo exit >> $(BUILD)/$(BOARD).jlink
- $(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
deleted file mode 100644
index 667b83de38..0000000000
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Jerzy Kasenberg
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include
-#include
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
- tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PIN 33 // P1.1
-#define LED_STATE_ON 1
-#define LED_STATE_OFF (1-LED_STATE_ON)
-
-#define BUTTON_PIN 6
-
-void UnhandledIRQ(void)
-{
- CRG_TOP->SYS_CTRL_REG = 0x80;
- __BKPT(1);
- while(1);
-}
-
-// DA146xx driver function that must be called whenever VBUS changes.
-extern void tusb_vbus_changed(bool present);
-
-void board_init(void)
-{
- // LED
- hal_gpio_init_out(LED_PIN, LED_STATE_ON);
-
- hal_gpio_init_out(1, 0);
- hal_gpio_init_out(2, 0);
- hal_gpio_init_out(3, 0);
- hal_gpio_init_out(4, 0);
- hal_gpio_init_out(5, 0);
-
- // Button
- hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_DOWN);
-
- // 1ms tick timer
- SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUD_ENABLED
- // This board is USB powered there is no need to monitor
- // VBUS line. Notify driver that VBUS is present.
- tusb_vbus_changed(true);
-
- /* Setup USB IRQ */
- NVIC_SetPriority(USB_IRQn, 2);
- NVIC_EnableIRQ(USB_IRQn);
-
- /* Use PLL96 / 2 clock not HCLK */
- CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk;
-
- mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
- mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
- hal_gpio_write(LED_PIN, state ? LED_STATE_ON : LED_STATE_OFF);
-}
-
-uint32_t board_button_read(void)
-{
- // button is active HIGH
- return hal_gpio_read(BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
- (void)buf;
- (void)len;
- return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
- (void)buf;
- (void)len;
-
- return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
- system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
- return system_ticks;
-}
-#endif
diff --git a/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..4d4379a6f7
--- /dev/null
+++ b/hw/bsp/da1469x/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,150 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "DA1469xAB.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+#define configRUN_FREERTOS_SECURE_ONLY 1
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<
#include
+#define LED_STATE_OFF (1-LED_STATE_ON)
+
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
tud_int_handler(0);
}
-#if CFG_TUD_ENABLED
-// DA146xx driver function that must be called whenever VBUS changes
+// DA146xx driver function that must be called whenever VBUS changes.
extern void tusb_vbus_changed(bool present);
+#if defined(NEED_VBUS_MONITOR) && CFG_TUD_ENABLED
// VBUS change interrupt handler
-void VBUS_IRQHandler(void)
-{
+void VBUS_IRQHandler(void) {
bool present = (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk) != 0;
// Clear VBUS interrupt
CRG_TOP->VBUS_IRQ_CLEAR_REG = 1;
@@ -54,22 +55,13 @@ void VBUS_IRQHandler(void)
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
-
-#define LED_PIN 33
-#define LED_STATE_ON 1
-#define LED_STATE_OFF 0
-
-#define BUTTON_PIN 6
-
-void UnhandledIRQ(void)
-{
+void UnhandledIRQ(void) {
CRG_TOP->SYS_CTRL_REG = 0x80;
__BKPT(1);
- while(1);
+ while (1);
}
-void board_init(void)
-{
+void board_init(void) {
// LED
hal_gpio_init_out(LED_PIN, LED_STATE_ON);
@@ -80,12 +72,13 @@ void board_init(void)
hal_gpio_init_out(5, 0);
// Button
- hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_UP);
+ hal_gpio_init_in(BUTTON_PIN, BUTTON_STATE_ACTIVE ? HAL_GPIO_PULL_DOWN : HAL_GPIO_PULL_UP);
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#if CFG_TUD_ENABLED
+ #ifdef NEED_VBUS_MONITOR
// Setup interrupt for both connect and disconnect
CRG_TOP->VBUS_IRQ_MASK_REG = CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk |
CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk;
@@ -94,6 +87,10 @@ void board_init(void)
// otherwise it could go unnoticed.
NVIC_SetPendingIRQ(VBUS_IRQn);
NVIC_EnableIRQ(VBUS_IRQn);
+ #else
+ // This board is USB powered there is no need to monitor VBUS line. Notify driver that VBUS is present.
+ tusb_vbus_changed(true);
+ #endif
/* Setup USB IRQ */
NVIC_SetPriority(USB_IRQn, 2);
@@ -111,41 +108,35 @@ void board_init(void)
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
hal_gpio_write(LED_PIN, state ? LED_STATE_ON : LED_STATE_OFF);
}
-uint32_t board_button_read(void)
-{
- // button is active LOW
- return hal_gpio_read(BUTTON_PIN) ^ 1;
+uint32_t board_button_read(void) {
+ return BUTTON_STATE_ACTIVE == hal_gpio_read(BUTTON_PIN);
}
-int board_uart_read(uint8_t* buf, int len)
-{
- (void)buf;
- (void)len;
+int board_uart_read(uint8_t* buf, int len) {
+ (void) buf;
+ (void) len;
return 0;
}
-int board_uart_write(void const * buf, int len)
-{
- (void)buf;
- (void)len;
+int board_uart_write(void const* buf, int len) {
+ (void) buf;
+ (void) len;
return 0;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
system_ticks++;
}
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
#endif
diff --git a/hw/bsp/da1469x/family.cmake b/hw/bsp/da1469x/family.cmake
new file mode 100644
index 0000000000..8c89141fee
--- /dev/null
+++ b/hw/bsp/da1469x/family.cmake
@@ -0,0 +1,141 @@
+include_guard()
+
+set(MCU_DIR ${TOP}/hw/mcu/dialog/da1469x)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(FAMILY_MCUS DA1469X CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/da1469x.ld)
+ endif ()
+
+ if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+ set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/gcc_startup_da1469x.S)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+ endif ()
+
+ add_library(${BOARD_TARGET} STATIC
+ ${MCU_DIR}/src/system_da1469x.c
+ ${MCU_DIR}/src/da1469x_clock.c
+ ${MCU_DIR}/src/hal_gpio.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_compile_options(${BOARD_TARGET} PUBLIC -mthumb-interwork)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CORE_M33
+ CFG_TUD_ENDPOINT0_SIZE=8
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ ${MCU_DIR}/include
+ ${MCU_DIR}/SDK_10.0.8.105/sdk/bsp/include
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -L${NRFX_DIR}/mdk
+ --specs=nosys.specs --specs=nano.specs
+ -nostartfiles
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -L${NRFX_DIR}/mdk
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+
+function(family_flash_jlink_dialog TARGET)
+ set(JLINKEXE JLinkExe)
+ set(JLINK_IF swd)
+
+ # mkimage from sdk
+ set(MKIMAGE $ENV{HOME}/code/tinyusb-mcu-driver/dialog/SDK_10.0.8.105/binaries/mkimage)
+
+ file(GENERATE OUTPUT $/version.h
+ CONTENT "#define SW_VERSION \"v_1.0.0.1\"
+#define SW_VERSION_DATE \"2024-07-17 17:55\""
+ )
+
+ file(GENERATE OUTPUT $/${TARGET}.jlink
+ CONTENT "r
+halt
+loadfile $/${TARGET}-image.bin 0x16000000
+r
+go
+exit"
+ )
+
+ add_custom_target(${TARGET}-image
+ DEPENDS ${TARGET}
+ COMMAND ${MKIMAGE} da1469x $/${TARGET}.bin $/version.h $/${TARGET}.bin.img
+ COMMAND cp ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/product_header.dump $/${TARGET}-image.bin
+ COMMAND cat $/${TARGET}.bin.img >> $/${TARGET}-image.bin
+ )
+ add_custom_target(${TARGET}-jlink
+ DEPENDS ${TARGET}-image
+ COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink
+ )
+endfunction()
+
+
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_DA1469X ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/dialog/da146xx/dcd_da146xx.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_add_bin_hex(${TARGET})
+ family_flash_jlink_dialog(${TARGET})
+endfunction()
diff --git a/hw/bsp/da1469x_dk_pro/board.mk b/hw/bsp/da1469x/family.mk
similarity index 52%
rename from hw/bsp/da1469x_dk_pro/board.mk
rename to hw/bsp/da1469x/family.mk
index 5282f93a38..f35fe2cb5f 100644
--- a/hw/bsp/da1469x_dk_pro/board.mk
+++ b/hw/bsp/da1469x/family.mk
@@ -1,4 +1,6 @@
-MCU_FAMILY_DIR = hw/mcu/dialog/da1469x
+MCU_DIR = hw/mcu/dialog/da1469x
+
+include $(TOP)/$(BOARD_PATH)/board.mk
CFLAGS += \
-flto \
@@ -8,48 +10,52 @@ CFLAGS += \
-mcpu=cortex-m33+nodsp \
-mfloat-abi=hard \
-mfpu=fpv5-sp-d16 \
- -nostdlib \
-DCORE_M33 \
-DCFG_TUSB_MCU=OPT_MCU_DA1469X \
-DCFG_TUD_ENDPOINT0_SIZE=8\
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+LDFLAGS_GCC += \
+ -nostdlib \
+ --specs=nosys.specs --specs=nano.specs
# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/da1469x.ld
+LD_FILE = $(FAMILY_PATH)/linker/da1469x.ld
# While this is for da1469x chip, there is chance that da1468x chip family will also work
SRC_C += \
src/portable/dialog/da146xx/dcd_da146xx.c \
- $(MCU_FAMILY_DIR)/src/system_da1469x.c \
- $(MCU_FAMILY_DIR)/src/da1469x_clock.c \
- $(MCU_FAMILY_DIR)/src/hal_gpio.c \
+ ${MCU_DIR}/src/system_da1469x.c \
+ ${MCU_DIR}/src/da1469x_clock.c \
+ ${MCU_DIR}/src/hal_gpio.c \
-SRC_S += hw/bsp/$(BOARD)/gcc_startup_da1469x.S
+SRC_S += $(FAMILY_PATH)/gcc_startup_da1469x.S
INC += \
- $(TOP)/hw/bsp/$(BOARD) \
- $(TOP)/$(MCU_FAMILY_DIR)/include \
- $(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/${MCU_DIR}/include \
+ $(TOP)/${MCU_DIR}/SDK_10.0.8.105/sdk/bsp/include
# For freeRTOS port source
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
-# For flash-jlink target
-JLINK_DEVICE = DA14699
-
# flash using jlink but with some twists
flash: flash-dialog
-flash-dialog: $(BUILD)/$(PROJECT).bin
+# SDK_BINARY_PATH is the path to the SDK binary files
+SDK_BINARY_PATH = $(HOME)/code/tinyusb-mcu-driver/dialog/SDK_10.0.8.105/binaries
+MKIMAGE = $(SDK_BINARY_PATH)/mkimage
+
+$(BUILD)/$(PROJECT)-image.bin: $(BUILD)/$(PROJECT).bin
@echo '#define SW_VERSION "v_1.0.0.1"' >$(BUILD)/version.h
- @echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >>$(BUILD)/version.h
- mkimage da1469x $(BUILD)/$(PROJECT).bin $(BUILD)/version.h $^.img
- cp $(TOP)/hw/bsp/$(BOARD)/product_header.dump $(BUILD)/$(BOARD)-image.bin
- cat $^.img >> $(BUILD)/$(BOARD)-image.bin
+ @echo '#define SW_VERSION_DATE "'`date +"%Y-%m-%d %H:%M"`'"' >> $(BUILD)/version.h
+ $(MKIMAGE) da1469x $^ $(BUILD)/version.h $^.img
+ cp $(TOP)/$(FAMILY_PATH)/product_header.dump $(BUILD)/$(PROJECT)-image.bin
+ cat $^.img >> $(BUILD)/$(PROJECT)-image.bin
+
+flash-dialog: $(BUILD)/$(PROJECT)-image.bin
@echo r > $(BUILD)/$(BOARD).jlink
@echo halt >> $(BUILD)/$(BOARD).jlink
- @echo loadfile $(BUILD)/$(BOARD)-image.bin 0x16000000 >> $(BUILD)/$(BOARD).jlink
+ @echo loadfile $^ 0x16000000 >> $(BUILD)/$(BOARD).jlink
@echo r >> $(BUILD)/$(BOARD).jlink
@echo go >> $(BUILD)/$(BOARD).jlink
@echo exit >> $(BUILD)/$(BOARD).jlink
diff --git a/hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S b/hw/bsp/da1469x/gcc_startup_da1469x.S
similarity index 100%
rename from hw/bsp/da14695_dk_usb/gcc_startup_da1469x.S
rename to hw/bsp/da1469x/gcc_startup_da1469x.S
diff --git a/hw/bsp/da14695_dk_usb/da1469x.ld b/hw/bsp/da1469x/linker/da1469x.ld
similarity index 100%
rename from hw/bsp/da14695_dk_usb/da1469x.ld
rename to hw/bsp/da1469x/linker/da1469x.ld
diff --git a/hw/bsp/da14695_dk_usb/product_header.dump b/hw/bsp/da1469x/product_header.dump
similarity index 100%
rename from hw/bsp/da14695_dk_usb/product_header.dump
rename to hw/bsp/da1469x/product_header.dump
diff --git a/hw/bsp/da1469x_dk_pro/da1469x.ld b/hw/bsp/da1469x_dk_pro/da1469x.ld
deleted file mode 100644
index 8cc1d9d99d..0000000000
--- a/hw/bsp/da1469x_dk_pro/da1469x.ld
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-MEMORY
-{
- /*
- * Flash is remapped at 0x0 by 1st stage bootloader, but this is done with
- * an offset derived from image header thus it is safer to use remapped
- * address space at 0x0 instead of QSPI_M address space at 0x16000000.
- * Bootloader partition is 32K, but 9K is currently reserved for product
- * header (8K) and image header (1K).
- * First 512 bytes of SYSRAM are remapped at 0x0 and used as ISR vector
- * (there's no need to reallocate ISR vector) and thus cannot be used by
- * application.
- */
-
- FLASH (r) : ORIGIN = (0x00000000), LENGTH = (1024 * 1024)
- RAM (rw) : ORIGIN = (0x20000000), LENGTH = (512 * 1024)
-}
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __HeapBase
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- * __bssnz_start__
- * __bssnz_end__
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- __text = .;
-
- .text :
- {
- __isr_vector_start = .;
- KEEP(*(.isr_vector))
- /* ISR vector shall have exactly 512 bytes */
- . = __isr_vector_start + 0x200;
- __isr_vector_end = .;
-
- *(.text)
- *(.text.*)
-
- *(.libcmac.rom)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- *(.eh_frame*)
- . = ALIGN(4);
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- . = ALIGN(4);
- } > FLASH
-
- __exidx_start = .;
- .ARM :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- . = ALIGN(4);
- } > FLASH
- __exidx_end = .;
-
- .intvect :
- {
- . = ALIGN(4);
- __intvect_start__ = .;
- . = . + (__isr_vector_end - __isr_vector_start);
- . = ALIGN(4);
- } > RAM
-
- .sleep_state (NOLOAD) :
- {
- . = ALIGN(4);
- *(sleep_state)
- } > RAM
-
- /* This section will be zeroed by RTT package init */
- .rtt (NOLOAD):
- {
- . = ALIGN(4);
- *(.rtt)
- . = ALIGN(4);
- } > RAM
-
- __text_ram_addr = LOADADDR(.text_ram);
-
- .text_ram :
- {
- . = ALIGN(4);
- __text_ram_start__ = .;
- *(.text_ram*)
- . = ALIGN(4);
- __text_ram_end__ = .;
- } > RAM AT > FLASH
-
- __etext = LOADADDR(.data);
-
- .data :
- {
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- *(.preinit_array)
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- *(SORT(.init_array.*))
- *(.init_array)
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- *(SORT(.fini_array.*))
- *(.fini_array)
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- *(.jcr)
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
- } > RAM AT > FLASH
-
- .bssnz :
- {
- . = ALIGN(4);
- __bssnz_start__ = .;
- *(.bss.core.nz*)
- . = ALIGN(4);
- __bssnz_end__ = .;
- } > RAM
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- __bss_end__ = .;
- } > RAM
-
- .cmac (NOLOAD) :
- {
- . = ALIGN(0x400);
- *(.libcmac.ram)
- } > RAM
-
- /* Heap starts after BSS */
- . = ALIGN(8);
- __HeapBase = .;
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
-
- _ram_start = ORIGIN(RAM);
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Top of head is the bottom of the stack */
- __HeapLimit = __StackLimit;
- end = __HeapLimit;
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
-
- /* Check that intvect is at the beginning of RAM */
- ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
-}
diff --git a/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S b/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S
deleted file mode 100644
index d47fbcd976..0000000000
--- a/hw/bsp/da1469x_dk_pro/gcc_startup_da1469x.S
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
- #include "syscfg/syscfg.h"
-
- .syntax unified
- .arch armv7-m
-
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0xC00
-#endif
- .equ SYS_CTRL_REG, 0x50000024
- .equ CACHE_FLASH_REG, 0x100C0040
- .equ RESET_STAT_REG, 0x500000BC
-
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop
- .long Reset_Handler
- /* Cortex-M33 interrupts */
- .long NMI_Handler
- .long HardFault_Handler
- .long MemoryManagement_Handler
- .long BusFault_Handler
- .long UsageFault_Handler
- .long SecureFault_Handler
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler
- .long DebugMonitor_Handler
- .long 0 /* Reserved */
- .long PendSV_Handler
- .long SysTick_Handler
- /* DA1469x interrupts */
- .long SENSOR_NODE_IRQHandler
- .long DMA_IRQHandler
- .long CHARGER_STATE_IRQHandler
- .long CHARGER_ERROR_IRQHandler
- .long CMAC2SYS_IRQHandler
- .long UART_IRQHandler
- .long UART2_IRQHandler
- .long UART3_IRQHandler
- .long I2C_IRQHandler
- .long I2C2_IRQHandler
- .long SPI_IRQHandler
- .long SPI2_IRQHandler
- .long PCM_IRQHandler
- .long SRC_IN_IRQHandler
- .long SRC_OUT_IRQHandler
- .long USB_IRQHandler
- .long TIMER_IRQHandler
- .long TIMER2_IRQHandler
- .long RTC_IRQHandler
- .long KEY_WKUP_GPIO_IRQHandler
- .long PDC_IRQHandler
- .long VBUS_IRQHandler
- .long MRM_IRQHandler
- .long MOTOR_CONTROLLER_IRQHandler
- .long TRNG_IRQHandler
- .long DCDC_IRQHandler
- .long XTAL32M_RDY_IRQHandler
- .long ADC_IRQHandler
- .long ADC2_IRQHandler
- .long CRYPTO_IRQHandler
- .long CAPTIMER1_IRQHandler
- .long RFDIAG_IRQHandler
- .long LCD_CONTROLLER_IRQHandler
- .long PLL_LOCK_IRQHandler
- .long TIMER3_IRQHandler
- .long TIMER4_IRQHandler
- .long LRA_IRQHandler
- .long RTC_EVENT_IRQHandler
- .long GPIO_P0_IRQHandler
- .long GPIO_P1_IRQHandler
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .size __isr_vector, . - __isr_vector
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- /* Make sure interrupt vector is remapped at 0x0 */
- ldr r1, =SYS_CTRL_REG
- ldrh r2, [r1, #0]
- orrs r2, r2, #8
- strh r2, [r1, #0]
-
-#if !MYNEWT_VAL(RAM_RESIDENT)
-/*
- * Flash is remapped at 0x0 with an offset, i.e. 0x0 does not correspond to
- * 0x16000000 but to start of an image on flash. This is calculated from product
- * header by 1st state bootloader and configured in CACHE_FLASH_REG. We need to
- * retrieve proper offset value for calculations later.
- */
- ldr r1, =CACHE_FLASH_REG
- ldr r4, [r1, #0]
- mov r2, r4
- mov r3, #0xFFFF
- bic r4, r4, r3 /* CACHE_FLASH_REG[FLASH_REGION_BASE] */
- mov r3, #0xFFF0
- and r2, r2, r3 /* CACHE_FLASH_REG[FLASH_REGION_OFFSET] */
- lsr r2, r2, #2
- orr r4, r4, r2
-
-/* Copy ISR vector from flash to RAM */
- ldr r1, =__isr_vector_start /* src ptr */
- ldr r2, =__isr_vector_end /* src end */
- ldr r3, =__intvect_start__ /* dst ptr */
-/* Make sure we copy from QSPIC address range, not from remapped range */
- cmp r1, r4
- itt lt
- addlt r1, r1, r4
- addlt r2, r2, r4
-.loop_isr_copy:
- cmp r1, r2
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r3], #4
- blt .loop_isr_copy
-
-/* Copy QSPI code from flash to RAM */
- ldr r1, =__text_ram_addr /* src ptr */
- ldr r2, =__text_ram_start__ /* ptr */
- ldr r3, =__text_ram_end__ /* dst end */
-.loop_code_text_ram_copy:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .loop_code_text_ram_copy
-
-/* Copy data from flash to RAM */
- ldr r1, =__etext /* src ptr */
- ldr r2, =__data_start__ /* dst ptr */
- ldr r3, =__data_end__ /* dst end */
-.loop_data_copy:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .loop_data_copy
-#endif
-
-/* Clear BSS */
- movs r0, 0
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-.loop_bss_clear:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .loop_bss_clear
-
- ldr r0, =__HeapBase
- ldr r1, =__HeapLimit
-/* Call static constructors */
- bl __libc_init_array
-
- bl SystemInit
- bl main
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-/* Default interrupt handler */
- .type Default_Handler, %function
-Default_Handler:
- ldr r1, =SYS_CTRL_REG
- ldrh r2, [r1, #0]
- orrs r2, r2, #0x80 /* DEBUGGER_ENABLE */
- strh r2, [r1, #0]
- b .
-
- .size Default_Handler, . - Default_Handler
-
-/* Default handlers for all interrupts */
- .macro IRQ handler
- .weak \handler
- .set \handler, Default_Handler
- .endm
-
- /* Cortex-M33 interrupts */
- IRQ NMI_Handler
- IRQ HardFault_Handler
- IRQ MemoryManagement_Handler
- IRQ BusFault_Handler
- IRQ UsageFault_Handler
- IRQ SecureFault_Handler
- IRQ SVC_Handler
- IRQ DebugMonitor_Handler
- IRQ PendSV_Handler
- IRQ SysTick_Handler
- /* DA1469x interrupts */
- IRQ SENSOR_NODE_IRQHandler
- IRQ DMA_IRQHandler
- IRQ CHARGER_STATE_IRQHandler
- IRQ CHARGER_ERROR_IRQHandler
- IRQ CMAC2SYS_IRQHandler
- IRQ UART_IRQHandler
- IRQ UART2_IRQHandler
- IRQ UART3_IRQHandler
- IRQ I2C_IRQHandler
- IRQ I2C2_IRQHandler
- IRQ SPI_IRQHandler
- IRQ SPI2_IRQHandler
- IRQ PCM_IRQHandler
- IRQ SRC_IN_IRQHandler
- IRQ SRC_OUT_IRQHandler
- IRQ USB_IRQHandler
- IRQ TIMER_IRQHandler
- IRQ TIMER2_IRQHandler
- IRQ RTC_IRQHandler
- IRQ KEY_WKUP_GPIO_IRQHandler
- IRQ PDC_IRQHandler
- IRQ VBUS_IRQHandler
- IRQ MRM_IRQHandler
- IRQ MOTOR_CONTROLLER_IRQHandler
- IRQ TRNG_IRQHandler
- IRQ DCDC_IRQHandler
- IRQ XTAL32M_RDY_IRQHandler
- IRQ ADC_IRQHandler
- IRQ ADC2_IRQHandler
- IRQ CRYPTO_IRQHandler
- IRQ CAPTIMER1_IRQHandler
- IRQ RFDIAG_IRQHandler
- IRQ LCD_CONTROLLER_IRQHandler
- IRQ PLL_LOCK_IRQHandler
- IRQ TIMER3_IRQHandler
- IRQ TIMER4_IRQHandler
- IRQ LRA_IRQHandler
- IRQ RTC_EVENT_IRQHandler
- IRQ GPIO_P0_IRQHandler
- IRQ GPIO_P1_IRQHandler
- IRQ RESERVED40_IRQHandler
- IRQ RESERVED41_IRQHandler
- IRQ RESERVED42_IRQHandler
- IRQ RESERVED43_IRQHandler
- IRQ RESERVED44_IRQHandler
- IRQ RESERVED45_IRQHandler
- IRQ RESERVED46_IRQHandler
- IRQ RESERVED47_IRQHandler
-
-.end
diff --git a/hw/bsp/da1469x_dk_pro/product_header.dump b/hw/bsp/da1469x_dk_pro/product_header.dump
deleted file mode 100644
index ea48422426..0000000000
Binary files a/hw/bsp/da1469x_dk_pro/product_header.dump and /dev/null differ
diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt
index 8209e87471..434f777048 100644
--- a/hw/bsp/espressif/boards/CMakeLists.txt
+++ b/hw/bsp/espressif/boards/CMakeLists.txt
@@ -2,7 +2,5 @@ set(hw_dir "${CMAKE_CURRENT_LIST_DIR}/../../../")
idf_component_register(SRCS family.c
INCLUDE_DIRS "." ${BOARD} ${hw_dir}
- PRIV_REQUIRES "driver"
+ PRIV_REQUIRES driver usb
REQUIRES led_strip src tinyusb_src)
-
-target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake
new file mode 100644
index 0000000000..84ea4940b7
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h
new file mode 100644
index 0000000000..0c53df06b2
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN 0
+#define NEOPIXEL_POWER_PIN 2
+#define NEOPIXEL_POWER_STATE 1
+
+#define BUTTON_PIN 38
+#define BUTTON_STATE_ACTIVE 0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI3_HOST
+#define MAX3421_SCK_PIN 5
+#define MAX3421_MOSI_PIN 19
+#define MAX3421_MISO_PIN 21
+#define MAX3421_CS_PIN 33
+#define MAX3421_INTR_PIN 15
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
index abbdf7abc7..0bbf5a013d 100644
--- a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
@@ -1,2 +1,3 @@
# Apply board specific content here
set(IDF_TARGET "esp32s2")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake
new file mode 100644
index 0000000000..dd204f0a4c
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h
new file mode 100644
index 0000000000..9aa2e75353
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN 33
+#define NEOPIXEL_POWER_PIN 21
+#define NEOPIXEL_POWER_STATE 1
+
+#define BUTTON_PIN 0
+#define BUTTON_STATE_ACTIVE 0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN 36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN 10
+#define MAX3421_INTR_PIN 9
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
index abbdf7abc7..0bbf5a013d 100644
--- a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
@@ -1,2 +1,3 @@
# Apply board specific content here
set(IDF_TARGET "esp32s2")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake
new file mode 100644
index 0000000000..6a0060f9eb
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32c3")
+set(MAX3421_HOST 1)
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h
similarity index 83%
rename from hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
rename to hw/bsp/espressif/boards/espressif_c3_devkitc/board.h
index 072cb27143..243dd47f60 100644
--- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
+++ b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h
@@ -31,19 +31,18 @@
extern "C" {
#endif
-#define _PINNUM(port, pin) ((port)*32 + (pin))
+#define NEOPIXEL_PIN 8
-// LED
-#define LED_PIN _PINNUM(0, 23)
-#define LED_STATE_ON 0
-
-// Button
-#define BUTTON_PIN _PINNUM(0, 18)
+#define BUTTON_PIN 9
#define BUTTON_STATE_ACTIVE 0
-// UART
-#define UART_RX_PIN 2
-#define UART_TX_PIN 3
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN 4
+#define MAX3421_MOSI_PIN 6
+#define MAX3421_MISO_PIN 5
+#define MAX3421_CS_PIN 10
+#define MAX3421_INTR_PIN 7
#ifdef __cplusplus
}
diff --git a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake
new file mode 100644
index 0000000000..9adaefb173
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32c6")
+set(MAX3421_HOST 1)
diff --git a/src/portable/mentor/musb/musb_tm4c.h b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h
similarity index 75%
rename from src/portable/mentor/musb/musb_tm4c.h
rename to hw/bsp/espressif/boards/espressif_c6_devkitc/board.h
index 65a1751b0f..243dd47f60 100644
--- a/src/portable/mentor/musb/musb_tm4c.h
+++ b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h
@@ -1,7 +1,7 @@
/*
* The MIT License (MIT)
*
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -24,22 +24,28 @@
* This file is part of the TinyUSB stack.
*/
-#ifndef _TUSB_MUSB_TM4C_H_
-#define _TUSB_MUSB_TM4C_H_
+#ifndef BOARD_H_
+#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
-#if CFG_TUSB_MCU == OPT_MCU_TM4C123
- #include "TM4C123.h"
-//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129
-#else
- #error "Unsupported MCUs"
-#endif
+#define NEOPIXEL_PIN 8
+
+#define BUTTON_PIN 9
+#define BUTTON_STATE_ACTIVE 0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN 4
+#define MAX3421_MOSI_PIN 6
+#define MAX3421_MISO_PIN 5
+#define MAX3421_CS_PIN 10
+#define MAX3421_INTR_PIN 7
#ifdef __cplusplus
}
#endif
-#endif
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake
new file mode 100644
index 0000000000..fe4db4fc1d
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32p4")
diff --git a/src/portable/mentor/musb/musb_msp432e.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
similarity index 85%
rename from src/portable/mentor/musb/musb_msp432e.h
rename to hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
index fce21de889..9c8aa409f2 100644
--- a/src/portable/mentor/musb/musb_msp432e.h
+++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h
@@ -1,7 +1,7 @@
/*
* The MIT License (MIT)
*
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -24,17 +24,20 @@
* This file is part of the TinyUSB stack.
*/
-#ifndef _TUSB_MUSB_MSP432E_H_
-#define _TUSB_MUSB_MSP432E_H_
+#ifndef BOARD_H_
+#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
-#include "msp.h"
+// #define NEOPIXEL_PIN 48
+
+#define BUTTON_PIN 0
+#define BUTTON_STATE_ACTIVE 0
#ifdef __cplusplus
}
#endif
-#endif
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 5599d1504a..a1b4334b20 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -30,17 +30,10 @@
#include "esp_rom_gpio.h"
#include "esp_mac.h"
#include "hal/gpio_ll.h"
-#include "hal/usb_hal.h"
-#include "soc/usb_periph.h"
#include "driver/gpio.h"
#include "driver/uart.h"
-
-#if ESP_IDF_VERSION_MAJOR > 4
- #include "esp_private/periph_ctrl.h"
-#else
- #include "driver/periph_ctrl.h"
-#endif
+#include "esp_private/periph_ctrl.h"
// Note; current code use UART0 can cause device to reset while monitoring
#define USE_UART 0
@@ -56,7 +49,7 @@ static led_strip_handle_t led_strip;
static void max3421_init(void);
#endif
-static void configure_pins(usb_hal_context_t* usb);
+static bool usb_init(void);
//--------------------------------------------------------------------+
// Implementation
@@ -100,7 +93,6 @@ void board_init(void) {
};
ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip));
-
led_strip_clear(led_strip); // off
#endif
@@ -109,50 +101,18 @@ void board_init(void) {
gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
- // USB Controller Hal init
- periph_module_reset(PERIPH_USB_MODULE);
- periph_module_enable(PERIPH_USB_MODULE);
-
- usb_hal_context_t hal = {
- .use_external_phy = false // use built-in PHY
- };
- usb_hal_init(&hal);
- configure_pins(&hal);
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
+ usb_init();
+#endif
#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
max3421_init();
#endif
}
-static void configure_pins(usb_hal_context_t* usb) {
- /* usb_periph_iopins currently configures USB_OTG as USB Device.
- * Introduce additional parameters in usb_hal_context_t when adding support
- * for USB Host. */
- for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
- if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
- esp_rom_gpio_pad_select_gpio(iopin->pin);
- if (iopin->is_output) {
- esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
- } else {
- esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-#if ESP_IDF_VERSION_MAJOR > 4
- if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
-#else
- if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
-#endif
- {
- gpio_ll_input_enable(&GPIO, iopin->pin);
- }
- }
- esp_rom_gpio_pad_unhold(iopin->pin);
- }
- }
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
- if (!usb->use_external_phy) {
- gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
- gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
- }
-}
+#endif
//--------------------------------------------------------------------+
// Board porting API
@@ -198,6 +158,87 @@ int board_getchar(void) {
return board_uart_read(&c, 1) > 0 ? (int) c : (-1);
}
+//--------------------------------------------------------------------
+// PHY Init
+//--------------------------------------------------------------------
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4)
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 0)
+
+#include "esp_private/usb_phy.h"
+#include "soc/usb_pins.h"
+
+static usb_phy_handle_t phy_hdl;
+
+bool usb_init(void) {
+ // Configure USB PHY
+ usb_phy_config_t phy_conf = {
+ .controller = USB_PHY_CTRL_OTG,
+ .target = USB_PHY_TARGET_INT,
+ .otg_mode = USB_OTG_MODE_DEVICE,
+ };
+
+ // OTG IOs config
+ // const usb_phy_otg_io_conf_t otg_io_conf = USB_PHY_SELF_POWERED_DEVICE(config->vbus_monitor_io);
+ // if (config->self_powered) {
+ // phy_conf.otg_io_conf = &otg_io_conf;
+ // }
+ // ESP_RETURN_ON_ERROR(usb_new_phy(&phy_conf, &phy_hdl), TAG, "Install USB PHY failed");
+
+ usb_new_phy(&phy_conf, &phy_hdl);
+
+ return true;
+}
+
+#else
+
+#include "esp_private/usb_phy.h"
+#include "hal/usb_hal.h"
+#include "soc/usb_periph.h"
+
+static void configure_pins(usb_hal_context_t* usb) {
+ /* usb_periph_iopins currently configures USB_OTG as USB Device.
+ * Introduce additional parameters in usb_hal_context_t when adding support
+ * for USB Host. */
+ for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
+ if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
+ esp_rom_gpio_pad_select_gpio(iopin->pin);
+ if (iopin->is_output) {
+ esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
+ } else {
+ esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
+ if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT)) {
+ gpio_ll_input_enable(&GPIO, iopin->pin);
+ }
+ }
+ esp_rom_gpio_pad_unhold(iopin->pin);
+ }
+ }
+
+ if (!usb->use_external_phy) {
+ gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
+ gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
+ }
+}
+
+bool usb_init(void) {
+ // USB Controller Hal init
+ periph_module_reset(PERIPH_USB_MODULE);
+ periph_module_enable(PERIPH_USB_MODULE);
+
+ usb_hal_context_t hal = {
+ .use_external_phy = false // use built-in PHY
+ };
+
+ usb_hal_init(&hal);
+ configure_pins(&hal);
+
+ return true;
+}
+
+#endif
+#endif
+
//--------------------------------------------------------------------+
// API: SPI transfer with MAX3421E, must be implemented by application
//--------------------------------------------------------------------+
@@ -208,15 +249,12 @@ SemaphoreHandle_t max3421_intr_sem;
static void IRAM_ATTR max3421_isr_handler(void* arg) {
(void) arg; // arg is gpio num
- gpio_set_level(13, 1);
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
xSemaphoreGiveFromISR(max3421_intr_sem, &xHigherPriorityTaskWoken);
if (xHigherPriorityTaskWoken) {
portYIELD_FROM_ISR();
}
-
- gpio_set_level(13, 0);
}
static void max3421_intr_task(void* param) {
@@ -250,16 +288,12 @@ static void max3421_init(void) {
spi_device_interface_config_t max3421_cfg = {
.mode = 0,
- .clock_speed_hz = 26000000,
+ .clock_speed_hz = 20000000, // S2/S3 can work with 26 Mhz, but esp32 seems only work up to 20 Mhz
.spics_io_num = -1, // manual control CS
.queue_size = 1
};
ESP_ERROR_CHECK(spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi));
- // debug
- gpio_set_direction(13, GPIO_MODE_OUTPUT);
- gpio_set_level(13, 0);
-
// Interrupt pin
max3421_intr_sem = xSemaphoreCreateBinary();
xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES - 2, NULL);
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/dependencies.lock b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/dependencies.lock
deleted file mode 100644
index 97840a1538..0000000000
--- a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/dependencies.lock
+++ /dev/null
@@ -1,15 +0,0 @@
-dependencies:
- espressif/led_strip:
- component_hash: null
- source:
- path: /home/hathach/code/idf-extra-components/led_strip
- type: local
- version: 2.5.2
- idf:
- component_hash: null
- source:
- type: idf
- version: 5.1.1
-manifest_hash: 47d47762be26168b388cb0e6cbfee6b22c68d630ebf4b27a49c47c4c54191590
-target: esp32s3
-version: 1.0.0
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index abe2769101..26c7e40303 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -5,20 +5,13 @@ set(includes_public)
set(compile_options)
set(tusb_src "${CMAKE_CURRENT_SOURCE_DIR}/../../../../../src")
-if(target STREQUAL "esp32s3")
- set(tusb_mcu "OPT_MCU_ESP32S3")
-elseif(target STREQUAL "esp32s2")
- set(tusb_mcu "OPT_MCU_ESP32S2")
-else()
- # CONFIG_TINYUSB dependency has been guaranteed by Kconfig logic,
- # So it's not possible that cmake goes here
- message(FATAL_ERROR "TinyUSB is not support on ${target}.")
- return()
-endif()
-
+string(TOUPPER OPT_MCU_${target} tusb_mcu)
list(APPEND compile_definitions
CFG_TUSB_MCU=${tusb_mcu}
CFG_TUSB_OS=OPT_OS_FREERTOS
+ # EXAMPLE port selection: port0 is fullspeed, port1 is highspeed
+ BOARD_TUD_RHPORT=${TUD_PORT}
+ BOARD_TUD_MAX_SPEED=$
)
list(APPEND srcs
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
index 92a9bcb049..ada082c768 100644
--- a/hw/bsp/espressif/family.cmake
+++ b/hw/bsp/espressif/family.cmake
@@ -2,14 +2,21 @@ cmake_minimum_required(VERSION 3.5)
# Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
+string(TOUPPER ${IDF_TARGET} FAMILY_MCUS)
-if(IDF_TARGET STREQUAL "esp32s2")
- set(FAMILY_MCUS ESP32S2)
-elseif(IDF_TARGET STREQUAL "esp32s3")
- set(FAMILY_MCUS ESP32S3)
+# Device port default to Port1 for P4 (highspeed), Port0 for others (fullspeed)
+if (NOT DEFINED TUD_PORT)
+ if (IDF_TARGET STREQUAL "esp32p4")
+ set(TUD_PORT 1)
+ else ()
+ set(TUD_PORT 0)
+ endif ()
endif()
# Add example src and bsp directories
set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
+# set SDKCONFIG for each IDF Target
+set(SDKCONFIG ${CMAKE_SOURCE_DIR}/sdkconfig.${IDF_TARGET})
+
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
diff --git a/hw/bsp/f1c100s/board.h b/hw/bsp/f1c100s/board.h
deleted file mode 100644
index 0ef9a17005..0000000000
--- a/hw/bsp/f1c100s/board.h
+++ /dev/null
@@ -1 +0,0 @@
-// Nothing valuable here
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
deleted file mode 100644
index 3596e54149..0000000000
--- a/hw/bsp/f1c100s/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-MCU_DIR = hw/mcu/allwinner/f1c100s
-DEPS_SUBMODULES += hw/mcu/allwinner
-DEFINES += -D__ARM32_ARCH__=5 -D__ARM926EJS__
-
-CFLAGS += \
- -ffreestanding \
- -std=gnu99 \
- -march=armv5te \
- -mtune=arm926ej-s \
- -mfloat-abi=soft \
- -marm \
- -mno-thumb-interwork \
- -Wno-unused-parameter \
- -Wno-float-equal \
- -DCFG_TUSB_MCU=OPT_MCU_F1C100S \
- -Wno-error=cast-align \
- -Wno-error=address-of-packed-member \
- $(DEFINES)
-
-LD_FILE = hw/mcu/allwinner/f1c100s/f1c100s.ld
-# TODO may skip nanolib
-LDFLAGS += -nostdlib -lgcc -specs=nosys.specs -specs=nano.specs
-
-SRC_C += \
- src/portable/sunxi/dcd_sunxi_musb.c \
- $(MCU_DIR)/machine/sys-uart.c \
- $(MCU_DIR)/machine/exception.c \
- $(MCU_DIR)/machine/sys-clock.c \
- $(MCU_DIR)/machine/sys-copyself.c \
- $(MCU_DIR)/machine/sys-dram.c \
- $(MCU_DIR)/machine/sys-mmu.c \
- $(MCU_DIR)/machine/sys-spi-flash.c \
- $(MCU_DIR)/machine/f1c100s-intc.c \
- $(MCU_DIR)/lib/malloc.c \
- $(MCU_DIR)/lib/printf.c
-
-SRC_S += \
- $(MCU_DIR)/machine/start.S \
- $(MCU_DIR)/lib/memcpy.S \
- $(MCU_DIR)/lib/memset.S
-
-INC += \
- $(TOP)/$(MCU_DIR)/include \
- $(TOP)/$(BOARD_PATH)
-
-# flash target using xfel
-flash: flash-xfel
-
-exec: $(BUILD)/$(PROJECT).bin
- xfel ddr
- xfel write 0x80000000 $<
- xfel exec 0x80000000
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.cmake b/hw/bsp/f1c100s/boards/f1c100s/board.cmake
new file mode 100644
index 0000000000..98ed56c57e
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.cmake
@@ -0,0 +1,3 @@
+function(update_board TARGET)
+ # nothing to do
+endfunction()
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.h b/hw/bsp/f1c100s/boards/f1c100s/board.h
new file mode 100644
index 0000000000..3b56a3a57d
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.h
@@ -0,0 +1,6 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+// Nothing valuable here
+
+#endif
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.mk b/hw/bsp/f1c100s/boards/f1c100s/board.mk
new file mode 100644
index 0000000000..be830bd8c9
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.mk
@@ -0,0 +1 @@
+# nothing to do
diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/family.c
similarity index 78%
rename from hw/bsp/f1c100s/f1c100s.c
rename to hw/bsp/f1c100s/family.c
index 272b756f27..6df4a0ed8a 100644
--- a/hw/bsp/f1c100s/f1c100s.c
+++ b/hw/bsp/f1c100s/family.c
@@ -39,10 +39,9 @@ extern void sys_uart_putc(char c);
static void timer_init(void);
-void board_init(void)
-{
+void board_init(void) {
arch_local_irq_disable();
- do_init_mem_pool();
+ do_init_mem_pool();
f1c100s_intc_init();
timer_init();
printf("Timer INIT done\n");
@@ -50,42 +49,38 @@ void board_init(void)
}
// No LED, no button
-void board_led_write(bool state)
-{
-
+void board_led_write(bool state) {
+ (void) state;
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
return 0;
}
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
+ (void) buf;
+ (void) len;
return 0;
}
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
int txsize = len;
while (txsize--) {
- sys_uart_putc(*(uint8_t const*)buf);
+ sys_uart_putc(*(uint8_t const*) buf);
buf++;
}
return len;
}
-#if CFG_TUSB_OS == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
-static void timer_handler(void)
-{
- volatile uint32_t *temp_addr = (uint32_t *)(0x01C20C00 + 0x04);
+static void timer_handler(void) {
+ volatile uint32_t* temp_addr = (uint32_t*) (0x01C20C00 + 0x04);
/* clear timer */
*temp_addr |= 0x01;
@@ -95,36 +90,37 @@ static void timer_handler(void)
static void timer_init(void) {
uint32_t temp;
- volatile uint32_t *temp_addr;
+ volatile uint32_t* temp_addr;
/* reload value */
temp = 12000000 / 1000;
- temp_addr = (uint32_t *)(0x01C20C00 + 0x14);
+ temp_addr = (uint32_t*) (0x01C20C00 + 0x14);
*temp_addr = temp;
/* continuous | /2 | 24Mhz | reload*/
temp = (0x00 << 7) | (0x01 << 4) | (0x01 << 2) | (0x00 << 1);
- temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
+ temp_addr = (uint32_t*) (0x01C20C00 + 0x10);
*temp_addr &= 0xffffff00;
*temp_addr |= temp;
/* open timer irq */
temp = 0x01 << 0;
- temp_addr = (uint32_t *)(0x01C20C00);
+ temp_addr = (uint32_t*) (0x01C20C00);
*temp_addr |= temp;
/* set init value */
- temp_addr = (uint32_t *)(0x01C20C00 + 0x18);
+ temp_addr = (uint32_t*) (0x01C20C00 + 0x18);
*temp_addr = 0;
/* begin run timer */
temp = 0x01 << 0;
- temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
+ temp_addr = (uint32_t*) (0x01C20C00 + 0x10);
*temp_addr |= temp;
f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler);
f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0);
}
+
#else
static void timer_init(void) { }
#endif
diff --git a/hw/bsp/f1c100s/family.cmake b/hw/bsp/f1c100s/family.cmake
new file mode 100644
index 0000000000..0903a01431
--- /dev/null
+++ b/hw/bsp/f1c100s/family.cmake
@@ -0,0 +1,114 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/allwinner/f1c100s)
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR arm926ej-s CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS F1C100S CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ # LD_FILE and STARTUP_FILE can be defined in board.cmake
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${SDK_DIR}/f1c100s.ld)
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ if (NOT DEFINED STARTUP_FILE_GNU)
+ set(STARTUP_FILE_GNU ${SDK_DIR}/machine/start.S)
+ endif ()
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/lib/malloc.c
+ ${SDK_DIR}/lib/printf.c
+ ${SDK_DIR}/lib/memcpy.S
+ ${SDK_DIR}/lib/memset.S
+ ${SDK_DIR}/machine/sys-uart.c
+ ${SDK_DIR}/machine/exception.c
+ ${SDK_DIR}/machine/sys-clock.c
+ ${SDK_DIR}/machine/sys-copyself.c
+ ${SDK_DIR}/machine/sys-dram.c
+ ${SDK_DIR}/machine/sys-mmu.c
+ ${SDK_DIR}/machine/sys-spi-flash.c
+ ${SDK_DIR}/machine/f1c100s-intc.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ __ARM32_ARCH__=5
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}/include
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -lgcc
+ --specs=nosys.specs --specs=nano.specs
+ "LINKER:--defsym=__bss_end__=__bss_end"
+ "LINKER:--defsym=__bss_start__=__bss_start"
+ "LINKER:--defsym=end=__bss_end"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_F1C100S ${RTOS})
+ target_sources(${TARGET}-tinyusb PRIVATE
+ ${TOP}/src/portable/sunxi/dcd_sunxi_musb.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/f1c100s/family.mk b/hw/bsp/f1c100s/family.mk
new file mode 100644
index 0000000000..be416e72ee
--- /dev/null
+++ b/hw/bsp/f1c100s/family.mk
@@ -0,0 +1,58 @@
+SDK_DIR = hw/mcu/allwinner/f1c100s
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= arm926ej-s
+
+#CFLAGS += \
+# -march=armv5te \
+# -mtune=arm926ej-s \
+# -mfloat-abi=soft \
+# -marm \
+
+CFLAGS += \
+ -ffreestanding \
+ -std=gnu99 \
+ -mno-thumb-interwork \
+ -D__ARM32_ARCH__=5 \
+ -D__ARM926EJS__ \
+ -Wno-float-equal \
+ -Wno-unused-parameter \
+ -DCFG_TUSB_MCU=OPT_MCU_F1C100S \
+ -Wno-error=array-bounds \
+
+LD_FILE = ${SDK_DIR}/f1c100s.ld
+
+# TODO may skip nanolib
+LDFLAGS += \
+ -nostdlib -lgcc \
+ --specs=nosys.specs --specs=nano.specs \
+
+SRC_C += \
+ src/portable/sunxi/dcd_sunxi_musb.c \
+ ${SDK_DIR}/machine/sys-uart.c \
+ ${SDK_DIR}/machine/exception.c \
+ ${SDK_DIR}/machine/sys-clock.c \
+ ${SDK_DIR}/machine/sys-copyself.c \
+ ${SDK_DIR}/machine/sys-dram.c \
+ ${SDK_DIR}/machine/sys-mmu.c \
+ ${SDK_DIR}/machine/sys-spi-flash.c \
+ ${SDK_DIR}/machine/f1c100s-intc.c \
+ ${SDK_DIR}/lib/malloc.c \
+ ${SDK_DIR}/lib/printf.c
+
+SRC_S += \
+ ${SDK_DIR}/machine/start.S \
+ ${SDK_DIR}/lib/memcpy.S \
+ ${SDK_DIR}/lib/memset.S
+
+INC += \
+ $(TOP)/${SDK_DIR}/include \
+ $(TOP)/$(BOARD_PATH)
+
+# flash target using xfel
+flash: flash-xfel
+
+exec: $(BUILD)/$(PROJECT).bin
+ xfel ddr
+ xfel write 0x80000000 $<
+ xfel exec 0x80000000
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 5f06536462..aa5e037d1c 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -6,6 +6,8 @@ include(CMakePrintHelpers)
set(TOP "${CMAKE_CURRENT_LIST_DIR}/../..")
get_filename_component(TOP ${TOP} ABSOLUTE)
+set(UF2CONV_PY ${TOP}/tools/uf2/utils/uf2conv.py)
+
#-------------------------------------------------------------
# Toolchain
# Can be changed via -DTOOLCHAIN=gcc|iar or -DCMAKE_C_COMPILER=
@@ -67,6 +69,10 @@ if (NOT FAMILY STREQUAL rp2040)
endif()
endif()
+if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED)
+ set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1)
+endif()
+
set(WARNING_FLAGS_GNU
-Wall
-Wextra
@@ -138,7 +144,6 @@ function(family_filter RESULT DIR)
endif()
endfunction()
-
function(family_add_subdirectory DIR)
family_filter(SHOULD_ADD "${DIR}")
if (SHOULD_ADD)
@@ -146,13 +151,11 @@ function(family_add_subdirectory DIR)
endif()
endfunction()
-
function(family_get_project_name OUTPUT_NAME DIR)
get_filename_component(SHORT_NAME ${DIR} NAME)
set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
endfunction()
-
function(family_initialize_project PROJECT DIR)
# set output suffix to .elf (skip espressif and rp2040)
if(NOT FAMILY STREQUAL "espressif" AND NOT FAMILY STREQUAL "rp2040")
@@ -166,7 +169,6 @@ function(family_initialize_project PROJECT DIR)
endif()
endfunction()
-
#-------------------------------------------------------------
# Common Target Configure
# Most families use these settings except rp2040 and espressif
@@ -192,7 +194,6 @@ function(family_add_rtos TARGET RTOS)
endif ()
endfunction()
-
# Add common configuration to example
function(family_configure_common TARGET RTOS)
family_add_rtos(${TARGET} ${RTOS})
@@ -203,20 +204,17 @@ function(family_configure_common TARGET RTOS)
BOARD_${BOARD_UPPER}
)
- # run size after build
- find_program(SIZE_EXE ${CMAKE_SIZE})
- if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND)
- add_custom_command(TARGET ${TARGET} POST_BUILD
- COMMAND ${SIZE_EXE} $
- )
- endif ()
- # Add warnings flags
+ # compile define from command line
+ if(DEFINED CFLAGS_CLI)
+ target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI})
+ endif()
+
target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}})
# Generate linker map file
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map")
- if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+ if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED)
target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
endif ()
elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
@@ -233,7 +231,6 @@ function(family_configure_common TARGET RTOS)
# LOGGER option
if (DEFINED LOGGER)
target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
-
# Add segger rtt to example
if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
if (NOT TARGET segger_rtt)
@@ -244,8 +241,15 @@ function(family_configure_common TARGET RTOS)
target_link_libraries(${TARGET} PUBLIC segger_rtt)
endif ()
endif ()
-endfunction()
+ # run size after build
+ find_program(SIZE_EXE ${CMAKE_SIZE})
+ if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND)
+ add_custom_command(TARGET ${TARGET} POST_BUILD
+ COMMAND ${SIZE_EXE} $
+ )
+ endif ()
+endfunction()
# Add tinyusb to example
function(family_add_tinyusb TARGET OPT_MCU RTOS)
@@ -287,7 +291,6 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS)
endfunction()
-
# Add bin/hex output
function(family_add_bin_hex TARGET)
add_custom_command(TARGET ${TARGET} POST_BUILD
@@ -296,6 +299,13 @@ function(family_add_bin_hex TARGET)
VERBATIM)
endfunction()
+# Add uf2 output
+function(family_add_uf2 TARGET FAMILY_ID)
+ set(BIN_FILE $/${TARGET}.hex)
+ add_custom_command(TARGET ${TARGET} POST_BUILD
+ COMMAND python ${UF2CONV_PY} -f ${FAMILY_ID} -c -o $/${TARGET}.uf2 ${BIN_FILE}
+ VERBATIM)
+endfunction()
#----------------------------------
# Example Target Configure (Default rule)
@@ -354,7 +364,7 @@ function(family_add_default_example_warnings TARGET)
)
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
- if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+ if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED)
target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
endif()
@@ -385,6 +395,15 @@ function(family_flash_jlink TARGET)
set(JLINKEXE JLinkExe)
endif ()
+ if (NOT DEFINED JLINK_IF)
+ set(JLINK_IF swd)
+ endif ()
+
+ if (NOT DEFINED JLINK_OPTION)
+ set(JLINK_OPTION "")
+ endif ()
+ separate_arguments(OPTION_LIST UNIX_COMMAND ${JLINK_OPTION})
+
file(GENERATE
OUTPUT $/${TARGET}.jlink
CONTENT "halt
@@ -396,8 +415,15 @@ exit"
add_custom_target(${TARGET}-jlink
DEPENDS ${TARGET}
- COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink
+ COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink
+ VERBATIM
)
+
+ # optional flash post build
+# add_custom_command(TARGET ${TARGET} POST_BUILD
+# COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink
+# VERBATIM
+# )
endfunction()
@@ -414,22 +440,84 @@ function(family_flash_stlink TARGET)
endfunction()
+# Add flash st-flash target
+function(family_flash_stflash TARGET)
+ if (NOT DEFINED ST_FLASH)
+ set(ST_FLASH st-flash)
+ endif ()
+
+ add_custom_target(${TARGET}-stflash
+ DEPENDS ${TARGET}
+ COMMAND ${ST_FLASH} write $/${TARGET}.bin 0x8000000
+ )
+endfunction()
+
+
# Add flash openocd target
-function(family_flash_openocd TARGET CLI_OPTIONS)
+function(family_flash_openocd TARGET)
if (NOT DEFINED OPENOCD)
set(OPENOCD openocd)
endif ()
- separate_arguments(CLI_OPTIONS_LIST UNIX_COMMAND ${CLI_OPTIONS})
+ if (NOT DEFINED OPENOCD_OPTION2)
+ set(OPENOCD_OPTION2 "")
+ endif ()
+
+ separate_arguments(OPTION_LIST UNIX_COMMAND ${OPENOCD_OPTION})
+ separate_arguments(OPTION_LIST2 UNIX_COMMAND ${OPENOCD_OPTION2})
# note skip verify since it has issue with rp2040
add_custom_target(${TARGET}-openocd
DEPENDS ${TARGET}
- COMMAND ${OPENOCD} ${CLI_OPTIONS_LIST} -c "program $ reset exit"
+ COMMAND ${OPENOCD} -c "tcl_port disabled" -c "gdb_port disabled" ${OPTION_LIST} -c init -c halt -c "program $" -c reset ${OPTION_LIST2} -c exit
VERBATIM
)
endfunction()
+
+# Add flash openocd-wch target
+# compiled from https://github.com/hathach/riscv-openocd-wch or https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
+function(family_flash_openocd_wch TARGET)
+ if (NOT DEFINED OPENOCD)
+ set(OPENOCD $ENV{HOME}/app/riscv-openocd-wch/src/openocd)
+ endif ()
+
+ family_flash_openocd(${TARGET})
+endfunction()
+
+
+# Add flash openocd adi (Analog Devices) target
+# included with msdk or compiled from release branch of https://github.com/analogdevicesinc/openocd
+function(family_flash_openocd_adi TARGET)
+ if (DEFINED $ENV{MAXIM_PATH})
+ # use openocd from msdk
+ set(OPENOCD ENV{MAXIM_PATH}/Tools/OpenOCD/openocd)
+ set(OPENOCD_OPTION2 "-s ENV{MAXIM_PATH}/Tools/OpenOCD/scripts")
+ else()
+ # compiled from source
+ if (NOT DEFINED OPENOCD_ADI_PATH)
+ set(OPENOCD_ADI_PATH $ENV{HOME}/app/openocd_adi)
+ endif ()
+ set(OPENOCD ${OPENOCD_ADI_PATH}/src/openocd)
+ set(OPENOCD_OPTION2 "-s ${OPENOCD_ADI_PATH}/tcl")
+ endif ()
+
+ family_flash_openocd(${TARGET})
+endfunction()
+
+# Add flash with https://github.com/ch32-rs/wlink
+function(family_flash_wlink_rs TARGET)
+ if (NOT DEFINED WLINK_RS)
+ set(WLINK_RS wlink)
+ endif ()
+
+ add_custom_target(${TARGET}-wlink-rs
+ DEPENDS ${TARGET}
+ COMMAND ${WLINK_RS} flash $
+ )
+endfunction()
+
+
# Add flash pycod target
function(family_flash_pyocd TARGET)
if (NOT DEFINED PYOC)
@@ -443,6 +531,15 @@ function(family_flash_pyocd TARGET)
endfunction()
+# Flash with UF2
+function(family_flash_uf2 TARGET FAMILY_ID)
+ add_custom_target(${TARGET}-uf2
+ DEPENDS ${TARGET}
+ COMMAND python ${UF2CONV_PY} -f ${FAMILY_ID} --deploy $/${TARGET}.uf2
+ )
+endfunction()
+
+
# Add flash teensy_cli target
function(family_flash_teensy TARGET)
if (NOT DEFINED TEENSY_CLI)
@@ -455,6 +552,7 @@ function(family_flash_teensy TARGET)
)
endfunction()
+
# Add flash using NXP's LinkServer (redserver)
# https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
function(family_flash_nxplink TARGET)
@@ -500,6 +598,21 @@ function(family_flash_msp430flasher TARGET)
)
endfunction()
+
+function(family_flash_uniflash TARGET)
+ if (NOT DEFINED DSLITE)
+ set(DSLITE dslite.sh)
+ endif ()
+
+ separate_arguments(OPTION_LIST UNIX_COMMAND ${UNIFLASH_OPTION})
+
+ add_custom_target(${TARGET}-uniflash
+ DEPENDS ${TARGET}
+ COMMAND ${DSLITE} ${UNIFLASH_OPTION} -f $/${TARGET}.hex
+ VERBATIM
+ )
+endfunction()
+
#----------------------------------
# Family specific
#----------------------------------
diff --git a/hw/bsp/fomu/boards/fomu/board.cmake b/hw/bsp/fomu/boards/fomu/board.cmake
new file mode 100644
index 0000000000..9f56820422
--- /dev/null
+++ b/hw/bsp/fomu/boards/fomu/board.cmake
@@ -0,0 +1,4 @@
+function(update_board TARGET)
+# target_compile_definitions(${TARGET} PUBLIC
+# )
+endfunction()
diff --git a/hw/bsp/fomu/dfu.py b/hw/bsp/fomu/dfu.py
old mode 100644
new mode 100755
index 32479350c5..8383852e3a
--- a/hw/bsp/fomu/dfu.py
+++ b/hw/bsp/fomu/dfu.py
@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/env python3
# Written by Antonio Galea - 2010/11/18
# Updated for DFU 1.1 by Sean Cross - 2020/03/31
diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/family.c
similarity index 99%
rename from hw/bsp/fomu/fomu.c
rename to hw/bsp/fomu/family.c
index d155b743dc..ccf2b12f49 100644
--- a/hw/bsp/fomu/fomu.c
+++ b/hw/bsp/fomu/family.c
@@ -26,10 +26,11 @@
#include
#include
-#include "../board_api.h"
#include "csr.h"
#include "irq.h"
+#include "bsp/board_api.h"
+
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
diff --git a/hw/bsp/fomu/family.cmake b/hw/bsp/fomu/family.cmake
new file mode 100644
index 0000000000..8d5ab144c4
--- /dev/null
+++ b/hw/bsp/fomu/family.cmake
@@ -0,0 +1,91 @@
+include_guard()
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR rv32i-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS VALENTYUSB_EPTRI CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/fomu.ld)
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ if (NOT DEFINED STARTUP_FILE_GNU)
+ set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/crt0-vexriscv.S)
+ endif ()
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/include
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ message(FATAL_ERROR "Clang is not supported for MSP432E4")
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_VALENTYUSB_EPTRI ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/valentyusb/eptri/dcd_eptri.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_add_bin_hex(${TARGET})
+endfunction()
diff --git a/hw/bsp/fomu/family.mk b/hw/bsp/fomu/family.mk
index f8a3c9ebf7..69a5469642 100644
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@@ -1,14 +1,15 @@
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE = riscv-none-embed-
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE = riscv-none-elf-
+
+CPU_CORE ?= rv32i-ilp32
CFLAGS += \
-flto \
- -march=rv32i \
- -mabi=ilp32 \
- -nostdlib \
-DCFG_TUSB_MCU=OPT_MCU_VALENTYUSB_EPTRI
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+LDFLAGS_GCC += \
+ -nostdlib \
+ --specs=nosys.specs --specs=nano.specs \
# All source paths should be relative to the top level.
LD_FILE = $(FAMILY_PATH)/fomu.ld
diff --git a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.cmake b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.cmake
new file mode 100644
index 0000000000..403ac08cf1
--- /dev/null
+++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.cmake
@@ -0,0 +1,13 @@
+set(JLINK_DEVICE gd32vf103cbt6)
+
+set(SDK_BSP_DIR ${SOC_DIR}/Board/gd32vf103c_longan_nano)
+set(LD_FILE_GNU ${SDK_BSP_DIR}/Source/GCC/gcc_gd32vf103xb_flashxip.ld)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${SDK_BSP_DIR}/Source/gd32vf103c_longan_nano.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ ${SDK_BSP_DIR}/Include
+ )
+endfunction()
diff --git a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
index 3b89444528..fc49b7317f 100644
--- a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
+++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
@@ -10,4 +10,3 @@ INC += $(TOP)/$(LONGAN_NANO_SDK_BSP)/Include
# Longan Nano 128k ROM 32k RAM
JLINK_DEVICE = gd32vf103cbt6
-#JLINK_DEVICE = gd32vf103c8t6 # Longan Nano Lite 64k ROM 20k RAM
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index 27d7e87bb7..d4a819fb3a 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -24,11 +24,11 @@
* This file is part of the TinyUSB stack.
*/
-#include "board.h"
#include "drv_usb_hw.h"
#include "drv_usb_dev.h"
-#include "../board_api.h"
+#include "bsp/board_api.h"
+#include "board.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake
new file mode 100644
index 0000000000..5f4a3da8d7
--- /dev/null
+++ b/hw/bsp/gd32vf103/family.cmake
@@ -0,0 +1,119 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/gd/nuclei-sdk)
+set(SOC_DIR ${SDK_DIR}/SoC/gd32vf103)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS GD32VF103 CACHE INTERNAL "")
+
+set(JLINK_IF jtag)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ if (NOT DEFINED LD_FILE_GNU)
+ message(FATAL_ERROR "LD_FILE_GNU is not defined")
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ if (NOT DEFINED STARTUP_FILE_GNU)
+ set(STARTUP_FILE_GNU
+ ${SOC_DIR}/Common/Source/GCC/startup_gd32vf103.S
+ ${SOC_DIR}/Common/Source/GCC/intexc_gd32vf103.S
+ )
+ endif ()
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_gd32vf103.c
+ ${SOC_DIR}/Common/Source/Drivers/gd32vf103_rcu.c
+ ${SOC_DIR}/Common/Source/Drivers/gd32vf103_gpio.c
+ ${SOC_DIR}/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c
+ ${SOC_DIR}/Common/Source/Drivers/gd32vf103_usart.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}/NMSIS/Core/Include
+ ${SOC_DIR}/Common/Include
+ ${SOC_DIR}/Common/Include/Usb
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ DOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -mcmodel=medlow
+ -mstrict-align
+ )
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ message(FATAL_ERROR "Clang is not supported for MSP432E4")
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ ${SOC_DIR}/Common/Source/Stubs/sbrk.c
+ ${SOC_DIR}/Common/Source/Stubs/close.c
+ ${SOC_DIR}/Common/Source/Stubs/isatty.c
+ ${SOC_DIR}/Common/Source/Stubs/fstat.c
+ ${SOC_DIR}/Common/Source/Stubs/lseek.c
+ ${SOC_DIR}/Common/Source/Stubs/read.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 1725559c40..48588886c7 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -4,12 +4,11 @@
# Toolchain from https://nucleisys.com/download.php
#CROSS_COMPILE ?= riscv-nuclei-elf-
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE ?= riscv-none-embed-
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
# Submodules
NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
-DEPS_SUBMODULES += $(NUCLEI_SDK)
# Nuclei-SDK paths
GD32VF103_SDK_SOC = $(NUCLEI_SDK)/SoC/gd32vf103
@@ -18,12 +17,9 @@ LIBC_STUBS = $(GD32VF103_SDK_SOC)/Common/Source/Stubs
STARTUP_ASM = $(GD32VF103_SDK_SOC)/Common/Source/GCC
include $(TOP)/$(BOARD_PATH)/board.mk
-
-SKIP_NANOLIB = 1
+CPU_CORE ?= rv32imac-ilp32
CFLAGS += \
- -march=rv32imac \
- -mabi=ilp32 \
-mcmodel=medlow \
-mstrict-align \
-nostdlib -nostartfiles \
@@ -35,10 +31,10 @@ CFLAGS += -Wno-error=unused-parameter
SRC_C += \
src/portable/synopsys/dwc2/dcd_dwc2.c \
- $(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
- $(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
+ $(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
+ $(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
$(LIBC_STUBS)/sbrk.c \
$(LIBC_STUBS)/close.c \
$(LIBC_STUBS)/isatty.c \
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
index fd335cdf55..f70a5f923a 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
@@ -1,6 +1,7 @@
set(MCU_VARIANT MIMXRT1062)
set(JLINK_DEVICE MIMXRT1062xxx6A)
+#set(JLINK_OPTION "-USB 000726129165")
set(PYOCD_TARGET mimxrt1060)
set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index c9c4918ef4..6087ee37db 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -40,23 +40,12 @@
#include "fsl_iomuxc.h"
#include "fsl_clock.h"
#include "fsl_lpuart.h"
+#include "fsl_ocotp.h"
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
-#if defined(BOARD_TUD_RHPORT) && CFG_TUD_ENABLED
- #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
-#else
- #define PORT_SUPPORT_DEVICE(_n) 0
-#endif
-
-#if defined(BOARD_TUH_RHPORT) && CFG_TUH_ENABLED
- #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n)
-#else
- #define PORT_SUPPORT_HOST(_n) 0
-#endif
-
// needed by fsl_flexspi_nor_boot
TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 };
@@ -155,23 +144,11 @@ void board_init(void)
// USB Interrupt Handler
//--------------------------------------------------------------------+
void USB_OTG1_IRQHandler(void) {
- #if PORT_SUPPORT_DEVICE(0)
- tud_int_handler(0);
- #endif
-
- #if PORT_SUPPORT_HOST(0)
- tuh_int_handler(0, true);
- #endif
+ tusb_int_handler(0, true);
}
void USB_OTG2_IRQHandler(void) {
- #if PORT_SUPPORT_DEVICE(1)
- tud_int_handler(1);
- #endif
-
- #if PORT_SUPPORT_HOST(1)
- tuh_int_handler(1, true);
- #endif
+ tusb_int_handler(1, true);
}
//--------------------------------------------------------------------+
@@ -186,6 +163,29 @@ uint32_t board_button_read(void) {
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ (void) max_len;
+
+ #if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL
+ OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk));
+ #else
+ OCOTP_Init(OCOTP, 0u);
+ #endif
+
+ // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info)
+ // into 8 bit wide destination, avoiding punning.
+ for (int i = 0; i < 4; ++i) {
+ uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1);
+ for (int j = 0; j < 4; j++) {
+ id[i*4+j] = wr & 0xff;
+ wr >>= 8;
+ }
+ }
+ OCOTP_Deinit(OCOTP);
+
+ return 16;
+}
+
int board_uart_read(uint8_t* buf, int len) {
int count = 0;
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index f4d7378a5f..d917e9777e 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -44,6 +44,7 @@ function(add_board_target BOARD_TARGET)
${SDK_DIR}/drivers/igpio/fsl_gpio.c
${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+ ${SDK_DIR}/drivers/ocotp/fsl_ocotp.c
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT_WITH_CORE}.c
${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
@@ -75,6 +76,7 @@ function(add_board_target BOARD_TARGET)
${SDK_DIR}/drivers/igpio
${SDK_DIR}/drivers/lpspi
${SDK_DIR}/drivers/lpuart
+ ${SDK_DIR}/drivers/ocotp
)
update_board(${BOARD_TARGET})
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index bde4c4ba6e..f00afb6a43 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -50,7 +50,8 @@ SRC_C += \
$(SDK_DIR)/drivers/common/fsl_common.c \
$(SDK_DIR)/drivers/common/fsl_common_arm.c \
$(SDK_DIR)/drivers/igpio/fsl_gpio.c \
- $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
+ $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c \
+ $(SDK_DIR)/drivers/ocotp/fsl_ocotp.c \
# Optional drivers: only available for some mcus: rt1160, rt1170
ifneq (,$(wildcard ${TOP}/${MCU_DIR}/drivers/fsl_dcdc.c))
@@ -68,7 +69,8 @@ INC += \
$(TOP)/$(MCU_DIR)/drivers \
$(TOP)/$(SDK_DIR)/drivers/common \
$(TOP)/$(SDK_DIR)/drivers/igpio \
- $(TOP)/$(SDK_DIR)/drivers/lpuart
+ $(TOP)/$(SDK_DIR)/drivers/lpuart \
+ $(TOP)/$(SDK_DIR)/drivers/ocotp \
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT_WITH_CORE).S
diff --git a/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..e6604d360f
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,169 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 2
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<SOPT5 = ((SIM->SOPT5 &
+ /* Mask bits to zero which are setting */
+ (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
+ /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
+ | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
+ /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
+ | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
+
+ BOARD_BootClockRUN();
+ SystemCoreClockUpdate();
+ CLOCK_SetLpuart0Clock(1);
+}
#endif /* BOARD_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
index e74000827f..86eb42ef85 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
@@ -48,7 +48,7 @@ board: FRDM-K32L2B
* Variables
******************************************************************************/
/* System clock frequency. */
-extern uint32_t SystemCoreClock;
+//extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c
deleted file mode 100644
index 3f99b0cbdc..0000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- * Copyright (c) 2020, Koji Kitayama
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include "board.h"
-#include "fsl_gpio.h"
-#include "fsl_port.h"
-#include "fsl_clock.h"
-#include "fsl_lpuart.h"
-
-#include "clock_config.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
- tud_int_handler(0);
-}
-
-void board_init(void)
-{
- /* Enable port clocks for UART/LED/Button pins */
- CLOCK_EnableClock(UART_PIN_CLOCK);
- CLOCK_EnableClock(LED_PIN_CLOCK);
- CLOCK_EnableClock(BUTTON_PIN_CLOCK);
-
- gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
- GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
- PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio);
-
- gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
- GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
- const port_pin_config_t BUTTON_CFG = {
- kPORT_PullUp,
- kPORT_FastSlewRate,
- kPORT_PassiveFilterDisable,
- kPORT_LowDriveStrength,
- kPORT_MuxAsGpio
- };
- PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
-
- /* PORTA1 (pin 23) is configured as LPUART0_RX */
- PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
- /* PORTA2 (pin 24) is configured as LPUART0_TX */
- PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);
-
- SIM->SOPT5 = ((SIM->SOPT5 &
- /* Mask bits to zero which are setting */
- (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
- /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
- | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
- /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
- | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
-
- BOARD_BootClockRUN();
- SystemCoreClockUpdate();
- CLOCK_SetLpuart0Clock(1);
-
-#if CFG_TUSB_OS == OPT_OS_NONE
- // 1ms tick timer
- SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
- // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
- NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
- lpuart_config_t uart_config;
- LPUART_GetDefaultConfig(&uart_config);
- uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
- uart_config.enableTx = true;
- uart_config.enableRx = true;
- LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
-
- // USB
- CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
- GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
- return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
- LPUART_ReadBlocking(UART_PORT, buf, len);
- return len;
-}
-
-int board_uart_write(void const * buf, int len)
-{
- LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
- return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
- system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
- return system_ticks;
-}
-#endif
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.cmake b/hw/bsp/kinetis_k32l2/boards/kuiic/board.cmake
new file mode 100644
index 0000000000..cf14000ac2
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT K32L2B31A)
+
+set(JLINK_DEVICE K32L2B31xxxxA)
+set(PYOCD_TARGET K32L2B)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/kuiic.ld)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_K32L2B31VLH0A
+ )
+endfunction()
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.h b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h
index 1e2d4f18be..ec37023766 100644
--- a/hw/bsp/kinetis_k32l2/boards/kuiic/board.h
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h
@@ -30,6 +30,8 @@
#include "fsl_device_registers.h"
+#define USB_CLOCK_SOURCE kCLOCK_UsbSrcIrc48M
+
// LED
#define LED_PIN_CLOCK kCLOCK_PortA
#define LED_GPIO GPIOA
@@ -42,4 +44,22 @@
#define UART_PIN_RX 3u
#define UART_PIN_TX 0u
+#define UART_CLOCK_SOURCE_HZ CLOCK_GetFreq(kCLOCK_McgIrc48MClk)
+
+static inline void BOARD_InitBootPins(void) {
+ /* PORTC3 is configured as LPUART0_RX */
+ PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3);
+ /* PORTA2 (pin 24) is configured as LPUART0_TX */
+ PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
+
+ SIM->SOPT5 = ((SIM->SOPT5 &
+ /* Mask bits to zero which are setting */
+ (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK)))
+ /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
+ | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX)
+ /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
+ | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX));
+ CLOCK_SetLpuart1Clock(1);
+}
+
#endif /* BOARD_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
index fc5bdeec81..2bc5b1e343 100644
--- a/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
@@ -6,7 +6,7 @@ CFLAGS += -DCPU_K32L2B31VLH0A
CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/K32L2B31xxxxA_flash.ld
+LD_FILE = $(BOARD_PATH)/kuiic.ld
# For flash-jlink target
JLINK_DEVICE = K32L2B31xxxxA
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.c b/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.c
new file mode 100644
index 0000000000..c1a6d1a8d0
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.c
@@ -0,0 +1,39 @@
+#include "clock_config.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+// extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
+ .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
+ .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+ .ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
+ .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+ .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+ .hircEnableInNotHircMode = true, /* HIRC source is enabled */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+ .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
+ .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+};
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Set the system clock dividers in SIM to safe value. */
+ CLOCK_SetSimSafeDivs();
+ /* Set MCG to HIRC mode. */
+ CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
+ /* Set the clock configuration in SIM module. */
+ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.h b/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.h
new file mode 100644
index 0000000000..920cad98f8
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/clock_config.h
@@ -0,0 +1,14 @@
+#ifndef CLOCK_CONFIG_H
+#define CLOCK_CONFIG_H
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
+#define SOPT5_LPUART1RXSRC_LPUART_RX 0x00u /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */
+#define SOPT5_LPUART1TXSRC_LPUART_TX 0x00u /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
+
+void BOARD_BootClockRUN(void);
+
+#endif
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
deleted file mode 100644
index b83d5c820e..0000000000
--- a/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- * Copyright (c) 2020, Koji Kitayama
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include "board.h"
-#include "fsl_smc.h"
-#include "fsl_gpio.h"
-#include "fsl_port.h"
-#include "fsl_clock.h"
-#include "fsl_lpuart.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
-#define SOPT5_LPUART1RXSRC_LPUART_RX 0x00u /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */
-#define SOPT5_LPUART1TXSRC_LPUART_TX 0x00u /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-// extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- * Variables for BOARD_BootClockRUN configuration
- ******************************************************************************/
-const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
- .outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
- .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
- .ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
- .fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
- .lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
- .hircEnableInNotHircMode = true, /* HIRC source is enabled */
-};
-const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
- .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
- .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
-};
-
-/*******************************************************************************
- * Code for BOARD_BootClockRUN configuration
- ******************************************************************************/
-void BOARD_BootClockRUN(void)
-{
- /* Set the system clock dividers in SIM to safe value. */
- CLOCK_SetSimSafeDivs();
- /* Set MCG to HIRC mode. */
- CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
- /* Set the clock configuration in SIM module. */
- CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
- /* Set SystemCoreClock variable. */
- SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
-}
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
- tud_int_handler(0);
-}
-
-void board_init(void)
-{
- /* Enable port clocks for GPIO pins */
- CLOCK_EnableClock(kCLOCK_PortA);
- CLOCK_EnableClock(kCLOCK_PortB);
- CLOCK_EnableClock(kCLOCK_PortC);
- CLOCK_EnableClock(kCLOCK_PortD);
- CLOCK_EnableClock(kCLOCK_PortE);
-
-
- gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 };
- GPIO_PinInit(GPIOA, 1U, &led_config);
- PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio);
- led_config.outputLogic = 0;
- GPIO_PinInit(GPIOA, 2U, &led_config);
- PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio);
-
-#ifdef BUTTON_PIN
- gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
- GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
- const port_pin_config_t BUTTON_CFG = {
- kPORT_PullUp,
- kPORT_FastSlewRate,
- kPORT_PassiveFilterDisable,
- kPORT_LowDriveStrength,
- kPORT_MuxAsGpio
- };
- PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
-#endif
-
- /* PORTC3 is configured as LPUART0_RX */
- PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3);
- /* PORTA2 (pin 24) is configured as LPUART0_TX */
- PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
-
- SIM->SOPT5 = ((SIM->SOPT5 &
- /* Mask bits to zero which are setting */
- (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK)))
- /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
- | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX)
- /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
- | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX));
-
- BOARD_BootClockRUN();
- SystemCoreClockUpdate();
- CLOCK_SetLpuart1Clock(1);
-
-#if CFG_TUSB_OS == OPT_OS_NONE
- // 1ms tick timer
- SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
- // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
- NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
- lpuart_config_t uart_config;
- LPUART_GetDefaultConfig(&uart_config);
- uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
- uart_config.enableTx = true;
- uart_config.enableRx = true;
- LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
-
- // USB
- CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
- if (state) {
- LED_GPIO->PDDR |= GPIO_FIT_REG((1UL << LED_PIN));
- } else {
- LED_GPIO->PDDR &= GPIO_FIT_REG(~(1UL << LED_PIN));
- }
-// GPIO_PinWrite(GPIOA, 1, state ? LED_STATE_ON : (1-LED_STATE_ON) );
-// GPIO_PinWrite(GPIOA, 2, state ? (1-LED_STATE_ON) : LED_STATE_ON );
-}
-
-uint32_t board_button_read(void)
-{
-#ifdef BUTTON_PIN
- return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
-#else
- return 0;
-#endif
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
- LPUART_ReadBlocking(UART_PORT, buf, len);
- return len;
-}
-
-int board_uart_write(void const * buf, int len)
-{
- LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
- return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
- system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
- return system_ticks;
-}
-#endif
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.ld
similarity index 100%
rename from hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld
rename to hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.ld
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis_k32l2/family.c
similarity index 60%
rename from hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
rename to hw/bsp/kinetis_k32l2/family.c
index 39783b7e1d..92f5ba6d3a 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
+++ b/hw/bsp/kinetis_k32l2/family.c
@@ -25,77 +25,57 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board_api.h"
-#include "board.h"
#include "fsl_gpio.h"
#include "fsl_port.h"
#include "fsl_clock.h"
#include "fsl_lpuart.h"
#include "clock_config.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
+void USB0_IRQHandler(void) {
tud_int_handler(0);
}
-void board_init(void)
-{
- /* Enable port clocks for UART/LED/Button pins */
- CLOCK_EnableClock(UART_PIN_CLOCK);
- CLOCK_EnableClock(LED_PIN_CLOCK);
- CLOCK_EnableClock(BUTTON_PIN_CLOCK);
+void board_init(void) {
+ /* Enable port clocks for GPIO pins */
+ CLOCK_EnableClock(kCLOCK_PortA);
+ CLOCK_EnableClock(kCLOCK_PortB);
+ CLOCK_EnableClock(kCLOCK_PortC);
+ CLOCK_EnableClock(kCLOCK_PortD);
+ CLOCK_EnableClock(kCLOCK_PortE);
+
+ BOARD_InitBootPins();
+ BOARD_BootClockRUN();
+ SystemCoreClockUpdate();
- gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
+ gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0};
GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio);
- gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
+#ifdef BUTTON_PIN
+ gpio_pin_config_t button_config = {kGPIO_DigitalInput, 0};
GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
const port_pin_config_t BUTTON_CFG = {
- kPORT_PullUp,
- kPORT_FastSlewRate,
- kPORT_PassiveFilterDisable,
- kPORT_OpenDrainDisable,
- kPORT_LowDriveStrength,
- kPORT_MuxAsGpio,
- kPORT_UnlockRegister
+ kPORT_PullUp,
+ kPORT_FastSlewRate,
+ kPORT_PassiveFilterDisable,
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+ kPORT_OpenDrainDisable,
+#endif
+ kPORT_LowDriveStrength,
+ kPORT_MuxAsGpio,
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+ kPORT_UnlockRegister
+#endif
};
PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
-
- /*
- Enable LPUART0 clock and configure port pins.
- FIR clock is being used so the USB examples work.
- */
- PCC_LPUART0 = 0U; /* Clock must be off to set PCS */
- PCC_LPUART0 = PCC_CLKCFG_PCS( 3U ); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */
- PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U ); /* Enable LPUART */
-
- /* PORTB16 (pin 62) is configured as LPUART0_RX */
- gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 };
- GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx);
- const port_pin_config_t UART_CFG = {
- kPORT_PullUp,
- kPORT_FastSlewRate,
- kPORT_PassiveFilterDisable,
- kPORT_OpenDrainDisable,
- kPORT_LowDriveStrength,
- kPORT_MuxAsGpio,
- kPORT_UnlockRegister
- };
- PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG);
- PORT_SetPinMux( UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3);
-
- /* PORTB17 (pin 63) is configured as LPUART0_TX */
- gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 };
- GPIO_PinInit( UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx);
- PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3);
-
- BOARD_BootClockRUN();
- SystemCoreClockUpdate();
+#endif
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
@@ -110,28 +90,29 @@ void board_init(void)
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
uart_config.enableTx = true;
uart_config.enableRx = true;
- LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk));
+ LPUART_Init(UART_PORT, &uart_config, UART_CLOCK_SOURCE_HZ);
// USB
- CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U);
+ CLOCK_EnableUsbfs0Clock(USB_CLOCK_SOURCE, 48000000U);
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
- GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+ GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
+#ifdef BUTTON_PIN
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#else
+ return 0;
+#endif
}
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
#if 0 /*
Use this version if want the LED to blink during BOARD=board_test,
without having to hit a key.
@@ -151,21 +132,39 @@ int board_uart_read(uint8_t* buf, int len)
#endif
}
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
return len;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
system_ticks++;
}
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
+
+#endif
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+
+TU_ATTR_UNUSED void _start(void) {
+ // called by startup code
+ main();
+ while (1) {}
+}
+
+#ifdef __clang__
+void _exit (int __status) {
+ while (1) {}
+}
+#endif
+
#endif
diff --git a/hw/bsp/kinetis_k32l2/family.cmake b/hw/bsp/kinetis_k32l2/family.cmake
new file mode 100644
index 0000000000..406ae99d3b
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/family.cmake
@@ -0,0 +1,112 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS KINETIS_K32L CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ # LD_FILE and STARTUP_FILE can be defined in board.cmake
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+ set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+ ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ __STARTUP_CLEAR_BSS
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ ${SDK_DIR}/devices/${MCU_VARIANT}
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+ ${SDK_DIR}/drivers/common
+ ${SDK_DIR}/drivers/gpio
+ ${SDK_DIR}/drivers/lpuart
+ ${SDK_DIR}/drivers/port
+ ${SDK_DIR}/drivers/smc
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ --specs=nosys.specs --specs=nano.specs
+ -nostartfiles
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K32L ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/nxp/khci/dcd_khci.c
+ ${TOP}/src/portable/nxp/khci/hcd_khci.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+
+ if (DEFINED TEENSY_MCU)
+ family_add_bin_hex(${TARGET})
+ family_flash_teensy(${TARGET})
+ endif ()
+endfunction()
diff --git a/hw/bsp/kinetis_k32l2/family.mk b/hw/bsp/kinetis_k32l2/family.mk
index 0bfd57d29e..e18348d4d3 100644
--- a/hw/bsp/kinetis_k32l2/family.mk
+++ b/hw/bsp/kinetis_k32l2/family.mk
@@ -1,6 +1,5 @@
UF2_FAMILY_ID = 0x7f83e793
SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
MCU_DIR = $(SDK_DIR)/devices/$(MCU)
include $(TOP)/$(BOARD_PATH)/board.mk
@@ -9,7 +8,9 @@ CPU_CORE ?= cortex-m0plus
CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32L
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+LDFLAGS_GCC += \
+ -nostartfiles \
+ -specs=nosys.specs -specs=nano.specs
SRC_C += \
src/portable/nxp/khci/dcd_khci.c \
@@ -25,10 +26,10 @@ INC += \
$(TOP)/$(MCU_DIR) \
$(TOP)/$(MCU_DIR)/project_template \
$(TOP)/$(MCU_DIR)/drivers \
- $(TOP)/$(SDK_DIR)/drivers/smc \
$(TOP)/$(SDK_DIR)/drivers/common \
$(TOP)/$(SDK_DIR)/drivers/gpio \
- $(TOP)/$(SDK_DIR)/drivers/port \
$(TOP)/$(SDK_DIR)/drivers/lpuart \
+ $(TOP)/$(SDK_DIR)/drivers/port \
+ $(TOP)/$(SDK_DIR)/drivers/smc \
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
diff --git a/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..27b2d76f53
--- /dev/null
+++ b/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,178 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #ifdef __GNUC__
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wunused-parameter"
+ #endif
+
+ #include "chip.h"
+
+ #ifdef __GNUC__
+ #pragma GCC diagnostic pop
+ #endif
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 2
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 2
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 2
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 2
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
+
+ POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+ CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
+
+ /*!< Set up PLL */
+ CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+ const pll_setup_t pll0Setup = {
+ .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
+ .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
+ .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
+ .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+ .pllRate = 100000000U,
+ .flags = PLL_SETUPFLAG_WAITLOCK
+ };
+ CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
+
+ /*< Set SystemCoreClock variable. */
+ SystemCoreClock = 100000000U;
}
void board_init(void) {
// Enable IOCON clock
CLOCK_EnableClock(kCLOCK_Iocon);
- // Init 96 MHz clock
- BootClockFROHF96M();
+ // Init 100 MHz clock
+ BOARD_BootClockPLL100M();
+#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+ // Explicitly disable systick to prevent its ISR runs before scheduler start
+ SysTick->CTRL &= ~1U;
+
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+ NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#endif
// Init all GPIO ports
@@ -175,7 +197,7 @@ void board_init(void) {
/* PORT0 PIN22 configured as USB0_VBUS */
IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
-#if PORT_SUPPORT_DEVICE(0)
+#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
// Port0 is Full Speed
/* Turn on USB0 Phy */
@@ -200,7 +222,7 @@ void board_init(void) {
CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
#endif
-#if PORT_SUPPORT_DEVICE(1)
+#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1
// Port1 is High Speed
/* Turn on USB1 Phy */
@@ -239,6 +261,10 @@ void board_init(void) {
// phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
// phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
// USBPHY->TX = phytx;
+
+ ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
+ ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
+ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
#endif
}
diff --git a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..e5a76af85c
--- /dev/null
+++ b/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake.
+
+Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP
+compatible debug probe. However, at the time of writing, the necessary flashing
+algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
+branch. To utilize the provided debug probes, please install the bundled MSDK
+package which includes the appropriate OpenOCD modifications. To leverage this
+OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake
+target.
+
+### MAX32651
+
+The MAX32651 features an integrated secure bootloader which requires the
+application image be signed prior to flashing. Both the Makefile and CMake
+scripts account for this signing automatically when building for the
+MAX32651EVKIT.
+
+To flash the signed image, the MSDK's OpenOCD variant must be used. To flash
+the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk`
+and `-msdk` rule and target.
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.cmake b/hw/bsp/max32650/boards/max32650evkit/board.cmake
new file mode 100644
index 0000000000..fffdcc9fb1
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650evkit/board.cmake
@@ -0,0 +1,10 @@
+# Use the standard, non-secure linker file
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld)
+
+function(update_board_extras TARGET)
+ #No extra arguments
+endfunction()
+
+function(prepare_image TARGET_IN)
+ #No signing required
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.h b/hw/bsp/max32650/boards/max32650evkit/board.h
new file mode 100644
index 0000000000..196abdaca7
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650evkit/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT MXC_GPIO2
+#define LED_PIN MXC_GPIO_PIN_25
+#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON 0
+
+// Button
+#define BUTTON_PORT MXC_GPIO2
+#define BUTTON_PIN MXC_GPIO_PIN_28
+#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32650/boards/max32650evkit/board.mk b/hw/bsp/max32650/boards/max32650evkit/board.mk
new file mode 100644
index 0000000000..0bc210e112
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650evkit/board.mk
@@ -0,0 +1,2 @@
+# Use the standard, non-secure linker file
+LD_FILE = $(BOARD_PATH)/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32650evkit/max32650.ld b/hw/bsp/max32650/boards/max32650evkit/max32650.ld
new file mode 100644
index 0000000000..0e56a91ec3
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650evkit/max32650.ld
@@ -0,0 +1,119 @@
+MEMORY {
+ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */
+}
+
+SECTIONS {
+ .text :
+ {
+ _text = .;
+ KEEP(*(.isr_vector))
+ *(.text*) /* program code */
+ *(.rodata*) /* read-only data: "const" */
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* C++ Exception handling */
+ KEEP(*(.eh_frame*))
+ _etext = .;
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ /* it's used for C++ exception handling */
+ /* we need to keep this to avoid overlapping */
+ .ARM.exidx :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > FLASH
+
+ .data :
+ {
+ _data = ALIGN(., 4);
+ *(vtable)
+ *(.data*) /*read-write initialized data: initialized global variable*/
+ *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
+ *(.flashprog*) /* Flash program */
+
+
+ /* These array sections are used by __libc_init_array to call static C++ constructors */
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ _edata = ALIGN(., 4);
+ } > SRAM AT>FLASH
+ __load_data = LOADADDR(.data);
+ .bss :
+ {
+ . = ALIGN(4);
+ _bss = .;
+ *(.bss*) /*read-write zero initialized data: uninitialized global variable*/
+ *(COMMON)
+ _ebss = ALIGN(., 4);
+ } > SRAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SRAM
+
+ .heap (COPY):
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ *(.heap*)
+ __HeapLimit = ABSOLUTE(__StackLimit);
+ } > SRAM
+
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.cmake b/hw/bsp/max32650/boards/max32650fthr/board.cmake
new file mode 100644
index 0000000000..fffdcc9fb1
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650fthr/board.cmake
@@ -0,0 +1,10 @@
+# Use the standard, non-secure linker file
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld)
+
+function(update_board_extras TARGET)
+ #No extra arguments
+endfunction()
+
+function(prepare_image TARGET_IN)
+ #No signing required
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.h b/hw/bsp/max32650/boards/max32650fthr/board.h
new file mode 100644
index 0000000000..d80a8fcae4
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650fthr/board.h
@@ -0,0 +1,57 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT MXC_GPIO1
+#define LED_PIN MXC_GPIO_PIN_14
+#define LED_VDDIO MXC_GPIO_VSSEL_VDDIO
+#define LED_STATE_ON 0
+
+// Button
+#define BUTTON_PORT MXC_GPIO1
+#define BUTTON_PIN MXC_GPIO_PIN_19
+#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for SWD UART Pins. Pin Mux handled by the HAL
+#define UART_NUM 0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32650/boards/max32650fthr/board.mk b/hw/bsp/max32650/boards/max32650fthr/board.mk
new file mode 100644
index 0000000000..0bc210e112
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650fthr/board.mk
@@ -0,0 +1,2 @@
+# Use the standard, non-secure linker file
+LD_FILE = $(BOARD_PATH)/max32650.ld
diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld
new file mode 100644
index 0000000000..0e56a91ec3
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32650fthr/max32650.ld
@@ -0,0 +1,119 @@
+MEMORY {
+ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */
+}
+
+SECTIONS {
+ .text :
+ {
+ _text = .;
+ KEEP(*(.isr_vector))
+ *(.text*) /* program code */
+ *(.rodata*) /* read-only data: "const" */
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* C++ Exception handling */
+ KEEP(*(.eh_frame*))
+ _etext = .;
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ /* it's used for C++ exception handling */
+ /* we need to keep this to avoid overlapping */
+ .ARM.exidx :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > FLASH
+
+ .data :
+ {
+ _data = ALIGN(., 4);
+ *(vtable)
+ *(.data*) /*read-write initialized data: initialized global variable*/
+ *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
+ *(.flashprog*) /* Flash program */
+
+
+ /* These array sections are used by __libc_init_array to call static C++ constructors */
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ _edata = ALIGN(., 4);
+ } > SRAM AT>FLASH
+ __load_data = LOADADDR(.data);
+ .bss :
+ {
+ . = ALIGN(4);
+ _bss = .;
+ *(.bss*) /*read-write zero initialized data: uninitialized global variable*/
+ *(COMMON)
+ _ebss = ALIGN(., 4);
+ } > SRAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SRAM
+
+ .heap (COPY):
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ *(.heap*)
+ __HeapLimit = ABSOLUTE(__StackLimit);
+ } > SRAM
+
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.cmake b/hw/bsp/max32650/boards/max32651evkit/board.cmake
new file mode 100644
index 0000000000..bd8077a421
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32651evkit/board.cmake
@@ -0,0 +1,30 @@
+# Use the secure linker file
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld)
+
+function(update_board_extras TARGET)
+ # for the signed target, need to add the __SLA_FWK__ define
+ target_compile_definitions(${TARGET} PUBLIC
+ __SLA_FWK__
+ )
+endfunction()
+
+function(prepare_image TARGET_IN)
+ #For the signed target, set up a POST_BUILD command to sign the elf file once
+ #created
+ if((WIN32) OR (MINGW) OR (MSYS))
+ set(SIGN_EXE "sign_app.exe")
+ else()
+ set(SIGN_EXE "sign_app")
+ endif()
+ set(MCU_PATH "${TOP}/hw/mcu/analog/max32/")
+
+ # Custom POST_BUILD command
+ add_custom_command(
+ TARGET ${TARGET_IN} POST_BUILD
+ COMMAND ${CMAKE_OBJCOPY} $ -R .sig -O binary $/${TARGET_IN}.bin
+ COMMAND ${MCU_PATH}/Tools/SBT/bin/${SIGN_EXE} -c MAX32651 key_file=${MCU_PATH}/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key
+ ca=$/${TARGET_IN}.bin sca=$/${TARGET_IN}.sbin
+ COMMAND ${CMAKE_OBJCOPY} $ --update-section .sig=$/${TARGET_IN}.sig
+ VERBATIM
+ )
+endfunction()
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.h b/hw/bsp/max32650/boards/max32651evkit/board.h
new file mode 100644
index 0000000000..196abdaca7
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32651evkit/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT MXC_GPIO2
+#define LED_PIN MXC_GPIO_PIN_25
+#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON 0
+
+// Button
+#define BUTTON_PORT MXC_GPIO2
+#define BUTTON_PIN MXC_GPIO_PIN_28
+#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32650/boards/max32651evkit/board.mk b/hw/bsp/max32650/boards/max32651evkit/board.mk
new file mode 100644
index 0000000000..b609598c16
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32651evkit/board.mk
@@ -0,0 +1,5 @@
+# Use the secure linker file
+LD_FILE = $(BOARD_PATH)/max32651.ld
+
+# Let the family script know the build needs to be signed
+SIGNED_BUILD := 1
diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/max32650/boards/max32651evkit/max32651.ld
new file mode 100644
index 0000000000..3921d10f23
--- /dev/null
+++ b/hw/bsp/max32650/boards/max32651evkit/max32651.ld
@@ -0,0 +1,132 @@
+MEMORY {
+ HEADER (rx): ORIGIN = 0x10000000, LENGTH = 0x200
+ FLASH (rx) : ORIGIN = 0x10000200, LENGTH = 0x002FFE00 /* 3MB flash */
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */
+}
+
+/* Added Oct 9, 2018 to go to correct reset vector. */
+ENTRY(Reset_Handler)
+PROVIDE( _start_SWAP = (((Reset_Handler) >> 24) | (((Reset_Handler) & 0x00FF0000) >> 8) | (((Reset_Handler) & 0x0000FF00) << 8) | ((Reset_Handler) << 24)));
+PROVIDE_HIDDEN( _SLA_Size = _endimage - __end_header );
+PROVIDE( _SLA_Size_SWAP = (((_SLA_Size) >> 24) | (((_SLA_Size) & 0x00FF0000) >> 8) | (((_SLA_Size) & 0x0000FF00) << 8) | ((_SLA_Size) << 24)));
+
+/* Sections Definitions */
+SECTIONS {
+ .sb_sla_header : ALIGN(4)
+ {
+ FILL(0xFF)
+ KEEP(*(.sb_sla_header)) /* Header for ROM code */
+ __end_header = . ;
+ . = ALIGN(512);
+ } > HEADER
+
+ .text :
+ {
+ _text = .;
+ KEEP(*(.isr_vector))
+ *(.text*) /* program code */
+ *(.rodata*) /* read-only data: "const" */
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* C++ Exception handling */
+ KEEP(*(.eh_frame*))
+ _etext = .;
+ } > FLASH
+
+ /* it's used for C++ exception handling */
+ /* we need to keep this to avoid overlapping */
+ .ARM.exidx :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > FLASH
+
+ .data :
+ {
+ _data = ALIGN(., 4);
+ *(.data*) /*read-write initialized data: initialized global variable*/
+ *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
+ *(.flashprog*) /* Flash program */
+
+
+ /* These array sections are used by __libc_init_array to call static C++ constructors */
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ _edata = ALIGN(., 4);
+ } > SRAM AT>FLASH
+ __load_data = LOADADDR(.data);
+ _enddata = LOADADDR(.data)+SIZEOF(.data);
+
+ .sb_sla_trailer : AT(_enddata)
+ {
+ KEEP(*(.sb_sla_trailer))
+ /* Align image with 16 byte boundary to conform to flash encryption block size. */
+ FILL(0xDEADC0DE);
+ /* NOTE: The FILL and ALIGN will not work unless something is written to the section. So, we use LONG. */
+ LONG(0xDEADC0DE);
+ . = ALIGN(16);
+ } > FLASH
+ _endimage = LOADADDR(.sb_sla_trailer)+SIZEOF(.sb_sla_trailer);
+ .sig :
+ {
+ KEEP(*(.sig))
+ LONG(0xDEADBEEF);
+
+ } > FLASH
+ .bss :
+ {
+ . = ALIGN(4);
+ _bss = .;
+ *(.bss*) /*read-write zero initialized data: uninitialized global variable*/
+ *(COMMON)
+ _ebss = ALIGN(., 4);
+ } > SRAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SRAM
+
+ .heap (COPY):
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ *(.heap*)
+ __HeapLimit = ABSOLUTE(__StackLimit);
+ } > SRAM
+
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c
new file mode 100644
index 0000000000..bb382cdd42
--- /dev/null
+++ b/hw/bsp/max32650/family.c
@@ -0,0 +1,173 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
+#endif
+
+#include "gpio.h"
+#include "mxc_sys.h"
+#include "mxc_device.h"
+#include "uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "board.h"
+#include "bsp/board_api.h"
+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+ tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+ // 1ms tick timer
+ SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+ mxc_gpio_cfg_t gpioConfig;
+
+ // LED
+ gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+ gpioConfig.func = MXC_GPIO_FUNC_OUT;
+ gpioConfig.mask = LED_PIN;
+ gpioConfig.pad = MXC_GPIO_PAD_NONE;
+ gpioConfig.port = LED_PORT;
+ gpioConfig.vssel = LED_VDDIO;
+ MXC_GPIO_Config(&gpioConfig);
+ board_led_write(false);
+
+ // Button
+ gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+ gpioConfig.func = MXC_GPIO_FUNC_IN;
+ gpioConfig.mask = BUTTON_PIN;
+ gpioConfig.pad = BUTTON_PULL;
+ gpioConfig.port = BUTTON_PORT;
+ gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+ MXC_GPIO_Config(&gpioConfig);
+
+ // UART
+ MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE);
+
+ //USB
+ // Startup the HIRC96M clock if it's not on already
+ if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) {
+ MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN;
+ MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY);
+ }
+
+ MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+ MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#if LED_STATE_ON
+ state = !state;
+#endif
+ if (state) {
+ MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+ } else {
+ MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+ }
+}
+
+uint32_t board_button_read(void) {
+ uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+ return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ uint8_t hw_id[13];//USN Buffer
+ MXC_SYS_GetUSN(hw_id, 13);
+
+ size_t act_len = TU_MIN(max_len, 13);
+ memcpy(id, hw_id, act_len);
+ return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+ int uart_val;
+ int act_len = 0;
+
+ while (act_len < len) {
+ if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+ break;
+ } else {
+ *buf++ = (uint8_t) uart_val;
+ act_len++;
+ }
+ }
+ return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+ int act_len = 0;
+ const uint8_t *ch_ptr = (const uint8_t *) buf;
+ while (act_len < len) {
+ MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+ act_len++;
+ }
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+ system_ticks++;
+}
+
+uint32_t board_millis(void) {
+ return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+ __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake
new file mode 100644
index 0000000000..48853b92c6
--- /dev/null
+++ b/hw/bsp/max32650/family.cmake
@@ -0,0 +1,169 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific information and functions
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max32650)
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32650.cfg")
+
+set(FAMILY_MCUS MAX32650 CACHE INTERNAL "")
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ TARGET=MAX32650
+ TARGET_REV=0x4131
+ MXC_ASSERT_ENABLE
+ MAX32650
+ IAR_PRAGMAS=0
+ CFG_TUSB_MCU=OPT_MCU_MAX32650
+ BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ )
+
+ # Run any board specific updates
+ update_board_extras(${TARGET})
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+ add_library(${BOARD_TARGET} STATIC
+ ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/heap.c
+ ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/header_MAX32650.c
+ ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/system_max32650.c
+ ${PERIPH_SRC}/SYS/mxc_assert.c
+ ${PERIPH_SRC}/SYS/mxc_delay.c
+ ${PERIPH_SRC}/SYS/mxc_lock.c
+ ${PERIPH_SRC}/SYS/nvic_table.c
+ ${PERIPH_SRC}/SYS/pins_me10.c
+ ${PERIPH_SRC}/SYS/sys_me10.c
+ ${PERIPH_SRC}/TPU/tpu_me10.c
+ ${PERIPH_SRC}/TPU/tpu_reva.c
+ ${PERIPH_SRC}/FLC/flc_common.c
+ ${PERIPH_SRC}/FLC/flc_me10.c
+ ${PERIPH_SRC}/FLC/flc_reva.c
+ ${PERIPH_SRC}/GPIO/gpio_common.c
+ ${PERIPH_SRC}/GPIO/gpio_me10.c
+ ${PERIPH_SRC}/GPIO/gpio_reva.c
+ ${PERIPH_SRC}/ICC/icc_me10.c
+ ${PERIPH_SRC}/ICC/icc_reva.c
+ ${PERIPH_SRC}/ICC/icc_common.c
+ ${PERIPH_SRC}/UART/uart_common.c
+ ${PERIPH_SRC}/UART/uart_me10.c
+ ${PERIPH_SRC}/UART/uart_reva.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${MAX32_CMSIS}/Include
+ ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include
+ ${MAX32_PERIPH}/Include/MAX32650
+ ${PERIPH_SRC}/SYS
+ ${PERIPH_SRC}/GPIO
+ ${PERIPH_SRC}/TPU
+ ${PERIPH_SRC}/ICC
+ ${PERIPH_SRC}/FLC
+ ${PERIPH_SRC}/UART
+ )
+
+ target_compile_options(${BOARD_TARGET} PRIVATE
+ -Wno-error=strict-prototypes
+ )
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ -u sb_header #Needed when linking libraries to not lose the Signing header
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_MAX32650 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/mentor/musb/dcd_musb.c
+ )
+ target_compile_options(${TARGET} PRIVATE
+ -Wno-error=strict-prototypes
+ )
+
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+ target_compile_options(${TARGET}-tinyusb PRIVATE
+ -Wno-error=strict-prototypes
+ )
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ family_flash_openocd_adi(${TARGET})
+
+ # Add the optional MSDK OpenOCD flashing
+ family_flash_msdk(${TARGET})
+endfunction()
+
+function(family_flash_msdk TARGET)
+ # Prepare the image (signed) if the board requires it
+ prepare_image(${TARGET})
+
+ set(MAXIM_PATH "$ENV{MAXIM_PATH}")
+ add_custom_target(${TARGET}-msdk
+ DEPENDS ${TARGET}
+ COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts
+ -f interface/cmsis-dap.cfg -f target/max32650.cfg
+ -c "program $ verify; init; reset; exit"
+ VERBATIM
+ )
+endfunction()
diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk
new file mode 100644
index 0000000000..d2fc293e4f
--- /dev/null
+++ b/hw/bsp/max32650/family.mk
@@ -0,0 +1,140 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX32650/1/2 SDK
+CFLAGS += -DTARGET=MAX32650 \
+ -DTARGET_REV=0x4131 \
+ -DMXC_ASSERT_ENABLE \
+ -DMAX32650 \
+ -DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+ -DCFG_TUSB_MCU=OPT_MCU_MAX32650 \
+ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=strict-prototypes \
+ -Wno-error=unused-parameter \
+ -Wno-error=cast-align \
+ -Wno-error=cast-qual \
+ -Wno-error=sign-compare
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# Configure the flash rule. By default, use JLink.
+SIGNED_BUILD ?= 0
+DEFAULT_FLASH = flash-jlink
+
+# If the applications needs to be signed (for the MAX32651), sign it first and
+# then need to use MSDK's OpenOCD to flash it
+# Also need to include the __SLA_FWK__ define to enable the signed header into
+# memory
+ifeq ($(SIGNED_BUILD), 1)
+# Extra definitions to build for the secure part
+CFLAGS += -D__SLA_FWK__
+DEFAULT_FLASH := sign-build flash-msdk
+endif
+
+# For flash-jlink target
+JLINK_DEVICE = max32650
+
+# Configure the flash rule
+flash: $(DEFAULT_FLASH)
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+ src/portable/mentor/musb/dcd_musb.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \
+ $(PERIPH_SRC)/SYS/mxc_assert.c \
+ $(PERIPH_SRC)/SYS/mxc_delay.c \
+ $(PERIPH_SRC)/SYS/mxc_lock.c \
+ $(PERIPH_SRC)/SYS/nvic_table.c \
+ $(PERIPH_SRC)/SYS/pins_me10.c \
+ $(PERIPH_SRC)/SYS/sys_me10.c \
+ $(PERIPH_SRC)/FLC/flc_common.c \
+ $(PERIPH_SRC)/FLC/flc_me10.c \
+ $(PERIPH_SRC)/FLC/flc_reva.c \
+ $(PERIPH_SRC)/GPIO/gpio_common.c \
+ $(PERIPH_SRC)/GPIO/gpio_me10.c \
+ $(PERIPH_SRC)/GPIO/gpio_reva.c \
+ $(PERIPH_SRC)/ICC/icc_me10.c \
+ $(PERIPH_SRC)/ICC/icc_reva.c \
+ $(PERIPH_SRC)/ICC/icc_common.c \
+ $(PERIPH_SRC)/TPU/tpu_me10.c \
+ $(PERIPH_SRC)/TPU/tpu_reva.c \
+ $(PERIPH_SRC)/UART/uart_common.c \
+ $(PERIPH_SRC)/UART/uart_me10.c \
+ $(PERIPH_SRC)/UART/uart_reva.c \
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(MAX32_CMSIS)/Include \
+ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \
+ $(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \
+ $(PERIPH_SRC)/SYS \
+ $(PERIPH_SRC)/GPIO \
+ $(PERIPH_SRC)/ICC \
+ $(PERIPH_SRC)/FLC \
+ $(PERIPH_SRC)/TPU \
+ $(PERIPH_SRC)/UART
+
+
+# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the
+# MAX32651 has a secure bootloader which requires the image to be signed before
+# loading into flash. All MAX32651EVKIT's have the same key for evaluation
+# purposes, so create a special flash rule to sign the binary and flash using
+# the MSDK.
+MCU_PATH = $(TOP)/hw/mcu/analog/max32/
+# Assume no extension for sign utility
+SIGN_EXE = sign_app
+ifeq ($(OS), Windows_NT)
+# Must use .exe extension on Windows, since the binaries
+# for Linux may live in the same place.
+SIGN_EXE := sign_app.exe
+else
+UNAME = $(shell uname -s)
+ifneq ($(findstring MSYS_NT,$(UNAME)),)
+# Must also use .exe extension for MSYS2
+SIGN_EXE := sign_app.exe
+endif
+endif
+
+# Rule to sign the build. This will in-place modify the existing .elf file
+# an populate the .sig section with the signature value
+sign-build: $(BUILD)/$(PROJECT).elf
+ $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin
+ $(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \
+ key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \
+ ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin
+ $(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+ $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+ -f interface/cmsis-dap.cfg -f target/max32650.cfg \
+ -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
diff --git a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..e5a76af85c
--- /dev/null
+++ b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake.
+
+Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP
+compatible debug probe. However, at the time of writing, the necessary flashing
+algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
+branch. To utilize the provided debug probes, please install the bundled MSDK
+package which includes the appropriate OpenOCD modifications. To leverage this
+OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake
+target.
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.cmake b/hw/bsp/max32666/boards/max32666evkit/board.cmake
new file mode 100644
index 0000000000..9dc6962eb9
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666evkit/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.h b/hw/bsp/max32666/boards/max32666evkit/board.h
new file mode 100644
index 0000000000..0ab1483b8c
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666evkit/board.h
@@ -0,0 +1,57 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT MXC_GPIO1
+#define LED_PIN MXC_GPIO_PIN_14
+#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON 0
+
+// Button
+#define BUTTON_PORT MXC_GPIO1
+#define BUTTON_PIN MXC_GPIO_PIN_6
+#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM 1
+#define UART_MAP MAP_A
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32666/boards/max32666evkit/board.mk b/hw/bsp/max32666/boards/max32666evkit/board.mk
new file mode 100644
index 0000000000..a813a5327b
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666evkit/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.cmake b/hw/bsp/max32666/boards/max32666fthr/board.cmake
new file mode 100644
index 0000000000..9dc6962eb9
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666fthr/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.h b/hw/bsp/max32666/boards/max32666fthr/board.h
new file mode 100644
index 0000000000..c719b748a2
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666fthr/board.h
@@ -0,0 +1,57 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT MXC_GPIO0
+#define LED_PIN MXC_GPIO_PIN_29
+#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON 0
+
+// Button
+#define BUTTON_PORT MXC_GPIO1
+#define BUTTON_PIN MXC_GPIO_PIN_10
+#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for UART on SWD. Pin Mux handled by the HAL
+#define UART_NUM 1
+#define UART_MAP MAP_B
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32666/boards/max32666fthr/board.mk b/hw/bsp/max32666/boards/max32666fthr/board.mk
new file mode 100644
index 0000000000..a813a5327b
--- /dev/null
+++ b/hw/bsp/max32666/boards/max32666fthr/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c
new file mode 100644
index 0000000000..f96393fe11
--- /dev/null
+++ b/hw/bsp/max32666/family.c
@@ -0,0 +1,173 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
+#endif
+
+#include "gpio.h"
+#include "mxc_sys.h"
+#include "mcr_regs.h"
+#include "mxc_device.h"
+#include "uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "board.h"
+#include "bsp/board_api.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+ tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+ // 1ms tick timer
+ SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+ mxc_gpio_cfg_t gpioConfig;
+
+ // LED
+ gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+ gpioConfig.func = MXC_GPIO_FUNC_OUT;
+ gpioConfig.mask = LED_PIN;
+ gpioConfig.pad = MXC_GPIO_PAD_NONE;
+ gpioConfig.port = LED_PORT;
+ gpioConfig.vssel = LED_VDDIO;
+ MXC_GPIO_Config(&gpioConfig);
+ board_led_write(false);
+
+ // Button
+ gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+ gpioConfig.func = MXC_GPIO_FUNC_IN;
+ gpioConfig.mask = BUTTON_PIN;
+ gpioConfig.pad = BUTTON_PULL;
+ gpioConfig.port = BUTTON_PORT;
+ gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+ MXC_GPIO_Config(&gpioConfig);
+
+ // UART
+ MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, UART_MAP);
+
+ //USB
+ // Startup the HIRC96M clock if it's not on already
+ if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) {
+ MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN;
+ }
+
+ MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+ MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#if LED_STATE_ON
+ state = !state;
+#endif
+ if (state) {
+ MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+ } else {
+ MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+ }
+}
+
+uint32_t board_button_read(void) {
+ uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+ return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
+ /* All other 2nd parameter is optional checksum buffer */
+ MXC_SYS_GetUSN(hw_id, NULL);
+
+ size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
+ memcpy(id, hw_id, act_len);
+ return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+ int uart_val;
+ int act_len = 0;
+
+ while (act_len < len) {
+ if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+ break;
+ } else {
+ *buf++ = (uint8_t) uart_val;
+ act_len++;
+ }
+ }
+ return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+ int act_len = 0;
+ const uint8_t *ch_ptr = (const uint8_t *) buf;
+ while (act_len < len) {
+ MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+ act_len++;
+ }
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+ system_ticks++;
+}
+
+uint32_t board_millis(void) {
+ return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+ __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake
new file mode 100644
index 0000000000..fb8c322954
--- /dev/null
+++ b/hw/bsp/max32666/family.cmake
@@ -0,0 +1,147 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file from current location (family)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32666.ld)
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max32666)
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32665.cfg")
+
+set(FAMILY_MCUS MAX32666 CACHE INTERNAL "")
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ TARGET=MAX32665
+ TARGET_REV=0x4131
+ MXC_ASSERT_ENABLE
+ MAX32665
+ IAR_PRAGMAS=0
+ CFG_TUSB_MCU=OPT_MCU_MAX32666
+ BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ )
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+ add_library(${BOARD_TARGET} STATIC
+ ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/heap.c
+ ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/system_max32665.c
+ ${PERIPH_SRC}/SYS/mxc_assert.c
+ ${PERIPH_SRC}/SYS/mxc_delay.c
+ ${PERIPH_SRC}/SYS/mxc_lock.c
+ ${PERIPH_SRC}/SYS/nvic_table.c
+ ${PERIPH_SRC}/SYS/pins_me14.c
+ ${PERIPH_SRC}/SYS/sys_me14.c
+ ${PERIPH_SRC}/TPU/tpu_me14.c
+ ${PERIPH_SRC}/TPU/tpu_reva.c
+ ${PERIPH_SRC}/FLC/flc_common.c
+ ${PERIPH_SRC}/FLC/flc_me14.c
+ ${PERIPH_SRC}/FLC/flc_reva.c
+ ${PERIPH_SRC}/GPIO/gpio_common.c
+ ${PERIPH_SRC}/GPIO/gpio_me14.c
+ ${PERIPH_SRC}/GPIO/gpio_reva.c
+ ${PERIPH_SRC}/ICC/icc_me14.c
+ ${PERIPH_SRC}/ICC/icc_reva.c
+ ${PERIPH_SRC}/UART/uart_common.c
+ ${PERIPH_SRC}/UART/uart_me14.c
+ ${PERIPH_SRC}/UART/uart_reva.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${MAX32_CMSIS}/Include
+ ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include
+ ${MAX32_PERIPH}/Include/MAX32665
+ ${PERIPH_SRC}/SYS
+ ${PERIPH_SRC}/GPIO
+ ${PERIPH_SRC}/TPU
+ ${PERIPH_SRC}/ICC
+ ${PERIPH_SRC}/FLC
+ ${PERIPH_SRC}/UART
+ )
+
+ target_compile_options(${BOARD_TARGET} PRIVATE
+ -Wno-error=strict-prototypes
+ )
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_MAX32666 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/mentor/musb/dcd_musb.c
+ )
+ target_compile_options(${TARGET} PRIVATE
+ -Wno-error=strict-prototypes
+ )
+
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+ target_compile_options(${TARGET}-tinyusb PRIVATE
+ -Wno-error=strict-prototypes
+ )
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ family_flash_openocd_adi(${TARGET})
+endfunction()
diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk
new file mode 100644
index 0000000000..b4f7d1e575
--- /dev/null
+++ b/hw/bsp/max32666/family.mk
@@ -0,0 +1,93 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
+LD_FILE = $(FAMILY_PATH)/max32666.ld
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX32665/6 SDK
+CFLAGS += -DTARGET=MAX32665 \
+ -DTARGET_REV=0x4131 \
+ -DMXC_ASSERT_ENABLE \
+ -DMAX32665 \
+ -DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+ -DCFG_TUSB_MCU=OPT_MCU_MAX32666 \
+ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=strict-prototypes \
+ -Wno-error=unused-parameter \
+ -Wno-error=cast-align \
+ -Wno-error=cast-qual
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# For flash-jlink target
+JLINK_DEVICE = max32666
+
+# flash target using Jlink by default
+flash: flash-jlink
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+ $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+ -f interface/cmsis-dap.cfg -f target/max32665.cfg \
+ -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+ src/portable/mentor/musb/dcd_musb.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \
+ $(PERIPH_SRC)/SYS/mxc_assert.c \
+ $(PERIPH_SRC)/SYS/mxc_delay.c \
+ $(PERIPH_SRC)/SYS/mxc_lock.c \
+ $(PERIPH_SRC)/SYS/nvic_table.c \
+ $(PERIPH_SRC)/SYS/pins_me14.c \
+ $(PERIPH_SRC)/SYS/sys_me14.c \
+ $(PERIPH_SRC)/FLC/flc_common.c \
+ $(PERIPH_SRC)/FLC/flc_me14.c \
+ $(PERIPH_SRC)/FLC/flc_reva.c \
+ $(PERIPH_SRC)/GPIO/gpio_common.c \
+ $(PERIPH_SRC)/GPIO/gpio_me14.c \
+ $(PERIPH_SRC)/GPIO/gpio_reva.c \
+ $(PERIPH_SRC)/ICC/icc_me14.c \
+ $(PERIPH_SRC)/ICC/icc_reva.c \
+ $(PERIPH_SRC)/TPU/tpu_me14.c \
+ $(PERIPH_SRC)/TPU/tpu_reva.c \
+ $(PERIPH_SRC)/UART/uart_common.c \
+ $(PERIPH_SRC)/UART/uart_me14.c \
+ $(PERIPH_SRC)/UART/uart_reva.c \
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(MAX32_CMSIS)/Include \
+ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \
+ $(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \
+ $(PERIPH_SRC)/SYS \
+ $(PERIPH_SRC)/GPIO \
+ $(PERIPH_SRC)/ICC \
+ $(PERIPH_SRC)/FLC \
+ $(PERIPH_SRC)/TPU \
+ $(PERIPH_SRC)/UART
diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/max32666/max32666.ld
new file mode 100644
index 0000000000..06c1242471
--- /dev/null
+++ b/hw/bsp/max32666/max32666.ld
@@ -0,0 +1,135 @@
+/* SPID and SPIX Sections here are maximum possible sizes */
+/* If used, they should be adjusted for the external Flash/RAM size */
+MEMORY {
+
+ SPIX (rx) : ORIGIN = 0x08000000, LENGTH = 0x08000000
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00100000
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0008C000
+ SPID (rw) : ORIGIN = 0x80000000, LENGTH = 512M
+}
+
+/* Sections Definitions */
+SECTIONS {
+ .text :
+ {
+ _text = .;
+ KEEP(*(.isr_vector))
+ *(.text*) /* program code */
+ *(.rodata*) /* read-only data: "const" */
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* C++ Exception handling */
+ KEEP(*(.eh_frame*))
+ _etext = .;
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ /* This section will keep the SPIX data until loaded into the external device */
+ /* Upon initialization of SPIX (user code needs to do this) */
+ .xip_section :
+ {
+ KEEP(*(.xip_section*))
+ } > SPIX AT>FLASH
+
+ __load_start_xip = LOADADDR(.xip_section);
+ __load_length_xip = SIZEOF(.xip_section);
+
+ /* it's used for C++ exception handling */
+ /* we need to keep this to avoid overlapping */
+ .ARM.exidx :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > FLASH
+
+ .data :
+ {
+ _data = ALIGN(., 4);
+ *(vtable)
+ *(.data*) /*read-write initialized data: initialized global variable*/
+ *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
+ *(.flashprog*) /* Flash program */
+
+
+ /* These array sections are used by __libc_init_array to call static C++ constructors */
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ _edata = ALIGN(., 4);
+ } > SRAM AT>FLASH
+ __load_data = LOADADDR(.data);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ _bss = .;
+ *(.bss*) /*read-write zero initialized data: uninitialized global variable*/
+ *(COMMON)
+ _ebss = ALIGN(., 4);
+ } > SRAM
+
+ /* Setup the stack for Core 1, it will only be used if the user code
+ * includes a definition of Stack_Size_Core1, which defines the space
+ * reserved above the main core's stack for core 1's stack */
+
+ __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM);
+ __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1;
+
+ /* Set stack top to end of RAM, and stack limit move down by Stack_Size.
+ * If core 1 is used, set the stack to the bottom of Core 1's stack region */
+
+ __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM);
+ __StackLimit = __StackTop - Stack_Size;
+
+ .heap (COPY):
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ *(.heap*)
+ __HeapLimit = ABSOLUTE(__StackLimit);
+ } > SRAM
+
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack(s) exceeds RAM limit */
+ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..e5a76af85c
--- /dev/null
+++ b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake.
+
+Both the Evaluation Kit and APARD boards are shipped with a CMSIS-DAP
+compatible debug probe. However, at the time of writing, the necessary flashing
+algorithms for OpenOCD have not yet been incorporated into the OpenOCD master
+branch. To utilize the provided debug probes, please install the bundled MSDK
+package which includes the appropriate OpenOCD modifications. To leverage this
+OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake
+target.
diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake
new file mode 100644
index 0000000000..9dc6962eb9
--- /dev/null
+++ b/hw/bsp/max32690/boards/apard32690/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/max32690/boards/apard32690/board.h
new file mode 100644
index 0000000000..f94097ca9a
--- /dev/null
+++ b/hw/bsp/max32690/boards/apard32690/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT MXC_GPIO2
+#define LED_PIN MXC_GPIO_PIN_1
+#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON 1
+
+// Button
+#define BUTTON_PORT MXC_GPIO1
+#define BUTTON_PIN MXC_GPIO_PIN_27
+#define BUTTON_PULL MXC_GPIO_PAD_NONE
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for UART on ARM SWD Connector
+#define UART_NUM 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk
new file mode 100644
index 0000000000..a813a5327b
--- /dev/null
+++ b/hw/bsp/max32690/boards/apard32690/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.cmake b/hw/bsp/max32690/boards/max32690evkit/board.cmake
new file mode 100644
index 0000000000..9dc6962eb9
--- /dev/null
+++ b/hw/bsp/max32690/boards/max32690evkit/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/max32690/boards/max32690evkit/board.h
new file mode 100644
index 0000000000..05d60f2205
--- /dev/null
+++ b/hw/bsp/max32690/boards/max32690evkit/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT MXC_GPIO0
+#define LED_PIN MXC_GPIO_PIN_14
+#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON 0
+
+// Button
+#define BUTTON_PORT MXC_GPIO4
+#define BUTTON_PIN MXC_GPIO_PIN_0
+#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM 2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max32690/boards/max32690evkit/board.mk b/hw/bsp/max32690/boards/max32690evkit/board.mk
new file mode 100644
index 0000000000..a813a5327b
--- /dev/null
+++ b/hw/bsp/max32690/boards/max32690evkit/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c
new file mode 100644
index 0000000000..2418168d41
--- /dev/null
+++ b/hw/bsp/max32690/family.c
@@ -0,0 +1,171 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
+#endif
+
+#include "gpio.h"
+#include "mxc_sys.h"
+#include "mcr_regs.h"
+#include "mxc_device.h"
+#include "uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "board.h"
+#include "bsp/board_api.h"
+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+ tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+ // 1ms tick timer
+ SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+ mxc_gpio_cfg_t gpioConfig;
+
+ // LED
+ gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+ gpioConfig.func = MXC_GPIO_FUNC_OUT;
+ gpioConfig.mask = LED_PIN;
+ gpioConfig.pad = MXC_GPIO_PAD_NONE;
+ gpioConfig.port = LED_PORT;
+ gpioConfig.vssel = LED_VDDIO;
+ MXC_GPIO_Config(&gpioConfig);
+ board_led_write(false);
+
+ // Button
+ gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+ gpioConfig.func = MXC_GPIO_FUNC_IN;
+ gpioConfig.mask = BUTTON_PIN;
+ gpioConfig.pad = BUTTON_PULL;
+ gpioConfig.port = BUTTON_PORT;
+ gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+ MXC_GPIO_Config(&gpioConfig);
+
+ // UART
+ MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
+
+ //USB
+ MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO);
+ MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+ MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+ MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#if LED_STATE_ON
+ state = !state;
+#endif
+ if (state) {
+ MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+ } else {
+ MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+ }
+}
+
+uint32_t board_button_read(void) {
+ uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+ return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
+ /* All other 2nd parameter is optional checksum buffer */
+ MXC_SYS_GetUSN(hw_id, NULL);
+
+ size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
+ memcpy(id, hw_id, act_len);
+ return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+ int uart_val;
+ int act_len = 0;
+
+ while (act_len < len) {
+ if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+ break;
+ } else {
+ *buf++ = (uint8_t) uart_val;
+ act_len++;
+ }
+ }
+ return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+ int act_len = 0;
+ const uint8_t *ch_ptr = (const uint8_t *) buf;
+ while (act_len < len) {
+ MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+ act_len++;
+ }
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+ system_ticks++;
+}
+
+uint32_t board_millis(void) {
+ return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+ __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake
new file mode 100644
index 0000000000..96dcfedffd
--- /dev/null
+++ b/hw/bsp/max32690/family.cmake
@@ -0,0 +1,152 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file from current location (family)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld)
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max32690)
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg")
+
+set(FAMILY_MCUS MAX32690 CACHE INTERNAL "")
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ TARGET=MAX32690
+ TARGET_REV=0x4131
+ MXC_ASSERT_ENABLE
+ MAX32690
+ FLASH_ORIGIN=0x10000000
+ FLASH_SIZE=0x340000
+ SRAM_ORIGIN=0x20000000
+ SRAM_SIZE=0x100000
+ IAR_PRAGMAS=0
+ CFG_TUSB_MCU=OPT_MCU_MAX32690
+ BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ )
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+ add_library(${BOARD_TARGET} STATIC
+ ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c
+ ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c
+ ${PERIPH_SRC}/SYS/mxc_assert.c
+ ${PERIPH_SRC}/SYS/mxc_delay.c
+ ${PERIPH_SRC}/SYS/mxc_lock.c
+ ${PERIPH_SRC}/SYS/nvic_table.c
+ ${PERIPH_SRC}/SYS/pins_me18.c
+ ${PERIPH_SRC}/SYS/sys_me18.c
+ ${PERIPH_SRC}/CTB/ctb_me18.c
+ ${PERIPH_SRC}/CTB/ctb_reva.c
+ ${PERIPH_SRC}/CTB/ctb_common.c
+ ${PERIPH_SRC}/FLC/flc_common.c
+ ${PERIPH_SRC}/FLC/flc_me18.c
+ ${PERIPH_SRC}/FLC/flc_reva.c
+ ${PERIPH_SRC}/GPIO/gpio_common.c
+ ${PERIPH_SRC}/GPIO/gpio_me18.c
+ ${PERIPH_SRC}/GPIO/gpio_reva.c
+ ${PERIPH_SRC}/ICC/icc_me18.c
+ ${PERIPH_SRC}/ICC/icc_reva.c
+ ${PERIPH_SRC}/UART/uart_common.c
+ ${PERIPH_SRC}/UART/uart_me18.c
+ ${PERIPH_SRC}/UART/uart_revb.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${MAX32_CMSIS}/Include
+ ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include
+ ${MAX32_PERIPH}/Include/MAX32690
+ ${PERIPH_SRC}/SYS
+ ${PERIPH_SRC}/GPIO
+ ${PERIPH_SRC}/CTB
+ ${PERIPH_SRC}/ICC
+ ${PERIPH_SRC}/FLC
+ ${PERIPH_SRC}/UART
+ )
+
+ target_compile_options(${BOARD_TARGET} PRIVATE
+ -Wno-error=strict-prototypes
+ )
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_MAX32690 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/mentor/musb/dcd_musb.c
+ )
+ target_compile_options(${TARGET} PRIVATE
+ -Wno-error=strict-prototypes
+ )
+
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+ target_compile_options(${TARGET}-tinyusb PRIVATE
+ -Wno-error=strict-prototypes
+ )
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ family_flash_openocd_adi(${TARGET})
+endfunction()
diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk
new file mode 100644
index 0000000000..d4df8ef2fa
--- /dev/null
+++ b/hw/bsp/max32690/family.mk
@@ -0,0 +1,101 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S
+LD_FILE = $(FAMILY_PATH)/max32690.ld
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX32690 SDK
+CFLAGS += -DTARGET=MAX32690 \
+ -DTARGET_REV=0x4131 \
+ -DMXC_ASSERT_ENABLE \
+ -DMAX32690 \
+ -DFLASH_ORIGIN=0x10000000 \
+ -DFLASH_SIZE=0x340000 \
+ -DSRAM_ORIGIN=0x20000000 \
+ -DSRAM_SIZE=0x100000 \
+ -DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+ -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \
+ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter \
+ -Wno-error=strict-prototypes \
+ -Wno-error=old-style-declaration \
+ -Wno-error=sign-compare \
+ -Wno-error=cast-qual \
+ -Wno-lto-type-mismatch
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# For flash-jlink target
+JLINK_DEVICE = max32690
+
+# flash target using Jlink by default
+flash: flash-jlink
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+ $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+ -f interface/cmsis-dap.cfg -f target/max32690.cfg \
+ -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+ src/portable/mentor/musb/dcd_musb.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \
+ $(PERIPH_SRC)/SYS/mxc_assert.c \
+ $(PERIPH_SRC)/SYS/mxc_delay.c \
+ $(PERIPH_SRC)/SYS/mxc_lock.c \
+ $(PERIPH_SRC)/SYS/nvic_table.c \
+ $(PERIPH_SRC)/SYS/pins_me18.c \
+ $(PERIPH_SRC)/SYS/sys_me18.c \
+ $(PERIPH_SRC)/CTB/ctb_me18.c \
+ $(PERIPH_SRC)/CTB/ctb_reva.c \
+ $(PERIPH_SRC)/CTB/ctb_common.c \
+ $(PERIPH_SRC)/FLC/flc_common.c \
+ $(PERIPH_SRC)/FLC/flc_me18.c \
+ $(PERIPH_SRC)/FLC/flc_reva.c \
+ $(PERIPH_SRC)/GPIO/gpio_common.c \
+ $(PERIPH_SRC)/GPIO/gpio_me18.c \
+ $(PERIPH_SRC)/GPIO/gpio_reva.c \
+ $(PERIPH_SRC)/ICC/icc_me18.c \
+ $(PERIPH_SRC)/ICC/icc_reva.c \
+ $(PERIPH_SRC)/UART/uart_common.c \
+ $(PERIPH_SRC)/UART/uart_me18.c \
+ $(PERIPH_SRC)/UART/uart_revb.c \
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(MAX32_CMSIS)/Include \
+ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \
+ $(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \
+ $(PERIPH_SRC)/SYS \
+ $(PERIPH_SRC)/GPIO \
+ $(PERIPH_SRC)/CTB \
+ $(PERIPH_SRC)/ICC \
+ $(PERIPH_SRC)/FLC \
+ $(PERIPH_SRC)/UART
diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/max32690/max32690.ld
new file mode 100644
index 0000000000..64b906a541
--- /dev/null
+++ b/hw/bsp/max32690/max32690.ld
@@ -0,0 +1,164 @@
+MEMORY {
+ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 /* 128kB ROM */
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00340000
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000
+
+ /*
+ * Note that CS0/CS1 address mappings may be reversed using MXC_HPC->mbr0 and ->mbr1
+ * The following mappings are selected for simplicity
+ */
+ HPB_CS0 (rwx) : ORIGIN = 0x60000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 0 */
+ HPB_CS1 (rwx) : ORIGIN = 0x70000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 1 */
+}
+
+SECTIONS {
+ .rom :
+ {
+ KEEP(*(.rom_vector))
+ *(.rom_handlers*)
+ } > ROM
+
+ .text :
+ {
+ _text = .;
+ KEEP(*(.isr_vector))
+ EXCLUDE_FILE (*riscv.o) *(.text*) /* program code, exclude RISCV code */
+ *(.rodata*) /* read-only data: "const" */
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* C++ Exception handling */
+ KEEP(*(.eh_frame*))
+ _etext = .;
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ /* These sections allow code to be compiled/linked for HPB addresses, but reside in
+ * flash until copied by code to the external HPB flash device
+ */
+ .hpb_cs0_section :
+ {
+ __hpb_cs0_start = ABSOLUTE(.);
+ KEEP(*(.hpb_cs0_section*))
+ } > HPB_CS0 AT>FLASH
+
+ __load_start_hpb_cs0 = LOADADDR(.hpb_cs0_section);
+ __load_length_hpb_cs0 = SIZEOF(.hpb_cs0_section);
+
+ .hpb_cs1_section :
+ {
+ __hpb_cs1_start = ABSOLUTE(.);
+ KEEP(*(.hpb_cs1_section*))
+ } > HPB_CS1 AT>FLASH
+
+ __load_start_hpb_cs1 = LOADADDR(.hpb_cs1_section);
+ __load_length_hpb_cs1 = SIZEOF(.hpb_cs1_section);
+
+ /* Binary import */
+ .bin_storage :
+ {
+ FILL(0xFF)
+ _bin_start_ = .;
+ KEEP(*(.bin_storage_img))
+ _bin_end_ = .;
+ . = ALIGN(4);
+ } > FLASH
+
+ /* it's used for C++ exception handling */
+ /* we need to keep this to avoid overlapping */
+ .ARM.exidx :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > FLASH
+
+ .data :
+ {
+ _data = ALIGN(., 4);
+ *(vtable)
+ *(.data*) /*read-write initialized data: initialized global variable*/
+
+ /* These array sections are used by __libc_init_array to call static C++ constructors */
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ /* Run the flash programming functions from SRAM */
+ *(.flashprog)
+
+ _edata = ALIGN(., 4);
+ } > SRAM AT>FLASH
+ __load_data = LOADADDR(.data);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ _bss = .;
+ *(.bss*) /*read-write zero initialized data: uninitialized global variable*/
+ *(COMMON)
+ _ebss = ALIGN(., 4);
+ } > SRAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SRAM
+
+ .heap (COPY):
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ *(.heap*)
+ __HeapLimit = ABSOLUTE(__StackLimit);
+ } > SRAM
+
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
diff --git a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..e5a76af85c
--- /dev/null
+++ b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "mxc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake.
+
+The Evaluation Kit is shipped with a CMSIS-DAP compatible debug probe. However,
+at the time of writing, the necessary flashing algorithms for OpenOCD have not
+yet been incorporated into the OpenOCD master branch. To utilize the provided
+debug probes, please install the bundled MSDK package which includes the
+appropriate OpenOCD modifications. To leverage this OpenOCD instance, run the
+`flash-msdk` Makefile rule, or `-msdk` CMake target.
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.cmake b/hw/bsp/max78002/boards/max78002evkit/board.cmake
new file mode 100644
index 0000000000..9dc6962eb9
--- /dev/null
+++ b/hw/bsp/max78002/boards/max78002evkit/board.cmake
@@ -0,0 +1 @@
+# Nothing to be done at the board level
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.h b/hw/bsp/max78002/boards/max78002evkit/board.h
new file mode 100644
index 0000000000..f8102c3946
--- /dev/null
+++ b/hw/bsp/max78002/boards/max78002evkit/board.h
@@ -0,0 +1,58 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "gpio.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT MXC_GPIO2
+#define LED_PIN MXC_GPIO_PIN_4
+#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH
+#define LED_STATE_ON 1
+
+// Button
+#define BUTTON_PORT MXC_GPIO2
+#define BUTTON_PIN MXC_GPIO_PIN_6
+#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP
+#define BUTTON_STATE_ACTIVE 0
+
+// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL
+#define UART_NUM 0
+#define UART_PORT MXC_GPIO0
+#define UART_VDDIO_BITS 0xF
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/max78002/boards/max78002evkit/board.mk b/hw/bsp/max78002/boards/max78002evkit/board.mk
new file mode 100644
index 0000000000..a813a5327b
--- /dev/null
+++ b/hw/bsp/max78002/boards/max78002evkit/board.mk
@@ -0,0 +1 @@
+# No specific build requirements for the board.
diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c
new file mode 100644
index 0000000000..8d51f141c4
--- /dev/null
+++ b/hw/bsp/max78002/family.c
@@ -0,0 +1,169 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state()
+#endif
+
+#include "gpio.h"
+#include "mxc_sys.h"
+#include "mcr_regs.h"
+#include "mxc_device.h"
+#include "uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "board.h"
+#include "bsp/board_api.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+ tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM);
+
+void board_init(void) {
+#if CFG_TUSB_OS == OPT_OS_NONE
+ // 1ms tick timer
+ SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+ mxc_gpio_cfg_t gpioConfig;
+
+ // LED
+ gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+ gpioConfig.func = MXC_GPIO_FUNC_OUT;
+ gpioConfig.mask = LED_PIN;
+ gpioConfig.pad = MXC_GPIO_PAD_NONE;
+ gpioConfig.port = LED_PORT;
+ gpioConfig.vssel = LED_VDDIO;
+ MXC_GPIO_Config(&gpioConfig);
+ board_led_write(false);
+
+ // Button
+ gpioConfig.drvstr = MXC_GPIO_DRVSTR_0;
+ gpioConfig.func = MXC_GPIO_FUNC_IN;
+ gpioConfig.mask = BUTTON_PIN;
+ gpioConfig.pad = BUTTON_PULL;
+ gpioConfig.port = BUTTON_PORT;
+ gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO;
+ MXC_GPIO_Config(&gpioConfig);
+
+ // UART
+ MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK);
+ UART_PORT->vssel |= UART_VDDIO_BITS; //Set necessary bits to 3.3V
+
+ //USB
+ MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN;
+ MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+#if LED_STATE_ON
+ state = !state;
+#endif
+ if (state) {
+ MXC_GPIO_OutClr(LED_PORT, LED_PIN);
+ } else {
+ MXC_GPIO_OutSet(LED_PORT, LED_PIN);
+ }
+}
+
+uint32_t board_button_read(void) {
+ uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0;
+ return BUTTON_STATE_ACTIVE == state;
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer
+ /* All other 2nd parameter is optional checksum buffer */
+ MXC_SYS_GetUSN(hw_id, NULL);
+
+ size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN);
+ memcpy(id, hw_id, act_len);
+ return act_len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+ int uart_val;
+ int act_len = 0;
+
+ while (act_len < len) {
+ if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) {
+ break;
+ } else {
+ *buf++ = (uint8_t) uart_val;
+ act_len++;
+ }
+ }
+ return act_len;
+}
+
+int board_uart_write(void const *buf, int len) {
+ int act_len = 0;
+ const uint8_t *ch_ptr = (const uint8_t *) buf;
+ while (act_len < len) {
+ MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++);
+ act_len++;
+ }
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+ system_ticks++;
+}
+
+uint32_t board_millis(void) {
+ return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+ __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake
new file mode 100644
index 0000000000..446930bd88
--- /dev/null
+++ b/hw/bsp/max78002/family.cmake
@@ -0,0 +1,166 @@
+include_guard()
+
+set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers)
+set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS)
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# Get the linker file from current location (family)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld)
+set(LD_FILE_Clang ${LD_FILE_GNU})
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(JLINK_DEVICE max78000)
+
+set(FAMILY_MCUS MAX78002 CACHE INTERNAL "")
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ TARGET=MAX78002
+ TARGET_REV=0x4131
+ MXC_ASSERT_ENABLE
+ MAX78002
+ IAR_PRAGMAS=0
+ CFG_TUSB_MCU=OPT_MCU_MAX78002
+ BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ )
+endfunction()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ set(PERIPH_SRC ${MAX32_PERIPH}/Source)
+ add_library(${BOARD_TARGET} STATIC
+ ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/heap.c
+ ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/system_max78002.c
+ ${PERIPH_SRC}/SYS/mxc_assert.c
+ ${PERIPH_SRC}/SYS/mxc_delay.c
+ ${PERIPH_SRC}/SYS/mxc_lock.c
+ ${PERIPH_SRC}/SYS/nvic_table.c
+ ${PERIPH_SRC}/SYS/pins_ai87.c
+ ${PERIPH_SRC}/SYS/sys_ai87.c
+ ${PERIPH_SRC}/AES/aes_ai87.c
+ ${PERIPH_SRC}/AES/aes_revb.c
+ ${PERIPH_SRC}/FLC/flc_common.c
+ ${PERIPH_SRC}/FLC/flc_ai87.c
+ ${PERIPH_SRC}/FLC/flc_reva.c
+ ${PERIPH_SRC}/GPIO/gpio_common.c
+ ${PERIPH_SRC}/GPIO/gpio_ai87.c
+ ${PERIPH_SRC}/GPIO/gpio_reva.c
+ ${PERIPH_SRC}/ICC/icc_ai87.c
+ ${PERIPH_SRC}/ICC/icc_reva.c
+ ${PERIPH_SRC}/TRNG/trng_ai87.c
+ ${PERIPH_SRC}/TRNG/trng_revb.c
+ ${PERIPH_SRC}/UART/uart_common.c
+ ${PERIPH_SRC}/UART/uart_ai87.c
+ ${PERIPH_SRC}/UART/uart_revb.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${MAX32_CMSIS}/Include
+ ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include
+ ${MAX32_PERIPH}/Include/MAX78002
+ ${PERIPH_SRC}/SYS
+ ${PERIPH_SRC}/GPIO
+ ${PERIPH_SRC}/AES
+ ${PERIPH_SRC}/TRNG
+ ${PERIPH_SRC}/ICC
+ ${PERIPH_SRC}/FLC
+ ${PERIPH_SRC}/UART
+ )
+
+ target_compile_options(${BOARD_TARGET} PRIVATE
+ -Wno-error=strict-prototypes
+ -Wno-error=redundant-decls
+ )
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ target_compile_options(${TARGET} PRIVATE
+ -Wno-error=strict-prototypes
+ -Wno-error=redundant-decls
+ )
+
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_MAX78002 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/mentor/musb/dcd_musb.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+ target_compile_options(${TARGET}-tinyusb PRIVATE
+ -Wno-error=strict-prototypes
+ -Wno-error=redundant-decls
+ )
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ family_flash_msdk(${TARGET})
+endfunction()
+
+# Add flash msdk target
+function(family_flash_msdk TARGET)
+ set(MAXIM_PATH "$ENV{MAXIM_PATH}")
+
+ add_custom_target(${TARGET}-msdk
+ DEPENDS ${TARGET}
+ COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts
+ -f interface/cmsis-dap.cfg -f target/max78002.cfg
+ -c "program $ verify; init; reset; exit"
+ VERBATIM
+ )
+endfunction()
diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk
new file mode 100644
index 0000000000..997816261f
--- /dev/null
+++ b/hw/bsp/max78002/family.mk
@@ -0,0 +1,99 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32
+
+# Important locations in the hw support for MCU
+MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS
+MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers
+
+# Add any board specific make rules
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m4
+PORT ?= 0
+
+# GCC
+SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S
+LD_FILE = $(FAMILY_PATH)/max78002.ld
+
+# --------------
+# Compiler Flags
+# --------------
+# Flags for the MAX78002 SDK
+CFLAGS += -DTARGET=MAX78002 \
+ -DTARGET_REV=0x4131 \
+ -DMXC_ASSERT_ENABLE \
+ -DMAX78002 \
+ -DIAR_PRAGMAS=0
+
+# Flags for TUSB features
+CFLAGS += \
+ -DCFG_TUSB_MCU=OPT_MCU_MAX78002 \
+ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=redundant-decls \
+ -Wno-error=strict-prototypes \
+ -Wno-error=unused-parameter \
+ -Wno-error=enum-conversion \
+ -Wno-error=sign-compare \
+ -Wno-error=cast-qual
+
+LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs
+
+# For flash-jlink target
+JLINK_DEVICE = max78000
+
+# flash target using Jlink by default
+flash: flash-jlink
+
+# Optional flash option when running within an installed MSDK to use OpenOCD
+# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated.
+# If the MSDK is installed, flash-msdk can be run to utilize the the modified
+# openocd with the algorithms
+MAXIM_PATH := $(subst \,/,$(MAXIM_PATH))
+flash-msdk: $(BUILD)/$(PROJECT).elf
+ $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \
+ -f interface/cmsis-dap.cfg -f target/max78002.cfg \
+ -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit"
+
+# -----------------
+# Sources & Include
+# -----------------
+PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source
+SRC_C += \
+ src/portable/mentor/musb/dcd_musb.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \
+ $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \
+ $(PERIPH_SRC)/SYS/mxc_assert.c \
+ $(PERIPH_SRC)/SYS/mxc_delay.c \
+ $(PERIPH_SRC)/SYS/mxc_lock.c \
+ $(PERIPH_SRC)/SYS/nvic_table.c \
+ $(PERIPH_SRC)/SYS/pins_ai87.c \
+ $(PERIPH_SRC)/SYS/sys_ai87.c \
+ $(PERIPH_SRC)/AES/aes_ai87.c \
+ $(PERIPH_SRC)/AES/aes_revb.c \
+ $(PERIPH_SRC)/FLC/flc_common.c \
+ $(PERIPH_SRC)/FLC/flc_ai87.c \
+ $(PERIPH_SRC)/FLC/flc_reva.c \
+ $(PERIPH_SRC)/GPIO/gpio_common.c \
+ $(PERIPH_SRC)/GPIO/gpio_ai87.c \
+ $(PERIPH_SRC)/GPIO/gpio_reva.c \
+ $(PERIPH_SRC)/ICC/icc_ai87.c \
+ $(PERIPH_SRC)/ICC/icc_reva.c \
+ $(PERIPH_SRC)/TRNG/trng_ai87.c \
+ $(PERIPH_SRC)/TRNG/trng_revb.c \
+ $(PERIPH_SRC)/UART/uart_common.c \
+ $(PERIPH_SRC)/UART/uart_ai87.c \
+ $(PERIPH_SRC)/UART/uart_revb.c \
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(MAX32_CMSIS)/Include \
+ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \
+ $(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \
+ $(PERIPH_SRC)/SYS \
+ $(PERIPH_SRC)/GPIO \
+ $(PERIPH_SRC)/AES \
+ $(PERIPH_SRC)/ICC \
+ $(PERIPH_SRC)/FLC \
+ $(PERIPH_SRC)/TRNG \
+ $(PERIPH_SRC)/UART
diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/max78002/max78002.ld
new file mode 100644
index 0000000000..e5c4866ee0
--- /dev/null
+++ b/hw/bsp/max78002/max78002.ld
@@ -0,0 +1,182 @@
+MEMORY {
+ ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64 kB ROM */
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00280000 /* 2.5 MB Flash */
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00060000 /* 384 kB SRAM */
+ /*CSI2 (rwx) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 4096 B CSI2 Buffer */
+}
+
+SECTIONS {
+ .rom :
+ {
+ KEEP(*(.rom_vector))
+ *(.rom_handlers*)
+ } > ROM
+
+ .text :
+ {
+ _text = .;
+ KEEP(*(.isr_vector))
+ EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */
+ *(.rodata*) /* read-only data: "const" */
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* C++ Exception handling */
+ KEEP(*(.eh_frame*))
+ _etext = .;
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ /* Binary import */
+ .bin_storage :
+ {
+ FILL(0xFF)
+ _bin_start_ = .;
+ KEEP(*(.bin_storage_img))
+ _bin_end_ = .;
+ . = ALIGN(4);
+ } > FLASH
+
+ .rom_code :
+ {
+ . = ALIGN(16);
+ _sran_code = .;
+ *(.rom_code_section)
+ _esran_code = .;
+ } > ROM
+
+ .flash_code :
+ {
+ . = ALIGN(16);
+ _sran_code = .;
+ *(.flash_code_section)
+ _esran_code = .;
+ } > FLASH
+
+ .sram_code :
+ {
+ . = ALIGN(16);
+ _sran_code = .;
+ *(.sram_code_section)
+ _esran_code = .;
+ } > SRAM
+
+ /* it's used for C++ exception handling */
+ /* we need to keep this to avoid overlapping */
+ .ARM.exidx :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > FLASH
+
+ .data :
+ {
+ _data = ALIGN(., 4);
+ _csi = . + 0x20000;
+ *(vtable)
+ *(.data*) /*read-write initialized data: initialized global variable*/
+
+
+ /* These array sections are used by __libc_init_array to call static C++ constructors */
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ _edata = ALIGN(., 4);
+
+ } > SRAM AT>FLASH
+ __load_data = LOADADDR(.data);
+
+ .bss :
+ {
+ . = ALIGN(4);
+ _bss = .;
+ *(.bss*) /*read-write zero initialized data: uninitialized global variable*/
+ *(COMMON)
+ _ebss = ALIGN(., 4);
+ } > SRAM
+
+ .shared :
+ {
+ . = ALIGN(4);
+ _shared = .;
+ *(.mailbox*)
+ . = ALIGN(4);
+ *(.shared*) /*read-write zero initialized data: uninitialized global variable*/
+ _eshared = ALIGN(., 4);
+ } > SRAM
+ __shared_data = LOADADDR(.shared);
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SRAM
+
+ .heap (COPY):
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ *(.heap*)
+ __HeapLimit = ABSOLUTE(__StackLimit);
+ } > SRAM
+
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+
+ /* Section used by RISCV loader projects. See RISCV_LOAD documentation in the build system. */
+ .riscv_flash :
+ {
+ /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/
+ . = ALIGN(256); /* ALIGN operatator is used here. Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/
+ . += 0x100;
+ _riscv_boot = .;
+ KEEP(*riscv.o (.text*))
+ } > FLASH
+}
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index cc675a49d3..ce54097fe1 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -33,39 +33,23 @@
#include "pin_mux.h"
#include "clock_config.h"
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#ifdef BOARD_TUD_RHPORT
- #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
-#else
- #define PORT_SUPPORT_DEVICE(_n) 0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
- #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n)
-#else
- #define PORT_SUPPORT_HOST(_n) 0
-#endif
-
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
#if CFG_TUSB_MCU == OPT_MCU_MCXN9
void USB0_FS_IRQHandler(void) {
- tud_int_handler(0);
+ tusb_int_handler(0, true);
}
void USB1_HS_IRQHandler(void) {
- tud_int_handler(1);
+ tusb_int_handler(1, true);
}
#elif CFG_TUSB_MCU == OPT_MCU_MCXA15
void USB0_IRQHandler(void) {
- tud_int_handler(0);
+ tusb_int_handler(0, true);
}
#endif
@@ -133,7 +117,7 @@ void board_init(void) {
// USB VBUS
/* PORT0 PIN22 configured as USB0_VBUS */
-#if PORT_SUPPORT_DEVICE(0)
+#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
// Port0 is Full Speed
#if CFG_TUSB_MCU == OPT_MCU_MCXA15
@@ -147,7 +131,7 @@ void board_init(void) {
CLOCK_EnableUsbfsClock();
#endif
-#if PORT_SUPPORT_DEVICE(1) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
+#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1 && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
// Port1 is High Speed
// Power
diff --git a/hw/bsp/mm32/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mm32/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..6622cf801b
--- /dev/null
+++ b/hw/bsp/mm32/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,150 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "mm32_device.h"
+ extern u32 SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 0
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<CFGR &= ~(0x3 << 22);
- RCC->CFGR |= (0x1 << 22);
-
- /* Enable USB clock */
- RCC->AHB2ENR |= 0x1 << 7;
-}
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-
-extern u32 SystemCoreClock;
-const int baudrate = 115200;
-
-void board_init (void)
-{
-// usb clock
- USB_DeviceClockInit();
-
- if ( SysTick_Config(SystemCoreClock / 1000) )
- {
- while ( 1 )
- ;
- }
- NVIC_SetPriority(SysTick_IRQn, 0x0);
-
- // LED on PB2
- GPIO_InitTypeDef GPIO_InitStruct;
- RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, ENABLE);
- GPIO_StructInit(&GPIO_InitStruct);
-
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2;
- GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_Init(GPIOB, &GPIO_InitStruct);
-
- board_led_write(true);
-
- // KEY on PA0
- RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
- GPIO_StructInit(&GPIO_InitStruct);
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_0;
- GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPD;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
-
- // UART
- UART_InitTypeDef UART_InitStruct;
-
- RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock
- RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); //
- //UART initialset
-
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
-
- UART_StructInit(&UART_InitStruct);
- UART_InitStruct.UART_BaudRate = baudrate;
- UART_InitStruct.UART_WordLength = UART_WordLength_8b;
- UART_InitStruct.UART_StopBits = UART_StopBits_1; //one stopbit
- UART_InitStruct.UART_Parity = UART_Parity_No; //none odd-even verify bit
- UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None; //No hardware flow control
- UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent mode
-
- UART_Init(UART1, &UART_InitStruct); //initial uart 1
- UART_Cmd(UART1, ENABLE); //enable uart 1
-
- //UART1_TX GPIOA.9
- GPIO_StructInit(&GPIO_InitStruct);
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
-
- //UART1_RX GPIOA.10
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-}
-
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write (bool state)
-{
- state ? (GPIO_ResetBits(GPIOB, GPIO_Pin_2)) : (GPIO_SetBits(GPIOB, GPIO_Pin_2));
-}
-
-uint32_t board_button_read (void)
-{
- uint32_t key = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) == Bit_SET;
- return key;
-}
-
-int board_uart_read (uint8_t *buf, int len)
-{
- (void) buf;
- (void) len;
- return 0;
-}
-
-int board_uart_write (void const *buf, int len)
-{
- const char *buff = buf;
- while ( len )
- {
- while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
- ; //The loop is sent until it is finished
- UART1->TDR = (*buff & 0xFF);
- buff++;
- len--;
- }
- return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
- system_ticks++;
-}
-
-uint32_t board_millis (void)
-{
- return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.cmake b/hw/bsp/mm32/boards/mm32f327x_mb39/board.cmake
new file mode 100644
index 0000000000..4f3d145cf0
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT mm32f327x)
+set(JLINK_DEVICE MM32F3273G9P)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/flash.ld)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ HSE_VALUE=8000000
+ )
+endfunction()
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.h b/hw/bsp/mm32/boards/mm32f327x_mb39/board.h
new file mode 100644
index 0000000000..3ac048cf13
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.h
@@ -0,0 +1,19 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+// GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15); //Disable JTDI AF to AF15
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_Pin_15
+#define LED_STATE_ON 1
+
+//#define BUTTON_PORT GPIOC
+//#define BUTTON_PIN GPIO_PIN_13
+//#define BUTTON_STATE_ACTIVE 1
+
+#define UART_DEV UART1
+#define UART_GPIO_PORT GPIOA
+#define UART_GPIO_AF GPIO_AF_7
+#define UART_TX_PIN 9
+#define UART_RX_PIN 10
+
+#endif
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
index a0d92d1c7e..f6d18315d4 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
@@ -1,12 +1,9 @@
+MCU_VARIANT = mm32f327x
CFLAGS += \
-DHSE_VALUE=8000000
-LD_FILE = $(BOARD_PATH)/flash.ld
-SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
-
+JLINK_DEVICE = MM32F3273G9P
-# For flash-jlink target
-#JLINK_DEVICE = stm32f411ve
+LD_FILE = $(BOARD_PATH)/flash.ld
-# flash target using on-board stlink
-#flash: flash-jlink
+flash: flash-jlink
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
deleted file mode 100644
index 086532179d..0000000000
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 MM32 SE TEAM
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "mm32_device.h"
-#include "hal_conf.h"
-#include "tusb.h"
-#include "bsp/board_api.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler (void)
-{
- tud_int_handler(0);
-
-}
-void USB_DeviceClockInit (void)
-{
- /* Select USBCLK source */
- // RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
- RCC->CFGR &= ~(0x3 << 22);
- RCC->CFGR |= (0x1 << 22);
-
- /* Enable USB clock */
- RCC->AHB2ENR |= 0x1 << 7;
-}
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-
-extern u32 SystemCoreClock;
-const int baudrate = 115200;
-
-void board_init (void)
-{
-// usb clock
- USB_DeviceClockInit();
-
- if ( SysTick_Config(SystemCoreClock / 1000) )
- {
- while ( 1 )
- ;
- }
- NVIC_SetPriority(SysTick_IRQn, 0x0);
-
- // LED
- GPIO_InitTypeDef GPIO_InitStruct;
- RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
- GPIO_StructInit(&GPIO_InitStruct);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15); //Disable JTDI AF to AF15
-
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15;
- GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
-
- board_led_write(true);
-
- // UART
- UART_InitTypeDef UART_InitStruct;
-
- RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock
- RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); //
- //UART initialset
-
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
-
- UART_StructInit(&UART_InitStruct);
- UART_InitStruct.UART_BaudRate = baudrate;
- UART_InitStruct.UART_WordLength = UART_WordLength_8b;
- UART_InitStruct.UART_StopBits = UART_StopBits_1; //one stopbit
- UART_InitStruct.UART_Parity = UART_Parity_No; //none odd-even verify bit
- UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None; //No hardware flow control
- UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent mode
-
- UART_Init(UART1, &UART_InitStruct); //initial uart 1
- UART_Cmd(UART1, ENABLE); //enable uart 1
-
- //UART1_TX GPIOA.9
- GPIO_StructInit(&GPIO_InitStruct);
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
- GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
-
- //UART1_RX GPIOA.10
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write (bool state)
-{
- state ? (GPIO_ResetBits(GPIOA, GPIO_Pin_15)) : (GPIO_SetBits(GPIOA, GPIO_Pin_15));
-}
-
-uint32_t board_button_read (void)
-{
- return 0;
-}
-
-int board_uart_read (uint8_t *buf, int len)
-{
- (void) buf;
- (void) len;
- return 0;
-}
-
-int board_uart_write (void const *buf, int len)
-{
- const char *buff = buf;
- while ( len )
- {
- while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
- ; //The loop is sent until it is finished
- UART1->TDR = (*buff & 0xFF);
- buff++;
- len--;
- }
- return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
- system_ticks++;
-}
-
-uint32_t board_millis (void)
-{
- return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.cmake b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.cmake
new file mode 100644
index 0000000000..4de25e2c41
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT mm32f327x)
+set(JLINK_DEVICE MM32F3273G8P)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/flash.ld)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ HSE_VALUE=12000000
+ )
+endfunction()
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h
new file mode 100644
index 0000000000..2b3f54a601
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h
@@ -0,0 +1,14 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+// GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15); //Disable JTDI AF to AF15
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_Pin_1
+#define LED_STATE_ON 1
+
+#define BUTTON_PORT GPIOA
+#define BUTTON_PIN GPIO_Pin_0
+#define BUTTON_STATE_ACTIVE 0
+
+
+#endif
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
index a778e749f4..dbcd314c82 100644
--- a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
@@ -1,11 +1,12 @@
+MCU_VARIANT = mm32f327x
+
CFLAGS += \
-DHSE_VALUE=12000000
LD_FILE = $(BOARD_PATH)/flash.ld
-SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
# For flash-jlink target
-#JLINK_DEVICE = MM32F3273G8P
+JLINK_DEVICE = MM32F3273G8P
# flash target using on-board stlink
#flash: flash-jlink
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c b/hw/bsp/mm32/family.c
similarity index 61%
rename from hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
rename to hw/bsp/mm32/family.c
index bd2d36ae0a..f0fd6d334d 100644
--- a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
+++ b/hw/bsp/mm32/family.c
@@ -24,23 +24,35 @@
* This file is part of the TinyUSB stack.
*/
-/* DshanMCU Pitaya Lite with MM32F3273 */
-
-#include "mm32_device.h"
#include "hal_conf.h"
-#include "tusb.h"
+#include "mm32_device.h"
+
#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+#ifdef __GNUC__ // caused by extra declaration of SystemCoreClock in freeRTOSConfig.h
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
+extern u32 SystemCoreClock;
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler (void)
-{
+void OTG_FS_IRQHandler(void) {
tud_int_handler(0);
-
}
-void USB_DeviceClockInit (void)
-{
+
+void USB_DeviceClockInit(void) {
/* Select USBCLK source */
// RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
RCC->CFGR &= ~(0x3 << 22);
@@ -49,134 +61,117 @@ void USB_DeviceClockInit (void)
/* Enable USB clock */
RCC->AHB2ENR |= 0x1 << 7;
}
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-extern u32 SystemCoreClock;
-const int baudrate = 115200;
-
-void board_init (void)
-{
+void board_init(void) {
// usb clock
-// requires SYSCLK_FREQ_XXMHz (HSE_VALUE*8) in system_mm32f327x.c
USB_DeviceClockInit();
- if ( SysTick_Config(SystemCoreClock / 1000) )
- {
- while ( 1 )
- ;
- }
+ SysTick_Config(SystemCoreClock / 1000);
NVIC_SetPriority(SysTick_IRQn, 0x0);
- // LED on PA1
- GPIO_InitTypeDef GPIO_InitStruct;
RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
- GPIO_StructInit(&GPIO_InitStruct);
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_1;
+ // LED
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_StructInit(&GPIO_InitStruct);
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOA, &GPIO_InitStruct);
board_led_write(true);
- // KEY on PA0
+ #ifdef BUTTON_PORT
GPIO_StructInit(&GPIO_InitStruct);
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_0;
+ GPIO_InitStruct.GPIO_Pin = BUTTON_PIN;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
- GPIO_InitStruct.GPIO_Mode = GPIO_Mode_FLOATING;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
+ GPIO_InitStruct.GPIO_Mode = BUTTON_STATE_ACTIVE ? GPIO_Mode_IPD : GPIO_Mode_IPU;
+ GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+ #endif
+ #ifdef UART_DEV
// UART
UART_InitTypeDef UART_InitStruct;
- RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock
- RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); //
- //UART initialset
-
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
- GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+ RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock
+ GPIO_PinAFConfig(GPIOA, UART_TX_PIN, UART_GPIO_AF);
+ GPIO_PinAFConfig(GPIOA, UART_RX_PIN, UART_GPIO_AF);
UART_StructInit(&UART_InitStruct);
- UART_InitStruct.UART_BaudRate = baudrate;
+ UART_InitStruct.UART_BaudRate = CFG_BOARD_UART_BAUDRATE;
UART_InitStruct.UART_WordLength = UART_WordLength_8b;
- UART_InitStruct.UART_StopBits = UART_StopBits_1; //one stopbit
- UART_InitStruct.UART_Parity = UART_Parity_No; //none odd-even verify bit
- UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None; //No hardware flow control
- UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent mode
+ UART_InitStruct.UART_StopBits = UART_StopBits_1;
+ UART_InitStruct.UART_Parity = UART_Parity_No;
+ UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
+ UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
- UART_Init(UART1, &UART_InitStruct); //initial uart 1
- UART_Cmd(UART1, ENABLE); //enable uart 1
+ UART_Init(UART_DEV, &UART_InitStruct);
+ UART_Cmd(UART_DEV, ENABLE);
- //UART1_TX GPIOA.9
GPIO_StructInit(&GPIO_InitStruct);
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+ GPIO_InitStruct.GPIO_Pin = 1 << UART_TX_PIN;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
+ GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
- //UART1_RX GPIOA.10
- GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+ GPIO_InitStruct.GPIO_Pin = 1 << UART_RX_PIN;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_Init(GPIOA, &GPIO_InitStruct);
-
+ GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+ #endif
}
-
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write (bool state)
-{
- state ? (GPIO_ResetBits(GPIOA, GPIO_Pin_1)) : (GPIO_SetBits(GPIOA, GPIO_Pin_1));
+void board_led_write(bool state) {
+ GPIO_WriteBit(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
}
-uint32_t board_button_read (void)
-{
- uint32_t key = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) == Bit_RESET;
- return key;
+uint32_t board_button_read(void) {
+#ifdef BUTTON_PORT
+ return GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN) == BUTTON_STATE_ACTIVE;
+#else
+ return 0;
+#endif
}
-int board_uart_read (uint8_t *buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
(void) buf;
(void) len;
return 0;
}
-int board_uart_write (void const *buf, int len)
-{
- const char *buff = buf;
- while ( len )
- {
- while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
- ; //The loop is sent until it is finished
+int board_uart_write(void const* buf, int len) {
+ #ifdef UART_DEV
+ const char* buff = buf;
+ while (len) {
+ while ((UART1->CSR & UART_IT_TXIEN) == 0); //The loop is sent until it is finished
UART1->TDR = (*buff & 0xFF);
buff++;
len--;
}
return len;
+ #else
+ (void) buf;
+ (void) len;
+ return 0;
+ #endif
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
system_ticks++;
}
-uint32_t board_millis (void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
#endif
// Required by __libc_init_array in startup code if we are compiling using
// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
}
diff --git a/hw/bsp/mm32/family.cmake b/hw/bsp/mm32/family.cmake
new file mode 100644
index 0000000000..bf315acaa9
--- /dev/null
+++ b/hw/bsp/mm32/family.cmake
@@ -0,0 +1,101 @@
+include_guard()
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+string(REPLACE "mm32f" "MM32F" MCU_VARIANT_UPPER ${MCU_VARIANT})
+set(SDK_DIR ${TOP}/hw/mcu/mindmotion/mm32sdk/${MCU_VARIANT_UPPER})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS MM32F327X CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${SDK_DIR}/Source/GCC_StartAsm/startup_${MCU_VARIANT}_gcc.s)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+ set(STARTUP_FILE_IAR ${SDK_DIR}/Source/IAR_StartAsm/startup_${MCU_VARIANT}_iar.s)
+
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+ # set(LD_FILE_IAR )
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/Source/system_${MCU_VARIANT}.c
+ ${SDK_DIR}/HAL_Lib/Src/hal_gpio.c
+ ${SDK_DIR}/HAL_Lib/Src/hal_rcc.c
+ ${SDK_DIR}/HAL_Lib/Src/hal_uart.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMSIS_5}/CMSIS/Core/Include
+ ${SDK_DIR}/Include
+ ${SDK_DIR}/HAL_Lib/Inc
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_MM32F327X ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
index 3981e4e410..a790663ab9 100644
--- a/hw/bsp/mm32/family.mk
+++ b/hw/bsp/mm32/family.mk
@@ -1,32 +1,33 @@
UF2_FAMILY_ID = 0x0
-SDK_DIR = hw/mcu/mindmotion/mm32sdk
-DEPS_SUBMODULES += lib/CMSIS_5 $(SDK_DIR)
-
include $(TOP)/$(BOARD_PATH)/board.mk
+
+MCU_VARIANT_UPPER = $(subst mm32f,MM32F,${MCU_VARIANT})
+SDK_DIR = hw/mcu/mindmotion/mm32sdk/${MCU_VARIANT_UPPER}
+
CPU_CORE ?= cortex-m3
CFLAGS += \
-flto \
- -nostdlib -nostartfiles \
- -DCFG_TUSB_MCU=OPT_MCU_MM32F327X
+ -DCFG_TUSB_MCU=OPT_MCU_MM32F327X \
# suppress warning caused by vendor mcu driver
CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=cast-qual
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+LDFLAGS_GCC += \
+ -nostdlib -nostartfiles \
+ -specs=nosys.specs -specs=nano.specs \
SRC_C += \
src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \
- $(SDK_DIR)/mm32f327x/MM32F327x/Source/system_mm32f327x.c \
- $(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c \
- $(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c \
- $(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c \
+ $(SDK_DIR)/Source/system_${MCU_VARIANT}.c \
+ $(SDK_DIR)/HAL_Lib/Src/hal_gpio.c \
+ $(SDK_DIR)/HAL_Lib/Src/hal_rcc.c \
+ $(SDK_DIR)/HAL_Lib/Src/hal_uart.c \
+
+SRC_S += ${SDK_DIR}/Source/GCC_StartAsm/startup_${MCU_VARIANT}_gcc.s
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
- $(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/Include \
- $(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
-
-# flash target using on-board
-flash: flash-jlink
+ $(TOP)/$(SDK_DIR)/Include \
+ $(TOP)/$(SDK_DIR)/HAL_Lib/Inc
diff --git a/hw/bsp/msp430/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/msp430/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..4049fba650
--- /dev/null
+++ b/hw/bsp/msp430/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "msp430.h"
+#endif
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+#define configCPU_CLOCK_HZ ( ( unsigned long ) 7995392 ) /* Clock setup from main.c in the demo application. */
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES ( 4 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 50 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1700 ) )
+#define configMAX_TASK_NAME_LEN ( 8 )
+#define configUSE_TRACE_FACILITY 0
+#define configUSE_16_BIT_TICKS 1
+#define configIDLE_SHOULD_YIELD 1
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/hw/bsp/msp432e4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/msp432e4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..3dd5a1ee1f
--- /dev/null
+++ b/hw/bsp/msp432e4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "msp.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<unique_id_bytes, max_len);
+ return max_len;
+}
+
int board_uart_read(uint8_t *buf, int len) {
(void) buf;
(void) len;
@@ -169,50 +176,25 @@ void SysTick_Handler(void) {
uint32_t board_millis(void) {
return system_ticks;
}
-
#endif
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-#if CFG_TUD_ENABLED && defined(BOARD_TUD_RHPORT)
- #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
-#else
- #define PORT_SUPPORT_DEVICE(_n) 0
-#endif
-
-#if CFG_TUH_ENABLED && defined(BOARD_TUH_RHPORT)
- #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n)
-#else
- #define PORT_SUPPORT_HOST(_n) 0
-#endif
-
//------------- USB0 FullSpeed -------------//
void usbfs_interrupt_handler(void) {
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
- #if PORT_SUPPORT_HOST(0)
- tuh_int_handler(0, true);
- #endif
-
- #if PORT_SUPPORT_DEVICE(0)
- tud_int_handler(0);
- #endif
+ tusb_int_handler(0, true);
}
void usbfs_resume_handler(void) {
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
- #if PORT_SUPPORT_HOST(0)
- tuh_int_handler(0, true);
- #endif
-
- #if PORT_SUPPORT_DEVICE(0)
- tud_int_handler(0);
- #endif
+ tusb_int_handler(0, true);
}
void usbfs_d0fifo_handler(void) {
@@ -234,13 +216,7 @@ void usbhs_interrupt_handler(void) {
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
- #if PORT_SUPPORT_HOST(1)
- tuh_int_handler(1, true);
- #endif
-
- #if PORT_SUPPORT_DEVICE(1)
- tud_int_handler(1);
- #endif
+ tusb_int_handler(1, true);
}
void usbhs_d0fifo_handler(void) {
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index 3849894ce2..733e937975 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -78,7 +78,12 @@
// USB Host MAX3421E
//--------------------------------------------------------------------
-#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE
+#ifdef PICO_DEFAULT_SPI
+#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2
+#else
+#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1
+#endif
+
#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN
#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN
#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN
diff --git a/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake
index b8e5890f3f..2afe0f2649 100644
--- a/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake
+++ b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake
@@ -1,3 +1,4 @@
+set(PICO_PLATFORM rp2040)
set(PICO_BOARD adafruit_feather_rp2040)
# Enable MAX3421E USB Host
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
index f9887c09c4..804cdb50a5 100644
--- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
@@ -1 +1,2 @@
+set(PICO_PLATFORM rp2040)
set(PICO_BOARD pico)
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake
new file mode 100644
index 0000000000..3482e2674e
--- /dev/null
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake
@@ -0,0 +1,2 @@
+set(PICO_PLATFORM rp2350-arm-s)
+set(PICO_BOARD pico2)
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index cffb632f34..ccc1e1f706 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -31,6 +31,7 @@
#include "hardware/gpio.h"
#include "hardware/sync.h"
#include "hardware/resets.h"
+#include "hardware/clocks.h"
#include "hardware/structs/ioqspi.h"
#include "hardware/structs/sio.h"
@@ -41,7 +42,7 @@
static uart_inst_t *uart_inst;
#endif
-#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
+#if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB)
#include "pio_usb.h"
#endif
@@ -125,7 +126,7 @@ void stdio_rtt_init(void) {
void board_init(void)
{
-#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
+#if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB)
// Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
set_sys_clock_khz(120000, true);
@@ -204,7 +205,9 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) {
pico_get_unique_board_id(&pico_id);
size_t len = PICO_UNIQUE_BOARD_ID_SIZE_BYTES;
- if (len > max_len) len = max_len;
+ if (len > max_len) {
+ len = max_len;
+ }
memcpy(id, pico_id.id, len);
return len;
@@ -274,7 +277,15 @@ static void max3421_init(void) {
gpio_set_function(MAX3421_SCK_PIN, GPIO_FUNC_SPI);
gpio_set_function(MAX3421_MOSI_PIN, GPIO_FUNC_SPI);
gpio_set_function(MAX3421_MISO_PIN, GPIO_FUNC_SPI);
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wnull-dereference"
+#endif
spi_set_format(MAX3421_SPI, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
}
//// API to enable/disable MAX3421 INTR pin interrupt
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index a298e684b6..8f01eac749 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -6,21 +6,32 @@ if (NOT BOARD)
set(BOARD pico_sdk)
endif()
-if (TOOLCHAIN STREQUAL "clang")
- set(PICO_COMPILER "pico_arm_clang")
-else()
- set(PICO_COMPILER "pico_arm_gcc")
-endif()
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+#if (TOOLCHAIN STREQUAL "clang")
+# set(PICO_COMPILER "pico_arm_clang")
+#else()
+# set(PICO_COMPILER "pico_arm_gcc")
+#endif()
# add the SDK in case we are standalone tinyusb example (noop if already present)
include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake)
# include basic family CMake functionality
set(FAMILY_MCUS RP2040)
-set(JLINK_DEVICE rp2040_m0_0)
-set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"")
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+if (PICO_PLATFORM STREQUAL "rp2040")
+ set(JLINK_DEVICE rp2040_m0_0)
+ set(OPENOCD_TARGET rp2040)
+elseif (PICO_PLATFORM STREQUAL "rp2350-arm-s" OR PICO_PLATFORM STREQUAL "rp2350")
+ set(JLINK_DEVICE rp2350_m33_0)
+ set(OPENOCD_TARGET rp2350)
+elseif (PICO_PLATFORM STREQUAL "rp2350-riscv")
+ set(JLINK_DEVICE rp2350_riscv_0)
+ set(OPENOCD_TARGET rp2350-riscv)
+endif()
+
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${OPENOCD_TARGET}.cfg -c \"adapter speed 5000\"")
if (NOT PICO_TINYUSB_PATH)
set(PICO_TINYUSB_PATH ${TOP})
@@ -133,7 +144,10 @@ target_sources(tinyusb_bsp INTERFACE
target_include_directories(tinyusb_bsp INTERFACE
${TOP}/hw
)
-target_link_libraries(tinyusb_bsp INTERFACE pico_unique_id)
+target_link_libraries(tinyusb_bsp INTERFACE
+ pico_unique_id
+ hardware_clocks
+ )
# tinyusb_additions will hold our extra settings for examples
add_library(tinyusb_additions INTERFACE)
@@ -175,11 +189,16 @@ function(family_configure_target TARGET RTOS)
# export RTOS_SUFFIX to parent scope
set(RTOS_SUFFIX ${RTOS_SUFFIX} PARENT_SCOPE)
+ # compile define from command line
+ if(DEFINED CFLAGS_CLI)
+ target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI})
+ endif()
+
pico_add_extra_outputs(${TARGET})
pico_enable_stdio_uart(${TARGET} 1)
target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_board${RTOS_SUFFIX} tinyusb_additions)
- family_flash_openocd(${TARGET} ${OPENOCD_OPTION})
+ family_flash_openocd(${TARGET})
family_flash_jlink(${TARGET})
endfunction()
diff --git a/hw/bsp/samd11/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd11/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..6c9ecae2df
--- /dev/null
+++ b/hw/bsp/samd11/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
#define configENABLE_TRUSTZONE 0
#define configMINIMAL_SECURE_STACK_SIZE (1024)
diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake
index 540a0ee338..c836b85d91 100644
--- a/hw/bsp/samd21/family.cmake
+++ b/hw/bsp/samd21/family.cmake
@@ -26,9 +26,7 @@ function(add_board_target BOARD_TARGET)
message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
endif ()
- if (NOT DEFINED STARTUP_FILE_GNU)
- set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_samd21.c)
- endif ()
+ set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_samd21.c)
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
add_library(${BOARD_TARGET} STATIC
@@ -50,7 +48,9 @@ function(add_board_target BOARD_TARGET)
${SDK_DIR}/hri
${SDK_DIR}/CMSIS/Include
)
- target_compile_definitions(${BOARD_TARGET} PUBLIC CONF_DFLL_OVERWRITE_CALIBRATION=0)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CONF_DFLL_OVERWRITE_CALIBRATION=0
+ )
update_board(${BOARD_TARGET})
@@ -108,5 +108,5 @@ function(family_configure_example TARGET RTOS)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
- #family_flash_openocd(${TARGET} ${OPENOCD_OPTION})
+ #family_flash_openocd(${TARGET})
endfunction()
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index aabcff4a24..08c5c5b0ec 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -25,14 +25,14 @@ SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
${SDK_DIR}/gcc/gcc/startup_samd21.c \
${SDK_DIR}/gcc/system_samd21.c \
+ ${SDK_DIR}/hal/src/hal_atomic.c \
${SDK_DIR}/hpl/gclk/hpl_gclk.c \
${SDK_DIR}/hpl/pm/hpl_pm.c \
${SDK_DIR}/hpl/sysctrl/hpl_sysctrl.c \
- ${SDK_DIR}/hal/src/hal_atomic.c
INC += \
$(TOP)/$(BOARD_PATH) \
- $(TOP)/${SDK_DIR}/ \
+ $(TOP)/${SDK_DIR} \
$(TOP)/${SDK_DIR}/config \
$(TOP)/${SDK_DIR}/include \
$(TOP)/${SDK_DIR}/hal/include \
@@ -40,7 +40,7 @@ INC += \
$(TOP)/${SDK_DIR}/hpl/pm/ \
$(TOP)/${SDK_DIR}/hpl/port \
$(TOP)/${SDK_DIR}/hri \
- $(TOP)/${SDK_DIR}/CMSIS/Include
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
# flash using bossac at least version 1.8
# can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/samd51/boards/pyportal/board.cmake b/hw/bsp/samd51/boards/pyportal/board.cmake
deleted file mode 100644
index d83211d9ec..0000000000
--- a/hw/bsp/samd51/boards/pyportal/board.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(JLINK_DEVICE ATSAMD51J19)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
-
-function(update_board TARGET)
- target_compile_definitions(${TARGET} PUBLIC
- __SAMD51J19A__
- )
-endfunction()
diff --git a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd5x_e5x/FreeRTOSConfig/FreeRTOSConfig.h
similarity index 100%
rename from hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
rename to hw/bsp/samd5x_e5x/FreeRTOSConfig/FreeRTOSConfig.h
diff --git a/hw/bsp/samd5x_e5x/boards/d5035_01/board.cmake b/hw/bsp/samd5x_e5x/boards/d5035_01/board.cmake
new file mode 100644
index 0000000000..adf4f6a6d6
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.cmake
@@ -0,0 +1,13 @@
+set(SAM_FAMILY same51)
+
+set(JLINK_DEVICE ATSAME51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/same51j19a_flash.ld)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ __SAME51J19A__
+ SVC_Handler=SVCall_Handler
+ CONF_CPU_FREQUENCY=80000000
+ CONF_GCLK_USB_FREQUENCY=48000000
+ )
+endfunction()
diff --git a/hw/bsp/samd5x_e5x/boards/d5035_01/board.h b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h
new file mode 100644
index 0000000000..2cf59f5d1a
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h
@@ -0,0 +1,198 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PIN PIN_PA02
+#define LED_STATE_ON 1
+
+// Button: no button
+
+// UART: HWREV < 3: SERCOM5 on PB02, otherwise SERCOM0 on PA08
+// XTAL configure is also different for HWREV as well
+
+#if 0
+static inline void init_clock(void) {
+ /* AUTOWS is enabled by default in REG_NVMCTRL_CTRLA - no need to change the number of wait states when changing the core clock */
+#if HWREV == 1
+ /* configure XOSC1 for a 16MHz crystal connected to XIN1/XOUT1 */
+ OSCCTRL->XOSCCTRL[1].reg =
+ OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms
+ OSCCTRL_XOSCCTRL_RUNSTDBY |
+ OSCCTRL_XOSCCTRL_ENALC |
+ OSCCTRL_XOSCCTRL_IMULT(4) |
+ OSCCTRL_XOSCCTRL_IPTAT(3) |
+ OSCCTRL_XOSCCTRL_XTALEN |
+ OSCCTRL_XOSCCTRL_ENABLE;
+ while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
+
+ OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 8, input = XOSC1 */
+ OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
+ OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
+ while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
+
+ OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 16, input = XOSC1 */
+ OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
+ OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
+ while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
+#else // HWREV >= 1
+ /* configure XOSC0 for a 16MHz crystal connected to XIN0/XOUT0 */
+ OSCCTRL->XOSCCTRL[0].reg =
+ OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms
+ OSCCTRL_XOSCCTRL_RUNSTDBY |
+ OSCCTRL_XOSCCTRL_ENALC |
+ OSCCTRL_XOSCCTRL_IMULT(4) |
+ OSCCTRL_XOSCCTRL_IPTAT(3) |
+ OSCCTRL_XOSCCTRL_XTALEN |
+ OSCCTRL_XOSCCTRL_ENABLE;
+ while (0 == OSCCTRL->STATUS.bit.XOSCRDY0);
+
+ OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(
+ OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 8, input = XOSC1 */
+ OSCCTRL->Dpll[0].DPLLRATIO.reg =
+ OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
+ OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
+ while (0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
+
+ OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(
+ OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 16, input = XOSC1 */
+ OSCCTRL->Dpll[1].DPLLRATIO.reg =
+ OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
+ OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
+ while (0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
+#endif // HWREV
+
+ /* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
+ GCLK->GENCTRL[0].reg =
+ GCLK_GENCTRL_DIV(0) |
+ GCLK_GENCTRL_RUNSTDBY |
+ GCLK_GENCTRL_GENEN |
+ GCLK_GENCTRL_SRC_DPLL0 | /* DPLL0 */
+ GCLK_GENCTRL_IDC;
+ while (1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
+
+ /* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */
+ GCLK->GENCTRL[1].reg =
+ GCLK_GENCTRL_DIV(0) |
+ GCLK_GENCTRL_RUNSTDBY |
+ GCLK_GENCTRL_GENEN |
+ GCLK_GENCTRL_SRC_DPLL1 |
+ GCLK_GENCTRL_IDC;
+ while (1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */
+
+ /* configure clock-generator 2 to use DPLL0 as source -> for use with SERCOM */
+ GCLK->GENCTRL[2].reg =
+ GCLK_GENCTRL_DIV(1) | /* 80MHz */
+ GCLK_GENCTRL_RUNSTDBY |
+ GCLK_GENCTRL_GENEN |
+ GCLK_GENCTRL_SRC_DPLL0 |
+ GCLK_GENCTRL_IDC;
+ while (1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
+}
+
+static inline void uart_init(void) {
+#if HWREV < 3
+ /* configure SERCOM5 on PB02 */
+ PORT->Group[1].WRCONFIG.reg =
+ PORT_WRCONFIG_WRPINCFG |
+ PORT_WRCONFIG_WRPMUX |
+ PORT_WRCONFIG_PMUX(3) | /* function D */
+ PORT_WRCONFIG_DRVSTR |
+ PORT_WRCONFIG_PINMASK(0x0004) | /* PB02 */
+ PORT_WRCONFIG_PMUXEN;
+
+ MCLK->APBDMASK.bit.SERCOM5_ = 1;
+ GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg =
+ GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
+
+ SERCOM5->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
+ while (SERCOM5->USART.SYNCBUSY.bit.ENABLE);
+
+ SERCOM5->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
+ SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
+ // SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
+ SERCOM_USART_CTRLA_DORD | /* LSB first */
+ SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
+ SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
+ SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
+
+ SERCOM5->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
+ SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
+ SERCOM5->USART.CTRLC.reg = 0x00;
+ // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
+ SERCOM5->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
+
+// SERCOM5->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+ SERCOM5->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+ while (SERCOM5->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
+#else
+ /* configure SERCOM0 on PA08 */
+ PORT->Group[0].WRCONFIG.reg =
+ PORT_WRCONFIG_WRPINCFG |
+ PORT_WRCONFIG_WRPMUX |
+ PORT_WRCONFIG_PMUX(2) | /* function C */
+ PORT_WRCONFIG_DRVSTR |
+ PORT_WRCONFIG_PINMASK(0x0100) | /* PA08 */
+ PORT_WRCONFIG_PMUXEN;
+
+ MCLK->APBAMASK.bit.SERCOM0_ = 1;
+ GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
+
+ SERCOM0->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
+ while(SERCOM0->USART.SYNCBUSY.bit.ENABLE);
+
+ SERCOM0->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
+ SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
+ // SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
+ SERCOM_USART_CTRLA_DORD | /* LSB first */
+ SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
+ SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
+ SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
+
+ SERCOM0->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
+ SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
+ SERCOM0->USART.CTRLC.reg = 0x00;
+ // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
+ SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
+
+ // SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+ SERCOM0->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+ while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
+#endif
+}
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/same5x/boards/d5035_01/board.mk b/hw/bsp/samd5x_e5x/boards/d5035_01/board.mk
similarity index 95%
rename from hw/bsp/same5x/boards/d5035_01/board.mk
rename to hw/bsp/samd5x_e5x/boards/d5035_01/board.mk
index c53411bb85..4aa6b89fe1 100644
--- a/hw/bsp/same5x/boards/d5035_01/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.mk
@@ -1,4 +1,4 @@
-MCU = same51
+SAM_FAMILY = same51
HWREV ?= 1
diff --git a/hw/bsp/same5x/boards/d5035_01/same51j19a_flash.ld b/hw/bsp/samd5x_e5x/boards/d5035_01/same51j19a_flash.ld
similarity index 99%
rename from hw/bsp/same5x/boards/d5035_01/same51j19a_flash.ld
rename to hw/bsp/samd5x_e5x/boards/d5035_01/same51j19a_flash.ld
index 486043f22e..59afb604ba 100644
--- a/hw/bsp/same5x/boards/d5035_01/same51j19a_flash.ld
+++ b/hw/bsp/samd5x_e5x/boards/d5035_01/same51j19a_flash.ld
@@ -44,6 +44,8 @@ MEMORY
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+ENTRY(Reset_Handler)
+
/* Section Definitions */
SECTIONS
{
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/board.cmake b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.cmake
similarity index 89%
rename from hw/bsp/samd51/boards/itsybitsy_m4/board.cmake
rename to hw/bsp/samd5x_e5x/boards/feather_m4_express/board.cmake
index d83211d9ec..86d12ca24f 100644
--- a/hw/bsp/samd51/boards/itsybitsy_m4/board.cmake
+++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.cmake
@@ -1,3 +1,5 @@
+set(SAM_FAMILY samd51)
+
set(JLINK_DEVICE ATSAMD51J19)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h
similarity index 100%
rename from hw/bsp/samd51/boards/feather_m4_express/board.h
rename to hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h
diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.mk b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.mk
similarity index 86%
rename from hw/bsp/samd51/boards/feather_m4_express/board.mk
rename to hw/bsp/samd5x_e5x/boards/feather_m4_express/board.mk
index a8a98a9876..811c5f4e3d 100644
--- a/hw/bsp/samd51/boards/feather_m4_express/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
CFLAGS += -D__SAMD51J19A__
LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd51/boards/feather_m4_express/feather_m4_express.ld b/hw/bsp/samd5x_e5x/boards/feather_m4_express/feather_m4_express.ld
similarity index 100%
rename from hw/bsp/samd51/boards/feather_m4_express/feather_m4_express.ld
rename to hw/bsp/samd5x_e5x/boards/feather_m4_express/feather_m4_express.ld
diff --git a/hw/bsp/samd51/boards/pybadge/board.cmake b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.cmake
similarity index 89%
rename from hw/bsp/samd51/boards/pybadge/board.cmake
rename to hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.cmake
index d83211d9ec..86d12ca24f 100644
--- a/hw/bsp/samd51/boards/pybadge/board.cmake
+++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.cmake
@@ -1,3 +1,5 @@
+set(SAM_FAMILY samd51)
+
set(JLINK_DEVICE ATSAMD51J19)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/board.h b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h
similarity index 100%
rename from hw/bsp/samd51/boards/itsybitsy_m4/board.h
rename to hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.mk b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.mk
similarity index 90%
rename from hw/bsp/samd51/boards/metro_m4_express/board.mk
rename to hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.mk
index 57a680e91f..eba7070c1c 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
CFLAGS += -D__SAMD51J19A__
# All source paths should be relative to the top level.
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/itsybitsy_m4.ld b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/itsybitsy_m4.ld
similarity index 100%
rename from hw/bsp/samd51/boards/itsybitsy_m4/itsybitsy_m4.ld
rename to hw/bsp/samd5x_e5x/boards/itsybitsy_m4/itsybitsy_m4.ld
diff --git a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake
new file mode 100644
index 0000000000..ebc32b1f79
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake
@@ -0,0 +1,13 @@
+set(SAM_FAMILY samd51)
+
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+# force max3421e for testing with hardware-in-the-loop
+set(MAX3421_HOST 1)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ __SAMD51J19A__
+ )
+endfunction()
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h
similarity index 100%
rename from hw/bsp/samd51/boards/metro_m4_express/board.h
rename to hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/board.mk b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.mk
similarity index 90%
rename from hw/bsp/samd51/boards/itsybitsy_m4/board.mk
rename to hw/bsp/samd5x_e5x/boards/metro_m4_express/board.mk
index 57a680e91f..eba7070c1c 100644
--- a/hw/bsp/samd51/boards/itsybitsy_m4/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
CFLAGS += -D__SAMD51J19A__
# All source paths should be relative to the top level.
diff --git a/hw/bsp/samd51/boards/metro_m4_express/metro_m4_express.ld b/hw/bsp/samd5x_e5x/boards/metro_m4_express/metro_m4_express.ld
similarity index 100%
rename from hw/bsp/samd51/boards/metro_m4_express/metro_m4_express.ld
rename to hw/bsp/samd5x_e5x/boards/metro_m4_express/metro_m4_express.ld
diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.cmake b/hw/bsp/samd5x_e5x/boards/pybadge/board.cmake
similarity index 89%
rename from hw/bsp/samd51/boards/feather_m4_express/board.cmake
rename to hw/bsp/samd5x_e5x/boards/pybadge/board.cmake
index d83211d9ec..86d12ca24f 100644
--- a/hw/bsp/samd51/boards/feather_m4_express/board.cmake
+++ b/hw/bsp/samd5x_e5x/boards/pybadge/board.cmake
@@ -1,3 +1,5 @@
+set(SAM_FAMILY samd51)
+
set(JLINK_DEVICE ATSAMD51J19)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
diff --git a/hw/bsp/samd51/boards/pybadge/board.h b/hw/bsp/samd5x_e5x/boards/pybadge/board.h
similarity index 100%
rename from hw/bsp/samd51/boards/pybadge/board.h
rename to hw/bsp/samd5x_e5x/boards/pybadge/board.h
diff --git a/hw/bsp/samd51/boards/pybadge/board.mk b/hw/bsp/samd5x_e5x/boards/pybadge/board.mk
similarity index 86%
rename from hw/bsp/samd51/boards/pybadge/board.mk
rename to hw/bsp/samd5x_e5x/boards/pybadge/board.mk
index a8a98a9876..811c5f4e3d 100644
--- a/hw/bsp/samd51/boards/pybadge/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/pybadge/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
CFLAGS += -D__SAMD51J19A__
LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd51/boards/pybadge/pybadge.ld b/hw/bsp/samd5x_e5x/boards/pybadge/pybadge.ld
similarity index 100%
rename from hw/bsp/samd51/boards/pybadge/pybadge.ld
rename to hw/bsp/samd5x_e5x/boards/pybadge/pybadge.ld
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.cmake b/hw/bsp/samd5x_e5x/boards/pyportal/board.cmake
similarity index 89%
rename from hw/bsp/samd51/boards/metro_m4_express/board.cmake
rename to hw/bsp/samd5x_e5x/boards/pyportal/board.cmake
index d83211d9ec..86d12ca24f 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.cmake
+++ b/hw/bsp/samd5x_e5x/boards/pyportal/board.cmake
@@ -1,3 +1,5 @@
+set(SAM_FAMILY samd51)
+
set(JLINK_DEVICE ATSAMD51J19)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
diff --git a/hw/bsp/samd51/boards/pyportal/board.h b/hw/bsp/samd5x_e5x/boards/pyportal/board.h
similarity index 100%
rename from hw/bsp/samd51/boards/pyportal/board.h
rename to hw/bsp/samd5x_e5x/boards/pyportal/board.h
diff --git a/hw/bsp/samd51/boards/pyportal/board.mk b/hw/bsp/samd5x_e5x/boards/pyportal/board.mk
similarity index 86%
rename from hw/bsp/samd51/boards/pyportal/board.mk
rename to hw/bsp/samd5x_e5x/boards/pyportal/board.mk
index a8a98a9876..811c5f4e3d 100644
--- a/hw/bsp/samd51/boards/pyportal/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/pyportal/board.mk
@@ -1,3 +1,5 @@
+SAM_FAMILY = samd51
+
CFLAGS += -D__SAMD51J19A__
LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd51/boards/pyportal/pyportal.ld b/hw/bsp/samd5x_e5x/boards/pyportal/pyportal.ld
similarity index 100%
rename from hw/bsp/samd51/boards/pyportal/pyportal.ld
rename to hw/bsp/samd5x_e5x/boards/pyportal/pyportal.ld
diff --git a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.cmake b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.cmake
new file mode 100644
index 0000000000..4d98205bc8
--- /dev/null
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.cmake
@@ -0,0 +1,10 @@
+set(SAM_FAMILY same54)
+
+set(JLINK_DEVICE ATSAME54P20)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/same54p20a_flash.ld)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ __SAME54P20A__
+ )
+endfunction()
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h
similarity index 84%
rename from hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
rename to hw/bsp/samd5x_e5x/boards/same54_xplained/board.h
index bc203f0735..faaa52b8e6 100644
--- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h
@@ -31,19 +31,17 @@
extern "C" {
#endif
-#define _PINNUM(port, pin) ((port)*32 + (pin))
-
// LED
-#define LED_PIN _PINNUM(1, 13)
-#define LED_STATE_ON 0
+#define LED_PIN PIN_PC18
+#define LED_STATE_ON 1
-// Button
-#define BUTTON_PIN _PINNUM(0, 15)
+// Button: D5
+#define BUTTON_PIN PIN_PB31
#define BUTTON_STATE_ACTIVE 0
-// UART
-#define UART_RX_PIN 25
-#define UART_TX_PIN 24
+// UART: SERCOM2
+//#define UART_TX_PIN 23
+//#define UART_RX_PIN 22
#ifdef __cplusplus
}
diff --git a/hw/bsp/same5x/boards/same54_xplained/board.mk b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.mk
similarity index 54%
rename from hw/bsp/same5x/boards/same54_xplained/board.mk
rename to hw/bsp/samd5x_e5x/boards/same54_xplained/board.mk
index 41cf95bfcd..d10e9e34ce 100644
--- a/hw/bsp/same5x/boards/same54_xplained/board.mk
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.mk
@@ -1,9 +1,6 @@
-MCU = same54
+SAM_FAMILY = same54
-CFLAGS += \
- -DCONF_CPU_FREQUENCY=48000000 \
- -D__SAME54P20A__ \
- -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
+CFLAGS += -D__SAME54P20A__
# All source paths should be relative to the top level.
LD_FILE = $(BOARD_PATH)/same54p20a_flash.ld
diff --git a/hw/bsp/same5x/boards/same54_xplained/same54p20a_flash.ld b/hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_flash.ld
similarity index 99%
rename from hw/bsp/same5x/boards/same54_xplained/same54p20a_flash.ld
rename to hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_flash.ld
index 7a7f1be460..8a9fd7d9f6 100644
--- a/hw/bsp/same5x/boards/same54_xplained/same54p20a_flash.ld
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_flash.ld
@@ -44,6 +44,8 @@ MEMORY
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
+ENTRY(Reset_Handler)
+
/* Section Definitions */
SECTIONS
{
@@ -160,4 +162,5 @@ SECTIONS
. = ALIGN(4);
_end = . ;
+ end = .;
}
diff --git a/hw/bsp/same5x/boards/same54_xplained/same54p20a_sram.ld b/hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_sram.ld
similarity index 99%
rename from hw/bsp/same5x/boards/same54_xplained/same54p20a_sram.ld
rename to hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_sram.ld
index c768f9c9aa..c886177296 100644
--- a/hw/bsp/same5x/boards/same54_xplained/same54p20a_sram.ld
+++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/same54p20a_sram.ld
@@ -43,6 +43,8 @@ MEMORY
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
+ENTRY(Reset_Handler)
+
/* Section Definitions */
SECTIONS
{
@@ -159,4 +161,5 @@ SECTIONS
. = ALIGN(4);
_end = . ;
+ end = .;
}
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd5x_e5x/family.c
similarity index 83%
rename from hw/bsp/samd51/family.c
rename to hw/bsp/samd5x_e5x/family.c
index d56d9f6957..abaee353b1 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd5x_e5x/family.c
@@ -34,8 +34,8 @@
#pragma GCC diagnostic ignored "-Wcast-qual"
#endif
-#include "hal/include/hal_gpio.h"
-#include "hal/include/hal_init.h"
+#include "hal_gpio.h"
+#include "hal_init.h"
#include "hpl/gclk/hpl_gclk_base.h"
#include "hpl_mclk_config.h"
@@ -106,9 +106,11 @@ void board_init(void) {
gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
gpio_set_pin_level(LED_PIN, 0);
+#ifdef BUTTON_PIN
// Button init
gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+#endif
#if CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
@@ -154,7 +156,11 @@ void board_led_write(bool state) {
uint32_t board_button_read(void) {
// button is active low
+ #ifdef BUTTON_PIN
return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
+ #else
+ return 0;
+ #endif
}
size_t board_get_unique_id(uint8_t id[], size_t max_len) {
@@ -194,6 +200,53 @@ uint32_t board_millis(void) {
return system_ticks;
}
+#if 0
+/* Initialize SERCOM2 for 115200 bps 8N1 using a 48 MHz clock */
+static inline void uart_init(void) {
+ gpio_set_pin_function(PIN_PB24, PINMUX_PB24D_SERCOM2_PAD1);
+ gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
+
+ MCLK->APBBMASK.bit.SERCOM2_ = 1;
+ GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
+
+ BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
+ while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
+
+ BOARD_SERCOM->USART.CTRLA.reg =
+ SERCOM_USART_CTRLA_SAMPR(0) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
+ SERCOM_USART_CTRLA_SAMPA(0) | /* 16x over sampling */
+ SERCOM_USART_CTRLA_FORM(0) | /* 0x0 USART frame, 0x1 USART frame with parity, ... */
+ SERCOM_USART_CTRLA_DORD | /* LSB first */
+ SERCOM_USART_CTRLA_MODE(1) | /* 0x0 USART with external clock, 0x1 USART with internal clock */
+ SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
+ SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
+
+ BOARD_SERCOM->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
+ SERCOM_USART_CTRLB_TXEN | /* transmitter enabled */
+ SERCOM_USART_CTRLB_RXEN; /* receiver enabled */
+ // BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26); /* 48000000/(16*115200) = 26.041666667 */
+ BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_BAUD(63019); /* 65536*(1−16*115200/48000000) */
+
+ BOARD_SERCOM->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+ while (BOARD_SERCOM->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
+}
+
+static inline void uart_send_buffer(uint8_t const* text, size_t len) {
+ for (size_t i = 0; i < len; ++i) {
+ BOARD_SERCOM->USART.DATA.reg = text[i];
+ while ((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
+ }
+}
+
+static inline void uart_send_str(const char* text) {
+ while (*text) {
+ BOARD_SERCOM->USART.DATA.reg = *text++;
+ while ((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
+ }
+}
+
+#endif
+
#endif
//--------------------------------------------------------------------+
diff --git a/hw/bsp/samd51/family.cmake b/hw/bsp/samd5x_e5x/family.cmake
similarity index 90%
rename from hw/bsp/samd51/family.cmake
rename to hw/bsp/samd5x_e5x/family.cmake
index 3ddd2e290c..fd95ce10e0 100644
--- a/hw/bsp/samd51/family.cmake
+++ b/hw/bsp/samd5x_e5x/family.cmake
@@ -1,16 +1,15 @@
include_guard()
-set(SDK_DIR ${TOP}/hw/mcu/microchip/samd51)
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+set(SDK_DIR ${TOP}/hw/mcu/microchip/${SAM_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
# toolchain set up
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-set(FAMILY_MCUS SAMD51 CACHE INTERNAL "")
+set(FAMILY_MCUS SAMD51 SAME54 CACHE INTERNAL "")
set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -c \"set CHIPNAME samd51\" -f target/atsame5x.cfg")
#------------------------------------
@@ -27,22 +26,20 @@ function(add_board_target BOARD_TARGET)
message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
endif ()
- if (NOT DEFINED STARTUP_FILE_GNU)
- set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_samd51.c)
- endif ()
+ set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_${SAM_FAMILY}.c)
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
add_library(${BOARD_TARGET} STATIC
- ${SDK_DIR}/gcc/system_samd51.c
+ ${SDK_DIR}/gcc/system_${SAM_FAMILY}.c
+ ${SDK_DIR}/hal/src/hal_atomic.c
${SDK_DIR}/hpl/gclk/hpl_gclk.c
${SDK_DIR}/hpl/mclk/hpl_mclk.c
${SDK_DIR}/hpl/osc32kctrl/hpl_osc32kctrl.c
${SDK_DIR}/hpl/oscctrl/hpl_oscctrl.c
- ${SDK_DIR}/hal/src/hal_atomic.c
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
)
target_include_directories(${BOARD_TARGET} PUBLIC
- ${SDK_DIR}/
+ ${SDK_DIR}
${SDK_DIR}/config
${SDK_DIR}/include
${SDK_DIR}/hal/include
@@ -108,5 +105,5 @@ function(family_configure_example TARGET RTOS)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_jlink(${TARGET})
- #family_flash_openocd(${TARGET} ${OPENOCD_OPTION})
+ #family_flash_openocd(${TARGET})
endfunction()
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd5x_e5x/family.mk
similarity index 54%
rename from hw/bsp/samd51/family.mk
rename to hw/bsp/samd5x_e5x/family.mk
index 7b90efad08..9b1a23db41 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd5x_e5x/family.mk
@@ -1,9 +1,10 @@
UF2_FAMILY_ID = 0x55114460
-DEPS_SUBMODULES += hw/mcu/microchip
include $(TOP)/$(BOARD_PATH)/board.mk
CPU_CORE ?= cortex-m4
+SDK_DIR = hw/mcu/microchip/${SAM_FAMILY}
+
CFLAGS += \
-flto \
-DCFG_TUSB_MCU=OPT_MCU_SAMD51
@@ -17,23 +18,23 @@ LDFLAGS_GCC += \
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
- hw/mcu/microchip/samd51/gcc/gcc/startup_samd51.c \
- hw/mcu/microchip/samd51/gcc/system_samd51.c \
- hw/mcu/microchip/samd51/hpl/gclk/hpl_gclk.c \
- hw/mcu/microchip/samd51/hpl/mclk/hpl_mclk.c \
- hw/mcu/microchip/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c \
- hw/mcu/microchip/samd51/hpl/oscctrl/hpl_oscctrl.c \
- hw/mcu/microchip/samd51/hal/src/hal_atomic.c
+ ${SDK_DIR}/gcc/gcc/startup_${SAM_FAMILY}.c \
+ ${SDK_DIR}/gcc/system_${SAM_FAMILY}.c \
+ ${SDK_DIR}/hpl/gclk/hpl_gclk.c \
+ ${SDK_DIR}/hpl/mclk/hpl_mclk.c \
+ ${SDK_DIR}/hpl/osc32kctrl/hpl_osc32kctrl.c \
+ ${SDK_DIR}/hpl/oscctrl/hpl_oscctrl.c \
+ ${SDK_DIR}/hal/src/hal_atomic.c
INC += \
$(TOP)/$(BOARD_PATH) \
- $(TOP)/hw/mcu/microchip/samd51/ \
- $(TOP)/hw/mcu/microchip/samd51/config \
- $(TOP)/hw/mcu/microchip/samd51/include \
- $(TOP)/hw/mcu/microchip/samd51/hal/include \
- $(TOP)/hw/mcu/microchip/samd51/hal/utils/include \
- $(TOP)/hw/mcu/microchip/samd51/hpl/port \
- $(TOP)/hw/mcu/microchip/samd51/hri \
+ $(TOP)/${SDK_DIR} \
+ $(TOP)/${SDK_DIR}/config \
+ $(TOP)/${SDK_DIR}/include \
+ $(TOP)/${SDK_DIR}/hal/include \
+ $(TOP)/${SDK_DIR}/hal/utils/include \
+ $(TOP)/${SDK_DIR}/hpl/port \
+ $(TOP)/${SDK_DIR}/hri \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
# flash using bossac at least version 1.8
@@ -44,3 +45,7 @@ BOSSAC = bossac
flash-bossac: $(BUILD)/$(PROJECT).bin
@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x4000 -e -w $^ -R
+
+# flash using edbg from https://github.com/ataradov/edbg
+flash-edbg: $(BUILD)/$(PROJECT).bin
+ edbg --verbose -t $(MCU) -pv -f $<
diff --git a/hw/bsp/same5x/boards/d5035_01/d5035_01.c b/hw/bsp/same5x/boards/d5035_01/d5035_01.c
deleted file mode 100644
index eb5768d0d3..0000000000
--- a/hw/bsp/same5x/boards/d5035_01/d5035_01.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 Jean Gressmann
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include
-#include "bsp/board_api.h"
-
-#include
-
-#if CONF_CPU_FREQUENCY != 80000000
-# error "CONF_CPU_FREQUENCY" must 80000000
-#endif
-
-#if CONF_GCLK_USB_FREQUENCY != 48000000
-# error "CONF_GCLK_USB_FREQUENCY" must 48000000
-#endif
-
-#if !defined(HWREV)
-# error Define "HWREV"
-#endif
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler (void)
-{
- tud_int_handler(0);
-}
-
-void USB_1_Handler (void)
-{
- tud_int_handler(0);
-}
-
-void USB_2_Handler (void)
-{
- tud_int_handler(0);
-}
-
-void USB_3_Handler (void)
-{
- tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define LED_PIN PIN_PA02
-
-#if HWREV < 3
-# define BOARD_SERCOM SERCOM5
-#else
-# define BOARD_SERCOM SERCOM0
-#endif
-
-static inline void init_clock(void)
-{
- /* AUTOWS is enabled by default in REG_NVMCTRL_CTRLA - no need to change the number of wait states when changing the core clock */
-#if HWREV == 1
- /* configure XOSC1 for a 16MHz crystal connected to XIN1/XOUT1 */
- OSCCTRL->XOSCCTRL[1].reg =
- OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms
- OSCCTRL_XOSCCTRL_RUNSTDBY |
- OSCCTRL_XOSCCTRL_ENALC |
- OSCCTRL_XOSCCTRL_IMULT(4) |
- OSCCTRL_XOSCCTRL_IPTAT(3) |
- OSCCTRL_XOSCCTRL_XTALEN |
- OSCCTRL_XOSCCTRL_ENABLE;
- while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
-
- OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 8, input = XOSC1 */
- OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
- OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
- while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
- OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 16, input = XOSC1 */
- OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
- OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
- while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
-#else // HWREV >= 1
- /* configure XOSC0 for a 16MHz crystal connected to XIN0/XOUT0 */
- OSCCTRL->XOSCCTRL[0].reg =
- OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms
- OSCCTRL_XOSCCTRL_RUNSTDBY |
- OSCCTRL_XOSCCTRL_ENALC |
- OSCCTRL_XOSCCTRL_IMULT(4) |
- OSCCTRL_XOSCCTRL_IPTAT(3) |
- OSCCTRL_XOSCCTRL_XTALEN |
- OSCCTRL_XOSCCTRL_ENABLE;
- while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
-
- OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 8, input = XOSC1 */
- OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */
- OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
- while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
- OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 16, input = XOSC1 */
- OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */
- OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
- while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */
-#endif // HWREV
-
- /* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
- GCLK->GENCTRL[0].reg =
- GCLK_GENCTRL_DIV(0) |
- GCLK_GENCTRL_RUNSTDBY |
- GCLK_GENCTRL_GENEN |
- GCLK_GENCTRL_SRC_DPLL0 | /* DPLL0 */
- GCLK_GENCTRL_IDC ;
- while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
-
- /* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */
- GCLK->GENCTRL[1].reg =
- GCLK_GENCTRL_DIV(0) |
- GCLK_GENCTRL_RUNSTDBY |
- GCLK_GENCTRL_GENEN |
- GCLK_GENCTRL_SRC_DPLL1 |
- GCLK_GENCTRL_IDC ;
- while(1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */
-
- /* configure clock-generator 2 to use DPLL0 as source -> for use with SERCOM */
- GCLK->GENCTRL[2].reg =
- GCLK_GENCTRL_DIV(1) | /* 80MHz */
- GCLK_GENCTRL_RUNSTDBY |
- GCLK_GENCTRL_GENEN |
- GCLK_GENCTRL_SRC_DPLL0 |
- GCLK_GENCTRL_IDC ;
- while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
-}
-
-static inline void uart_init(void)
-{
-#if HWREV < 3
- /* configure SERCOM5 on PB02 */
- PORT->Group[1].WRCONFIG.reg =
- PORT_WRCONFIG_WRPINCFG |
- PORT_WRCONFIG_WRPMUX |
- PORT_WRCONFIG_PMUX(3) | /* function D */
- PORT_WRCONFIG_DRVSTR |
- PORT_WRCONFIG_PINMASK(0x0004) | /* PB02 */
- PORT_WRCONFIG_PMUXEN;
-
- MCLK->APBDMASK.bit.SERCOM5_ = 1;
- GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
-
- SERCOM5->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
- while(SERCOM5->USART.SYNCBUSY.bit.ENABLE);
-
- SERCOM5->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
- SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
-// SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
- SERCOM_USART_CTRLA_DORD | /* LSB first */
- SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
- SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
- SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
- SERCOM5->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
- SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
- SERCOM5->USART.CTRLC.reg = 0x00;
- // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
- SERCOM5->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
-
-// SERCOM5->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
- SERCOM5->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
- while(SERCOM5->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-#else
-/* configure SERCOM0 on PA08 */
- PORT->Group[0].WRCONFIG.reg =
- PORT_WRCONFIG_WRPINCFG |
- PORT_WRCONFIG_WRPMUX |
- PORT_WRCONFIG_PMUX(2) | /* function C */
- PORT_WRCONFIG_DRVSTR |
- PORT_WRCONFIG_PINMASK(0x0100) | /* PA08 */
- PORT_WRCONFIG_PMUXEN;
-
- MCLK->APBAMASK.bit.SERCOM0_ = 1;
- GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */
-
- SERCOM0->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */
- while(SERCOM0->USART.SYNCBUSY.bit.ENABLE);
-
- SERCOM0->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
- SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
-// SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
- SERCOM_USART_CTRLA_DORD | /* LSB first */
- SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
- SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
- SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
- SERCOM0->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
- SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */
- SERCOM0->USART.CTRLC.reg = 0x00;
- // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E
- SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21);
-
-// SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
- SERCOM0->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
- while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-#endif
-}
-
-static inline void uart_send_buffer(uint8_t const *text, size_t len)
-{
- for (size_t i = 0; i < len; ++i) {
- BOARD_SERCOM->USART.DATA.reg = text[i];
- while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
- }
-}
-
-static inline void uart_send_str(const char* text)
-{
- while (*text) {
- BOARD_SERCOM->USART.DATA.reg = *text++;
- while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) == 0);
- }
-}
-
-
-void board_init(void)
-{
- init_clock();
-
- SystemCoreClock = CONF_CPU_FREQUENCY;
-
-#if CFG_TUSB_OS == OPT_OS_NONE
- SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-#endif
-
- uart_init();
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " UART initialized\n");
- tu_printf(BOARD_NAME " reset cause %#02x\n", RSTC->RCAUSE.reg);
-#endif
-
- // Led init
- gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
- gpio_set_pin_level(LED_PIN, 0);
-
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " LED pin configured\n");
-#endif
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
- // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
- NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
- NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
- NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
- NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-
-#if CFG_TUD_ENABLED
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " USB device enabled\n");
-#endif
-
- /* USB clock init
- * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
- * for low speed and full speed operation. */
- hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
- hri_mclk_set_AHBMASK_USB_bit(MCLK);
- hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
- // USB pin init
- gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
- gpio_set_pin_level(PIN_PA24, false);
- gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
- gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
- gpio_set_pin_level(PIN_PA25, false);
- gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
- gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
- gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
-
-
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " USB device configured\n");
-#endif
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
- gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
- // this board has no button
- return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
- return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
- if (len < 0) {
- uart_send_str(buf);
- } else {
- uart_send_buffer(buf, len);
- }
- return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void)
-{
- system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
- return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c b/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
deleted file mode 100644
index 93adea63ef..0000000000
--- a/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021 Jean Gressmann
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#include
-#include "bsp/board_api.h"
-
-#include
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler(void)
-{
- tud_int_handler(0);
-}
-
-void USB_1_Handler(void)
-{
- tud_int_handler(0);
-}
-
-void USB_2_Handler(void)
-{
- tud_int_handler(0);
-}
-
-void USB_3_Handler(void)
-{
- tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define LED_PIN PIN_PC18
-#define BUTTON_PIN PIN_PB31
-#define BOARD_SERCOM SERCOM2
-
-/** Initializes the clocks from the external 12 MHz crystal
- *
- * The goal of this setup is to preserve the second PLL
- * for the application code while still having a reasonable
- * 48 MHz clock for USB / UART.
- *
- * GCLK0: CONF_CPU_FREQUENCY (default 120 MHz) from PLL0
- * GCLK1: unused
- * GCLK2: 12 MHz from XOSC1
- * DFLL48M: closed loop from GLCK2
- * GCLK3: 48 MHz
- */
-static inline void init_clock_xtal(void)
-{
- /* configure for a 12MHz crystal connected to XIN1/XOUT1 */
- OSCCTRL->XOSCCTRL[1].reg =
- OSCCTRL_XOSCCTRL_STARTUP(6) | // 1.953 ms
- OSCCTRL_XOSCCTRL_RUNSTDBY |
- OSCCTRL_XOSCCTRL_ENALC |
- OSCCTRL_XOSCCTRL_IMULT(4) | OSCCTRL_XOSCCTRL_IPTAT(3) | // 8MHz to 16MHz
- OSCCTRL_XOSCCTRL_XTALEN |
- OSCCTRL_XOSCCTRL_ENABLE;
- while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
-
- OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(2) | OSCCTRL_DPLLCTRLB_REFCLK_XOSC1; /* 12MHz / 6 = 2Mhz, input = XOSC1 */
- OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR((CONF_CPU_FREQUENCY / 1000000 / 2) - 1); /* multiply to get CONF_CPU_FREQUENCY (default = 120MHz) */
- OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE;
- while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */
-
- /* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */
- GCLK->GENCTRL[0].reg =
- GCLK_GENCTRL_DIV(0) |
- GCLK_GENCTRL_RUNSTDBY |
- GCLK_GENCTRL_GENEN |
- GCLK_GENCTRL_SRC_DPLL0 |
- GCLK_GENCTRL_IDC;
- while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */
-
- // configure GCLK2 for 12MHz from XOSC1
- GCLK->GENCTRL[2].reg =
- GCLK_GENCTRL_DIV(0) |
- GCLK_GENCTRL_RUNSTDBY |
- GCLK_GENCTRL_GENEN |
- GCLK_GENCTRL_SRC_XOSC1 |
- GCLK_GENCTRL_IDC;
- while(1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */
-
- /* setup DFLL48M to use GLCK2 */
- GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN;
-
- OSCCTRL->DFLLCTRLA.reg = 0;
- while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
-
- OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_MODE | OSCCTRL_DFLLCTRLB_WAITLOCK;
- OSCCTRL->DFLLMUL.bit.MUL = 4; // 4 * 12MHz -> 48MHz
-
- OSCCTRL->DFLLCTRLA.reg =
- OSCCTRL_DFLLCTRLA_ENABLE |
- OSCCTRL_DFLLCTRLA_RUNSTDBY;
- while(1 == OSCCTRL->DFLLSYNC.bit.ENABLE);
-
- // setup 48 MHz GCLK3 from DFLL48M
- GCLK->GENCTRL[3].reg =
- GCLK_GENCTRL_DIV(0) |
- GCLK_GENCTRL_RUNSTDBY |
- GCLK_GENCTRL_GENEN |
- GCLK_GENCTRL_SRC_DFLL |
- GCLK_GENCTRL_IDC;
- while(1 == GCLK->SYNCBUSY.bit.GENCTRL3);
-}
-
-/* Initialize SERCOM2 for 115200 bps 8N1 using a 48 MHz clock */
-static inline void uart_init(void)
-{
- gpio_set_pin_function(PIN_PB24, PINMUX_PB24D_SERCOM2_PAD1);
- gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
-
- MCLK->APBBMASK.bit.SERCOM2_ = 1;
- GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
-
- BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
- while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
-
- BOARD_SERCOM->USART.CTRLA.reg =
- SERCOM_USART_CTRLA_SAMPR(0) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
- SERCOM_USART_CTRLA_SAMPA(0) | /* 16x over sampling */
- SERCOM_USART_CTRLA_FORM(0) | /* 0x0 USART frame, 0x1 USART frame with parity, ... */
- SERCOM_USART_CTRLA_DORD | /* LSB first */
- SERCOM_USART_CTRLA_MODE(1) | /* 0x0 USART with external clock, 0x1 USART with internal clock */
- SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */
- SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */
-
- BOARD_SERCOM->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */
- SERCOM_USART_CTRLB_TXEN | /* transmitter enabled */
- SERCOM_USART_CTRLB_RXEN; /* receiver enabled */
- // BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26); /* 48000000/(16*115200) = 26.041666667 */
- BOARD_SERCOM->USART.BAUD.reg = SERCOM_USART_BAUD_BAUD(63019); /* 65536*(1−16*115200/48000000) */
-
- BOARD_SERCOM->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
- while (BOARD_SERCOM->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
-}
-
-static inline void uart_send_buffer(uint8_t const *text, size_t len)
-{
- for (size_t i = 0; i < len; ++i) {
- BOARD_SERCOM->USART.DATA.reg = text[i];
- while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
- }
-}
-
-static inline void uart_send_str(const char* text)
-{
- while (*text) {
- BOARD_SERCOM->USART.DATA.reg = *text++;
- while((BOARD_SERCOM->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
- }
-}
-
-
-void board_init(void)
-{
- // Uncomment this line and change the GCLK for UART/USB to run off the XTAL.
- // init_clock_xtal();
-
- SystemCoreClock = CONF_CPU_FREQUENCY;
-
-#if CFG_TUSB_OS == OPT_OS_NONE
- SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-#endif
-
- uart_init();
-
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " UART initialized\n");
- tu_printf(BOARD_NAME " reset cause %#02x\n", RSTC->RCAUSE.reg);
-#endif
-
- // LED0 init
- gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
- gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
- board_led_write(0);
-
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " LED pin configured\n");
-#endif
-
- // BTN0 init
- gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
- gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
- gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " Button pin configured\n");
-#endif
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
- // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
- NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
- NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
- NVIC_SetPriority(USB_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
- NVIC_SetPriority(USB_3_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-
-#if CFG_TUD_ENABLED
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " USB device enabled\n");
-#endif
-
- /* USB clock init
- * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
- * for low speed and full speed operation.
- */
- hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN);
- hri_mclk_set_AHBMASK_USB_bit(MCLK);
- hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
- // USB pin init
- gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
- gpio_set_pin_level(PIN_PA24, false);
- gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
- gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
- gpio_set_pin_level(PIN_PA25, false);
- gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
- gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
- gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
-
-
-#if CFG_TUSB_DEBUG >= 2
- uart_send_str(BOARD_NAME " USB device configured\n");
-#endif
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
- gpio_set_pin_level(LED_PIN, !state);
-}
-
-uint32_t board_button_read(void)
-{
- return (PORT->Group[1].IN.reg & 0x80000000) != 0x80000000;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
- return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
- if (len < 0) {
- uart_send_str(buf);
- } else {
- uart_send_buffer(buf, len);
- }
- return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler(void)
-{
- system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
- return system_ticks;
-}
-#endif
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/same5x/family.mk b/hw/bsp/same5x/family.mk
deleted file mode 100644
index b2bf0d359e..0000000000
--- a/hw/bsp/same5x/family.mk
+++ /dev/null
@@ -1,38 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-SDK_DIR = hw/mcu/microchip/$(MCU)
-include $(TOP)/$(BOARD_PATH)/board.mk
-CPU_CORE ?= cortex-m4
-
-CFLAGS += \
- -mthumb \
- -mlong-calls \
- -nostdlib -nostartfiles \
- -DCFG_TUSB_MCU=OPT_MCU_SAME5X
-
-# SAM driver is flooded with -Wcast-qual which slow down complication significantly
-CFLAGS_SKIP += -Wcast-qual
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
-
-SRC_C += \
- src/portable/microchip/samd/dcd_samd.c \
- $(SDK_DIR)/gcc/gcc/startup_$(MCU).c \
- $(SDK_DIR)/gcc/system_$(MCU).c \
- $(SDK_DIR)/hal/utils/src/utils_syscalls.c
-
-INC += \
- $(TOP)/$(SDK_DIR) \
- $(TOP)/$(SDK_DIR)/config \
- $(TOP)/$(SDK_DIR)/include \
- $(TOP)/$(SDK_DIR)/hal/include \
- $(TOP)/$(SDK_DIR)/hal/utils/include \
- $(TOP)/$(SDK_DIR)/hpl/port \
- $(TOP)/$(SDK_DIR)/hri \
- $(TOP)/$(SDK_DIR)/CMSIS/Include
-
-# flash using edbg from https://github.com/ataradov/edbg
-flash-edbg: $(BUILD)/$(PROJECT).bin
- edbg --verbose -t $(MCU) -pv -f $<
-
-flash: flash-edbg
diff --git a/hw/bsp/samg/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samg/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..02223f7665
--- /dev/null
+++ b/hw/bsp/samg/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*6*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< USB Clock Source
// <0=> USB Clock Controller (USB_48M)
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
deleted file mode 100644
index a9328be11c..0000000000
--- a/hw/bsp/samg55xplained/board.mk
+++ /dev/null
@@ -1,56 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-ASF_DIR = hw/mcu/microchip/samg55
-
-CFLAGS += \
- -flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
- -nostdlib -nostartfiles \
- -D__SAMG55J19__ \
- -DCFG_TUSB_MCU=OPT_MCU_SAMG
-
-# suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=null-dereference -Wno-error=redundant-decls
-
-# SAM driver is flooded with -Wcast-qual which slow down complication significantly
-CFLAGS_SKIP += -Wcast-qual
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/samg55j19_flash.ld
-
-SRC_C += \
- src/portable/microchip/samg/dcd_samg.c \
- $(ASF_DIR)/samg55/gcc/gcc/startup_samg55.c \
- $(ASF_DIR)/samg55/gcc/system_samg55.c \
- $(ASF_DIR)/hpl/core/hpl_init.c \
- $(ASF_DIR)/hpl/usart/hpl_usart.c \
- $(ASF_DIR)/hpl/pmc/hpl_pmc.c \
- $(ASF_DIR)/hal/src/hal_atomic.c
-
-INC += \
- $(TOP)/hw/bsp/$(BOARD) \
- $(TOP)/$(ASF_DIR) \
- $(TOP)/$(ASF_DIR)/config \
- $(TOP)/$(ASF_DIR)/samg55/include \
- $(TOP)/$(ASF_DIR)/hal/include \
- $(TOP)/$(ASF_DIR)/hal/utils/include \
- $(TOP)/$(ASF_DIR)/hpl/core \
- $(TOP)/$(ASF_DIR)/hpl/pio \
- $(TOP)/$(ASF_DIR)/hpl/pmc \
- $(TOP)/$(ASF_DIR)/hri \
- $(TOP)/$(ASF_DIR)/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMG55J19
-
-# flash using edbg from https://github.com/ataradov/edbg
-flash: $(BUILD)/$(PROJECT).bin
- edbg --verbose -t samg55 -pv -f $<
diff --git a/hw/bsp/saml2x/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/saml2x/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..6c9ecae2df
--- /dev/null
+++ b/hw/bsp/saml2x/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<RAM
-
/* Remove information from the standard libraries */
/DISCARD/ :
{
diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake
index 6eff708a87..e87be82557 100644
--- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake
+++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake
@@ -1,5 +1,5 @@
set(MCU_VARIANT stm32h750xx)
-set(JLINK_DEVICE stm32h750xb_m7)
+set(JLINK_DEVICE stm32h750xb)
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${MCU_VARIANT}_flash_CM7.ld)
set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk
index d37a425fba..923c907532 100644
--- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk
@@ -15,7 +15,7 @@ SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s
LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf
# For flash-jlink target
-JLINK_DEVICE = stm32h750xb_m7
+JLINK_DEVICE = stm32h750xb
# flash target using on-board stlink
flash: flash-stlink
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index adeb38e742..6e4b388d62 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -35,6 +35,12 @@ TU_ATTR_UNUSED static void Error_Handler(void) {
#include "board.h"
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+UART_HandleTypeDef UartHandle;
+
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
@@ -42,26 +48,15 @@ TU_ATTR_UNUSED static void Error_Handler(void) {
// Despite being call USB2_OTG_FS on some MCUs
// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
void OTG_FS_IRQHandler(void) {
- tud_int_handler(0);
+ tusb_int_handler(0, true);
}
// Despite being call USB1_OTG_HS on some MCUs
// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
void OTG_HS_IRQHandler(void) {
- tud_int_handler(1);
+ tusb_int_handler(1, true);
}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-UART_HandleTypeDef UartHandle;
-
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-
#ifdef TRACE_ETM
void trace_etm_init(void) {
// H7 trace pin is PE2 to PE6
@@ -102,9 +97,6 @@ void board_init(void) {
trace_etm_init();
- // Enable UART Clock
- UART_CLK_EN();
-
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
@@ -114,9 +106,10 @@ void board_init(void) {
SysTick->CTRL &= ~1U;
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-#ifdef USB_OTG_FS_PERIPH_BASE
+ #ifdef USB_OTG_FS_PERIPH_BASE
NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
+ #endif
+
NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#endif
@@ -136,7 +129,10 @@ void board_init(void) {
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+#ifdef UART_DEV
// Uart
+ UART_CLK_EN();
+
GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
@@ -153,6 +149,7 @@ void board_init(void) {
UartHandle.Init.Mode = UART_MODE_TX_RX;
UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
HAL_UART_Init(&UartHandle);
+#endif
#if BOARD_TUD_RHPORT == 0
// Despite being call USB2_OTG
@@ -205,13 +202,11 @@ void board_init(void) {
struct {
GPIO_TypeDef* port;
uint32_t pin;
- } const ulpi_pins[] =
- {
+ } const ulpi_pins[] = {
ULPI_PINS
};
- for (uint8_t i=0; i < sizeof(ulpi_pins)/sizeof(ulpi_pins[0]); i++)
- {
+ for (uint8_t i=0; i < sizeof(ulpi_pins)/sizeof(ulpi_pins[0]); i++) {
GPIO_InitStruct.Pin = ulpi_pins[i].pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -280,8 +275,13 @@ int board_uart_read(uint8_t *buf, int len) {
}
int board_uart_write(void const *buf, int len) {
+#ifdef UART_DEV
HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
buf, len, 0xffff);
+#else
+ (void) buf;
+#endif
+
return len;
}
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
index e5ae6c69d1..026c7c3df6 100644
--- a/hw/bsp/stm32h7/family.cmake
+++ b/hw/bsp/stm32h7/family.cmake
@@ -22,57 +22,59 @@ set(FAMILY_MCUS STM32H7 CACHE INTERNAL "")
#------------------------------------
# only need to be built ONCE for all examples
function(add_board_target BOARD_TARGET)
- if (NOT TARGET ${BOARD_TARGET})
- # Startup & Linker script
- set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
- set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
- set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-
- set(LD_FILE_Clang ${LD_FILE_GNU})
- if(NOT DEFINED LD_FILE_IAR)
- set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
- endif()
-
- add_library(${BOARD_TARGET} STATIC
- ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
- ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+ set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+ if(NOT DEFINED LD_FILE_IAR)
+ set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+ endif()
+
+ add_library(${BOARD_TARGET} STATIC
+ ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMSIS_5}/CMSIS/Core/Include
+ ${ST_CMSIS}/Include
+ ${ST_HAL_DRIVER}/Inc
+ )
+ #target_compile_options(${BOARD_TARGET} PUBLIC)
+ #target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
)
- target_include_directories(${BOARD_TARGET} PUBLIC
- ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
- ${CMSIS_5}/CMSIS/Core/Include
- ${ST_CMSIS}/Include
- ${ST_HAL_DRIVER}/Inc
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
)
- #target_compile_options(${BOARD_TARGET} PUBLIC)
- #target_compile_definitions(${BOARD_TARGET} PUBLIC)
-
- update_board(${BOARD_TARGET})
-
- if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--script=${LD_FILE_GNU}"
- -nostartfiles
- --specs=nosys.specs --specs=nano.specs
- )
- elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--script=${LD_FILE_Clang}"
- )
- elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--config=${LD_FILE_IAR}"
- )
- endif ()
endif ()
endfunction()
diff --git a/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld
index 336afc01fa..ba18c8cd16 100644
--- a/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld
+++ b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld
@@ -32,23 +32,24 @@
/* Entry Point */
ENTRY(Reset_Handler)
-/* Highest address of the user mode stack */
-_estack = 0x20020000; /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
/* Specify the memory areas */
MEMORY
{
-DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
-RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
-RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
-RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
-ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
+ DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
+ RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
+ RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
+ RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
+ ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
+
}
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1); /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
/* Define output sections */
SECTIONS
{
@@ -127,7 +128,7 @@ SECTIONS
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
- } >DTCMRAM AT> FLASH
+ } >RAM_D1 AT> FLASH
/* Uninitialized data section */
@@ -144,7 +145,9 @@ SECTIONS
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
- } >DTCMRAM
+ } >RAM_D1
+
+
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
@@ -155,9 +158,7 @@ SECTIONS
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
- } >DTCMRAM
-
-
+ } >RAM_D1
/* Remove information from the standard libraries */
/DISCARD/ :
diff --git a/hw/bsp/stm32l0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32l0/FreeRTOSConfig/FreeRTOSConfig.h
index 37e7e09435..40146e73a9 100644
--- a/hw/bsp/stm32l0/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32l0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -44,7 +44,7 @@
// skip if included from IAR assembler
#ifndef __IASMARM__
- #include "stm32f0xx.h"
+ #include "stm32l0xx.h"
#endif
/* Cortex M23/M33 port configuration. */
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
index c8963199b5..ee83bbcbcd 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
@@ -54,16 +54,17 @@
//--------------------------------------------------------------------+
static inline void board_stm32l0_clock_init(void)
{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
- static RCC_CRSInitTypeDef RCC_CRSInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
/* Enable HSI Oscillator to be used as System clock source
Enable HSI48 Oscillator to be used as USB clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Select HSI48 as USB clock source */
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake b/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake
index 8d7b537d54..895bbb3abc 100644
--- a/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.cmake
@@ -1,5 +1,6 @@
set(MCU_VARIANT stm32l053xx)
set(JLINK_DEVICE stm32l053r8)
+#set(JLINK_OPTION "-USB 778921770")
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L053C8Tx_FLASH.ld)
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
index 0722e31024..5cda1c15a6 100644
--- a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
@@ -54,16 +54,17 @@
//--------------------------------------------------------------------+
static inline void board_stm32l0_clock_init(void)
{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
- static RCC_CRSInitTypeDef RCC_CRSInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
/* Enable HSI Oscillator to be used as System clock source
Enable HSI48 Oscillator to be used as USB clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Select HSI48 as USB clock source */
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
index ea7f0b73d9..c8c88d687d 100644
--- a/hw/bsp/stm32l0/family.c
+++ b/hw/bsp/stm32l0/family.c
@@ -126,6 +126,19 @@ uint32_t board_button_read(void) {
return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ (void) max_len;
+ volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+ uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+ uint8_t const len = 12;
+
+ id32[0] = stm32_uuid[0];
+ id32[1] = stm32_uuid[1];
+ id32[2] = stm32_uuid[2];
+
+ return len;
+}
+
int board_uart_read(uint8_t* buf, int len) {
(void) buf;
(void) len;
diff --git a/hw/bsp/stm32l0/family.cmake b/hw/bsp/stm32l0/family.cmake
index 962c55587e..c04927585e 100644
--- a/hw/bsp/stm32l0/family.cmake
+++ b/hw/bsp/stm32l0/family.cmake
@@ -22,55 +22,57 @@ set(FAMILY_MCUS STM32L0 CACHE INTERNAL "")
#------------------------------------
# only need to be built ONCE for all examples
function(add_board_target BOARD_TARGET)
- if (NOT TARGET ${BOARD_TARGET})
- # Startup & Linker script
- set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
- set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
- set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-
- set(LD_FILE_Clang ${LD_FILE_GNU})
- set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
- add_library(${BOARD_TARGET} STATIC
- ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
- ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+ set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+ set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+ add_library(${BOARD_TARGET} STATIC
+ ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMSIS_5}/CMSIS/Core/Include
+ ${ST_CMSIS}/Include
+ ${ST_HAL_DRIVER}/Inc
+ )
+ #target_compile_options(${BOARD_TARGET} PUBLIC)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CFG_EXAMPLE_MSC_READONLY
+ CFG_EXAMPLE_VIDEO_READONLY
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
)
- target_include_directories(${BOARD_TARGET} PUBLIC
- ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
- ${CMSIS_5}/CMSIS/Core/Include
- ${ST_CMSIS}/Include
- ${ST_HAL_DRIVER}/Inc
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
)
- #target_compile_options(${BOARD_TARGET} PUBLIC)
- target_compile_definitions(${BOARD_TARGET} PUBLIC
- CFG_EXAMPLE_MSC_READONLY
- CFG_EXAMPLE_VIDEO_READONLY
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
)
-
- update_board(${BOARD_TARGET})
-
- if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--script=${LD_FILE_GNU}"
- -nostartfiles
- --specs=nosys.specs --specs=nano.specs
- )
- elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--script=${LD_FILE_Clang}"
- )
- elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--config=${LD_FILE_IAR}"
- )
- endif ()
endif ()
endfunction()
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake
index 4ade0a5c97..fd1c931c2a 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake
@@ -1,6 +1,6 @@
set(MCU_VARIANT stm32l476xx)
set(JLINK_DEVICE stm32l476vg)
-
+# set(JLINK_OPTION "-USB 000777632258")
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L476VGTx_FLASH.ld)
function(update_board TARGET)
diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake
index c42b6a8d7b..b6eae7c7f8 100644
--- a/hw/bsp/stm32l4/family.cmake
+++ b/hw/bsp/stm32l4/family.cmake
@@ -22,55 +22,57 @@ set(FAMILY_MCUS STM32L4 CACHE INTERNAL "")
#------------------------------------
# only need to be built ONCE for all examples
function(add_board_target BOARD_TARGET)
- if (NOT TARGET ${BOARD_TARGET})
- # Startup & Linker script
- set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
- set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
- set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-
- set(LD_FILE_Clang ${LD_FILE_GNU})
- set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
- add_library(${BOARD_TARGET} STATIC
- ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
- ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
- )
- target_include_directories(${BOARD_TARGET} PUBLIC
- ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
- ${CMSIS_5}/CMSIS/Core/Include
- ${ST_CMSIS}/Include
- ${ST_HAL_DRIVER}/Inc
- )
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+ set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+ set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+ add_library(${BOARD_TARGET} STATIC
+ ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMSIS_5}/CMSIS/Core/Include
+ ${ST_CMSIS}/Include
+ ${ST_HAL_DRIVER}/Inc
+ )
# target_compile_options(${BOARD_TARGET} PUBLIC)
# target_compile_definitions(${BOARD_TARGET} PUBLIC)
- update_board(${BOARD_TARGET})
-
- if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--script=${LD_FILE_GNU}"
- -nostartfiles
- --specs=nosys.specs --specs=nano.specs
- )
- elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--script=${LD_FILE_Clang}"
- )
- elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--config=${LD_FILE_IAR}"
- )
- endif ()
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
endif ()
endfunction()
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake
new file mode 100644
index 0000000000..1cb92d7109
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32u585xx)
+set(JLINK_DEVICE stm32u585zi)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ STM32U585xx
+ )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
new file mode 100644
index 0000000000..2f1c451db2
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h
@@ -0,0 +1,112 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOH
+#define LED_PIN GPIO_PIN_7
+#define LED_STATE_ON 0
+
+// BUTTON
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV USART1
+#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOA
+#define UART_GPIO_AF GPIO_AF7_USART1
+#define UART_TX_PIN GPIO_PIN_9
+#define UART_RX_PIN GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static void SystemClock_Config(void) {
+ RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
+
+ /* Enable Power Clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /** Configure the main internal regulator output voltage
+ */
+ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+ RCC_OscInitStruct.PLL.PLLM = 1;
+ RCC_OscInitStruct.PLL.PLLN = 10;
+ RCC_OscInitStruct.PLL.PLLP = 2;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 1;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType =
+ RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+}
+
+static void SystemPower_Config(void) {
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk
new file mode 100644
index 0000000000..ae63afef32
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += \
+ -DSTM32U585xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
+
+MCU_VARIANT = stm32u585xx
+# For flash-jlink target
+JLINK_DEVICE = stm32u585zi
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake
new file mode 100644
index 0000000000..d425019485
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32u545xx)
+set(JLINK_DEVICE stm32u545re)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ STM32U545xx
+ )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
new file mode 100644
index 0000000000..7f3bf462ce
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h
@@ -0,0 +1,112 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOA
+#define LED_PIN GPIO_PIN_5
+#define LED_STATE_ON 1
+
+// BUTTON
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV LPUART1
+#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOA
+#define UART_GPIO_AF GPIO_AF8_LPUART1
+#define UART_TX_PIN GPIO_PIN_2
+#define UART_RX_PIN GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static void SystemClock_Config(void) {
+ RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
+
+ /* Enable Power Clock */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /** Configure the main internal regulator output voltage
+ */
+ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+ RCC_OscInitStruct.PLL.PLLM = 1;
+ RCC_OscInitStruct.PLL.PLLN = 10;
+ RCC_OscInitStruct.PLL.PLLP = 2;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 1;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType =
+ RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+}
+
+static void SystemPower_Config(void) {
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
new file mode 100644
index 0000000000..072c595fbc
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += \
+ -DSTM32U545xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = ${FAMILY_PATH}/linker/STM32U545xx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u545xx.s
+
+MCU_VARIANT = stm32u545xx
+# For flash-jlink target
+JLINK_DEVICE = stm32u545re
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
index 922d67f83a..fee56f2baa 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
@@ -6,5 +6,6 @@ LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
+MCU_VARIANT = stm32u575xx
# For flash-jlink target
JLINK_DEVICE = stm32u575ai
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
index 1dd157a688..c83ec39992 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
@@ -6,5 +6,6 @@ LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
+MCU_VARIANT = stm32u575xx
# For flash-jlink target
JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
index e759cec24c..4bebe33301 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
@@ -7,5 +7,6 @@ LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s
+MCU_VARIANT = stm32u5a5xx
# For flash-jlink target
JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index ec64f7622b..3cc7cc5115 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -72,7 +72,9 @@ void board_init(void) {
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
+#ifdef GPIOF
__HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
@@ -140,6 +142,17 @@ void board_init(void) {
GPIO_InitStruct.Alternate = GPIO_AF10_USB;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+#ifdef USB_DRD_FS
+ // STM32U535/STM32U545
+
+ /* Enable USB power on Pwrctrl CR2 register */
+ HAL_PWREx_EnableVddUSB();
+
+ /* USB clock enable */
+ __HAL_RCC_USB_FS_CLK_ENABLE();
+
+#endif
+
#ifdef USB_OTG_FS
#if CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
@@ -170,7 +183,9 @@ void board_init(void) {
/* USB clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-#else
+#endif
+
+#ifdef USB_OTG_HS
// STM59x/Ax/Fx/Gx only have 1 USB HS port
#if CFG_TUSB_OS == OPT_OS_FREERTOS
@@ -203,7 +218,8 @@ void board_init(void) {
//--------------------------------------------------------------------+
void board_led_write(bool state) {
- HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+ GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
+ HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
}
uint32_t board_button_read(void) {
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
index d3cb78abf2..f7a7aeb337 100644
--- a/hw/bsp/stm32u5/family.cmake
+++ b/hw/bsp/stm32u5/family.cmake
@@ -22,55 +22,57 @@ set(FAMILY_MCUS STM32U5 CACHE INTERNAL "")
#------------------------------------
# only need to be built ONCE for all examples
function(add_board_target BOARD_TARGET)
- if (NOT TARGET ${BOARD_TARGET})
- # Startup & Linker script
- set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
- set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
- set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-
- string(REPLACE "stm32u" "STM32U" MCU_VARIANT_UPPER ${MCU_VARIANT})
- if (NOT DEFINED LD_FILE_GNU)
- set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT_UPPER}_FLASH.ld)
- endif ()
- set(LD_FILE_Clang ${LD_FILE_GNU})
- set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
- add_library(${BOARD_TARGET} STATIC
- ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_icache.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
- ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
- ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+ set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+ string(REPLACE "stm32u" "STM32U" MCU_VARIANT_UPPER ${MCU_VARIANT})
+ if (NOT DEFINED LD_FILE_GNU)
+ set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT_UPPER}_FLASH.ld)
+ endif ()
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+ set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+ add_library(${BOARD_TARGET} STATIC
+ ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_icache.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMSIS_5}/CMSIS/Core/Include
+ ${ST_CMSIS}/Include
+ ${ST_HAL_DRIVER}/Inc
+ )
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
)
- target_include_directories(${BOARD_TARGET} PUBLIC
- ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
- ${CMSIS_5}/CMSIS/Core/Include
- ${ST_CMSIS}/Include
- ${ST_HAL_DRIVER}/Inc
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_Clang}"
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
)
- update_board(${BOARD_TARGET})
-
- if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--script=${LD_FILE_GNU}"
- -nostartfiles
- --specs=nosys.specs --specs=nano.specs
- )
- elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--script=${LD_FILE_Clang}"
- )
- elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
- target_link_options(${BOARD_TARGET} PUBLIC
- "LINKER:--config=${LD_FILE_IAR}"
- )
- endif ()
endif ()
endfunction()
@@ -100,10 +102,16 @@ function(family_configure_example TARGET RTOS)
# Add TinyUSB target and port source
family_add_tinyusb(${TARGET} OPT_MCU_STM32U5 ${RTOS})
- target_sources(${TARGET}-tinyusb PUBLIC
- ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
- #${TOP}/src/portable/st/typec/typec_stm32.c
- )
+ if ((${MCU_VARIANT} STREQUAL "stm32u535xx") OR (${MCU_VARIANT} STREQUAL "stm32u545xx"))
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+ )
+ else ()
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+ #${TOP}/src/portable/st/typec/typec_stm32.c
+ )
+ endif ()
target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
# Link dependencies
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index be58093407..89193b99f5 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -27,18 +27,28 @@ LDFLAGS_GCC += \
--specs=nosys.specs --specs=nano.specs
SRC_C += \
- src/portable/synopsys/dwc2/dcd_dwc2.c \
$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
- $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
+ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+ifeq ($(MCU_VARIANT),stm32u545xx)
+SRC_C += \
+ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+else ifeq ($(MCU_VARIANT),stm32u535xx)
+SRC_C += \
+ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+else
+SRC_C += \
+ src/portable/synopsys/dwc2/dcd_dwc2.c
+endif
+
INC += \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(ST_CMSIS)/Include \
diff --git a/hw/bsp/stm32wb/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32wb/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..6ad115f606
--- /dev/null
+++ b/hw/bsp/stm32wb/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "stm32wbxx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+ #define configENABLE_FPU 1
+#else
+ #define configENABLE_FPU 0
+#endif
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/bsp/tm4c123/boards/ek_tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
similarity index 77%
rename from hw/bsp/tm4c123/boards/ek_tm4c123gxl/tm4c123.ld
rename to hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
index 351857bd6a..11e9608cc0 100644
--- a/hw/bsp/tm4c123/boards/ek_tm4c123gxl/tm4c123.ld
+++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/tm4c123.ld
@@ -24,6 +24,7 @@ SECTIONS
*(.fini)
*(.rodata)
*(.rodata.*)
+ *(.ARM.exidx*)
. = ALIGN(4) ;
__end_text = . ;
} >FLASH
@@ -52,14 +53,14 @@ SECTIONS
. = ALIGN(4);
}>SRAM
- /* User_heap_stack section, used to check that there is enough RAM left */
- ._user_heap_stack :
- {
- . = ALIGN(8);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(8);
- } >SRAM
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >SRAM
}
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c/family.c
similarity index 72%
rename from hw/bsp/tm4c123/family.c
rename to hw/bsp/tm4c/family.c
index 738bc3fa0d..5e1f6d3ffd 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c/family.c
@@ -5,8 +5,7 @@
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USB0_Handler(void)
-{
+void USB0_Handler(void) {
#if CFG_TUH_ENABLED
tuh_int_handler(0, true);
#endif
@@ -20,8 +19,7 @@ void USB0_Handler(void)
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
-static void board_uart_init (void)
-{
+static void board_uart_init(void) {
SYSCTL->RCGCUART |= (1 << 0); // Enable the clock to UART0
SYSCTL->RCGCGPIO |= (1 << 0); // Enable the clock to GPIOA
@@ -42,13 +40,12 @@ static void board_uart_init (void)
UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Receive Enable
}
-static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk)
-{
+static void initialize_board_led(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk) {
/* Enable PortF Clock */
SYSCTL->RCGCGPIO |= (1 << 5);
/* Let the clock stabilize */
- while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) {}
+ while (!((SYSCTL->PRGPIO) & (1 << 5))) {}
/* Port Digital Enable */
port->DEN |= PinMsk;
@@ -57,46 +54,33 @@ static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirm
port->DIR = dirmsk;
}
-static void board_switch_init (void)
-{
- GPIOF->DIR &= ~(1 << BOARD_BTN);
- GPIOF->PUR |= (1 << BOARD_BTN);
- GPIOF->DEN |= (1 << BOARD_BTN);
-}
-
-static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state)
-{
- if ( state )
- {
+static void WriteGPIOPin(GPIOA_Type* port, uint8_t PinMsk, bool state) {
+ if (state) {
port->DATA |= PinMsk;
- }
- else
- {
+ } else {
port->DATA &= ~(PinMsk);
}
}
-static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk)
-{
+static uint32_t ReadGPIOPin(GPIOA_Type* port, uint8_t pinMsk) {
return (port->DATA & pinMsk);
}
-void board_init (void)
-{
+void board_init(void) {
SystemCoreClockUpdate();
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
- // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
- NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#endif
/* Reset USB */
SYSCTL->SRCR2 |= (1u << 16);
- for ( volatile uint8_t i = 0; i < 20; i++ ) {}
+ for (volatile uint8_t i = 0; i < 20; i++) {}
SYSCTL->SRCR2 &= ~(1u << 16);
@@ -110,7 +94,7 @@ void board_init (void)
SYSCTL->RCGCGPIO |= (1u << 3);
/* Let the clock stabilize */
- while ( !(SYSCTL->PRGPIO & (1u << 3)) ) {}
+ while (!(SYSCTL->PRGPIO & (1u << 3))) {}
/* USB IOs to Analog Mode */
GPIOD->AFSEL &= ~((1u << 4) | (1u << 5));
@@ -124,7 +108,9 @@ void board_init (void)
initialize_board_led(LED_PORT, leds, dirmsk);
/* Configure GPIO for board switch */
- board_switch_init();
+ GPIOF->DIR &= ~(1 << BOARD_BTN);
+ GPIOF->PUR |= (1 << BOARD_BTN);
+ GPIOF->DEN |= (1 << BOARD_BTN);
/* Initialize board UART */
board_uart_init();
@@ -132,32 +118,35 @@ void board_init (void)
TU_LOG1_INT(SystemCoreClock);
}
-void board_led_write (bool state)
-{
+void board_led_write(bool state) {
WriteGPIOPin(LED_PORT, (1 << LED_PIN_BLUE), state);
}
-uint32_t board_button_read (void)
-{
+uint32_t board_button_read(void) {
uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk);
return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value;
}
-int board_uart_write (void const *buf, int len)
-{
- uint8_t const * data = buf;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ (void) max_len;
+ uint8_t const len = 8;
+ // Note: DID0, DID1 are variant ID, they aer used since TM4C123 does not have unique ID
+ memcpy(id, (void*)(uintptr_t) &SYSCTL->DID0, len);
+ return len;
+}
- for ( int i = 0; i < len; i++ )
- {
- while ( (UART0->FR & (1 << 5)) != 0 ) {} // Poll until previous data was shofted out
- UART0->DR = data[i]; // Write UART0 DATA REGISTER
+int board_uart_write(void const* buf, int len) {
+ uint8_t const* data = buf;
+
+ for (int i = 0; i < len; i++) {
+ while ((UART0->FR & (1 << 5)) != 0) {} // Poll until previous data was shofted out
+ UART0->DR = data[i]; // Write UART0 DATA REGISTER
}
return len;
}
-int board_uart_read (uint8_t *buf, int len)
-{
+int board_uart_read(uint8_t* buf, int len) {
(void) buf;
(void) len;
return 0;
@@ -165,13 +154,13 @@ int board_uart_read (uint8_t *buf, int len)
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
system_ticks++;
}
-uint32_t board_millis (void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
+
#endif
diff --git a/hw/bsp/tm4c/family.cmake b/hw/bsp/tm4c/family.cmake
new file mode 100644
index 0000000000..9c083759bd
--- /dev/null
+++ b/hw/bsp/tm4c/family.cmake
@@ -0,0 +1,96 @@
+include_guard()
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(MCU_VARIANT tm4c${MCU_SUB_VARIANT})
+set(MCU_VARIANT_UPPER TM4C${MCU_SUB_VARIANT})
+
+set(SDK_DIR ${TOP}/hw/mcu/ti/${MCU_VARIANT}xx)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS TM4C123 CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ set(LD_FILE_Clang ${LD_FILE_GNU})
+
+ set(STARTUP_FILE_GNU ${SDK_DIR}/Source/GCC/${MCU_VARIANT}_startup.c)
+ set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/Source/system_${MCU_VARIANT_UPPER}.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}/Include/${MCU_VARIANT_UPPER}
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ --specs=nosys.specs --specs=nano.specs
+ -uvectors
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+ message(FATAL_ERROR "Clang is not supported for MSP432E4")
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_TM4C123 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/mentor/musb/dcd_musb.c
+ ${TOP}/src/portable/mentor/musb/hcd_musb.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_add_bin_hex(${TARGET})
+ family_flash_openocd(${TARGET})
+ family_flash_uniflash(${TARGET})
+endfunction()
diff --git a/hw/bsp/tm4c/family.mk b/hw/bsp/tm4c/family.mk
new file mode 100644
index 0000000000..76ae785b23
--- /dev/null
+++ b/hw/bsp/tm4c/family.mk
@@ -0,0 +1,28 @@
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
+MCU_VARIANT = tm4c${MCU_SUB_VARIANT}
+MCU_VARIANT_UPPER = TM4C${MCU_SUB_VARIANT}
+
+SDK_DIR = hw/mcu/ti/${MCU_VARIANT}xx
+
+CFLAGS += \
+ -flto \
+ -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
+ -uvectors \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
+
+LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
+
+INC += \
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+ $(TOP)/$(SDK_DIR)/Include/${MCU_VARIANT_UPPER} \
+ $(TOP)/$(BOARD_PATH)
+
+SRC_C += \
+ src/portable/mentor/musb/dcd_musb.c \
+ src/portable/mentor/musb/hcd_musb.c \
+ $(SDK_DIR)/Source/system_${MCU_VARIANT_UPPER}.c \
+ $(SDK_DIR)/Source/GCC/${MCU_VARIANT}_startup.c
diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk
deleted file mode 100644
index 49e39f6a03..0000000000
--- a/hw/bsp/tm4c123/family.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/ti
-MCU_DIR=hw/mcu/ti/tm4c123xx
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-CPU_CORE ?= cortex-m4
-
-CFLAGS += \
- -flto \
- -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
- -uvectors \
- -DTM4C123GH6PM
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/tm4c123.ld
-
-INC += \
- $(TOP)/$(MCU_DIR)/CMSIS/5.7.0/CMSIS/Include \
- $(TOP)/$(MCU_DIR)/Include/TM4C123 \
- $(TOP)/$(BOARD_PATH)
-
-SRC_C += \
- src/portable/mentor/musb/dcd_musb.c \
- src/portable/mentor/musb/hcd_musb.c \
- $(MCU_DIR)/Source/system_TM4C123.c \
- $(MCU_DIR)/Source/GCC/tm4c123_startup.c
diff --git a/hw/bsp/xmc4000/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/xmc4000/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 0000000000..76eacea39e
--- /dev/null
+++ b/hw/bsp/xmc4000/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "xmc_device.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configCHECK_HANDLER_INSTALLATION 0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 6
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< 0
- IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
+ tu_static IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO
+ tu_static osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO
#endif
#endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
- IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
+ tu_static IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO
+ tu_static osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO
#endif
#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
- IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
+ tu_static IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO
+ tu_static osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO
#endif
#endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
#endif // CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
@@ -144,38 +147,38 @@
// - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
#if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING)
#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
- CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
+ tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
#endif
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
- CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
+ tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
#endif
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
- CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
+ tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
#endif
#endif // CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
// EP OUT software buffers and mutexes
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
- OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+ tu_static OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO
+ tu_static osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO
#endif
#endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
- OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
+ tu_static OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO
+ tu_static osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO
#endif
#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
- OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
+ tu_static OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO
+ tu_static osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO
#endif
#endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
@@ -185,89 +188,89 @@
// - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
- CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
+ tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
#endif
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
- CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
+ tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
#endif
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
- CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
+ tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
#endif
#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
// Control buffers
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
+tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
#if CFG_TUD_AUDIO > 1
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
+tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
#endif
#if CFG_TUD_AUDIO > 2
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
+tu_static CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
#endif
// Active alternate setting of interfaces
-uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
+tu_static uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_N_AS_INT > 0
-uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
+tu_static uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
#endif
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_N_AS_INT > 0
-uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
+tu_static uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
#endif
// Software encoding/decoding support FIFOs
#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
#if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
- CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
- tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
+ tu_static CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
+ tu_static tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
+ tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
#endif
#endif
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
- CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
- tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
+ tu_static CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
+ tu_static tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
+ tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
#endif
#endif
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
- CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
- tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
+ tu_static CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
+ tu_static tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
+ tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
#endif
#endif
#endif
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
#if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
- CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
- tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
+ tu_static CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
+ tu_static tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
+ tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
#endif
#endif
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
- CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
- tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
+ tu_static CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
+ tu_static tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
+ tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
#endif
#endif
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
- CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
- tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
+ tu_static CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
+ tu_static tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
#if CFG_FIFO_MUTEX
- osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
+ tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
#endif
#endif
#endif
@@ -300,32 +303,18 @@ typedef struct
bool mounted; // Device opened
- /*------------- From this point, data is not cleared by bus reset -------------*/
-
uint16_t desc_length; // Length of audio function descriptor
- // Buffer for control requests
- uint8_t * ctrl_buf;
- uint8_t ctrl_buf_sz;
-
- // Current active alternate settings
- uint8_t * alt_setting; // We need to save the current alternate setting this way, because it is possible that there are AS interfaces which do not have an EP!
-
- // EP Transfer buffers and FIFOs
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
-#if !CFG_TUD_AUDIO_ENABLE_DECODING
- tu_fifo_t ep_out_ff;
-#endif
-
#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
struct {
- CFG_TUSB_MEM_ALIGN uint32_t value; // Feedback value for asynchronous mode (in 16.16 format).
+ CFG_TUSB_MEM_ALIGN uint32_t send_buf;
+ uint32_t value; // Feedback value for asynchronous mode (in 16.16 format).
uint32_t min_value; // min value according to UAC2 FMT-2.0 section 2.3.1.1.
uint32_t max_value; // max value according to UAC2 FMT-2.0 section 2.3.1.1.
uint8_t frame_shift; // bInterval-1 in unit of frame (FS), micro-frame (HS)
uint8_t compute_method;
-
+ bool format_correction;
union {
uint8_t power_of_2; // pre-computed power of 2 shift
float float_const; // pre-computed float constant
@@ -335,28 +324,17 @@ typedef struct
uint32_t mclk_freq;
}fixed;
-#if 0 // implement later
struct {
- uint32_t nominal_value;
- uint32_t threshold_bytes;
+ uint32_t nom_value; // In 16.16 format
+ uint32_t fifo_lvl_avg; // In 16.16 format
+ uint16_t fifo_lvl_thr; // fifo level threshold
+ uint16_t rate_const[2]; // pre-computed feedback/fifo_depth rate
}fifo_count;
-#endif
}compute;
} feedback;
#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
-
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
- tu_fifo_t ep_in_ff;
-#endif
-
- // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
-#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
- CFG_TUSB_MEM_ALIGN uint8_t ep_int_buf[6];
-#endif
-
// Decoding parameters - parameters are set when alternate AS interface is set by host
// Coding is currently only supported for EP. Software coding corresponding to AS interfaces without EPs are not supported currently.
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
@@ -365,8 +343,7 @@ typedef struct
#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
audio_data_format_type_I_t format_type_I_rx;
- uint8_t n_bytes_per_sampe_rx;
- uint8_t n_channels_per_ff_rx;
+ uint8_t n_bytes_per_sample_rx;
uint8_t n_ff_used_rx;
#endif
#endif
@@ -382,26 +359,54 @@ typedef struct
#if CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL)
audio_format_type_t format_type_tx;
uint8_t n_channels_tx;
- uint8_t n_bytes_per_sampe_tx;
+ uint8_t n_bytes_per_sample_tx;
#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
audio_data_format_type_I_t format_type_I_tx;
- uint8_t n_channels_per_ff_tx;
uint8_t n_ff_used_tx;
#endif
#endif
+ /*------------- From this point, data is not cleared by bus reset -------------*/
+
+ // Buffer for control requests
+ uint8_t * ctrl_buf;
+ uint8_t ctrl_buf_sz;
+
+ // Current active alternate settings
+ uint8_t * alt_setting; // We need to save the current alternate setting this way, because it is possible that there are AS interfaces which do not have an EP!
+
+ // EP Transfer buffers and FIFOs
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
+ tu_fifo_t ep_out_ff;
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
+ tu_fifo_t ep_in_ff;
+#endif
+
+ // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+ CFG_TUSB_MEM_ALIGN uint8_t ep_int_buf[6];
+#endif
+
// Support FIFOs for software encoding and decoding
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
tu_fifo_t * rx_supp_ff;
uint8_t n_rx_supp_ff;
uint16_t rx_supp_ff_sz_max;
+#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+ uint8_t n_channels_per_ff_rx;
+#endif
#endif
#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
tu_fifo_t * tx_supp_ff;
uint8_t n_tx_supp_ff;
uint16_t tx_supp_ff_sz_max;
+#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+ uint8_t n_channels_per_ff_tx;
+#endif
#endif
// Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR the support FIFOs are used
@@ -427,10 +432,147 @@ typedef struct
#define ITF_MEM_RESET_SIZE offsetof(audiod_function_t, ctrl_buf)
+//--------------------------------------------------------------------+
+// WEAK FUNCTION STUBS
+//--------------------------------------------------------------------+
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN
+TU_ATTR_WEAK bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting) {
+ (void) rhport;
+ (void) func_id;
+ (void) ep_in;
+ (void) cur_alt_setting;
+ return true;
+}
+
+TU_ATTR_WEAK bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting) {
+ (void) rhport;
+ (void) n_bytes_copied;
+ (void) func_id;
+ (void) ep_in;
+ (void) cur_alt_setting;
+ return true;
+}
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+TU_ATTR_WEAK bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting) {
+ (void) rhport;
+ (void) n_bytes_received;
+ (void) func_id;
+ (void) ep_out;
+ (void) cur_alt_setting;
+ return true;
+}
+
+TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting) {
+ (void) rhport;
+ (void) n_bytes_received;
+ (void) func_id;
+ (void) ep_out;
+ (void) cur_alt_setting;
+ return true;
+}
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id) {
+ (void) func_id;
+}
+
+TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param) {
+ (void) func_id;
+ (void) alt_itf;
+ feedback_param->method = AUDIO_FEEDBACK_METHOD_DISABLED;
+}
+
+TU_ATTR_WEAK bool tud_audio_feedback_format_correction_cb(uint8_t func_id) {
+ (void) func_id;
+ return CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION;
+}
+#endif
+
+TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift) {
+ (void) func_id;
+ (void) frame_number;
+ (void) interval_shift;
+}
+
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+TU_ATTR_WEAK void tud_audio_int_done_cb(uint8_t rhport) {
+ (void) rhport;
+}
+#endif
+
+// Invoked when audio set interface request received
+TU_ATTR_WEAK bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request) {
+ (void) rhport;
+ (void) p_request;
+ return true;
+}
+
+// Invoked when audio set interface request received which closes an EP
+TU_ATTR_WEAK bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request) {
+ (void) rhport;
+ (void) p_request;
+ return true;
+}
+
+// Invoked when audio class specific set request received for an EP
+TU_ATTR_WEAK bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff) {
+ (void) rhport;
+ (void) p_request;
+ (void) pBuff;
+ TU_LOG2(" No EP set request callback available!\r\n");
+ return false; // In case no callback function is present or request can not be conducted we stall it
+}
+
+// Invoked when audio class specific set request received for an interface
+TU_ATTR_WEAK bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff) {
+ (void) rhport;
+ (void) p_request;
+ (void) pBuff;
+ TU_LOG2(" No interface set request callback available!\r\n");
+ return false; // In case no callback function is present or request can not be conducted we stall it
+}
+
+// Invoked when audio class specific set request received for an entity
+TU_ATTR_WEAK bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff) {
+ (void) rhport;
+ (void) p_request;
+ (void) pBuff;
+ TU_LOG2(" No entity set request callback available!\r\n");
+ return false; // In case no callback function is present or request can not be conducted we stall it
+}
+
+// Invoked when audio class specific get request received for an EP
+TU_ATTR_WEAK bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request) {
+ (void) rhport;
+ (void) p_request;
+ TU_LOG2(" No EP get request callback available!\r\n");
+ return false; // Stall
+}
+
+// Invoked when audio class specific get request received for an interface
+TU_ATTR_WEAK bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request) {
+ (void) rhport;
+ (void) p_request;
+ TU_LOG2(" No interface get request callback available!\r\n");
+ return false; // Stall
+}
+
+// Invoked when audio class specific get request received for an entity
+TU_ATTR_WEAK bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request) {
+ (void) rhport;
+ (void) p_request;
+ TU_LOG2(" No entity get request callback available!\r\n");
+ return false; // Stall
+}
+
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
-CFG_TUD_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO];
+tu_static CFG_TUD_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO];
#if CFG_TUD_AUDIO_ENABLE_EP_OUT
static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received);
@@ -473,7 +615,8 @@ static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t da
#endif
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq);
+static bool audiod_set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq);
+static void audiod_fb_fifo_count_update(audiod_function_t* audio, uint16_t lvl_new);
#endif
bool tud_audio_n_mounted(uint8_t func_id)
@@ -554,19 +697,13 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
uint8_t const *dummy2;
uint8_t idx_audio_fct = 0;
- if (tud_audio_rx_done_pre_read_cb || tud_audio_rx_done_post_read_cb)
- {
- idx_audio_fct = audiod_get_audio_fct_idx(audio);
- TU_VERIFY(audiod_get_AS_interface_index(audio->ep_out_as_intf_num, audio, &idxItf, &dummy2));
- }
+ idx_audio_fct = audiod_get_audio_fct_idx(audio);
+ TU_VERIFY(audiod_get_AS_interface_index(audio->ep_out_as_intf_num, audio, &idxItf, &dummy2));
// Call a weak callback here - a possibility for user to get informed an audio packet was received and data gets now loaded into EP FIFO (or decoded into support RX software FIFO)
- if (tud_audio_rx_done_pre_read_cb)
- {
- TU_VERIFY(tud_audio_rx_done_pre_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
- }
+ TU_VERIFY(tud_audio_rx_done_pre_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
-#if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT
+#if CFG_TUD_AUDIO_ENABLE_DECODING
switch (audio->format_type_rx)
{
@@ -615,13 +752,17 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_out, &audio->ep_out_ff, audio->ep_out_sz), false);
#endif
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+ if(audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FIFO_COUNT)
+ {
+ audiod_fb_fifo_count_update(audio, tu_fifo_count(&audio->ep_out_ff));
+ }
+#endif
+
#endif
// Call a weak callback here - a possibility for user to get informed decoding was completed
- if (tud_audio_rx_done_post_read_cb)
- {
- TU_VERIFY(tud_audio_rx_done_post_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
- }
+ TU_VERIFY(tud_audio_rx_done_post_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
return true;
}
@@ -707,16 +848,16 @@ static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, u
if (info.len_lin != 0)
{
info.len_lin = tu_min16(nBytesPerFFToRead, info.len_lin);
- src = &audio->lin_buf_out[cnt_ff*audio->n_channels_per_ff_rx * audio->n_bytes_per_sampe_rx];
+ src = &audio->lin_buf_out[cnt_ff*audio->n_channels_per_ff_rx * audio->n_bytes_per_sample_rx];
dst_end = info.ptr_lin + info.len_lin;
- src = audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sampe_rx, info.ptr_lin, dst_end, src, n_ff_used);
+ src = audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sample_rx, info.ptr_lin, dst_end, src, n_ff_used);
// Handle wrapped part of FIFO
info.len_wrap = tu_min16(nBytesPerFFToRead - info.len_lin, info.len_wrap);
if (info.len_wrap != 0)
{
dst_end = info.ptr_wrap + info.len_wrap;
- audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sampe_rx, info.ptr_wrap, dst_end, src, n_ff_used);
+ audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sample_rx, info.ptr_wrap, dst_end, src, n_ff_used);
}
tu_fifo_advance_write_pointer(&audio->rx_supp_ff[cnt_ff], info.len_lin + info.len_wrap);
}
@@ -725,6 +866,13 @@ static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, u
// Number of bytes should be a multiple of CFG_TUD_AUDIO_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_N_CHANNELS_RX but checking makes no sense - no way to correct it
// TU_VERIFY(cnt != n_bytes);
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+ if(audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FIFO_COUNT)
+ {
+ audiod_fb_fifo_count_update(audio, tu_fifo_count(&audio->rx_supp_ff[0]));
+ }
+#endif
+
return true;
}
#endif //CFG_TUD_AUDIO_ENABLE_DECODING
@@ -848,7 +996,7 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
// Call a weak callback here - a possibility for user to get informed former TX was completed and data gets now loaded into EP in buffer (in case FIFOs are used) or
// if no FIFOs are used the user may use this call back to load its data into the EP IN buffer by use of tud_audio_n_write_ep_in_buffer().
- if (tud_audio_tx_done_pre_load_cb) TU_VERIFY(tud_audio_tx_done_pre_load_cb(rhport, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf]));
+ TU_VERIFY(tud_audio_tx_done_pre_load_cb(rhport, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf]));
// Send everything in ISO EP FIFO
uint16_t n_bytes_tx;
@@ -911,7 +1059,7 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
#endif
// Call a weak callback here - a possibility for user to get informed former TX was completed and how many bytes were loaded for the next frame
- if (tud_audio_tx_done_post_load_cb) TU_VERIFY(tud_audio_tx_done_post_load_cb(rhport, n_bytes_tx, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf]));
+ TU_VERIFY(tud_audio_tx_done_post_load_cb(rhport, n_bytes_tx, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf]));
return true;
}
@@ -1024,7 +1172,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
// Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT!
nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, audio->ep_in_sz / n_ff_used);
// Round to full number of samples (flooring)
- uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx;
+ uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx;
nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize;
#endif
@@ -1036,7 +1184,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
for (cnt_ff = 0; cnt_ff < n_ff_used; cnt_ff++)
{
- dst = &audio->lin_buf_in[cnt_ff*audio->n_channels_per_ff_tx*audio->n_bytes_per_sampe_tx];
+ dst = &audio->lin_buf_in[cnt_ff*audio->n_channels_per_ff_tx*audio->n_bytes_per_sample_tx];
tu_fifo_get_read_info(&audio->tx_supp_ff[cnt_ff], &info);
@@ -1044,7 +1192,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
{
info.len_lin = tu_min16(nBytesPerFFToSend, info.len_lin); // Limit up to desired length
src_end = (uint8_t *)info.ptr_lin + info.len_lin;
- dst = audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sampe_tx, info.ptr_lin, src_end, dst, n_ff_used);
+ dst = audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sample_tx, info.ptr_lin, src_end, dst, n_ff_used);
// Limit up to desired length
info.len_wrap = tu_min16(nBytesPerFFToSend - info.len_lin, info.len_wrap);
@@ -1053,7 +1201,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
if (info.len_wrap != 0)
{
src_end = (uint8_t *)info.ptr_wrap + info.len_wrap;
- audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sampe_tx, info.ptr_wrap, src_end, dst, n_ff_used);
+ audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sample_tx, info.ptr_wrap, src_end, dst, n_ff_used);
}
tu_fifo_advance_read_pointer(&audio->tx_supp_ff[cnt_ff], info.len_lin + info.len_wrap);
@@ -1067,9 +1215,38 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
// This function is called once a transmit of a feedback packet was successfully completed. Here, we get the next feedback value to be sent
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-static inline bool audiod_fb_send(uint8_t rhport, audiod_function_t *audio)
+static inline bool audiod_fb_send(audiod_function_t *audio)
{
- return usbd_edpt_xfer(rhport, audio->ep_fb, (uint8_t *) &audio->feedback.value, 4);
+ bool apply_correction = (TUSB_SPEED_FULL == tud_speed_get()) && audio->feedback.format_correction;
+ // Format the feedback value
+ if (apply_correction)
+ {
+ uint8_t * fb = (uint8_t *) &audio->feedback.send_buf;
+
+ // For FS format is 10.14
+ *(fb++) = (audio->feedback.value >> 2) & 0xFF;
+ *(fb++) = (audio->feedback.value >> 10) & 0xFF;
+ *(fb++) = (audio->feedback.value >> 18) & 0xFF;
+ *fb = 0;
+ } else
+ {
+ audio->feedback.send_buf = audio->feedback.value;
+ }
+
+ // About feedback format on FS
+ //
+ // 3 variables: Format | packetSize | sendSize | Working OS:
+ // 16.16 4 4 Linux, Windows
+ // 16.16 4 3 Linux
+ // 16.16 3 4 Linux
+ // 16.16 3 3 Linux
+ // 10.14 4 4 Linux
+ // 10.14 4 3 Linux
+ // 10.14 3 4 Linux, OSX
+ // 10.14 3 3 Linux, OSX
+ //
+ // We send 3 bytes since sending packet larger than wMaxPacketSize is pretty ugly
+ return usbd_edpt_xfer(audio->rhport, audio->ep_fb, (uint8_t *) &audio->feedback.send_buf, apply_correction ? 3 : 4);
}
#endif
@@ -1490,7 +1667,8 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
#endif
uint8_t const *p_desc = _audiod_fct[i].p_desc;
uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
- while (p_desc < p_desc_end)
+ // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+ while (p_desc_end - p_desc > 0)
{
if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
{
@@ -1686,7 +1864,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
#endif
// Invoke callback - can be used to stop data sampling
- if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
+ TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
audio->ep_in = 0; // Necessary?
@@ -1717,7 +1895,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
#endif
// Invoke callback - can be used to stop data sampling
- if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
+ TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
audio->ep_out = 0; // Necessary?
@@ -1740,7 +1918,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
uint8_t const *p_desc_end = audio->p_desc + audio->desc_length - TUD_AUDIO_DESC_IAD_LEN;
// p_desc starts at required interface with alternate setting zero
- while (p_desc < p_desc_end)
+ // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+ while (p_desc_end - p_desc > 0)
{
// Find correct interface
if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == alt)
@@ -1750,7 +1929,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
#endif
// From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary
uint8_t foundEPs = 0, nEps = ((tusb_desc_interface_t const * )p_desc)->bNumEndpoints;
- while (foundEPs < nEps && p_desc < p_desc_end)
+ // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+ while (foundEPs < nEps && (p_desc_end - p_desc > 0))
{
if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
{
@@ -1779,8 +1959,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
// Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
#if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
- const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / (audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx))
- * (audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx));
+ const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / (audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx))
+ * (audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx));
for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
{
tu_fifo_config(&audio->tx_supp_ff[cnt], audio->tx_supp_ff[cnt].buffer, active_fifo_depth, 1, true);
@@ -1810,7 +1990,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
// Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
- const uint16_t active_fifo_depth = (audio->rx_supp_ff_sz_max / audio->n_bytes_per_sampe_rx) * audio->n_bytes_per_sampe_rx;
+ const uint16_t active_fifo_depth = (audio->rx_supp_ff_sz_max / audio->n_bytes_per_sample_rx) * audio->n_bytes_per_sample_rx;
for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++)
{
tu_fifo_config(&audio->rx_supp_ff[cnt], audio->rx_supp_ff[cnt].buffer, active_fifo_depth, 1, true);
@@ -1833,9 +2013,6 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
{
audio->ep_fb = ep_addr;
audio->feedback.frame_shift = desc_ep->bInterval -1;
-
- // Enable SOF interrupt if callback is implemented
- if (tud_audio_feedback_interval_isr) usbd_sof_enable(rhport, true);
}
#endif
#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -1848,20 +2025,23 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
TU_VERIFY(foundEPs == nEps);
// Invoke one callback for a final set interface
- if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+ TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
- // Prepare feedback computation if callback is available
- if (tud_audio_feedback_params_cb)
+ // Prepare feedback computation if endpoint is available
+ if(audio->ep_fb != 0)
{
audio_feedback_params_t fb_param;
tud_audio_feedback_params_cb(func_id, alt, &fb_param);
audio->feedback.compute_method = fb_param.method;
+ if(TUSB_SPEED_FULL == tud_speed_get())
+ audio->feedback.format_correction = tud_audio_feedback_format_correction_cb(func_id);
+
// Minimal/Maximum value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
uint32_t const frame_div = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
- audio->feedback.min_value = (fb_param.sample_freq/frame_div - 1) << 16;
+ audio->feedback.min_value = ((fb_param.sample_freq - 1)/frame_div) << 16;
audio->feedback.max_value = (fb_param.sample_freq/frame_div + 1) << 16;
switch(fb_param.method)
@@ -1869,20 +2049,32 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED:
case AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT:
case AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2:
- set_fb_params_freq(audio, fb_param.sample_freq, fb_param.frequency.mclk_freq);
+ audiod_set_fb_params_freq(audio, fb_param.sample_freq, fb_param.frequency.mclk_freq);
break;
- #if 0 // implement later
case AUDIO_FEEDBACK_METHOD_FIFO_COUNT:
{
- uint64_t fb64 = ((uint64_t) fb_param.sample_freq) << 16;
- audio->feedback.compute.fifo_count.nominal_value = (uint32_t) (fb64 / frame_div);
- audio->feedback.compute.fifo_count.threshold_bytes = fb_param.fifo_count.threshold_bytes;
-
- tud_audio_fb_set(audio->feedback.compute.fifo_count.nominal_value);
+ // Initialize the threshold level to half filled
+ uint16_t fifo_lvl_thr;
+#if CFG_TUD_AUDIO_ENABLE_DECODING
+ fifo_lvl_thr = tu_fifo_depth(&audio->rx_supp_ff[0]) / 2;
+#else
+ fifo_lvl_thr = tu_fifo_depth(&audio->ep_out_ff) / 2;
+#endif
+ audio->feedback.compute.fifo_count.fifo_lvl_thr = fifo_lvl_thr;
+ audio->feedback.compute.fifo_count.fifo_lvl_avg = ((uint32_t)fifo_lvl_thr) << 16;
+ // Avoid 64bit division
+ uint32_t nominal = ((fb_param.sample_freq / 100) << 16) / (frame_div / 100);
+ audio->feedback.compute.fifo_count.nom_value = nominal;
+ audio->feedback.compute.fifo_count.rate_const[0] = (uint16_t) ((audio->feedback.max_value - nominal) / fifo_lvl_thr);
+ audio->feedback.compute.fifo_count.rate_const[1] = (uint16_t) ((nominal - audio->feedback.min_value) / fifo_lvl_thr);
+ // On HS feedback is more sensitive since packet size can vary every MSOF, could cause instability
+ if(tud_speed_get() == TUSB_SPEED_HIGH) {
+ audio->feedback.compute.fifo_count.rate_const[0] /= 8;
+ audio->feedback.compute.fifo_count.rate_const[1] /= 8;
+ }
}
break;
- #endif
// nothing to do
default: break;
@@ -1900,16 +2092,19 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
// Disable SOF interrupt if no driver has any enabled feedback EP
- bool disable = true;
+ bool enable_sof = false;
for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
{
- if (_audiod_fct[i].ep_fb != 0)
+ if (_audiod_fct[i].ep_fb != 0 &&
+ (_audiod_fct[i].feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED ||
+ _audiod_fct[i].feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT ||
+ _audiod_fct[i].feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2 ))
{
- disable = false;
+ enable_sof = true;
break;
}
}
- if (disable) usbd_sof_enable(rhport, false);
+ usbd_sof_enable(rhport, SOF_CONSUMER_AUDIO, enable_sof);
#endif
#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
@@ -1939,35 +2134,19 @@ static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const
if (entityID != 0)
{
- if (tud_audio_set_req_entity_cb)
- {
- // Check if entity is present and get corresponding driver index
- TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
+ // Check if entity is present and get corresponding driver index
+ TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
- // Invoke callback
- return tud_audio_set_req_entity_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
- }
- else
- {
- TU_LOG2(" No entity set request callback available!\r\n");
- return false; // In case no callback function is present or request can not be conducted we stall it
- }
+ // Invoke callback
+ return tud_audio_set_req_entity_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
}
else
{
- if (tud_audio_set_req_itf_cb)
- {
- // Find index of audio driver structure and verify interface really exists
- TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
+ // Find index of audio driver structure and verify interface really exists
+ TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
- // Invoke callback
- return tud_audio_set_req_itf_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
- }
- else
- {
- TU_LOG2(" No interface set request callback available!\r\n");
- return false; // In case no callback function is present or request can not be conducted we stall it
- }
+ // Invoke callback
+ return tud_audio_set_req_itf_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
}
}
break;
@@ -1976,19 +2155,11 @@ static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const
{
uint8_t ep = TU_U16_LOW(p_request->wIndex);
- if (tud_audio_set_req_ep_cb)
- {
- // Check if entity is present and get corresponding driver index
- TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
+ // Check if entity is present and get corresponding driver index
+ TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
- // Invoke callback
- return tud_audio_set_req_ep_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
- }
- else
- {
- TU_LOG2(" No EP set request callback available!\r\n");
- return false; // In case no callback function is present or request can not be conducted we stall it
- }
+ // Invoke callback
+ return tud_audio_set_req_ep_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
}
break;
// Unknown/Unsupported recipient
@@ -2045,15 +2216,7 @@ static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const
// In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
{
- if (tud_audio_get_req_entity_cb)
- {
- return tud_audio_get_req_entity_cb(rhport, p_request);
- }
- else
- {
- TU_LOG2(" No entity get request callback available!\r\n");
- return false; // Stall
- }
+ return tud_audio_get_req_entity_cb(rhport, p_request);
}
}
else
@@ -2064,15 +2227,7 @@ static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const
// In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
{
- if (tud_audio_get_req_itf_cb)
- {
- return tud_audio_get_req_itf_cb(rhport, p_request);
- }
- else
- {
- TU_LOG2(" No interface get request callback available!\r\n");
- return false; // Stall
- }
+ return tud_audio_get_req_itf_cb(rhport, p_request);
}
}
}
@@ -2088,15 +2243,7 @@ static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const
// In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
{
- if (tud_audio_get_req_ep_cb)
- {
- return tud_audio_get_req_ep_cb(rhport, p_request);
- }
- else
- {
- TU_LOG2(" No EP get request callback available!\r\n");
- return false; // Stall
- }
+ return tud_audio_get_req_ep_cb(rhport, p_request);
}
}
break;
@@ -2151,7 +2298,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
// I assume here, that things above are handled by PHY
// All transmission is done - what remains to do is to inform job was completed
- if (tud_audio_int_done_cb) tud_audio_int_done_cb(rhport);
+ tud_audio_int_done_cb(rhport);
return true;
}
@@ -2192,13 +2339,13 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
// Transmission of feedback EP finished
if (audio->ep_fb == ep_addr)
{
- if (tud_audio_fb_done_cb) tud_audio_fb_done_cb(func_id);
+ tud_audio_fb_done_cb(func_id);
// Schedule a transmit with the new value if EP is not busy
- if (!usbd_edpt_busy(rhport, audio->ep_fb))
+ if (usbd_edpt_claim(rhport, audio->ep_fb))
{
// Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent
- return audiod_fb_send(rhport, audio);
+ return audiod_fb_send(audio);
}
}
#endif
@@ -2210,7 +2357,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq)
+static bool audiod_set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq)
{
// Check if frame interval is within sane limits
// The interval value n_frames was taken from the descriptors within audiod_set_interface()
@@ -2229,11 +2376,11 @@ static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, u
if ((mclk_freq % sample_freq) == 0 && tu_is_power_of_two(mclk_freq / sample_freq))
{
audio->feedback.compute_method = AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2;
- audio->feedback.compute.power_of_2 = 16 - audio->feedback.frame_shift - tu_log2(mclk_freq / sample_freq);
+ audio->feedback.compute.power_of_2 = (uint8_t) (16 - (audio->feedback.frame_shift - 1) - tu_log2(mclk_freq / sample_freq));
}
else if ( audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT)
{
- audio->feedback.compute.float_const = (float)sample_freq / mclk_freq * (1UL << (16 - audio->feedback.frame_shift));
+ audio->feedback.compute.float_const = (float)sample_freq / (float) mclk_freq * (1UL << (16 - (audio->feedback.frame_shift - 1)));
}
else
{
@@ -2244,6 +2391,38 @@ static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, u
return true;
}
+static void audiod_fb_fifo_count_update(audiod_function_t* audio, uint16_t lvl_new)
+{
+ /* Low-pass (averaging) filter */
+ uint32_t lvl = audio->feedback.compute.fifo_count.fifo_lvl_avg;
+ lvl = (uint32_t)(((uint64_t)lvl * 63 + ((uint32_t)lvl_new << 16)) >> 6);
+ audio->feedback.compute.fifo_count.fifo_lvl_avg = lvl;
+
+ uint32_t const ff_lvl = lvl >> 16;
+ uint16_t const ff_thr = audio->feedback.compute.fifo_count.fifo_lvl_thr;
+ uint16_t const *rate = audio->feedback.compute.fifo_count.rate_const;
+
+ uint32_t feedback;
+
+ if(ff_lvl < ff_thr)
+ {
+ feedback = audio->feedback.compute.fifo_count.nom_value + (ff_thr - ff_lvl) * rate[0];
+ } else
+ {
+ feedback = audio->feedback.compute.fifo_count.nom_value - (ff_lvl - ff_thr) * rate[1];
+ }
+
+ if ( feedback > audio->feedback.max_value ) feedback = audio->feedback.max_value;
+ if ( feedback < audio->feedback.min_value ) feedback = audio->feedback.min_value;
+ audio->feedback.value = feedback;
+
+ // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value
+ if (usbd_edpt_claim(audio->rhport, audio->ep_fb))
+ {
+ audiod_fb_send(audio);
+ }
+}
+
uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
{
audiod_function_t* audio = &_audiod_fct[func_id];
@@ -2261,7 +2440,7 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED:
{
- uint64_t fb64 = (((uint64_t) cycles) * audio->feedback.compute.fixed.sample_freq) << (16 - audio->feedback.frame_shift);
+ uint64_t fb64 = (((uint64_t) cycles) * audio->feedback.compute.fixed.sample_freq) << (16 - (audio->feedback.frame_shift - 1));
feedback = (uint32_t) (fb64 / audio->feedback.compute.fixed.mclk_freq);
}
break;
@@ -2280,6 +2459,21 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
return feedback;
}
+
+bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
+{
+ TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
+
+ _audiod_fct[func_id].feedback.value = feedback;
+
+ // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value
+ if (usbd_edpt_claim(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_fb))
+ {
+ return audiod_fb_send(&_audiod_fct[func_id]);
+ }
+
+ return true;
+}
#endif
TU_ATTR_FAST_FUNC void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
@@ -2306,7 +2500,7 @@ TU_ATTR_FAST_FUNC void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
uint32_t const interval = 1UL << (audio->feedback.frame_shift - hs_adjust);
if ( 0 == (frame_count & (interval-1)) )
{
- if(tud_audio_feedback_interval_isr) tud_audio_feedback_interval_isr(i, frame_count, audio->feedback.frame_shift);
+ tud_audio_feedback_interval_isr(i, frame_count, audio->feedback.frame_shift);
}
}
}
@@ -2394,7 +2588,8 @@ static bool audiod_get_AS_interface_index(uint8_t itf, audiod_function_t * audio
p_desc += ((audio_desc_cs_ac_interface_t const *)p_desc)->wTotalLength;
uint8_t tmp = 0;
- while (p_desc < p_desc_end)
+ // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+ while (p_desc_end - p_desc > 0)
{
// We assume the number of alternate settings is increasing thus we return the index of alternate setting zero!
if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == 0)
@@ -2447,7 +2642,8 @@ static bool audiod_verify_entity_exists(uint8_t itf, uint8_t entityID, uint8_t *
uint8_t const *p_desc_end = ((audio_desc_cs_ac_interface_t const *)p_desc)->wTotalLength + p_desc;
p_desc = tu_desc_next(p_desc); // Get past CS AC descriptor
- while (p_desc < p_desc_end)
+ // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+ while (p_desc_end - p_desc > 0)
{
if (p_desc[3] == entityID) // Entity IDs are always at offset 3
{
@@ -2471,8 +2667,8 @@ static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id)
// Get pointer at beginning and end
uint8_t const *p_desc = _audiod_fct[i].p_desc;
uint8_t const *p_desc_end = _audiod_fct[i].p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
-
- while (p_desc < p_desc_end)
+ // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+ while (p_desc_end - p_desc > 0)
{
if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const *)_audiod_fct[i].p_desc)->bInterfaceNumber == itf)
{
@@ -2500,7 +2696,8 @@ static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id)
uint8_t const *p_desc = tu_desc_next(_audiod_fct[i].p_desc);
p_desc += ((audio_desc_cs_ac_interface_t const *)p_desc)->wTotalLength;
- while (p_desc < p_desc_end)
+ // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+ while (p_desc_end - p_desc > 0)
{
if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT && ((tusb_desc_endpoint_t const * )p_desc)->bEndpointAddress == ep)
{
@@ -2531,8 +2728,8 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
#endif
p_desc = tu_desc_next(p_desc); // Exclude standard AS interface descriptor of current alternate interface descriptor
-
- while (p_desc < p_desc_end)
+ // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+ while (p_desc_end - p_desc > 0)
{
// Abort if follow up descriptor is a new standard interface descriptor - indicates the last AS descriptor was already finished
if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) break;
@@ -2581,14 +2778,14 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
#if CFG_TUD_AUDIO_ENABLE_EP_IN
if (as_itf == audio->ep_in_as_intf_num)
{
- audio->n_bytes_per_sampe_tx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize;
+ audio->n_bytes_per_sample_tx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize;
}
#endif
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
if (as_itf == audio->ep_out_as_intf_num)
{
- audio->n_bytes_per_sampe_rx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize;
+ audio->n_bytes_per_sample_rx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize;
}
#endif
}
@@ -2607,7 +2804,7 @@ static bool audiod_calc_tx_packet_sz(audiod_function_t* audio)
{
TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I);
TU_VERIFY(audio->n_channels_tx);
- TU_VERIFY(audio->n_bytes_per_sampe_tx);
+ TU_VERIFY(audio->n_bytes_per_sample_tx);
TU_VERIFY(audio->interval_tx);
TU_VERIFY(audio->sample_rate_tx);
@@ -2616,9 +2813,9 @@ static bool audiod_calc_tx_packet_sz(audiod_function_t* audio)
const uint16_t sample_normimal = (uint16_t)(audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000));
const uint16_t sample_reminder = (uint16_t)(audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000));
- const uint16_t packet_sz_tx_min = (uint16_t)((sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
- const uint16_t packet_sz_tx_norm = (uint16_t)(sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
- const uint16_t packet_sz_tx_max = (uint16_t)((sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
+ const uint16_t packet_sz_tx_min = (uint16_t)((sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sample_tx);
+ const uint16_t packet_sz_tx_norm = (uint16_t)(sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sample_tx);
+ const uint16_t packet_sz_tx_max = (uint16_t)((sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sample_tx);
// Endpoint size must larger than packet size
TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
@@ -2691,44 +2888,8 @@ static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t da
#endif
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-
-bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
-{
- TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
-
- // Format the feedback value
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION
- if ( TUSB_SPEED_FULL == tud_speed_get() )
- {
- uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].feedback.value;
-
- // For FS format is 10.14
- *(fb++) = (feedback >> 2) & 0xFF;
- *(fb++) = (feedback >> 10) & 0xFF;
- *(fb++) = (feedback >> 18) & 0xFF;
- // 4th byte is needed to work correctly with MS Windows
- *fb = 0;
- }else
-#else
- {
- // Send value as-is, caller will choose the appropriate format
- _audiod_fct[func_id].feedback.value = feedback;
- }
-#endif
-
- // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value
- if (!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_fb))
- {
- return audiod_fb_send(_audiod_fct[func_id].rhport, &_audiod_fct[func_id]);
- }
-
- return true;
-}
-#endif
-
// No security checks here - internal function only which should always succeed
-uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio)
+static uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio)
{
for (uint8_t cnt=0; cnt < CFG_TUD_AUDIO; cnt++)
{
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index b16514fd41..ae253f49d2 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -3,6 +3,7 @@
*
* Copyright (c) 2020 Ha Thach (tinyusb.org)
* Copyright (c) 2020 Reinhard Panhuber
+ * Copyright (c) 2023 HiFiPhile
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -192,6 +193,7 @@
#endif
// Enable/disable conversion from 16.16 to 10.14 format on full-speed devices. See tud_audio_n_fb_set().
+// Can be override by tud_audio_feedback_format_correction_cb()
#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION
#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION 0 // 0 or 1
#endif
@@ -242,7 +244,8 @@
// Enable encoding/decodings - for these to work, support FIFOs need to be setup in appropriate numbers and size
// The actual coding parameters of active AS alternate interface is parsed from the descriptors
-// The item size of the FIFO is always fixed to one i.e. bytes! Furthermore, the actively used FIFO depth is reconfigured such that the depth is a multiple of the current sample size in order to avoid samples to get split up in case of a wrap in the FIFO ring buffer (depth = (max_depth / sampe_sz) * sampe_sz)!
+// The item size of the FIFO is always fixed to one i.e. bytes! Furthermore, the actively used FIFO depth is reconfigured such that the depth is a multiple
+// of the current sample size in order to avoid samples to get split up in case of a wrap in the FIFO ring buffer (depth = (max_depth / sample_sz) * sample_sz)!
// This is important to remind in case you use DMAs! If the sample sizes changes, the DMA MUST BE RECONFIGURED just like the FIFOs for a different depth!!!
// For PCM encoding/decoding
@@ -446,63 +449,80 @@ static inline bool tud_audio_int_write (const audio_interru
bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_request_t const * p_request, void* data, uint16_t len);
//--------------------------------------------------------------------+
-// Application Callback API (weak is optional)
+// Application Callback API
//--------------------------------------------------------------------+
#if CFG_TUD_AUDIO_ENABLE_EP_IN
-TU_ATTR_WEAK bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting);
-TU_ATTR_WEAK bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting);
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting);
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting);
#endif
#if CFG_TUD_AUDIO_ENABLE_EP_OUT
-TU_ATTR_WEAK bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting);
-TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting);
+bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting);
+bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting);
#endif
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id);
+void tud_audio_fb_done_cb(uint8_t func_id);
-// determined by the user itself and set by use of tud_audio_n_fb_set(). The feedback value may be determined e.g. from some fill status of some FIFO buffer. Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load, disadvantage: typically a larger FIFO is needed to compensate for jitter (e.g. 8 frames), i.e. a larger delay is introduced.
-
-// Feedback value is calculated within the audio driver by use of SOF interrupt. The driver needs information about the master clock f_m from which the audio sample frequency f_s is derived, f_s itself, and the cycle count of f_m at time of the SOF interrupt (e.g. by use of a hardware counter) - see tud_audio_set_fb_params(). Advantage: Reduced jitter in the feedback value computation, hence, the receive FIFO can be smaller (e.g. 2 frames) and thus a smaller delay is possible, disadvantage: higher CPU load due to SOF ISR handling every frame i.e. 1ms or 125us. This option is a great starting point to try the SOF ISR option but depending on your hardware setup (performance of the CPU) it might not work. If so, figure out why and use the next option. (The most critical point is the reading of the cycle counter value of f_m. It is read from within the SOF ISR - see: audiod_sof() -, hence, the ISR must has a high priority such that no software dependent "random" delay i.e. jitter is introduced).
+// Note about feedback calculation
+//
+// Option 1 - AUDIO_FEEDBACK_METHOD_FIFO_COUNT
+// Feedback value is calculated within the audio driver by regulating the FIFO level to half fill.
+// Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load, well tested
+// (Windows, Linux, OSX) with a reliable result so far.
+// Disadvantage: A FIFO of minimal 4 frames is needed to compensate for jitter, an average delay of 2 frames is introduced.
+//
+// Option 2 - AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED / AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT
+// Feedback value is calculated within the audio driver by use of SOF interrupt. The driver needs information about the master clock f_m from
+// which the audio sample frequency f_s is derived, f_s itself, and the cycle count of f_m at time of the SOF interrupt (e.g. by use of a hardware counter).
+// See tud_audio_set_fb_params() and tud_audio_feedback_update()
+// Advantage: Reduced jitter in the feedback value computation, hence, the receive FIFO can be smaller and thus a smaller delay is possible.
+// Disadvantage: higher CPU load due to SOF ISR handling every frame i.e. 1ms or 125us. (The most critical point is the reading of the cycle counter value of f_m.
+// It is read from within the SOF ISR - see: audiod_sof() -, hence, the ISR must has a high priority such that no software dependent "random" delay i.e. jitter is introduced).
+// Long-term drift could occur since error is accumulated.
+//
+// Option 3 - manual
+// Determined by the user itself and set by use of tud_audio_n_fb_set(). The feedback value may be determined e.g. from some fill status of some FIFO buffer.
+// Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load.
+// Disadvantage: typically a larger FIFO is needed to compensate for jitter (e.g. 6 frames), i.e. a larger delay is introduced.
-// Feedback value is determined by the user by use of SOF interrupt. The user may use tud_audio_sof_isr() which is called every SOF (of course only invoked when an alternate interface other than zero was set). The number of frames used to determine the feedback value for the currently active alternate setting can be get by tud_audio_get_fb_n_frames(). The feedback value must be set by use of tud_audio_n_fb_set().
// This function is used to provide data rate feedback from an asynchronous sink. Feedback value will be sent at FB endpoint interval till it's changed.
//
// The feedback format is specified to be 16.16 for HS and 10.14 for FS devices (see Universal Serial Bus Specification Revision 2.0 5.12.4.2). By default,
-// the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set, then tinyusb
-// expects 16.16 format and handles the conversion to 10.14 on FS.
+// the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set or tud_audio_feedback_format_correction_cb()
+// return true, then tinyusb expects 16.16 format and handles the conversion to 10.14 on FS.
+//
+// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and it seems the
+// driver can work with either format.
//
-// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the
-// driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
-
// Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value.
-
+//
// Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
// Boiled down, the feedback value Ff = n_samples / (micro)frame.
-// Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_m is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
+// Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13
+// for high speed, f_s is the sampling frequency e.g. 48 kHz and f_m is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
// The update interval in the (4.10.2.1) Feedback Endpoint Descriptor must be less or equal to 2^(K - P), where P = min( ceil(log2(f_m / f_s)), K)
// feedback = n_cycles / n_frames * f_s / f_m in 16.16 format, where n_cycles are the number of main clock cycles within fb_n_frames
-
bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
-static inline bool tud_audio_fb_set(uint32_t feedback);
-// Update feedback value with passed cycles since last time this update function is called.
+// Update feedback value with passed MCLK cycles since last time this update function is called.
// Typically called within tud_audio_sof_isr(). Required tud_audio_feedback_params_cb() is implemented
// This function will also call tud_audio_feedback_set()
// return feedback value in 16.16 for reference (0 for error)
+// Example :
+// binterval=3 (4ms); FS = 48kHz; MCLK = 12.288MHz
+// In 4 SOF MCLK counted 49152 cycles
uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles);
enum {
AUDIO_FEEDBACK_METHOD_DISABLED,
AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED,
AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT,
- AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2,
-
- // impelemnt later
- // AUDIO_FEEDBACK_METHOD_FIFO_COUNT
+ AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2, // For driver internal use only
+ AUDIO_FEEDBACK_METHOD_FIFO_COUNT
};
typedef struct {
@@ -514,52 +534,50 @@ typedef struct {
uint32_t mclk_freq; // Main clock frequency in Hz i.e. master clock to which sample clock is based on
}frequency;
-#if 0 // implement later
- struct {
- uint32_t threshold_bytes; // minimum number of bytes received to be considered as filled/ready
- }fifo_count;
-#endif
};
}audio_feedback_params_t;
// Invoked when needed to set feedback parameters
-TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param);
+void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param);
// Callback in ISR context, invoked periodically according to feedback endpoint bInterval.
// Could be used to compute and update feedback value, should be placed in RAM if possible
// frame_number : current SOF count
// interval_shift: number of bit shift i.e log2(interval) from Feedback endpoint descriptor
-TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift);
+TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift);
+// (Full-Speed only) Callback to set feedback format correction is applied or not,
+// default to CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION if not implemented.
+bool tud_audio_feedback_format_correction_cb(uint8_t func_id);
#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-TU_ATTR_WEAK void tud_audio_int_done_cb(uint8_t rhport);
+void tud_audio_int_done_cb(uint8_t rhport);
#endif
// Invoked when audio set interface request received
-TU_ATTR_WEAK bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request);
// Invoked when audio set interface request received which closes an EP
-TU_ATTR_WEAK bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request);
// Invoked when audio class specific set request received for an EP
-TU_ATTR_WEAK bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
// Invoked when audio class specific set request received for an interface
-TU_ATTR_WEAK bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
// Invoked when audio class specific set request received for an entity
-TU_ATTR_WEAK bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff);
// Invoked when audio class specific get request received for an EP
-TU_ATTR_WEAK bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request);
// Invoked when audio class specific get request received for an interface
-TU_ATTR_WEAK bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request);
// Invoked when audio class specific get request received for an entity
-TU_ATTR_WEAK bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request);
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request);
//--------------------------------------------------------------------+
// Inline Functions
diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index cbf6e13321..a79908627b 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -42,10 +42,14 @@ typedef struct
uint8_t itf_num;
uint8_t ep_ev;
uint8_t ep_acl_in;
+ uint16_t ep_acl_in_pkt_sz;
uint8_t ep_acl_out;
uint8_t ep_voice[2]; // Not used yet
uint8_t ep_voice_size[2][CFG_TUD_BTH_ISO_ALT_COUNT];
+ // Previous amount of bytes sent when issuing ZLP
+ uint32_t prev_xferred_bytes;
+
// Endpoint Transfer buffer
CFG_TUSB_MEM_ALIGN bt_hci_cmd_t hci_cmd;
CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_BTH_DATA_EPSIZE];
@@ -127,11 +131,25 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_
TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0);
_btd_itf.ep_ev = desc_ep->bEndpointAddress;
+ desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep);
+
// Open endpoint pair
- TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(desc_ep), 2, TUSB_XFER_BULK, &_btd_itf.ep_acl_out,
- &_btd_itf.ep_acl_in), 0);
+ TU_ASSERT(usbd_open_edpt_pair(rhport, (uint8_t const *)desc_ep, 2,
+ TUSB_XFER_BULK, &_btd_itf.ep_acl_out,
+ &_btd_itf.ep_acl_in),
+ 0);
+
+ // Save acl in endpoint max packet size
+ tusb_desc_endpoint_t const *desc_ep_acl_in = desc_ep;
+ for (size_t p = 0; p < 2; p++) {
+ if (tu_edpt_dir(desc_ep_acl_in->bEndpointAddress) == TUSB_DIR_IN) {
+ _btd_itf.ep_acl_in_pkt_sz = tu_edpt_packet_size(desc_ep_acl_in);
+ break;
+ }
+ desc_ep_acl_in = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep_acl_in);
+ }
- itf_desc = (tusb_desc_interface_t const *)tu_desc_next(tu_desc_next(tu_desc_next(desc_ep)));
+ itf_desc = (tusb_desc_interface_t const *)tu_desc_next(tu_desc_next(desc_ep));
// Prepare for incoming data from host
TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_itf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE), 0);
@@ -238,10 +256,8 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c
return true;
}
-bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
- (void)result;
-
+bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result,
+ uint32_t xferred_bytes) {
// received new data from host
if (ep_addr == _btd_itf.ep_acl_out)
{
@@ -256,7 +272,20 @@ bool btd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t
}
else if (ep_addr == _btd_itf.ep_acl_in)
{
- if (tud_bt_acl_data_sent_cb) tud_bt_acl_data_sent_cb((uint16_t)xferred_bytes);
+ if ((result == XFER_RESULT_SUCCESS) && (xferred_bytes > 0) &&
+ ((xferred_bytes & (_btd_itf.ep_acl_in_pkt_sz - 1)) == 0)) {
+ // Save number of transferred bytes
+ _btd_itf.prev_xferred_bytes = xferred_bytes;
+
+ // Send zero-length packet
+ tud_bt_acl_data_send(NULL, 0);
+ } else if (tud_bt_acl_data_sent_cb) {
+ if (xferred_bytes == 0) {
+ xferred_bytes = _btd_itf.prev_xferred_bytes;
+ _btd_itf.prev_xferred_bytes = 0;
+ }
+ tud_bt_acl_data_sent_cb((uint16_t)xferred_bytes);
+ }
}
return true;
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 5057805e2c..6d4aae1f29 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -45,8 +45,7 @@
//--------------------------------------------------------------------+
#define BULK_PACKET_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
-typedef struct
-{
+typedef struct {
uint8_t rhport;
uint8_t itf_num;
uint8_t ep_notif;
@@ -57,7 +56,7 @@ typedef struct
uint8_t line_state;
/*------------- From this point, data is not cleared by bus reset -------------*/
- char wanted_char;
+ char wanted_char;
TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding;
// FIFO
@@ -74,18 +73,21 @@ typedef struct
CFG_TUSB_MEM_ALIGN cdc_notif_serial_state_t serial_state_buf;
CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
-
-}cdcd_interface_t;
+} cdcd_interface_t;
#define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, wanted_char)
//--------------------------------------------------------------------+
// INTERNAL OBJECT & FUNCTION DECLARATION
//--------------------------------------------------------------------+
-CFG_TUD_MEM_SECTION tu_static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+CFG_TUD_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+static tud_cdc_configure_fifo_t _cdcd_fifo_cfg;
+
+static bool _prep_out_transaction (cdcd_interface_t* p_cdc) {
+
+ // Skip if usb is not ready yet
+ TU_VERIFY(tud_ready() && p_cdc->ep_out);
-static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
-{
uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff);
// Prepare for incoming data but only allow what we can store in the ring buffer.
@@ -100,14 +102,11 @@ static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
// fifo can be changed before endpoint is claimed
available = tu_fifo_remaining(&p_cdc->rx_ff);
- if ( available >= sizeof(p_cdc->epout_buf) )
- {
+ if ( available >= sizeof(p_cdc->epout_buf) ) {
return usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf));
- }else
- {
+ }else {
// Release endpoint since we don't make any transfer
usbd_edpt_release(p_cdc->rhport, p_cdc->ep_out);
-
return false;
}
}
@@ -115,28 +114,35 @@ static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
//--------------------------------------------------------------------+
// APPLICATION API
//--------------------------------------------------------------------+
-bool tud_cdc_n_connected(uint8_t itf)
-{
+
+bool tud_cdc_configure_fifo(tud_cdc_configure_fifo_t const* cfg) {
+ TU_VERIFY(cfg);
+ _cdcd_fifo_cfg = (*cfg);
+ return true;
+}
+
+bool tud_cdc_n_ready(uint8_t itf) {
+ return tud_ready() && _cdcd_itf[itf].ep_in != 0 && _cdcd_itf[itf].ep_out != 0;
+}
+
+bool tud_cdc_n_connected(uint8_t itf) {
// DTR (bit 0) active is considered as connected
return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0);
}
-uint8_t tud_cdc_n_get_line_state (uint8_t itf)
-{
+uint8_t tud_cdc_n_get_line_state(uint8_t itf) {
return _cdcd_itf[itf].line_state;
}
-void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding)
-{
+void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t* coding) {
(*coding) = _cdcd_itf[itf].line_coding;
}
-bool tud_cdc_n_send_uart_state (uint8_t itf, cdc_uart_state_t state)
-{
+bool tud_cdc_n_send_uart_state (uint8_t itf, cdc_uart_state_t state) {
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
// Skip if usb is not ready yet
- TU_VERIFY( tud_ready(), 0 );
+ TU_VERIFY(tud_ready(), 0);
// claim endpoint
TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_notif));
@@ -152,34 +158,29 @@ bool tud_cdc_n_send_uart_state (uint8_t itf, cdc_uart_state_t state)
return usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_notif, (uint8_t *)&p_cdc->serial_state_buf, sizeof(p_cdc->serial_state_buf));
}
-void tud_cdc_n_set_wanted_char (uint8_t itf, char wanted)
-{
+void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted) {
_cdcd_itf[itf].wanted_char = wanted;
}
//--------------------------------------------------------------------+
// READ API
//--------------------------------------------------------------------+
-uint32_t tud_cdc_n_available(uint8_t itf)
-{
+uint32_t tud_cdc_n_available(uint8_t itf) {
return tu_fifo_count(&_cdcd_itf[itf].rx_ff);
}
-uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
-{
+uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize) {
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
_prep_out_transaction(p_cdc);
return num_read;
}
-bool tud_cdc_n_peek(uint8_t itf, uint8_t* chr)
-{
+bool tud_cdc_n_peek(uint8_t itf, uint8_t* chr) {
return tu_fifo_peek(&_cdcd_itf[itf].rx_ff, chr);
}
-void tud_cdc_n_read_flush (uint8_t itf)
-{
+void tud_cdc_n_read_flush(uint8_t itf) {
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
tu_fifo_clear(&p_cdc->rx_ff);
_prep_out_transaction(p_cdc);
@@ -188,16 +189,15 @@ void tud_cdc_n_read_flush (uint8_t itf)
//--------------------------------------------------------------------+
// WRITE API
//--------------------------------------------------------------------+
-uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
-{
+uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize) {
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
// flush if queue more than packet size
- if ( tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE
- #if CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE
- || tu_fifo_full(&p_cdc->tx_ff) // check full if fifo size is less than packet size
- #endif
+ if (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE
+ #if CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE
+ || tu_fifo_full(&p_cdc->tx_ff) // check full if fifo size is less than packet size
+ #endif
) {
tud_cdc_n_write_flush(itf);
}
@@ -205,28 +205,25 @@ uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
return ret;
}
-uint32_t tud_cdc_n_write_flush (uint8_t itf)
-{
+uint32_t tud_cdc_n_write_flush(uint8_t itf) {
cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
// Skip if usb is not ready yet
- TU_VERIFY( tud_ready(), 0 );
+ TU_VERIFY(tud_ready(), 0);
// No data to send
- if ( !tu_fifo_count(&p_cdc->tx_ff) ) return 0;
+ if (!tu_fifo_count(&p_cdc->tx_ff)) return 0;
// Claim the endpoint
- TU_VERIFY( usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_in), 0 );
+ TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_in), 0);
// Pull data from FIFO
uint16_t const count = tu_fifo_read_n(&p_cdc->tx_ff, p_cdc->epin_buf, sizeof(p_cdc->epin_buf));
- if ( count )
- {
- TU_ASSERT( usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
+ if (count) {
+ TU_ASSERT(usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0);
return count;
- }else
- {
+ } else {
// Release endpoint since we don't make any transfer
// Note: data is dropped if terminal is not connected
usbd_edpt_release(p_cdc->rhport, p_cdc->ep_in);
@@ -234,33 +231,30 @@ uint32_t tud_cdc_n_write_flush (uint8_t itf)
}
}
-uint32_t tud_cdc_n_write_available (uint8_t itf)
-{
+uint32_t tud_cdc_n_write_available(uint8_t itf) {
return tu_fifo_remaining(&_cdcd_itf[itf].tx_ff);
}
-bool tud_cdc_n_write_clear (uint8_t itf)
-{
+bool tud_cdc_n_write_clear(uint8_t itf) {
return tu_fifo_clear(&_cdcd_itf[itf].tx_ff);
}
//--------------------------------------------------------------------+
// USBD Driver API
//--------------------------------------------------------------------+
-void cdcd_init(void)
-{
+void cdcd_init(void) {
tu_memclr(_cdcd_itf, sizeof(_cdcd_itf));
+ tu_memclr(&_cdcd_fifo_cfg, sizeof(_cdcd_fifo_cfg));
- for(uint8_t i=0; iwanted_char = (char) -1;
// default line coding is : stop bit = 1, parity = none, data bits = 8
- p_cdc->line_coding.bit_rate = 115200;
+ p_cdc->line_coding.bit_rate = 115200;
p_cdc->line_coding.stop_bits = 0;
- p_cdc->line_coding.parity = 0;
+ p_cdc->line_coding.parity = 0;
p_cdc->line_coding.data_bits = 8;
// Config RX fifo
@@ -304,33 +298,28 @@ bool cdcd_deinit(void) {
return true;
}
-void cdcd_reset(uint8_t rhport)
-{
+void cdcd_reset(uint8_t rhport) {
(void) rhport;
- for(uint8_t i=0; irx_ff);
- tu_fifo_clear(&p_cdc->tx_ff);
+ if (!_cdcd_fifo_cfg.rx_persistent) tu_fifo_clear(&p_cdc->rx_ff);
+ if (!_cdcd_fifo_cfg.tx_persistent) tu_fifo_clear(&p_cdc->tx_ff);
tu_fifo_set_overwritable(&p_cdc->tx_ff, true);
}
}
-uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
+uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) {
// Only support ACM subclass
TU_VERIFY( TUSB_CLASS_CDC == itf_desc->bInterfaceClass &&
CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, 0);
// Find available interface
- cdcd_interface_t * p_cdc = NULL;
- for(uint8_t cdc_id=0; cdc_iditf_num = itf_desc->bInterfaceNumber;
uint16_t drv_len = sizeof(tusb_desc_interface_t);
- uint8_t const * p_desc = tu_desc_next( itf_desc );
+ uint8_t const* p_desc = tu_desc_next(itf_desc);
// Communication Functional Descriptors
- while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
- {
+ while (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len) {
drv_len += tu_desc_len(p_desc);
- p_desc = tu_desc_next(p_desc);
+ p_desc = tu_desc_next(p_desc);
}
- if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
- {
+ if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) {
// notification endpoint
- tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+ tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc;
- TU_ASSERT( usbd_edpt_open(rhport, desc_ep), 0 );
+ TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0);
p_cdc->ep_notif = desc_ep->bEndpointAddress;
drv_len += tu_desc_len(p_desc);
- p_desc = tu_desc_next(p_desc);
+ p_desc = tu_desc_next(p_desc);
}
//------------- Data Interface (if any) -------------//
- if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
- (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
- {
+ if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+ (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) {
// next to endpoint descriptor
drv_len += tu_desc_len(p_desc);
- p_desc = tu_desc_next(p_desc);
+ p_desc = tu_desc_next(p_desc);
// Open endpoint pair
- TU_ASSERT( usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &p_cdc->ep_out, &p_cdc->ep_in), 0 );
+ TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &p_cdc->ep_out, &p_cdc->ep_in), 0);
- drv_len += 2*sizeof(tusb_desc_endpoint_t);
+ drv_len += 2 * sizeof(tusb_desc_endpoint_t);
}
// Prepare for incoming data
@@ -386,8 +372,7 @@ uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
// Invoked when a control transfer occurred on an interface of this class
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
// return false to stall control endpoint (e.g unsupported request)
-bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
+bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) {
// Handle class request only
TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
@@ -395,42 +380,33 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
cdcd_interface_t* p_cdc = _cdcd_itf;
// Identify which interface to use
- for ( ; ; itf++, p_cdc++)
- {
+ for (;; itf++, p_cdc++) {
if (itf >= TU_ARRAY_SIZE(_cdcd_itf)) return false;
- if ( p_cdc->itf_num == request->wIndex ) break;
+ if (p_cdc->itf_num == request->wIndex) break;
}
- switch ( request->bRequest )
- {
+ switch (request->bRequest) {
case CDC_REQUEST_SET_LINE_CODING:
- if (stage == CONTROL_STAGE_SETUP)
- {
+ if (stage == CONTROL_STAGE_SETUP) {
TU_LOG_DRV(" Set Line Coding\r\n");
tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
+ } else if (stage == CONTROL_STAGE_ACK) {
+ if (tud_cdc_line_coding_cb) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
}
- else if ( stage == CONTROL_STAGE_ACK)
- {
- if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
- }
- break;
+ break;
case CDC_REQUEST_GET_LINE_CODING:
- if (stage == CONTROL_STAGE_SETUP)
- {
+ if (stage == CONTROL_STAGE_SETUP) {
TU_LOG_DRV(" Get Line Coding\r\n");
tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
}
- break;
+ break;
case CDC_REQUEST_SET_CONTROL_LINE_STATE:
- if (stage == CONTROL_STAGE_SETUP)
- {
+ if (stage == CONTROL_STAGE_SETUP) {
tud_control_status(rhport, request);
- }
- else if (stage == CONTROL_STAGE_ACK)
- {
+ } else if (stage == CONTROL_STAGE_ACK) {
// CDC PSTN v1.2 section 6.3.12
// Bit 0: Indicates if DTE is present or not.
// This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
@@ -447,61 +423,54 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
TU_LOG_DRV(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
// Invoke callback
- if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
+ if (tud_cdc_line_state_cb) tud_cdc_line_state_cb(itf, dtr, rts);
}
- break;
+ break;
+
case CDC_REQUEST_SEND_BREAK:
- if (stage == CONTROL_STAGE_SETUP)
- {
+ if (stage == CONTROL_STAGE_SETUP) {
tud_control_status(rhport, request);
- }
- else if (stage == CONTROL_STAGE_ACK)
- {
+ } else if (stage == CONTROL_STAGE_ACK) {
TU_LOG_DRV(" Send Break\r\n");
- if ( tud_cdc_send_break_cb ) tud_cdc_send_break_cb(itf, request->wValue);
+ if (tud_cdc_send_break_cb) tud_cdc_send_break_cb(itf, request->wValue);
}
- break;
+ break;
- default: return false; // stall unsupported request
+ default:
+ return false; // stall unsupported request
}
return true;
}
-bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
(void) result;
uint8_t itf;
cdcd_interface_t* p_cdc;
// Identify which interface to use
- for (itf = 0; itf < CFG_TUD_CDC; itf++)
- {
+ for (itf = 0; itf < CFG_TUD_CDC; itf++) {
p_cdc = &_cdcd_itf[itf];
- if ( ( ep_addr == p_cdc->ep_out ) || ( ep_addr == p_cdc->ep_in ) || ( ep_addr == p_cdc->ep_notif )) break;
+ if ((ep_addr == p_cdc->ep_out) || (ep_addr == p_cdc->ep_in)|| (ep_addr == p_cdc->ep_notif)) break;
}
TU_ASSERT(itf < CFG_TUD_CDC);
// Received new data
- if ( ep_addr == p_cdc->ep_out )
- {
+ if (ep_addr == p_cdc->ep_out) {
tu_fifo_write_n(&p_cdc->rx_ff, p_cdc->epout_buf, (uint16_t) xferred_bytes);
// Check for wanted char and invoke callback if needed
- if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
- {
- for ( uint32_t i = 0; i < xferred_bytes; i++ )
- {
- if ( (p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff) )
- {
+ if (tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1)) {
+ for (uint32_t i = 0; i < xferred_bytes; i++) {
+ if ((p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff)) {
tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
}
}
}
// invoke receive callback (if there is still data)
- if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
+ if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff)) tud_cdc_rx_cb(itf);
// prepare for OUT transaction
_prep_out_transaction(p_cdc);
@@ -510,19 +479,15 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
// Data sent to host, we continue to fetch from tx fifo to send.
// Note: This will cause incorrect baudrate set in line coding.
// Though maybe the baudrate is not really important !!!
- if ( ep_addr == p_cdc->ep_in )
- {
+ if (ep_addr == p_cdc->ep_in) {
// invoke transmit callback to possibly refill tx fifo
- if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf);
+ if (tud_cdc_tx_complete_cb) tud_cdc_tx_complete_cb(itf);
- if ( 0 == tud_cdc_n_write_flush(itf) )
- {
+ if (0 == tud_cdc_n_write_flush(itf)) {
// If there is no data left, a ZLP should be sent if
// xferred_bytes is multiple of EP Packet size and not zero
- if ( !tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE-1))) )
- {
- if ( usbd_edpt_claim(rhport, p_cdc->ep_in) )
- {
+ if (!tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE - 1)))) {
+ if (usbd_edpt_claim(rhport, p_cdc->ep_in)) {
usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0);
}
}
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index 92131f1591..be0f31844a 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -24,8 +24,8 @@
* This file is part of the TinyUSB stack.
*/
-#ifndef _TUSB_CDC_DEVICE_H_
-#define _TUSB_CDC_DEVICE_H_
+#ifndef TUSB_CDC_DEVICE_H_
+#define TUSB_CDC_DEVICE_H_
#include "cdc.h"
@@ -45,212 +45,174 @@
extern "C" {
#endif
-/** \addtogroup CDC_Serial Serial
- * @{
- * \defgroup CDC_Serial_Device Device
- * @{ */
+//--------------------------------------------------------------------+
+// Driver Configuration
+//--------------------------------------------------------------------+
+
+typedef struct TU_ATTR_PACKED {
+ uint8_t rx_persistent : 1; // keep rx fifo on bus reset or disconnect
+ uint8_t tx_persistent : 1; // keep tx fifo on bus reset or disconnect
+} tud_cdc_configure_fifo_t;
+
+// Configure CDC FIFOs behavior
+bool tud_cdc_configure_fifo(tud_cdc_configure_fifo_t const* cfg);
//--------------------------------------------------------------------+
-// Application API (Multiple Ports)
-// CFG_TUD_CDC > 1
+// Application API (Multiple Ports) i.e. CFG_TUD_CDC > 1
//--------------------------------------------------------------------+
+// Check if interface is ready
+bool tud_cdc_n_ready(uint8_t itf);
+
// Check if terminal is connected to this port
-bool tud_cdc_n_connected (uint8_t itf);
+bool tud_cdc_n_connected(uint8_t itf);
// Get current line state. Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
-uint8_t tud_cdc_n_get_line_state (uint8_t itf);
+uint8_t tud_cdc_n_get_line_state(uint8_t itf);
// Get current line encoding: bit rate, stop bits parity etc ..
-void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding);
+void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t* coding);
// Send UART status notification: DCD, DSR etc ..
-bool tud_cdc_n_send_uart_state (uint8_t itf, cdc_uart_state_t state);
+bool tud_cdc_n_send_uart_state(uint8_t itf, cdc_uart_state_t state);
// Set special character that will trigger tud_cdc_rx_wanted_cb() callback on receiving
-void tud_cdc_n_set_wanted_char (uint8_t itf, char wanted);
+void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted);
// Get the number of bytes available for reading
-uint32_t tud_cdc_n_available (uint8_t itf);
+uint32_t tud_cdc_n_available(uint8_t itf);
// Read received bytes
-uint32_t tud_cdc_n_read (uint8_t itf, void* buffer, uint32_t bufsize);
+uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize);
// Read a byte, return -1 if there is none
-static inline
-int32_t tud_cdc_n_read_char (uint8_t itf);
+TU_ATTR_ALWAYS_INLINE static inline int32_t tud_cdc_n_read_char(uint8_t itf) {
+ uint8_t ch;
+ return tud_cdc_n_read(itf, &ch, 1) ? (int32_t) ch : -1;
+}
// Clear the received FIFO
-void tud_cdc_n_read_flush (uint8_t itf);
+void tud_cdc_n_read_flush(uint8_t itf);
// Get a byte from FIFO without removing it
-bool tud_cdc_n_peek (uint8_t itf, uint8_t* ui8);
+bool tud_cdc_n_peek(uint8_t itf, uint8_t* ui8);
// Write bytes to TX FIFO, data may remain in the FIFO for a while
-uint32_t tud_cdc_n_write (uint8_t itf, void const* buffer, uint32_t bufsize);
+uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize);
// Write a byte
-static inline
-uint32_t tud_cdc_n_write_char (uint8_t itf, char ch);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch) {
+ return tud_cdc_n_write(itf, &ch, 1);
+}
// Write a null-terminated string
-static inline
-uint32_t tud_cdc_n_write_str (uint8_t itf, char const* str);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_n_write_str(uint8_t itf, char const* str) {
+ return tud_cdc_n_write(itf, str, strlen(str));
+}
// Force sending data if possible, return number of forced bytes
-uint32_t tud_cdc_n_write_flush (uint8_t itf);
+uint32_t tud_cdc_n_write_flush(uint8_t itf);
// Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation.
-uint32_t tud_cdc_n_write_available (uint8_t itf);
+uint32_t tud_cdc_n_write_available(uint8_t itf);
// Clear the transmit FIFO
-bool tud_cdc_n_write_clear (uint8_t itf);
+bool tud_cdc_n_write_clear(uint8_t itf);
//--------------------------------------------------------------------+
// Application API (Single Port)
//--------------------------------------------------------------------+
-static inline bool tud_cdc_connected (void);
-static inline uint8_t tud_cdc_get_line_state (void);
-static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding);
-static inline bool tud_cdc_send_uart_state (cdc_uart_state_t state);
-static inline void tud_cdc_set_wanted_char (char wanted);
-
-static inline uint32_t tud_cdc_available (void);
-static inline int32_t tud_cdc_read_char (void);
-static inline uint32_t tud_cdc_read (void* buffer, uint32_t bufsize);
-static inline void tud_cdc_read_flush (void);
-static inline bool tud_cdc_peek (uint8_t* ui8);
-
-static inline uint32_t tud_cdc_write_char (char ch);
-static inline uint32_t tud_cdc_write (void const* buffer, uint32_t bufsize);
-static inline uint32_t tud_cdc_write_str (char const* str);
-static inline uint32_t tud_cdc_write_flush (void);
-static inline uint32_t tud_cdc_write_available (void);
-static inline bool tud_cdc_write_clear (void);
-
-//--------------------------------------------------------------------+
-// Application Callback API (weak is optional)
-//--------------------------------------------------------------------+
-
-// Invoked when received new data
-TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
-
-// Invoked when received `wanted_char`
-TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char);
-
-// Invoked when a TX is complete and therefore space becomes available in TX buffer
-TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf);
-
-// Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE
-TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts);
-
-// Invoked when line coding is change via SET_LINE_CODING
-TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p_line_coding);
-
-// Invoked when received send break
-TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms);
-
-//--------------------------------------------------------------------+
-// Inline Functions
-//--------------------------------------------------------------------+
-static inline int32_t tud_cdc_n_read_char (uint8_t itf)
-{
- uint8_t ch;
- return tud_cdc_n_read(itf, &ch, 1) ? (int32_t) ch : -1;
-}
-static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch)
-{
- return tud_cdc_n_write(itf, &ch, 1);
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_ready(void) {
+ return tud_cdc_n_ready(0);
}
-static inline uint32_t tud_cdc_n_write_str (uint8_t itf, char const* str)
-{
- return tud_cdc_n_write(itf, str, strlen(str));
-}
-
-static inline bool tud_cdc_connected (void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_connected(void) {
return tud_cdc_n_connected(0);
}
-static inline uint8_t tud_cdc_get_line_state (void)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tud_cdc_get_line_state(void) {
return tud_cdc_n_get_line_state(0);
}
-static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding)
-{
+TU_ATTR_ALWAYS_INLINE static inline void tud_cdc_get_line_coding(cdc_line_coding_t* coding) {
tud_cdc_n_get_line_coding(0, coding);
}
-static inline bool tud_cdc_send_uart_state (cdc_uart_state_t state)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_send_uart_state(cdc_uart_state_t state) {
return tud_cdc_n_send_uart_state(0, state);
}
-static inline void tud_cdc_set_wanted_char (char wanted)
-{
+
+TU_ATTR_ALWAYS_INLINE static inline void tud_cdc_set_wanted_char(char wanted) {
tud_cdc_n_set_wanted_char(0, wanted);
}
-static inline uint32_t tud_cdc_available (void)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_available(void) {
return tud_cdc_n_available(0);
}
-static inline int32_t tud_cdc_read_char (void)
-{
+TU_ATTR_ALWAYS_INLINE static inline int32_t tud_cdc_read_char(void) {
return tud_cdc_n_read_char(0);
}
-static inline uint32_t tud_cdc_read (void* buffer, uint32_t bufsize)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_read(void* buffer, uint32_t bufsize) {
return tud_cdc_n_read(0, buffer, bufsize);
}
-static inline void tud_cdc_read_flush (void)
-{
+TU_ATTR_ALWAYS_INLINE static inline void tud_cdc_read_flush(void) {
tud_cdc_n_read_flush(0);
}
-static inline bool tud_cdc_peek (uint8_t* ui8)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_peek(uint8_t* ui8) {
return tud_cdc_n_peek(0, ui8);
}
-static inline uint32_t tud_cdc_write_char (char ch)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write_char(char ch) {
return tud_cdc_n_write_char(0, ch);
}
-static inline uint32_t tud_cdc_write (void const* buffer, uint32_t bufsize)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write(void const* buffer, uint32_t bufsize) {
return tud_cdc_n_write(0, buffer, bufsize);
}
-static inline uint32_t tud_cdc_write_str (char const* str)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write_str(char const* str) {
return tud_cdc_n_write_str(0, str);
}
-static inline uint32_t tud_cdc_write_flush (void)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write_flush(void) {
return tud_cdc_n_write_flush(0);
}
-static inline uint32_t tud_cdc_write_available(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_cdc_write_available(void) {
return tud_cdc_n_write_available(0);
}
-static inline bool tud_cdc_write_clear(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_write_clear(void) {
return tud_cdc_n_write_clear(0);
}
-/** @} */
-/** @} */
+//--------------------------------------------------------------------+
+// Application Callback API (weak is optional)
+//--------------------------------------------------------------------+
+
+// Invoked when received new data
+TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
+
+// Invoked when received `wanted_char`
+TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char);
+
+// Invoked when a TX is complete and therefore space becomes available in TX buffer
+TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf);
+
+// Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE
+TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts);
+
+// Invoked when line coding is change via SET_LINE_CODING
+TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p_line_coding);
+
+// Invoked when received send break
+TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms);
//--------------------------------------------------------------------+
// INTERNAL USBD-CLASS DRIVER API
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 133a10f6ec..8717970e60 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -341,14 +341,14 @@ uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) {
cdch_interface_t* p_cdc = get_itf(idx);
TU_VERIFY(p_cdc);
- return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize);
+ return tu_edpt_stream_write(p_cdc->daddr, &p_cdc->stream.tx, buffer, bufsize);
}
uint32_t tuh_cdc_write_flush(uint8_t idx) {
cdch_interface_t* p_cdc = get_itf(idx);
TU_VERIFY(p_cdc);
- return tu_edpt_stream_write_xfer(&p_cdc->stream.tx);
+ return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx);
}
bool tuh_cdc_write_clear(uint8_t idx) {
@@ -362,7 +362,7 @@ uint32_t tuh_cdc_write_available(uint8_t idx) {
cdch_interface_t* p_cdc = get_itf(idx);
TU_VERIFY(p_cdc);
- return tu_edpt_stream_write_available(&p_cdc->stream.tx);
+ return tu_edpt_stream_write_available(p_cdc->daddr, &p_cdc->stream.tx);
}
//--------------------------------------------------------------------+
@@ -373,7 +373,7 @@ uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) {
cdch_interface_t* p_cdc = get_itf(idx);
TU_VERIFY(p_cdc);
- return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize);
+ return tu_edpt_stream_read(p_cdc->daddr, &p_cdc->stream.rx, buffer, bufsize);
}
uint32_t tuh_cdc_read_available(uint8_t idx) {
@@ -395,7 +395,7 @@ bool tuh_cdc_read_clear (uint8_t idx) {
TU_VERIFY(p_cdc);
bool ret = tu_edpt_stream_clear(&p_cdc->stream.rx);
- tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
+ tu_edpt_stream_read_xfer(p_cdc->daddr, &p_cdc->stream.rx);
return ret;
}
@@ -677,10 +677,10 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
// invoke tx complete callback to possibly refill tx fifo
if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx);
- if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) ) {
+ if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) {
// If there is no data left, a ZLP should be sent if:
// - xferred_bytes is multiple of EP Packet size and not zero
- tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes);
+ tu_edpt_stream_write_zlp_if_needed(daddr, &p_cdc->stream.tx, xferred_bytes);
}
} else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
#if CFG_TUH_CDC_FTDI
@@ -698,7 +698,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx);
// prepare for next transfer if needed
- tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
+ tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
}else if ( ep_addr == p_cdc->ep_notif ) {
// TODO handle notification endpoint
}else {
@@ -719,9 +719,9 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t co
TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep));
if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
- tu_edpt_stream_open(&p_cdc->stream.rx, p_cdc->daddr, desc_ep);
+ tu_edpt_stream_open(&p_cdc->stream.rx, desc_ep);
} else {
- tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep);
+ tu_edpt_stream_open(&p_cdc->stream.tx, desc_ep);
}
desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(desc_ep);
@@ -763,7 +763,7 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i
if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
// Prepare for incoming data
- tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
+ tu_edpt_stream_read_xfer(p_cdc->daddr, &p_cdc->stream.rx);
// notify usbh that driver enumeration is complete
usbh_driver_set_config_complete(p_cdc->daddr, itf_num);
diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index fcaab7a503..c2b5a8a482 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -366,177 +366,224 @@ typedef enum
//--------------------------------------------------------------------+
// HID KEYCODE
//--------------------------------------------------------------------+
-#define HID_KEY_NONE 0x00
-#define HID_KEY_A 0x04
-#define HID_KEY_B 0x05
-#define HID_KEY_C 0x06
-#define HID_KEY_D 0x07
-#define HID_KEY_E 0x08
-#define HID_KEY_F 0x09
-#define HID_KEY_G 0x0A
-#define HID_KEY_H 0x0B
-#define HID_KEY_I 0x0C
-#define HID_KEY_J 0x0D
-#define HID_KEY_K 0x0E
-#define HID_KEY_L 0x0F
-#define HID_KEY_M 0x10
-#define HID_KEY_N 0x11
-#define HID_KEY_O 0x12
-#define HID_KEY_P 0x13
-#define HID_KEY_Q 0x14
-#define HID_KEY_R 0x15
-#define HID_KEY_S 0x16
-#define HID_KEY_T 0x17
-#define HID_KEY_U 0x18
-#define HID_KEY_V 0x19
-#define HID_KEY_W 0x1A
-#define HID_KEY_X 0x1B
-#define HID_KEY_Y 0x1C
-#define HID_KEY_Z 0x1D
-#define HID_KEY_1 0x1E
-#define HID_KEY_2 0x1F
-#define HID_KEY_3 0x20
-#define HID_KEY_4 0x21
-#define HID_KEY_5 0x22
-#define HID_KEY_6 0x23
-#define HID_KEY_7 0x24
-#define HID_KEY_8 0x25
-#define HID_KEY_9 0x26
-#define HID_KEY_0 0x27
-#define HID_KEY_ENTER 0x28
-#define HID_KEY_ESCAPE 0x29
-#define HID_KEY_BACKSPACE 0x2A
-#define HID_KEY_TAB 0x2B
-#define HID_KEY_SPACE 0x2C
-#define HID_KEY_MINUS 0x2D
-#define HID_KEY_EQUAL 0x2E
-#define HID_KEY_BRACKET_LEFT 0x2F
-#define HID_KEY_BRACKET_RIGHT 0x30
-#define HID_KEY_BACKSLASH 0x31
-#define HID_KEY_EUROPE_1 0x32
-#define HID_KEY_SEMICOLON 0x33
-#define HID_KEY_APOSTROPHE 0x34
-#define HID_KEY_GRAVE 0x35
-#define HID_KEY_COMMA 0x36
-#define HID_KEY_PERIOD 0x37
-#define HID_KEY_SLASH 0x38
-#define HID_KEY_CAPS_LOCK 0x39
-#define HID_KEY_F1 0x3A
-#define HID_KEY_F2 0x3B
-#define HID_KEY_F3 0x3C
-#define HID_KEY_F4 0x3D
-#define HID_KEY_F5 0x3E
-#define HID_KEY_F6 0x3F
-#define HID_KEY_F7 0x40
-#define HID_KEY_F8 0x41
-#define HID_KEY_F9 0x42
-#define HID_KEY_F10 0x43
-#define HID_KEY_F11 0x44
-#define HID_KEY_F12 0x45
-#define HID_KEY_PRINT_SCREEN 0x46
-#define HID_KEY_SCROLL_LOCK 0x47
-#define HID_KEY_PAUSE 0x48
-#define HID_KEY_INSERT 0x49
-#define HID_KEY_HOME 0x4A
-#define HID_KEY_PAGE_UP 0x4B
-#define HID_KEY_DELETE 0x4C
-#define HID_KEY_END 0x4D
-#define HID_KEY_PAGE_DOWN 0x4E
-#define HID_KEY_ARROW_RIGHT 0x4F
-#define HID_KEY_ARROW_LEFT 0x50
-#define HID_KEY_ARROW_DOWN 0x51
-#define HID_KEY_ARROW_UP 0x52
-#define HID_KEY_NUM_LOCK 0x53
-#define HID_KEY_KEYPAD_DIVIDE 0x54
-#define HID_KEY_KEYPAD_MULTIPLY 0x55
-#define HID_KEY_KEYPAD_SUBTRACT 0x56
-#define HID_KEY_KEYPAD_ADD 0x57
-#define HID_KEY_KEYPAD_ENTER 0x58
-#define HID_KEY_KEYPAD_1 0x59
-#define HID_KEY_KEYPAD_2 0x5A
-#define HID_KEY_KEYPAD_3 0x5B
-#define HID_KEY_KEYPAD_4 0x5C
-#define HID_KEY_KEYPAD_5 0x5D
-#define HID_KEY_KEYPAD_6 0x5E
-#define HID_KEY_KEYPAD_7 0x5F
-#define HID_KEY_KEYPAD_8 0x60
-#define HID_KEY_KEYPAD_9 0x61
-#define HID_KEY_KEYPAD_0 0x62
-#define HID_KEY_KEYPAD_DECIMAL 0x63
-#define HID_KEY_EUROPE_2 0x64
-#define HID_KEY_APPLICATION 0x65
-#define HID_KEY_POWER 0x66
-#define HID_KEY_KEYPAD_EQUAL 0x67
-#define HID_KEY_F13 0x68
-#define HID_KEY_F14 0x69
-#define HID_KEY_F15 0x6A
-#define HID_KEY_F16 0x6B
-#define HID_KEY_F17 0x6C
-#define HID_KEY_F18 0x6D
-#define HID_KEY_F19 0x6E
-#define HID_KEY_F20 0x6F
-#define HID_KEY_F21 0x70
-#define HID_KEY_F22 0x71
-#define HID_KEY_F23 0x72
-#define HID_KEY_F24 0x73
-#define HID_KEY_EXECUTE 0x74
-#define HID_KEY_HELP 0x75
-#define HID_KEY_MENU 0x76
-#define HID_KEY_SELECT 0x77
-#define HID_KEY_STOP 0x78
-#define HID_KEY_AGAIN 0x79
-#define HID_KEY_UNDO 0x7A
-#define HID_KEY_CUT 0x7B
-#define HID_KEY_COPY 0x7C
-#define HID_KEY_PASTE 0x7D
-#define HID_KEY_FIND 0x7E
-#define HID_KEY_MUTE 0x7F
-#define HID_KEY_VOLUME_UP 0x80
-#define HID_KEY_VOLUME_DOWN 0x81
-#define HID_KEY_LOCKING_CAPS_LOCK 0x82
-#define HID_KEY_LOCKING_NUM_LOCK 0x83
-#define HID_KEY_LOCKING_SCROLL_LOCK 0x84
-#define HID_KEY_KEYPAD_COMMA 0x85
-#define HID_KEY_KEYPAD_EQUAL_SIGN 0x86
-#define HID_KEY_KANJI1 0x87
-#define HID_KEY_KANJI2 0x88
-#define HID_KEY_KANJI3 0x89
-#define HID_KEY_KANJI4 0x8A
-#define HID_KEY_KANJI5 0x8B
-#define HID_KEY_KANJI6 0x8C
-#define HID_KEY_KANJI7 0x8D
-#define HID_KEY_KANJI8 0x8E
-#define HID_KEY_KANJI9 0x8F
-#define HID_KEY_LANG1 0x90
-#define HID_KEY_LANG2 0x91
-#define HID_KEY_LANG3 0x92
-#define HID_KEY_LANG4 0x93
-#define HID_KEY_LANG5 0x94
-#define HID_KEY_LANG6 0x95
-#define HID_KEY_LANG7 0x96
-#define HID_KEY_LANG8 0x97
-#define HID_KEY_LANG9 0x98
-#define HID_KEY_ALTERNATE_ERASE 0x99
-#define HID_KEY_SYSREQ_ATTENTION 0x9A
-#define HID_KEY_CANCEL 0x9B
-#define HID_KEY_CLEAR 0x9C
-#define HID_KEY_PRIOR 0x9D
-#define HID_KEY_RETURN 0x9E
-#define HID_KEY_SEPARATOR 0x9F
-#define HID_KEY_OUT 0xA0
-#define HID_KEY_OPER 0xA1
-#define HID_KEY_CLEAR_AGAIN 0xA2
-#define HID_KEY_CRSEL_PROPS 0xA3
-#define HID_KEY_EXSEL 0xA4
-// RESERVED 0xA5-DF
-#define HID_KEY_CONTROL_LEFT 0xE0
-#define HID_KEY_SHIFT_LEFT 0xE1
-#define HID_KEY_ALT_LEFT 0xE2
-#define HID_KEY_GUI_LEFT 0xE3
-#define HID_KEY_CONTROL_RIGHT 0xE4
-#define HID_KEY_SHIFT_RIGHT 0xE5
-#define HID_KEY_ALT_RIGHT 0xE6
-#define HID_KEY_GUI_RIGHT 0xE7
+#define HID_KEY_NONE 0x00
+#define HID_KEY_A 0x04
+#define HID_KEY_B 0x05
+#define HID_KEY_C 0x06
+#define HID_KEY_D 0x07
+#define HID_KEY_E 0x08
+#define HID_KEY_F 0x09
+#define HID_KEY_G 0x0A
+#define HID_KEY_H 0x0B
+#define HID_KEY_I 0x0C
+#define HID_KEY_J 0x0D
+#define HID_KEY_K 0x0E
+#define HID_KEY_L 0x0F
+#define HID_KEY_M 0x10
+#define HID_KEY_N 0x11
+#define HID_KEY_O 0x12
+#define HID_KEY_P 0x13
+#define HID_KEY_Q 0x14
+#define HID_KEY_R 0x15
+#define HID_KEY_S 0x16
+#define HID_KEY_T 0x17
+#define HID_KEY_U 0x18
+#define HID_KEY_V 0x19
+#define HID_KEY_W 0x1A
+#define HID_KEY_X 0x1B
+#define HID_KEY_Y 0x1C
+#define HID_KEY_Z 0x1D
+#define HID_KEY_1 0x1E
+#define HID_KEY_2 0x1F
+#define HID_KEY_3 0x20
+#define HID_KEY_4 0x21
+#define HID_KEY_5 0x22
+#define HID_KEY_6 0x23
+#define HID_KEY_7 0x24
+#define HID_KEY_8 0x25
+#define HID_KEY_9 0x26
+#define HID_KEY_0 0x27
+#define HID_KEY_ENTER 0x28
+#define HID_KEY_ESCAPE 0x29
+#define HID_KEY_BACKSPACE 0x2A
+#define HID_KEY_TAB 0x2B
+#define HID_KEY_SPACE 0x2C
+#define HID_KEY_MINUS 0x2D
+#define HID_KEY_EQUAL 0x2E
+#define HID_KEY_BRACKET_LEFT 0x2F
+#define HID_KEY_BRACKET_RIGHT 0x30
+#define HID_KEY_BACKSLASH 0x31
+#define HID_KEY_EUROPE_1 0x32
+#define HID_KEY_SEMICOLON 0x33
+#define HID_KEY_APOSTROPHE 0x34
+#define HID_KEY_GRAVE 0x35
+#define HID_KEY_COMMA 0x36
+#define HID_KEY_PERIOD 0x37
+#define HID_KEY_SLASH 0x38
+#define HID_KEY_CAPS_LOCK 0x39
+#define HID_KEY_F1 0x3A
+#define HID_KEY_F2 0x3B
+#define HID_KEY_F3 0x3C
+#define HID_KEY_F4 0x3D
+#define HID_KEY_F5 0x3E
+#define HID_KEY_F6 0x3F
+#define HID_KEY_F7 0x40
+#define HID_KEY_F8 0x41
+#define HID_KEY_F9 0x42
+#define HID_KEY_F10 0x43
+#define HID_KEY_F11 0x44
+#define HID_KEY_F12 0x45
+#define HID_KEY_PRINT_SCREEN 0x46
+#define HID_KEY_SCROLL_LOCK 0x47
+#define HID_KEY_PAUSE 0x48
+#define HID_KEY_INSERT 0x49
+#define HID_KEY_HOME 0x4A
+#define HID_KEY_PAGE_UP 0x4B
+#define HID_KEY_DELETE 0x4C
+#define HID_KEY_END 0x4D
+#define HID_KEY_PAGE_DOWN 0x4E
+#define HID_KEY_ARROW_RIGHT 0x4F
+#define HID_KEY_ARROW_LEFT 0x50
+#define HID_KEY_ARROW_DOWN 0x51
+#define HID_KEY_ARROW_UP 0x52
+#define HID_KEY_NUM_LOCK 0x53
+#define HID_KEY_KEYPAD_DIVIDE 0x54
+#define HID_KEY_KEYPAD_MULTIPLY 0x55
+#define HID_KEY_KEYPAD_SUBTRACT 0x56
+#define HID_KEY_KEYPAD_ADD 0x57
+#define HID_KEY_KEYPAD_ENTER 0x58
+#define HID_KEY_KEYPAD_1 0x59
+#define HID_KEY_KEYPAD_2 0x5A
+#define HID_KEY_KEYPAD_3 0x5B
+#define HID_KEY_KEYPAD_4 0x5C
+#define HID_KEY_KEYPAD_5 0x5D
+#define HID_KEY_KEYPAD_6 0x5E
+#define HID_KEY_KEYPAD_7 0x5F
+#define HID_KEY_KEYPAD_8 0x60
+#define HID_KEY_KEYPAD_9 0x61
+#define HID_KEY_KEYPAD_0 0x62
+#define HID_KEY_KEYPAD_DECIMAL 0x63
+#define HID_KEY_EUROPE_2 0x64
+#define HID_KEY_APPLICATION 0x65
+#define HID_KEY_POWER 0x66
+#define HID_KEY_KEYPAD_EQUAL 0x67
+#define HID_KEY_F13 0x68
+#define HID_KEY_F14 0x69
+#define HID_KEY_F15 0x6A
+#define HID_KEY_F16 0x6B
+#define HID_KEY_F17 0x6C
+#define HID_KEY_F18 0x6D
+#define HID_KEY_F19 0x6E
+#define HID_KEY_F20 0x6F
+#define HID_KEY_F21 0x70
+#define HID_KEY_F22 0x71
+#define HID_KEY_F23 0x72
+#define HID_KEY_F24 0x73
+#define HID_KEY_EXECUTE 0x74
+#define HID_KEY_HELP 0x75
+#define HID_KEY_MENU 0x76
+#define HID_KEY_SELECT 0x77
+#define HID_KEY_STOP 0x78
+#define HID_KEY_AGAIN 0x79
+#define HID_KEY_UNDO 0x7A
+#define HID_KEY_CUT 0x7B
+#define HID_KEY_COPY 0x7C
+#define HID_KEY_PASTE 0x7D
+#define HID_KEY_FIND 0x7E
+#define HID_KEY_MUTE 0x7F
+#define HID_KEY_VOLUME_UP 0x80
+#define HID_KEY_VOLUME_DOWN 0x81
+#define HID_KEY_LOCKING_CAPS_LOCK 0x82
+#define HID_KEY_LOCKING_NUM_LOCK 0x83
+#define HID_KEY_LOCKING_SCROLL_LOCK 0x84
+#define HID_KEY_KEYPAD_COMMA 0x85
+#define HID_KEY_KEYPAD_EQUAL_SIGN 0x86
+#define HID_KEY_KANJI1 0x87
+#define HID_KEY_KANJI2 0x88
+#define HID_KEY_KANJI3 0x89
+#define HID_KEY_KANJI4 0x8A
+#define HID_KEY_KANJI5 0x8B
+#define HID_KEY_KANJI6 0x8C
+#define HID_KEY_KANJI7 0x8D
+#define HID_KEY_KANJI8 0x8E
+#define HID_KEY_KANJI9 0x8F
+#define HID_KEY_LANG1 0x90
+#define HID_KEY_LANG2 0x91
+#define HID_KEY_LANG3 0x92
+#define HID_KEY_LANG4 0x93
+#define HID_KEY_LANG5 0x94
+#define HID_KEY_LANG6 0x95
+#define HID_KEY_LANG7 0x96
+#define HID_KEY_LANG8 0x97
+#define HID_KEY_LANG9 0x98
+#define HID_KEY_ALTERNATE_ERASE 0x99
+#define HID_KEY_SYSREQ_ATTENTION 0x9A
+#define HID_KEY_CANCEL 0x9B
+#define HID_KEY_CLEAR 0x9C
+#define HID_KEY_PRIOR 0x9D
+#define HID_KEY_RETURN 0x9E
+#define HID_KEY_SEPARATOR 0x9F
+#define HID_KEY_OUT 0xA0
+#define HID_KEY_OPER 0xA1
+#define HID_KEY_CLEAR_AGAIN 0xA2
+#define HID_KEY_CRSEL_PROPS 0xA3
+#define HID_KEY_EXSEL 0xA4
+// RESERVED 0xA5-AF
+#define HID_KEY_KEYPAD_00 0xB0
+#define HID_KEY_KEYPAD_000 0xB1
+#define HID_KEY_THOUSANDS_SEPARATOR 0xB2
+#define HID_KEY_DECIMAL_SEPARATOR 0xB3
+#define HID_KEY_CURRENCY_UNIT 0xB4
+#define HID_KEY_CURRENCY_SUBUNIT 0xB5
+#define HID_KEY_KEYPAD_LEFT_PARENTHESIS 0xB6
+#define HID_KEY_KEYPAD_RIGHT_PARENTHESIS 0xB7
+#define HID_KEY_KEYPAD_LEFT_BRACE 0xB8
+#define HID_KEY_KEYPAD_RIGHT_BRACE 0xB9
+#define HID_KEY_KEYPAD_TAB 0xBA
+#define HID_KEY_KEYPAD_BACKSPACE 0xBB
+#define HID_KEY_KEYPAD_A 0xBC
+#define HID_KEY_KEYPAD_B 0xBD
+#define HID_KEY_KEYPAD_C 0xBE
+#define HID_KEY_KEYPAD_D 0xBF
+#define HID_KEY_KEYPAD_E 0xC0
+#define HID_KEY_KEYPAD_F 0xC1
+#define HID_KEY_KEYPAD_XOR 0xC2
+#define HID_KEY_KEYPAD_CARET 0xC3
+#define HID_KEY_KEYPAD_PERCENT 0xC4
+#define HID_KEY_KEYPAD_LESS_THAN 0xC5
+#define HID_KEY_KEYPAD_GREATER_THAN 0xC6
+#define HID_KEY_KEYPAD_AMPERSAND 0xC7
+#define HID_KEY_KEYPAD_DOUBLE_AMPERSAND 0xC8
+#define HID_KEY_KEYPAD_VERTICAL_BAR 0xC9
+#define HID_KEY_KEYPAD_DOUBLE_VERTICAL_BAR 0xCA
+#define HID_KEY_KEYPAD_COLON 0xCB
+#define HID_KEY_KEYPAD_HASH 0xCC
+#define HID_KEY_KEYPAD_SPACE 0xCD
+#define HID_KEY_KEYPAD_AT 0xCE
+#define HID_KEY_KEYPAD_EXCLAMATION 0xCF
+#define HID_KEY_KEYPAD_MEMORY_STORE 0xD0
+#define HID_KEY_KEYPAD_MEMORY_RECALL 0xD1
+#define HID_KEY_KEYPAD_MEMORY_CLEAR 0xD2
+#define HID_KEY_KEYPAD_MEMORY_ADD 0xD3
+#define HID_KEY_KEYPAD_MEMORY_SUBTRACT 0xD4
+#define HID_KEY_KEYPAD_MEMORY_MULTIPLY 0xD5
+#define HID_KEY_KEYPAD_MEMORY_DIVIDE 0xD6
+#define HID_KEY_KEYPAD_PLUS_MINUS 0xD7
+#define HID_KEY_KEYPAD_CLEAR 0xD8
+#define HID_KEY_KEYPAD_CLEAR_ENTRY 0xD9
+#define HID_KEY_KEYPAD_BINARY 0xDA
+#define HID_KEY_KEYPAD_OCTAL 0xDB
+#define HID_KEY_KEYPAD_DECIMAL_2 0xDC
+#define HID_KEY_KEYPAD_HEXADECIMAL 0xDD
+// RESERVED 0xDE-DF
+#define HID_KEY_CONTROL_LEFT 0xE0
+#define HID_KEY_SHIFT_LEFT 0xE1
+#define HID_KEY_ALT_LEFT 0xE2
+#define HID_KEY_GUI_LEFT 0xE3
+#define HID_KEY_CONTROL_RIGHT 0xE4
+#define HID_KEY_SHIFT_RIGHT 0xE5
+#define HID_KEY_ALT_RIGHT 0xE6
+#define HID_KEY_GUI_RIGHT 0xE7
//--------------------------------------------------------------------+
@@ -697,32 +744,33 @@ enum {
/// HID Usage Table - Table 1: Usage Page Summary
enum {
- HID_USAGE_PAGE_DESKTOP = 0x01,
- HID_USAGE_PAGE_SIMULATE = 0x02,
- HID_USAGE_PAGE_VIRTUAL_REALITY = 0x03,
- HID_USAGE_PAGE_SPORT = 0x04,
- HID_USAGE_PAGE_GAME = 0x05,
- HID_USAGE_PAGE_GENERIC_DEVICE = 0x06,
- HID_USAGE_PAGE_KEYBOARD = 0x07,
- HID_USAGE_PAGE_LED = 0x08,
- HID_USAGE_PAGE_BUTTON = 0x09,
- HID_USAGE_PAGE_ORDINAL = 0x0a,
- HID_USAGE_PAGE_TELEPHONY = 0x0b,
- HID_USAGE_PAGE_CONSUMER = 0x0c,
- HID_USAGE_PAGE_DIGITIZER = 0x0d,
- HID_USAGE_PAGE_PID = 0x0f,
- HID_USAGE_PAGE_UNICODE = 0x10,
- HID_USAGE_PAGE_ALPHA_DISPLAY = 0x14,
- HID_USAGE_PAGE_MEDICAL = 0x40,
- HID_USAGE_PAGE_MONITOR = 0x80, //0x80 - 0x83
- HID_USAGE_PAGE_POWER = 0x84, // 0x084 - 0x87
- HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c,
- HID_USAGE_PAGE_SCALE = 0x8d,
- HID_USAGE_PAGE_MSR = 0x8e,
- HID_USAGE_PAGE_CAMERA = 0x90,
- HID_USAGE_PAGE_ARCADE = 0x91,
- HID_USAGE_PAGE_FIDO = 0xF1D0, // FIDO alliance HID usage page
- HID_USAGE_PAGE_VENDOR = 0xFF00 // 0xFF00 - 0xFFFF
+ HID_USAGE_PAGE_DESKTOP = 0x01,
+ HID_USAGE_PAGE_SIMULATE = 0x02,
+ HID_USAGE_PAGE_VIRTUAL_REALITY = 0x03,
+ HID_USAGE_PAGE_SPORT = 0x04,
+ HID_USAGE_PAGE_GAME = 0x05,
+ HID_USAGE_PAGE_GENERIC_DEVICE = 0x06,
+ HID_USAGE_PAGE_KEYBOARD = 0x07,
+ HID_USAGE_PAGE_LED = 0x08,
+ HID_USAGE_PAGE_BUTTON = 0x09,
+ HID_USAGE_PAGE_ORDINAL = 0x0a,
+ HID_USAGE_PAGE_TELEPHONY = 0x0b,
+ HID_USAGE_PAGE_CONSUMER = 0x0c,
+ HID_USAGE_PAGE_DIGITIZER = 0x0d,
+ HID_USAGE_PAGE_PID = 0x0f,
+ HID_USAGE_PAGE_UNICODE = 0x10,
+ HID_USAGE_PAGE_ALPHA_DISPLAY = 0x14,
+ HID_USAGE_PAGE_MEDICAL = 0x40,
+ HID_USAGE_PAGE_LIGHTING_AND_ILLUMINATION = 0x59,
+ HID_USAGE_PAGE_MONITOR = 0x80, // 0x80 - 0x83
+ HID_USAGE_PAGE_POWER = 0x84, // 0x084 - 0x87
+ HID_USAGE_PAGE_BARCODE_SCANNER = 0x8c,
+ HID_USAGE_PAGE_SCALE = 0x8d,
+ HID_USAGE_PAGE_MSR = 0x8e,
+ HID_USAGE_PAGE_CAMERA = 0x90,
+ HID_USAGE_PAGE_ARCADE = 0x91,
+ HID_USAGE_PAGE_FIDO = 0xF1D0, // FIDO alliance HID usage page
+ HID_USAGE_PAGE_VENDOR = 0xFF00 // 0xFF00 - 0xFFFF
};
/// HID Usage Table - Table 6: Generic Desktop Page
@@ -801,8 +849,7 @@ enum {
/// HID Usage Table: Consumer Page (0x0C)
/// Only contains controls that supported by Windows (whole list is too long)
-enum
-{
+enum {
// Generic Control
HID_USAGE_CONSUMER_CONTROL = 0x0001,
@@ -858,9 +905,45 @@ enum
HID_USAGE_CONSUMER_AC_PAN = 0x0238,
};
+/// HID Usage Table - Lighting And Illumination Page (0x59)
+enum {
+ HID_USAGE_LIGHTING_LAMP_ARRAY = 0x01,
+ HID_USAGE_LIGHTING_LAMP_ARRAY_ATTRIBUTES_REPORT = 0x02,
+ HID_USAGE_LIGHTING_LAMP_COUNT = 0x03,
+ HID_USAGE_LIGHTING_BOUNDING_BOX_WIDTH_IN_MICROMETERS = 0x04,
+ HID_USAGE_LIGHTING_BOUNDING_BOX_HEIGHT_IN_MICROMETERS = 0x05,
+ HID_USAGE_LIGHTING_BOUNDING_BOX_DEPTH_IN_MICROMETERS = 0x06,
+ HID_USAGE_LIGHTING_LAMP_ARRAY_KIND = 0x07,
+ HID_USAGE_LIGHTING_MIN_UPDATE_INTERVAL_IN_MICROSECONDS = 0x08,
+ HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_REQUEST_REPORT = 0x20,
+ HID_USAGE_LIGHTING_LAMP_ID = 0x21,
+ HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_RESPONSE_REPORT = 0x22,
+ HID_USAGE_LIGHTING_POSITION_X_IN_MICROMETERS = 0x23,
+ HID_USAGE_LIGHTING_POSITION_Y_IN_MICROMETERS = 0x24,
+ HID_USAGE_LIGHTING_POSITION_Z_IN_MICROMETERS = 0x25,
+ HID_USAGE_LIGHTING_LAMP_PURPOSES = 0x26,
+ HID_USAGE_LIGHTING_UPDATE_LATENCY_IN_MICROSECONDS = 0x27,
+ HID_USAGE_LIGHTING_RED_LEVEL_COUNT = 0x28,
+ HID_USAGE_LIGHTING_GREEN_LEVEL_COUNT = 0x29,
+ HID_USAGE_LIGHTING_BLUE_LEVEL_COUNT = 0x2A,
+ HID_USAGE_LIGHTING_INTENSITY_LEVEL_COUNT = 0x2B,
+ HID_USAGE_LIGHTING_IS_PROGRAMMABLE = 0x2C,
+ HID_USAGE_LIGHTING_INPUT_BINDING = 0x2D,
+ HID_USAGE_LIGHTING_LAMP_MULTI_UPDATE_REPORT = 0x50,
+ HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL = 0x51,
+ HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL = 0x52,
+ HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL = 0x53,
+ HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL = 0x54,
+ HID_USAGE_LIGHTING_LAMP_UPDATE_FLAGS = 0x55,
+ HID_USAGE_LIGHTING_LAMP_RANGE_UPDATE_REPORT = 0x60,
+ HID_USAGE_LIGHTING_LAMP_ID_START = 0x61,
+ HID_USAGE_LIGHTING_LAMP_ID_END = 0x62,
+ HID_USAGE_LIGHTING_LAMP_ARRAY_CONTROL_REPORT = 0x70,
+ HID_USAGE_LIGHTING_AUTONOMOUS_MODE = 0x71,
+};
+
/// HID Usage Table: FIDO Alliance Page (0xF1D0)
-enum
-{
+enum {
HID_USAGE_FIDO_U2FHID = 0x01, // U2FHID usage for top-level collection
HID_USAGE_FIDO_DATA_IN = 0x20, // Raw IN data report
HID_USAGE_FIDO_DATA_OUT = 0x21 // Raw OUT data report
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 5cc5a2488a..ef6c7f3afb 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -39,92 +39,109 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
uint8_t itf_num;
uint8_t ep_in;
- uint8_t ep_out; // optional Out endpoint
- uint8_t itf_protocol; // Boot mouse or keyboard
+ uint8_t ep_out; // optional Out endpoint
+ uint8_t itf_protocol; // Boot mouse or keyboard
+ uint16_t report_desc_len;
uint8_t protocol_mode; // Boot (0) or Report protocol (1)
uint8_t idle_rate; // up to application to handle idle rate
- uint16_t report_desc_len;
-
- CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE];
- CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE];
// TODO save hid descriptor since host can specifically request this after enumeration
// Note: HID descriptor may be not available from application after enumeration
- tusb_hid_descriptor_hid_t const * hid_descriptor;
+ tusb_hid_descriptor_hid_t const *hid_descriptor;
+
+ uint8_t ctrl_buf[CFG_TUD_HID_EP_BUFSIZE];
+ CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE];
+ CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE];
} hidd_interface_t;
CFG_TUD_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID];
/*------------- Helpers -------------*/
-static inline uint8_t get_index_by_itfnum(uint8_t itf_num)
-{
- for (uint8_t i=0; i < CFG_TUD_HID; i++ )
- {
- if ( itf_num == _hidd_itf[i].itf_num ) return i;
- }
-
- return 0xFF;
+TU_ATTR_ALWAYS_INLINE static inline uint8_t get_index_by_itfnum(uint8_t itf_num) {
+ for (uint8_t i = 0; i < CFG_TUD_HID; i++) {
+ if (itf_num == _hidd_itf[i].itf_num) {
+ return i;
+ }
+ }
+ return 0xFF;
+}
+
+//--------------------------------------------------------------------+
+// Weak stubs: invoked if no strong implementation is available
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol) {
+ (void) instance;
+ (void) protocol;
+}
+
+TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate) {
+ (void) instance;
+ (void) idle_rate;
+ return true;
+}
+
+TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len) {
+ (void) instance;
+ (void) report;
+ (void) len;
+}
+
+// Invoked when a transfer wasn't successful
+TU_ATTR_WEAK void tud_hid_report_failed_cb(uint8_t instance, hid_report_type_t report_type, uint8_t const* report, uint16_t xferred_bytes) {
+ (void) instance;
+ (void) report_type;
+ (void) report;
+ (void) xferred_bytes;
}
//--------------------------------------------------------------------+
// APPLICATION API
//--------------------------------------------------------------------+
-bool tud_hid_n_ready(uint8_t instance)
-{
+bool tud_hid_n_ready(uint8_t instance) {
uint8_t const rhport = 0;
uint8_t const ep_in = _hidd_itf[instance].ep_in;
return tud_ready() && (ep_in != 0) && !usbd_edpt_busy(rhport, ep_in);
}
-bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, uint16_t len)
-{
+bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const *report, uint16_t len) {
uint8_t const rhport = 0;
- hidd_interface_t * p_hid = &_hidd_itf[instance];
+ hidd_interface_t *p_hid = &_hidd_itf[instance];
// claim endpoint
- TU_VERIFY( usbd_edpt_claim(rhport, p_hid->ep_in) );
+ TU_VERIFY(usbd_edpt_claim(rhport, p_hid->ep_in));
// prepare data
- if (report_id)
- {
+ if (report_id) {
p_hid->epin_buf[0] = report_id;
- TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf+1, CFG_TUD_HID_EP_BUFSIZE-1, report, len));
+ TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf + 1, CFG_TUD_HID_EP_BUFSIZE - 1, report, len));
len++;
- }else
- {
+ } else {
TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf, CFG_TUD_HID_EP_BUFSIZE, report, len));
}
return usbd_edpt_xfer(rhport, p_hid->ep_in, p_hid->epin_buf, len);
}
-uint8_t tud_hid_n_interface_protocol(uint8_t instance)
-{
+uint8_t tud_hid_n_interface_protocol(uint8_t instance) {
return _hidd_itf[instance].itf_protocol;
}
-uint8_t tud_hid_n_get_protocol(uint8_t instance)
-{
+uint8_t tud_hid_n_get_protocol(uint8_t instance) {
return _hidd_itf[instance].protocol_mode;
}
-bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, uint8_t keycode[6])
-{
+bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, const uint8_t keycode[6]) {
hid_keyboard_report_t report;
-
report.modifier = modifier;
report.reserved = 0;
- if ( keycode )
- {
+ if (keycode) {
memcpy(report.keycode, keycode, sizeof(report.keycode));
- }else
- {
+ } else {
tu_memclr(report.keycode, 6);
}
@@ -132,45 +149,41 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi
}
bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id,
- uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal)
-{
- hid_mouse_report_t report =
- {
+ uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal) {
+ hid_mouse_report_t report = {
.buttons = buttons,
- .x = x,
- .y = y,
- .wheel = vertical,
- .pan = horizontal
+ .x = x,
+ .y = y,
+ .wheel = vertical,
+ .pan = horizontal
};
return tud_hid_n_report(instance, report_id, &report, sizeof(report));
}
-bool tud_hid_n_abs_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal)
-{
- hid_abs_mouse_report_t report =
- {
+bool tud_hid_n_abs_mouse_report(uint8_t instance, uint8_t report_id,
+ uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal) {
+ hid_abs_mouse_report_t report = {
.buttons = buttons,
- .x = x,
- .y = y,
- .wheel = vertical,
- .pan = horizontal
+ .x = x,
+ .y = y,
+ .wheel = vertical,
+ .pan = horizontal
};
return tud_hid_n_report(instance, report_id, &report, sizeof(report));
}
bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) {
- hid_gamepad_report_t report =
- {
- .x = x,
- .y = y,
- .z = z,
- .rz = rz,
- .rx = rx,
- .ry = ry,
- .hat = hat,
- .buttons = buttons,
+ hid_gamepad_report_t report = {
+ .x = x,
+ .y = y,
+ .z = z,
+ .rz = rz,
+ .rx = rx,
+ .ry = ry,
+ .hat = hat,
+ .buttons = buttons,
};
return tud_hid_n_report(instance, report_id, &report, sizeof(report));
@@ -187,59 +200,54 @@ bool hidd_deinit(void) {
return true;
}
-void hidd_reset(uint8_t rhport)
-{
- (void) rhport;
+void hidd_reset(uint8_t rhport) {
+ (void)rhport;
tu_memclr(_hidd_itf, sizeof(_hidd_itf));
}
-uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
- {
+uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const *desc_itf, uint16_t max_len) {
TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass, 0);
// len = interface + hid + n*endpoints
- uint16_t const drv_len =
- (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
+ uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
TU_ASSERT(max_len >= drv_len, 0);
// Find available interface
- hidd_interface_t * p_hid = NULL;
+ hidd_interface_t *p_hid = NULL;
uint8_t hid_id;
- for(hid_id=0; hid_idhid_descriptor = (tusb_hid_descriptor_hid_t const *) p_desc;
+ p_hid->hid_descriptor = (tusb_hid_descriptor_hid_t const *)p_desc;
//------------- Endpoint Descriptor -------------//
p_desc = tu_desc_next(p_desc);
TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_INTERRUPT, &p_hid->ep_out, &p_hid->ep_in), 0);
- if ( desc_itf->bInterfaceSubClass == HID_SUBCLASS_BOOT ) p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
+ if (desc_itf->bInterfaceSubClass == HID_SUBCLASS_BOOT) {
+ p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
+ }
p_hid->protocol_mode = HID_PROTOCOL_REPORT; // Per Specs: default is report mode
- p_hid->itf_num = desc_itf->bInterfaceNumber;
+ p_hid->itf_num = desc_itf->bInterfaceNumber;
// Use offsetof to avoid pointer to the odd/misaligned address
- p_hid->report_desc_len = tu_unaligned_read16((uint8_t const*) p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength));
+ p_hid->report_desc_len = tu_unaligned_read16((uint8_t const *)p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength));
// Prepare for output endpoint
- if (p_hid->ep_out)
- {
- if ( !usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)) )
- {
+ if (p_hid->ep_out) {
+ if (!usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf))) {
TU_LOG_FAILED();
TU_BREAKPOINT();
}
@@ -251,177 +259,146 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1
// Invoked when a control transfer occurred on an interface of this class
// Driver response accordingly to the request and the transfer stage (setup/data/ack)
// return false to stall control endpoint (e.g unsupported request)
-bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
+bool hidd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
- uint8_t const hid_itf = get_index_by_itfnum((uint8_t) request->wIndex);
+ uint8_t const hid_itf = get_index_by_itfnum((uint8_t)request->wIndex);
TU_VERIFY(hid_itf < CFG_TUD_HID);
- hidd_interface_t* p_hid = &_hidd_itf[hid_itf];
+ hidd_interface_t *p_hid = &_hidd_itf[hid_itf];
- if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD)
- {
+ if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) {
//------------- STD Request -------------//
- if ( stage == CONTROL_STAGE_SETUP )
- {
- uint8_t const desc_type = tu_u16_high(request->wValue);
- //uint8_t const desc_index = tu_u16_low (request->wValue);
+ if (stage == CONTROL_STAGE_SETUP) {
+ uint8_t const desc_type = tu_u16_high(request->wValue);
+ // uint8_t const desc_index = tu_u16_low (request->wValue);
- if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID)
- {
+ if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID) {
TU_VERIFY(p_hid->hid_descriptor);
- TU_VERIFY(tud_control_xfer(rhport, request, (void*)(uintptr_t) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
- }
- else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT)
- {
- uint8_t const * desc_report = tud_hid_descriptor_report_cb(hid_itf);
- tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_report, p_hid->report_desc_len);
- }
- else
- {
+ TU_VERIFY(tud_control_xfer(rhport, request, (void *)(uintptr_t)p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
+ } else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT) {
+ uint8_t const *desc_report = tud_hid_descriptor_report_cb(hid_itf);
+ tud_control_xfer(rhport, request, (void *)(uintptr_t)desc_report, p_hid->report_desc_len);
+ } else {
return false; // stall unsupported request
}
}
- }
- else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS)
- {
+ } else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS) {
//------------- Class Specific Request -------------//
- switch( request->bRequest )
- {
+ switch (request->bRequest) {
case HID_REQ_CONTROL_GET_REPORT:
- if ( stage == CONTROL_STAGE_SETUP )
- {
+ if (stage == CONTROL_STAGE_SETUP) {
uint8_t const report_type = tu_u16_high(request->wValue);
- uint8_t const report_id = tu_u16_low(request->wValue);
+ uint8_t const report_id = tu_u16_low(request->wValue);
- uint8_t* report_buf = p_hid->epin_buf;
+ uint8_t* report_buf = p_hid->ctrl_buf;
uint16_t req_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
-
uint16_t xferlen = 0;
// If host request a specific Report ID, add ID to as 1 byte of response
- if ( (report_id != HID_REPORT_TYPE_INVALID) && (req_len > 1) )
- {
+ if ((report_id != HID_REPORT_TYPE_INVALID) && (req_len > 1)) {
*report_buf++ = report_id;
req_len--;
-
xferlen++;
}
xferlen += tud_hid_get_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, req_len);
- TU_ASSERT( xferlen > 0 );
+ TU_ASSERT(xferlen > 0);
- tud_control_xfer(rhport, request, p_hid->epin_buf, xferlen);
+ tud_control_xfer(rhport, request, p_hid->ctrl_buf, xferlen);
}
- break;
+ break;
- case HID_REQ_CONTROL_SET_REPORT:
- if ( stage == CONTROL_STAGE_SETUP )
- {
- TU_VERIFY(request->wLength <= sizeof(p_hid->epout_buf));
- tud_control_xfer(rhport, request, p_hid->epout_buf, request->wLength);
- }
- else if ( stage == CONTROL_STAGE_ACK )
- {
+ case HID_REQ_CONTROL_SET_REPORT:
+ if (stage == CONTROL_STAGE_SETUP) {
+ TU_VERIFY(request->wLength <= sizeof(p_hid->ctrl_buf));
+ tud_control_xfer(rhport, request, p_hid->ctrl_buf, request->wLength);
+ } else if (stage == CONTROL_STAGE_ACK) {
uint8_t const report_type = tu_u16_high(request->wValue);
- uint8_t const report_id = tu_u16_low(request->wValue);
+ uint8_t const report_id = tu_u16_low(request->wValue);
- uint8_t const* report_buf = p_hid->epout_buf;
+ uint8_t const* report_buf = p_hid->ctrl_buf;
uint16_t report_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
// If host request a specific Report ID, extract report ID in buffer before invoking callback
- if ( (report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0]) )
- {
+ if ((report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0])) {
report_buf++;
report_len--;
}
tud_hid_set_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, report_len);
}
- break;
+ break;
case HID_REQ_CONTROL_SET_IDLE:
- if ( stage == CONTROL_STAGE_SETUP )
- {
+ if (stage == CONTROL_STAGE_SETUP) {
p_hid->idle_rate = tu_u16_high(request->wValue);
- if ( tud_hid_set_idle_cb )
- {
- // stall request if callback return false
- TU_VERIFY( tud_hid_set_idle_cb( hid_itf, p_hid->idle_rate) );
- }
-
+ TU_VERIFY(tud_hid_set_idle_cb(hid_itf, p_hid->idle_rate)); // stall if false
tud_control_status(rhport, request);
}
- break;
+ break;
case HID_REQ_CONTROL_GET_IDLE:
- if ( stage == CONTROL_STAGE_SETUP )
- {
+ if (stage == CONTROL_STAGE_SETUP) {
// TODO idle rate of report
tud_control_xfer(rhport, request, &p_hid->idle_rate, 1);
}
- break;
+ break;
case HID_REQ_CONTROL_GET_PROTOCOL:
- if ( stage == CONTROL_STAGE_SETUP )
- {
+ if (stage == CONTROL_STAGE_SETUP) {
tud_control_xfer(rhport, request, &p_hid->protocol_mode, 1);
}
- break;
+ break;
case HID_REQ_CONTROL_SET_PROTOCOL:
- if ( stage == CONTROL_STAGE_SETUP )
- {
+ if (stage == CONTROL_STAGE_SETUP) {
tud_control_status(rhport, request);
- }
- else if ( stage == CONTROL_STAGE_ACK )
- {
+ } else if (stage == CONTROL_STAGE_ACK) {
p_hid->protocol_mode = (uint8_t) request->wValue;
- if (tud_hid_set_protocol_cb)
- {
- tud_hid_set_protocol_cb(hid_itf, p_hid->protocol_mode);
- }
+ tud_hid_set_protocol_cb(hid_itf, p_hid->protocol_mode);
}
- break;
+ break;
- default: return false; // stall unsupported request
+ default:
+ return false; // stall unsupported request
}
- }else
- {
+ } else {
return false; // stall unsupported request
}
return true;
}
-bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
- (void) result;
-
+bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
uint8_t instance = 0;
- hidd_interface_t * p_hid = _hidd_itf;
+ hidd_interface_t *p_hid = _hidd_itf;
// Identify which interface to use
- for (instance = 0; instance < CFG_TUD_HID; instance++)
- {
+ for (instance = 0; instance < CFG_TUD_HID; instance++) {
p_hid = &_hidd_itf[instance];
- if ( (ep_addr == p_hid->ep_out) || (ep_addr == p_hid->ep_in) ) break;
+ if ((ep_addr == p_hid->ep_out) || (ep_addr == p_hid->ep_in)) {
+ break;
+ }
}
TU_ASSERT(instance < CFG_TUD_HID);
- // Sent report successfully
- if (ep_addr == p_hid->ep_in)
- {
- if (tud_hid_report_complete_cb)
- {
+ if (ep_addr == p_hid->ep_in) {
+ // Input report
+ if (XFER_RESULT_SUCCESS == result) {
tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint16_t) xferred_bytes);
+ } else {
+ tud_hid_report_failed_cb(instance, HID_REPORT_TYPE_INPUT, p_hid->epin_buf, (uint16_t) xferred_bytes);
}
- }
- // Received report
- else if (ep_addr == p_hid->ep_out)
- {
- tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_INVALID, p_hid->epout_buf, (uint16_t) xferred_bytes);
+ } else {
+ // Output report
+ if (XFER_RESULT_SUCCESS == result) {
+ tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_OUTPUT, p_hid->epout_buf, (uint16_t)xferred_bytes);
+ } else {
+ tud_hid_report_failed_cb(instance, HID_REPORT_TYPE_OUTPUT, p_hid->epout_buf, (uint16_t) xferred_bytes);
+ }
+
+ // prepare for new transfer
TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)));
}
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 040cad162f..ab2e273736 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -24,8 +24,8 @@
* This file is part of the TinyUSB stack.
*/
-#ifndef _TUSB_HID_DEVICE_H_
-#define _TUSB_HID_DEVICE_H_
+#ifndef TUSB_HID_DEVICE_H_
+#define TUSB_HID_DEVICE_H_
#include "hid.h"
@@ -48,8 +48,7 @@
#endif
//--------------------------------------------------------------------+
-// Application API (Multiple Instances)
-// CFG_TUD_HID > 1
+// Application API (Multiple Instances) i.e. CFG_TUD_HID > 1
//--------------------------------------------------------------------+
// Check if the interface is ready to use
@@ -66,7 +65,7 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u
// KEYBOARD: convenient helper to send keyboard report if application
// use template layout report as defined by hid_keyboard_report_t
-bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, uint8_t keycode[6]);
+bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, const uint8_t keycode[6]);
// MOUSE: convenient helper to send mouse report if application
// use template layout report as defined by hid_mouse_report_t
@@ -76,12 +75,6 @@ bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons
// use template layout report as defined by hid_abs_mouse_report_t
bool tud_hid_n_abs_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal);
-
-static inline bool tud_hid_abs_mouse_report(uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal)
-{
- return tud_hid_n_abs_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
-}
-
// Gamepad: convenient helper to send gamepad report if application
// use template layout report TUD_HID_REPORT_DESC_GAMEPAD
bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
@@ -89,16 +82,40 @@ bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, int8_t x, int
//--------------------------------------------------------------------+
// Application API (Single Port)
//--------------------------------------------------------------------+
-static inline bool tud_hid_ready(void);
-static inline uint8_t tud_hid_interface_protocol(void);
-static inline uint8_t tud_hid_get_protocol(void);
-static inline bool tud_hid_report(uint8_t report_id, void const* report, uint16_t len);
-static inline bool tud_hid_keyboard_report(uint8_t report_id, uint8_t modifier, uint8_t keycode[6]);
-static inline bool tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal);
-static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_ready(void) {
+ return tud_hid_n_ready(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tud_hid_interface_protocol(void) {
+ return tud_hid_n_interface_protocol(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tud_hid_get_protocol(void) {
+ return tud_hid_n_get_protocol(0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_report(uint8_t report_id, void const* report, uint16_t len) {
+ return tud_hid_n_report(0, report_id, report, len);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_keyboard_report(uint8_t report_id, uint8_t modifier, const uint8_t keycode[6]) {
+ return tud_hid_n_keyboard_report(0, report_id, modifier, keycode);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal) {
+ return tud_hid_n_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_abs_mouse_report(uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal) {
+ return tud_hid_n_abs_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) {
+ return tud_hid_n_gamepad_report(0, report_id, x, y, z, rz, rx, ry, hat, buttons);
+}
//--------------------------------------------------------------------+
-// Callbacks (Weak is optional)
+// Application Callbacks
//--------------------------------------------------------------------+
// Invoked when received GET HID REPORT DESCRIPTOR request
@@ -111,61 +128,25 @@ uint8_t const * tud_hid_descriptor_report_cb(uint8_t instance);
uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen);
// Invoked when received SET_REPORT control request or
-// received data on OUT endpoint ( Report ID = 0, Type = 0 )
+// received data on OUT endpoint (Report ID = 0, Type = OUTPUT)
void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize);
// Invoked when received SET_PROTOCOL request
// protocol is either HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
-TU_ATTR_WEAK void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol);
+void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol);
// Invoked when received SET_IDLE request. return false will stall the request
-// - Idle Rate = 0 : only send report if there is changes, i.e skip duplication
+// - Idle Rate = 0 : only send report if there is changes, i.e. skip duplication
// - Idle Rate > 0 : skip duplication, but send at least 1 report every idle rate (in unit of 4 ms).
-TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
+bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
// Invoked when sent REPORT successfully to host
// Application can use this to send the next report
// Note: For composite reports, report[0] is report ID
-TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
-
-//--------------------------------------------------------------------+
-// Inline Functions
-//--------------------------------------------------------------------+
-static inline bool tud_hid_ready(void)
-{
- return tud_hid_n_ready(0);
-}
-
-static inline uint8_t tud_hid_interface_protocol(void)
-{
- return tud_hid_n_interface_protocol(0);
-}
-
-static inline uint8_t tud_hid_get_protocol(void)
-{
- return tud_hid_n_get_protocol(0);
-}
-
-static inline bool tud_hid_report(uint8_t report_id, void const* report, uint16_t len)
-{
- return tud_hid_n_report(0, report_id, report, len);
-}
-
-static inline bool tud_hid_keyboard_report(uint8_t report_id, uint8_t modifier, uint8_t keycode[6])
-{
- return tud_hid_n_keyboard_report(0, report_id, modifier, keycode);
-}
-
-static inline bool tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal)
-{
- return tud_hid_n_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
-}
-
-static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons)
-{
- return tud_hid_n_gamepad_report(0, report_id, x, y, z, rz, rx, ry, hat, buttons);
-}
+// Invoked when a transfer wasn't successful
+void tud_hid_report_failed_cb(uint8_t instance, hid_report_type_t report_type, uint8_t const* report, uint16_t xferred_bytes);
/* --------------------------------------------------------------------+
* HID Report Descriptor Template
@@ -461,6 +442,178 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
HID_OUTPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
HID_COLLECTION_END \
+// HID Lighting and Illumination Report Descriptor Template
+// - 1st parameter is report id (required)
+// Creates 6 report ids for lighting HID usages in the following order:
+// report_id+0: HID_USAGE_LIGHTING_LAMP_ARRAY_ATTRIBUTES_REPORT
+// report_id+1: HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_REQUEST_REPORT
+// report_id+2: HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_RESPONSE_REPORT
+// report_id+3: HID_USAGE_LIGHTING_LAMP_MULTI_UPDATE_REPORT
+// report_id+4: HID_USAGE_LIGHTING_LAMP_RANGE_UPDATE_REPORT
+// report_id+5: HID_USAGE_LIGHTING_LAMP_ARRAY_CONTROL_REPORT
+#define TUD_HID_REPORT_DESC_LIGHTING(report_id) \
+ HID_USAGE_PAGE ( HID_USAGE_PAGE_LIGHTING_AND_ILLUMINATION ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ARRAY ),\
+ HID_COLLECTION ( HID_COLLECTION_APPLICATION ),\
+ /* Lamp Array Attributes Report */ \
+ HID_REPORT_ID (report_id ) \
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ARRAY_ATTRIBUTES_REPORT ),\
+ HID_COLLECTION ( HID_COLLECTION_LOGICAL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_COUNT ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 65535, 3 ),\
+ HID_REPORT_SIZE ( 16 ),\
+ HID_REPORT_COUNT ( 1 ),\
+ HID_FEATURE ( HID_CONSTANT | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BOUNDING_BOX_WIDTH_IN_MICROMETERS ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BOUNDING_BOX_HEIGHT_IN_MICROMETERS ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BOUNDING_BOX_DEPTH_IN_MICROMETERS ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ARRAY_KIND ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_MIN_UPDATE_INTERVAL_IN_MICROSECONDS ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 2147483647, 3 ),\
+ HID_REPORT_SIZE ( 32 ),\
+ HID_REPORT_COUNT ( 5 ),\
+ HID_FEATURE ( HID_CONSTANT | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_COLLECTION_END ,\
+ /* Lamp Attributes Request Report */ \
+ HID_REPORT_ID ( report_id + 1 ) \
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_REQUEST_REPORT ),\
+ HID_COLLECTION ( HID_COLLECTION_LOGICAL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ID ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 65535, 3 ),\
+ HID_REPORT_SIZE ( 16 ),\
+ HID_REPORT_COUNT ( 1 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_COLLECTION_END ,\
+ /* Lamp Attributes Response Report */ \
+ HID_REPORT_ID ( report_id + 2 ) \
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ATTRIBUTES_RESPONSE_REPORT ),\
+ HID_COLLECTION ( HID_COLLECTION_LOGICAL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ID ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 65535, 3 ),\
+ HID_REPORT_SIZE ( 16 ),\
+ HID_REPORT_COUNT ( 1 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_POSITION_X_IN_MICROMETERS ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_POSITION_Y_IN_MICROMETERS ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_POSITION_Z_IN_MICROMETERS ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_UPDATE_LATENCY_IN_MICROSECONDS ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_PURPOSES ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 2147483647, 3 ),\
+ HID_REPORT_SIZE ( 32 ),\
+ HID_REPORT_COUNT ( 5 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_LEVEL_COUNT ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_LEVEL_COUNT ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_LEVEL_COUNT ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_LEVEL_COUNT ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_IS_PROGRAMMABLE ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INPUT_BINDING ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 255, 2 ),\
+ HID_REPORT_SIZE ( 8 ),\
+ HID_REPORT_COUNT ( 6 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_COLLECTION_END ,\
+ /* Lamp Multi-Update Report */ \
+ HID_REPORT_ID ( report_id + 3 ) \
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_MULTI_UPDATE_REPORT ),\
+ HID_COLLECTION ( HID_COLLECTION_LOGICAL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_COUNT ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_UPDATE_FLAGS ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX ( 8 ),\
+ HID_REPORT_SIZE ( 8 ),\
+ HID_REPORT_COUNT ( 2 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ID ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 65535, 3 ),\
+ HID_REPORT_SIZE ( 16 ),\
+ HID_REPORT_COUNT ( 8 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 255, 2 ),\
+ HID_REPORT_SIZE ( 8 ),\
+ HID_REPORT_COUNT ( 32 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_COLLECTION_END ,\
+ /* Lamp Range Update Report */ \
+ HID_REPORT_ID ( report_id + 4 ) \
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_RANGE_UPDATE_REPORT ),\
+ HID_COLLECTION ( HID_COLLECTION_LOGICAL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_UPDATE_FLAGS ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX ( 8 ),\
+ HID_REPORT_SIZE ( 8 ),\
+ HID_REPORT_COUNT ( 1 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ID_START ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ID_END ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 65535, 3 ),\
+ HID_REPORT_SIZE ( 16 ),\
+ HID_REPORT_COUNT ( 2 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_RED_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_GREEN_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_BLUE_UPDATE_CHANNEL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_INTENSITY_UPDATE_CHANNEL ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX_N ( 255, 2 ),\
+ HID_REPORT_SIZE ( 8 ),\
+ HID_REPORT_COUNT ( 4 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_COLLECTION_END ,\
+ /* Lamp Array Control Report */ \
+ HID_REPORT_ID ( report_id + 5 ) \
+ HID_USAGE ( HID_USAGE_LIGHTING_LAMP_ARRAY_CONTROL_REPORT ),\
+ HID_COLLECTION ( HID_COLLECTION_LOGICAL ),\
+ HID_USAGE ( HID_USAGE_LIGHTING_AUTONOMOUS_MODE ),\
+ HID_LOGICAL_MIN ( 0 ),\
+ HID_LOGICAL_MAX ( 1 ),\
+ HID_REPORT_SIZE ( 8 ),\
+ HID_REPORT_COUNT ( 1 ),\
+ HID_FEATURE ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
+ HID_COLLECTION_END ,\
+ HID_COLLECTION_END \
+
//--------------------------------------------------------------------+
// Internal Class Driver API
//--------------------------------------------------------------------+
@@ -475,4 +628,4 @@ bool hidd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t ev
}
#endif
-#endif /* _TUSB_HID_DEVICE_H_ */
+#endif
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 115a8a4df8..7639a8fc6f 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -657,7 +657,9 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr,
uint8_t const data8 = desc_report[0];
TU_LOG(3, "tag = %d, type = %d, size = %d, data = ", tag, type, size);
- for (uint32_t i = 0; i < size; i++) TU_LOG(3, "%02X ", desc_report[i]);
+ for (uint32_t i = 0; i < size; i++) {
+ TU_LOG(3, "%02X ", desc_report[i]);
+ }
TU_LOG(3, "\r\n");
switch (type) {
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 588fcaacac..447560b4dd 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -689,6 +689,24 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
}
break;
+ case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
+ resplen = 0;
+
+ if (tud_msc_prevent_allow_medium_removal_cb)
+ {
+ scsi_prevent_allow_medium_removal_t const * prevent_allow = (scsi_prevent_allow_medium_removal_t const *) scsi_cmd;
+ if ( !tud_msc_prevent_allow_medium_removal_cb(lun, prevent_allow->prohibit_removal, prevent_allow->control) )
+ {
+ // Failed status response
+ resplen = - 1;
+
+ // set default sense if not set by callback
+ if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
+ }
+ }
+ break;
+
+
case SCSI_CMD_READ_CAPACITY_10:
{
uint32_t block_count;
diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h
index 4247a40bd8..29acd280ab 100644
--- a/src/class/msc/msc_device.h
+++ b/src/class/msc/msc_device.h
@@ -131,6 +131,9 @@ TU_ATTR_WEAK uint8_t tud_msc_get_maxlun_cb(void);
// - Start = 1 : active mode, if load_eject = 1 : load disk storage
TU_ATTR_WEAK bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject);
+//Invoked when we receive the Prevent / Allow Medium Removal command
+TU_ATTR_WEAK bool tud_msc_prevent_allow_medium_removal_cb(uint8_t lun, uint8_t prohibit_removal, uint8_t control);
+
// Invoked when received REQUEST_SENSE
TU_ATTR_WEAK int32_t tud_msc_request_sense_cb(uint8_t lun, void* buffer, uint16_t bufsize);
diff --git a/src/class/net/ncm.h b/src/class/net/ncm.h
index 96ba11fbc5..1b987fca04 100644
--- a/src/class/net/ncm.h
+++ b/src/class/net/ncm.h
@@ -2,6 +2,7 @@
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
+ * Copyright (c) 2024, Hardy Griech
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -24,22 +25,58 @@
* This file is part of the TinyUSB stack.
*/
-
#ifndef _TUSB_NCM_H_
#define _TUSB_NCM_H_
#include "common/tusb_common.h"
-#ifdef __cplusplus
- extern "C" {
+// NTB buffers size for reception side, must be >> MTU to avoid TCP retransmission (driver issue ?)
+// Linux use 2048 as minimal size
+#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
+ #define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200
#endif
-// Table 4.3 Data Class Interface Protocol Codes
-typedef enum
-{
- NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK = 0x01
-} ncm_data_interface_protocol_code_t;
+// NTB buffers size for reception side, must be > MTU
+// Linux use 2048 as minimal size
+#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
+ #define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200
+#endif
+
+// Number of NTB buffers for reception side
+// Depending on the configuration, this parameter could be increased with the cost of additional RAM requirements
+// On Full-Speed (RP2040) :
+// 1 - good performance
+// 2 - up to 30% more performance with iperf with small packets
+// >2 - no performance gain
+// On High-Speed (STM32F7) :
+// No performance gain
+#ifndef CFG_TUD_NCM_OUT_NTB_N
+ #define CFG_TUD_NCM_OUT_NTB_N 1
+#endif
+// Number of NTB buffers for transmission side
+// Depending on the configuration, this parameter could be increased with the cost of additional RAM requirements
+// On Full-Speed (RP2040) :
+// 1 - good performance but SystemView shows lost events (on load test)
+// 2 - up to 50% more performance with iperf with small packets, "tud_network_can_xmit: request blocked"
+// happens from time to time with SystemView
+// 3 - "tud_network_can_xmit: request blocked" never happens
+// >3 - no performance gain
+// On High-Speed (STM32F7) :
+// No performance gain
+#ifndef CFG_TUD_NCM_IN_NTB_N
+ #define CFG_TUD_NCM_IN_NTB_N 1
+#endif
+
+// How many datagrams it is allowed to put into an NTB for transmission side
+#ifndef CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB
+ #define CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB 8
+#endif
+
+// This tells the host how many datagrams it is allowed to put into an NTB
+#ifndef CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB
+ #define CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB 6
+#endif
// Table 6.2 Class-Specific Request Codes for Network Control Model subclass
typedef enum
@@ -62,8 +99,65 @@ typedef enum
NCM_SET_CRC_MODE = 0x8A,
} ncm_request_code_t;
-#ifdef __cplusplus
- }
-#endif
+#define NTH16_SIGNATURE 0x484D434E
+#define NDP16_SIGNATURE_NCM0 0x304D434E
+#define NDP16_SIGNATURE_NCM1 0x314D434E
+
+typedef struct TU_ATTR_PACKED {
+ uint16_t wLength;
+ uint16_t bmNtbFormatsSupported;
+ uint32_t dwNtbInMaxSize;
+ uint16_t wNdbInDivisor;
+ uint16_t wNdbInPayloadRemainder;
+ uint16_t wNdbInAlignment;
+ uint16_t wReserved;
+ uint32_t dwNtbOutMaxSize;
+ uint16_t wNdbOutDivisor;
+ uint16_t wNdbOutPayloadRemainder;
+ uint16_t wNdbOutAlignment;
+ uint16_t wNtbOutMaxDatagrams;
+} ntb_parameters_t;
+
+typedef struct TU_ATTR_PACKED {
+ uint32_t dwSignature;
+ uint16_t wHeaderLength;
+ uint16_t wSequence;
+ uint16_t wBlockLength;
+ uint16_t wNdpIndex;
+} nth16_t;
+
+typedef struct TU_ATTR_PACKED {
+ uint16_t wDatagramIndex;
+ uint16_t wDatagramLength;
+} ndp16_datagram_t;
+
+typedef struct TU_ATTR_PACKED {
+ uint32_t dwSignature;
+ uint16_t wLength;
+ uint16_t wNextNdpIndex;
+ //ndp16_datagram_t datagram[];
+} ndp16_t;
+
+typedef union TU_ATTR_PACKED {
+ struct {
+ nth16_t nth;
+ ndp16_t ndp;
+ ndp16_datagram_t ndp_datagram[CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB + 1];
+ };
+ uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
+} xmit_ntb_t;
+
+typedef union TU_ATTR_PACKED {
+ struct {
+ nth16_t nth;
+ // only the header is at a guaranteed position
+ };
+ uint8_t data[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+} recv_ntb_t;
+
+struct ncm_notify_t {
+ tusb_control_request_t header;
+ uint32_t downlink, uplink;
+};
#endif
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index f84bd9f736..90d7471850 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -1,9 +1,10 @@
/*
* The MIT License (MIT)
*
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2024 Hardy Griech
* Copyright (c) 2020 Jacob Berg Potter
* Copyright (c) 2020 Peter Lawrence
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -26,12 +27,37 @@
* This file is part of the TinyUSB stack.
*/
+/**
+ * Small Glossary (from the spec)
+ * --------------
+ * Datagram - A collection of bytes forming a single item of information, passed as a unit from source to destination.
+ * NCM - Network Control Model
+ * NDP - NCM Datagram Pointer: NTB structure that delineates Datagrams (typically Ethernet frames) within an NTB
+ * NTB - NCM Transfer Block: a data structure for efficient USB encapsulation of one or more datagrams
+ * Each NTB is designed to be a single USB transfer
+ * NTH - NTB Header: a data structure at the front of each NTB, which provides the information needed to validate
+ * the NTB and begin decoding
+ *
+ * Some explanations
+ * -----------------
+ * - rhport is the USB port of the device, in most cases "0"
+ * - itf_data_alt if != 0 -> data xmit/recv are allowed (see spec)
+ * - ep_in IN endpoints take data from the device intended to go in to the host (the device transmits)
+ * - ep_out OUT endpoints send data out of the host to the device (the device receives)
+ */
+
#include "tusb_option.h"
-#if ( CFG_TUD_ENABLED && CFG_TUD_NCM )
+#if (CFG_TUD_ENABLED && CFG_TUD_NCM)
+
+#include
+#include
+#include
#include "device/usbd.h"
#include "device/usbd_pvt.h"
+
+#include "ncm.h"
#include "net_device.h"
// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
@@ -41,482 +67,829 @@
#define TU_LOG_DRV(...) TU_LOG(CFG_TUD_NCM_LOG_LEVEL, __VA_ARGS__)
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-#define NTH16_SIGNATURE 0x484D434E
-#define NDP16_SIGNATURE_NCM0 0x304D434E
-#define NDP16_SIGNATURE_NCM1 0x314D434E
-
-typedef struct TU_ATTR_PACKED
-{
- uint16_t wLength;
- uint16_t bmNtbFormatsSupported;
- uint32_t dwNtbInMaxSize;
- uint16_t wNdbInDivisor;
- uint16_t wNdbInPayloadRemainder;
- uint16_t wNdbInAlignment;
- uint16_t wReserved;
- uint32_t dwNtbOutMaxSize;
- uint16_t wNdbOutDivisor;
- uint16_t wNdbOutPayloadRemainder;
- uint16_t wNdbOutAlignment;
- uint16_t wNtbOutMaxDatagrams;
-} ntb_parameters_t;
-
-typedef struct TU_ATTR_PACKED
-{
- uint32_t dwSignature;
- uint16_t wHeaderLength;
- uint16_t wSequence;
- uint16_t wBlockLength;
- uint16_t wNdpIndex;
-} nth16_t;
-
-typedef struct TU_ATTR_PACKED
-{
- uint16_t wDatagramIndex;
- uint16_t wDatagramLength;
-} ndp16_datagram_t;
-
-typedef struct TU_ATTR_PACKED
-{
- uint32_t dwSignature;
- uint16_t wLength;
- uint16_t wNextNdpIndex;
- ndp16_datagram_t datagram[];
-} ndp16_t;
-
-typedef union TU_ATTR_PACKED {
- struct {
- nth16_t nth;
- ndp16_t ndp;
- };
- uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
-} transmit_ntb_t;
-
-struct ecm_notify_struct
-{
- tusb_control_request_t header;
- uint32_t downlink, uplink;
+// Alignment must be 4
+#define TUD_NCM_ALIGNMENT 4
+// calculate alignment of xmit datagrams within an NTB
+#define XMIT_ALIGN_OFFSET(x) ((TUD_NCM_ALIGNMENT - ((x) & (TUD_NCM_ALIGNMENT - 1))) & (TUD_NCM_ALIGNMENT - 1))
+
+//-----------------------------------------------------------------------------
+//
+// Module global things
+//
+#define XMIT_NTB_N CFG_TUD_NCM_IN_NTB_N
+#define RECV_NTB_N CFG_TUD_NCM_OUT_NTB_N
+
+typedef struct {
+ // general
+ uint8_t ep_in; // endpoint for outgoing datagrams (naming is a little bit confusing)
+ uint8_t ep_out; // endpoint for incoming datagrams (naming is a little bit confusing)
+ uint8_t ep_notif; // endpoint for notifications
+ uint8_t itf_num; // interface number
+ uint8_t itf_data_alt; // ==0 -> no endpoints, i.e. no network traffic, ==1 -> normal operation with two endpoints (spec, chapter 5.3)
+ uint8_t rhport; // storage of \a rhport because some callbacks are done without it
+
+ // recv handling
+ CFG_TUSB_MEM_ALIGN recv_ntb_t recv_ntb[RECV_NTB_N]; // actual recv NTBs
+ recv_ntb_t *recv_free_ntb[RECV_NTB_N]; // free list of recv NTBs
+ recv_ntb_t *recv_ready_ntb[RECV_NTB_N]; // NTBs waiting for transmission to glue logic
+ recv_ntb_t *recv_tinyusb_ntb; // buffer for the running transfer TinyUSB -> driver
+ recv_ntb_t *recv_glue_ntb; // buffer for the running transfer driver -> glue logic
+ uint16_t recv_glue_ntb_datagram_ndx; // index into \a recv_glue_ntb_datagram
+
+ // xmit handling
+ CFG_TUSB_MEM_ALIGN xmit_ntb_t xmit_ntb[XMIT_NTB_N]; // actual xmit NTBs
+ xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N]; // free list of xmit NTBs
+ xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N]; // NTBs waiting for transmission to TinyUSB
+ xmit_ntb_t *xmit_tinyusb_ntb; // buffer for the running transfer driver -> TinyUSB
+ xmit_ntb_t *xmit_glue_ntb; // buffer for the running transfer glue logic -> driver
+ uint16_t xmit_sequence; // NTB sequence counter
+ uint16_t xmit_glue_ntb_datagram_ndx; // index into \a xmit_glue_ntb_datagram
+
+ // notification handling
+ enum {
+ NOTIFICATION_SPEED,
+ NOTIFICATION_CONNECTED,
+ NOTIFICATION_DONE
+ } notification_xmit_state; // state of notification transmission
+ bool notification_xmit_is_running; // notification is currently transmitted
+} ncm_interface_t;
+
+CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN tu_static ncm_interface_t ncm_interface;
+
+/**
+ * This is the NTB parameter structure
+ *
+ * \attention
+ * We are lucky, that byte order is correct
+ */
+CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = {
+ .wLength = sizeof(ntb_parameters_t),
+ .bmNtbFormatsSupported = 0x01,// 16-bit NTB supported
+ .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
+ .wNdbInDivisor = 1,
+ .wNdbInPayloadRemainder = 0,
+ .wNdbInAlignment = TUD_NCM_ALIGNMENT,
+ .wReserved = 0,
+ .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
+ .wNdbOutDivisor = 1,
+ .wNdbOutPayloadRemainder = 0,
+ .wNdbOutAlignment = TUD_NCM_ALIGNMENT,
+ .wNtbOutMaxDatagrams = CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB,
};
-typedef struct
-{
- uint8_t itf_num; // Index number of Management Interface, +1 for Data Interface
- uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active
+// Some confusing remarks about wNtbOutMaxDatagrams...
+// ==1 -> SystemView packets/s goes up to 2000 and events are lost during startup
+// ==0 -> SystemView runs fine, iperf shows in wireshark a lot of error
+// ==6 -> SystemView runs fine, iperf also
+// >6 -> iperf starts to show errors
+// -> 6 seems to be the best value. Why? Don't know, perhaps only on my system?
+//
+// iperf: for MSS in 100 200 400 800 1200 1450 1500; do iperf -c 192.168.14.1 -e -i 1 -M $MSS -l 8192 -P 1; sleep 2; done
+// sysview: SYSTICKS_PER_SEC=35000, IDLE_US=1000, PRINT_MOD=1000
+//
+
+//-----------------------------------------------------------------------------
+//
+// everything about notifications
+//
+tu_static struct ncm_notify_t ncm_notify_connected = {
+ .header = {
+ .bmRequestType_bit = {
+ .recipient = TUSB_REQ_RCPT_INTERFACE,
+ .type = TUSB_REQ_TYPE_CLASS,
+ .direction = TUSB_DIR_IN},
+ .bRequest = CDC_NOTIF_NETWORK_CONNECTION,
+ .wValue = 1 /* Connected */,
+ .wLength = 0,
+ },
+};
- uint8_t ep_notif;
- uint8_t ep_in;
- uint8_t ep_out;
+tu_static struct ncm_notify_t ncm_notify_speed_change = {
+ .header = {
+ .bmRequestType_bit = {
+ .recipient = TUSB_REQ_RCPT_INTERFACE,
+ .type = TUSB_REQ_TYPE_CLASS,
+ .direction = TUSB_DIR_IN},
+ .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
+ .wLength = 8,
+ },
+ .downlink = TUD_OPT_HIGH_SPEED ? 480000000 : 12000000,
+ .uplink = TUD_OPT_HIGH_SPEED ? 480000000 : 12000000,
+};
- const ndp16_t *ndp;
- uint8_t num_datagrams, current_datagram_index;
+/**
+ * Transmit next notification to the host (if appropriate).
+ * Notifications are transferred to the host once during connection setup.
+ */
+static void notification_xmit(uint8_t rhport, bool force_next) {
+ TU_LOG_DRV("notification_xmit(%d, %d) - %d %d\n", force_next, rhport, ncm_interface.notification_xmit_state, ncm_interface.notification_xmit_is_running);
- enum {
- REPORT_SPEED,
- REPORT_CONNECTED,
- REPORT_DONE
- } report_state;
- bool report_pending;
+ if (!force_next && ncm_interface.notification_xmit_is_running) {
+ return;
+ }
- uint8_t current_ntb; // Index in transmit_ntb[] that is currently being filled with datagrams
- uint8_t datagram_count; // Number of datagrams in transmit_ntb[current_ntb]
- uint16_t next_datagram_offset; // Offset in transmit_ntb[current_ntb].data to place the next datagram
- uint16_t ntb_in_size; // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE
- uint8_t max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
+ if (ncm_interface.notification_xmit_state == NOTIFICATION_SPEED) {
+ TU_LOG_DRV(" NOTIFICATION_SPEED\n");
+ ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
+ usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
+ ncm_interface.notification_xmit_state = NOTIFICATION_CONNECTED;
+ ncm_interface.notification_xmit_is_running = true;
+ } else if (ncm_interface.notification_xmit_state == NOTIFICATION_CONNECTED) {
+ TU_LOG_DRV(" NOTIFICATION_CONNECTED\n");
+ ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
+ usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
+ ncm_interface.notification_xmit_state = NOTIFICATION_DONE;
+ ncm_interface.notification_xmit_is_running = true;
+ } else {
+ TU_LOG_DRV(" NOTIFICATION_FINISHED\n");
+ }
+} // notification_xmit
- uint16_t nth_sequence; // Sequence number counter for transmitted NTBs
+//-----------------------------------------------------------------------------
+//
+// everything about packet transmission (driver -> TinyUSB)
+//
- bool transferring;
+/**
+ * Put NTB into the transmitter free list.
+ */
+static void xmit_put_ntb_into_free_list(xmit_ntb_t *free_ntb) {
+ TU_LOG_DRV("xmit_put_ntb_into_free_list() - %p\n", ncm_interface.xmit_tinyusb_ntb);
-} ncm_interface_t;
+ if (free_ntb == NULL) { // can happen due to ZLPs
+ return;
+ }
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = {
- .wLength = sizeof(ntb_parameters_t),
- .bmNtbFormatsSupported = 0x01,
- .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
- .wNdbInDivisor = 4,
- .wNdbInPayloadRemainder = 0,
- .wNdbInAlignment = CFG_TUD_NCM_ALIGNMENT,
- .wReserved = 0,
- .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
- .wNdbOutDivisor = 4,
- .wNdbOutPayloadRemainder = 0,
- .wNdbOutAlignment = CFG_TUD_NCM_ALIGNMENT,
- .wNtbOutMaxDatagrams = 0
-};
+ for (int i = 0; i < XMIT_NTB_N; ++i) {
+ if (ncm_interface.xmit_free_ntb[i] == NULL) {
+ ncm_interface.xmit_free_ntb[i] = free_ntb;
+ return;
+ }
+ }
+ TU_LOG_DRV("(EE) xmit_put_ntb_into_free_list - no entry in free list\n");// this should not happen
+} // xmit_put_ntb_into_free_list
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static transmit_ntb_t transmit_ntb[2];
+/**
+ * Get an NTB from the free list
+ */
+static xmit_ntb_t *xmit_get_free_ntb(void) {
+ TU_LOG_DRV("xmit_get_free_ntb()\n");
+
+ for (int i = 0; i < XMIT_NTB_N; ++i) {
+ if (ncm_interface.xmit_free_ntb[i] != NULL) {
+ xmit_ntb_t *free = ncm_interface.xmit_free_ntb[i];
+ ncm_interface.xmit_free_ntb[i] = NULL;
+ return free;
+ }
+ }
+ return NULL;
+} // xmit_get_free_ntb
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+/**
+ * Put a filled NTB into the ready list
+ */
+static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb) {
+ TU_LOG_DRV("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
-tu_static ncm_interface_t ncm_interface;
+ for (int i = 0; i < XMIT_NTB_N; ++i) {
+ if (ncm_interface.xmit_ready_ntb[i] == NULL) {
+ ncm_interface.xmit_ready_ntb[i] = ready_ntb;
+ return;
+ }
+ }
+ TU_LOG_DRV("(EE) xmit_put_ntb_into_ready_list: ready list full\n");// this should not happen
+} // xmit_put_ntb_into_ready_list
-/*
- * Set up the NTB state in ncm_interface to be ready to add datagrams.
+/**
+ * Get the next NTB from the ready list (and remove it from the list).
+ * If the ready list is empty, return NULL.
*/
-static void ncm_prepare_for_tx(void) {
- ncm_interface.datagram_count = 0;
- // datagrams start after all the headers
- ncm_interface.next_datagram_offset = sizeof(nth16_t) + sizeof(ndp16_t)
- + ((CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1) * sizeof(ndp16_datagram_t));
-}
+static xmit_ntb_t *xmit_get_next_ready_ntb(void) {
+ xmit_ntb_t *r = NULL;
-/*
- * If not already transmitting, start sending the current NTB to the host and swap buffers
- * to start filling the other one with datagrams.
+ r = ncm_interface.xmit_ready_ntb[0];
+ memmove(ncm_interface.xmit_ready_ntb + 0, ncm_interface.xmit_ready_ntb + 1, sizeof(ncm_interface.xmit_ready_ntb) - sizeof(ncm_interface.xmit_ready_ntb[0]));
+ ncm_interface.xmit_ready_ntb[XMIT_NTB_N - 1] = NULL;
+
+ TU_LOG_DRV("recv_get_next_ready_ntb: %p\n", r);
+ return r;
+} // xmit_get_next_ready_ntb
+
+/**
+ * Transmit a ZLP if required
+ *
+ * \note
+ * Insertion of the ZLPs is a little bit different then described in the spec.
+ * But the below implementation actually works. Don't know if this is a spec
+ * or TinyUSB issue.
+ *
+ * \pre
+ * This must be called from netd_xfer_cb() so that ep_in is ready
*/
-static void ncm_start_tx(void) {
- if (ncm_interface.transferring) {
- return;
+static bool xmit_insert_required_zlp(uint8_t rhport, uint32_t xferred_bytes) {
+ TU_LOG_DRV("xmit_insert_required_zlp(%d,%ld)\n", rhport, xferred_bytes);
+
+ if (xferred_bytes == 0 || xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE != 0) {
+ return false;
}
- transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
- size_t ntb_length = ncm_interface.next_datagram_offset;
+ TU_ASSERT(ncm_interface.itf_data_alt == 1, false);
+ TU_ASSERT(!usbd_edpt_busy(rhport, ncm_interface.ep_in), false);
- // Fill in NTB header
- ntb->nth.dwSignature = NTH16_SIGNATURE;
- ntb->nth.wHeaderLength = sizeof(nth16_t);
- ntb->nth.wSequence = ncm_interface.nth_sequence++;
- ntb->nth.wBlockLength = ntb_length;
- ntb->nth.wNdpIndex = sizeof(nth16_t);
+ TU_LOG_DRV("xmit_insert_required_zlp! (%u)\n", (unsigned) xferred_bytes);
- // Fill in NDP16 header and terminator
- ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0;
- ntb->ndp.wLength = sizeof(ndp16_t) + (ncm_interface.datagram_count + 1) * sizeof(ndp16_datagram_t);
- ntb->ndp.wNextNdpIndex = 0;
- ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = 0;
- ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = 0;
+ // start transmission of the ZLP
+ usbd_edpt_xfer(rhport, ncm_interface.ep_in, NULL, 0);
- // Kick off an endpoint transfer
- usbd_edpt_xfer(0, ncm_interface.ep_in, ntb->data, ntb_length);
- ncm_interface.transferring = true;
+ return true;
+} // xmit_insert_required_zlp
- // Swap to the other NTB and clear it out
- ncm_interface.current_ntb = 1 - ncm_interface.current_ntb;
- ncm_prepare_for_tx();
-}
+/**
+ * Start transmission if it there is a waiting packet and if can be done from interface side.
+ */
+static void xmit_start_if_possible(uint8_t rhport) {
+ TU_LOG_DRV("xmit_start_if_possible()\n");
-tu_static struct ecm_notify_struct ncm_notify_connected =
-{
- .header = {
- .bmRequestType_bit = {
- .recipient = TUSB_REQ_RCPT_INTERFACE,
- .type = TUSB_REQ_TYPE_CLASS,
- .direction = TUSB_DIR_IN
- },
- .bRequest = CDC_NOTIF_NETWORK_CONNECTION,
- .wValue = 1 /* Connected */,
- .wLength = 0,
- },
-};
+ if (ncm_interface.xmit_tinyusb_ntb != NULL) {
+ TU_LOG_DRV(" !xmit_start_if_possible 1\n");
+ return;
+ }
+ if (ncm_interface.itf_data_alt != 1) {
+ TU_LOG_DRV("(EE) !xmit_start_if_possible 2\n");
+ return;
+ }
+ if (usbd_edpt_busy(rhport, ncm_interface.ep_in)) {
+ TU_LOG_DRV(" !xmit_start_if_possible 3\n");
+ return;
+ }
-tu_static struct ecm_notify_struct ncm_notify_speed_change =
-{
- .header = {
- .bmRequestType_bit = {
- .recipient = TUSB_REQ_RCPT_INTERFACE,
- .type = TUSB_REQ_TYPE_CLASS,
- .direction = TUSB_DIR_IN
- },
- .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
- .wLength = 8,
- },
- .downlink = 10000000,
- .uplink = 10000000,
-};
+ ncm_interface.xmit_tinyusb_ntb = xmit_get_next_ready_ntb();
+ if (ncm_interface.xmit_tinyusb_ntb == NULL) {
+ if (ncm_interface.xmit_glue_ntb == NULL || ncm_interface.xmit_glue_ntb_datagram_ndx == 0) {
+ // -> really nothing is waiting
+ return;
+ }
+ ncm_interface.xmit_tinyusb_ntb = ncm_interface.xmit_glue_ntb;
+ ncm_interface.xmit_glue_ntb = NULL;
+ }
-void tud_network_recv_renew(void)
-{
- if (!ncm_interface.num_datagrams)
+ #if CFG_TUD_NCM_LOG_LEVEL >= 3
{
- usbd_edpt_xfer(0, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb));
- return;
+ uint16_t len = ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength;
+ TU_LOG_BUF(3, ncm_interface.xmit_tinyusb_ntb->data[i], len);
}
+ #endif
- const ndp16_t *ndp = ncm_interface.ndp;
- const int i = ncm_interface.current_datagram_index;
- ncm_interface.current_datagram_index++;
- ncm_interface.num_datagrams--;
-
- tud_network_recv_cb(receive_ntb + ndp->datagram[i].wDatagramIndex, ndp->datagram[i].wDatagramLength);
-}
+ if (ncm_interface.xmit_glue_ntb_datagram_ndx != 1) {
+ TU_LOG_DRV(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength, ncm_interface.xmit_glue_ntb_datagram_ndx);
+ }
-//--------------------------------------------------------------------+
-// USBD Driver API
-//--------------------------------------------------------------------+
+ // Kick off an endpoint transfer
+ usbd_edpt_xfer(0, ncm_interface.ep_in, ncm_interface.xmit_tinyusb_ntb->data, ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength);
+} // xmit_start_if_possible
-void netd_init(void)
-{
- tu_memclr(&ncm_interface, sizeof(ncm_interface));
- ncm_interface.ntb_in_size = CFG_TUD_NCM_IN_NTB_MAX_SIZE;
- ncm_interface.max_datagrams_per_ntb = CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB;
- ncm_prepare_for_tx();
-}
+/**
+ * check if a new datagram fits into the current NTB
+ */
+static bool xmit_requested_datagram_fits_into_current_ntb(uint16_t datagram_size) {
+ TU_LOG_DRV("xmit_requested_datagram_fits_into_current_ntb(%d) - %p %p\n", datagram_size, ncm_interface.xmit_tinyusb_ntb, ncm_interface.xmit_glue_ntb);
-bool netd_deinit(void) {
+ if (ncm_interface.xmit_glue_ntb == NULL) {
+ return false;
+ }
+ if (ncm_interface.xmit_glue_ntb_datagram_ndx >= CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB) {
+ return false;
+ }
+ if (ncm_interface.xmit_glue_ntb->nth.wBlockLength + datagram_size + XMIT_ALIGN_OFFSET(datagram_size) > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+ return false;
+ }
return true;
-}
+} // xmit_requested_datagram_fits_into_current_ntb
-void netd_reset(uint8_t rhport)
-{
- (void) rhport;
+/**
+ * Setup an NTB for the glue logic
+ */
+static bool xmit_setup_next_glue_ntb(void) {
+ TU_LOG_DRV("xmit_setup_next_glue_ntb - %p\n", ncm_interface.xmit_glue_ntb);
- netd_init();
-}
+ if (ncm_interface.xmit_glue_ntb != NULL) {
+ // put NTB into waiting list (the new datagram did not fit in)
+ xmit_put_ntb_into_ready_list(ncm_interface.xmit_glue_ntb);
+ }
-uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
- // confirm interface hasn't already been allocated
- TU_ASSERT(0 == ncm_interface.ep_notif, 0);
+ ncm_interface.xmit_glue_ntb = xmit_get_free_ntb();// get next buffer (if any)
+ if (ncm_interface.xmit_glue_ntb == NULL) {
+ TU_LOG_DRV(" xmit_setup_next_glue_ntb - nothing free\n");// should happen rarely
+ return false;
+ }
- //------------- Management Interface -------------//
- ncm_interface.itf_num = itf_desc->bInterfaceNumber;
+ ncm_interface.xmit_glue_ntb_datagram_ndx = 0;
- uint16_t drv_len = sizeof(tusb_desc_interface_t);
- uint8_t const * p_desc = tu_desc_next( itf_desc );
+ xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
- // Communication Functional Descriptors
- while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
- {
- drv_len += tu_desc_len(p_desc);
- p_desc = tu_desc_next(p_desc);
- }
+ // Fill in NTB header
+ ntb->nth.dwSignature = NTH16_SIGNATURE;
+ ntb->nth.wHeaderLength = sizeof(ntb->nth);
+ ntb->nth.wSequence = ncm_interface.xmit_sequence++;
+ ntb->nth.wBlockLength = sizeof(ntb->nth) + sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
+ ntb->nth.wNdpIndex = sizeof(ntb->nth);
- // notification endpoint (if any)
- if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
- {
- TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 );
+ // Fill in NDP16 header and terminator
+ ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0;
+ ntb->ndp.wLength = sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
+ ntb->ndp.wNextNdpIndex = 0;
+
+ memset(ntb->ndp_datagram, 0, sizeof(ntb->ndp_datagram));
+ return true;
+} // xmit_setup_next_glue_ntb
- ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+//-----------------------------------------------------------------------------
+//
+// all the recv_*() stuff (TinyUSB -> driver -> glue logic)
+//
- drv_len += tu_desc_len(p_desc);
- p_desc = tu_desc_next(p_desc);
+/**
+ * Return pointer to an available receive buffer or NULL.
+ * Returned buffer (if any) has the size \a CFG_TUD_NCM_OUT_NTB_MAX_SIZE.
+ */
+static recv_ntb_t *recv_get_free_ntb(void) {
+ TU_LOG_DRV("recv_get_free_ntb()\n");
+
+ for (int i = 0; i < RECV_NTB_N; ++i) {
+ if (ncm_interface.recv_free_ntb[i] != NULL) {
+ recv_ntb_t *free = ncm_interface.recv_free_ntb[i];
+ ncm_interface.recv_free_ntb[i] = NULL;
+ return free;
+ }
}
+ return NULL;
+} // recv_get_free_ntb
- //------------- Data Interface -------------//
- // - CDC-NCM data interface has 2 alternate settings
- // - 0 : zero endpoints for inactive (default)
- // - 1 : IN & OUT endpoints for transfer of NTBs
- TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0);
+/**
+ * Get the next NTB from the ready list (and remove it from the list).
+ * If the ready list is empty, return NULL.
+ */
+static recv_ntb_t *recv_get_next_ready_ntb(void) {
+ recv_ntb_t *r = NULL;
- do
- {
- tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc;
- TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0);
+ r = ncm_interface.recv_ready_ntb[0];
+ memmove(ncm_interface.recv_ready_ntb + 0, ncm_interface.recv_ready_ntb + 1, sizeof(ncm_interface.recv_ready_ntb) - sizeof(ncm_interface.recv_ready_ntb[0]));
+ ncm_interface.recv_ready_ntb[RECV_NTB_N - 1] = NULL;
- drv_len += tu_desc_len(p_desc);
- p_desc = tu_desc_next(p_desc);
- } while((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len));
+ TU_LOG_DRV("recv_get_next_ready_ntb: %p\n", r);
+ return r;
+} // recv_get_next_ready_ntb
- // Pair of endpoints
- TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0);
+/**
+ * Put NTB into the receiver free list.
+ */
+static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb) {
+ TU_LOG_DRV("recv_put_ntb_into_free_list(%p)\n", free_ntb);
- TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) );
+ for (int i = 0; i < RECV_NTB_N; ++i) {
+ if (ncm_interface.recv_free_ntb[i] == NULL) {
+ ncm_interface.recv_free_ntb[i] = free_ntb;
+ return;
+ }
+ }
+ TU_LOG_DRV("(EE) recv_put_ntb_into_free_list - no entry in free list\n");// this should not happen
+} // recv_put_ntb_into_free_list
- drv_len += 2*sizeof(tusb_desc_endpoint_t);
+/**
+ * \a ready_ntb holds a validated NTB,
+ * put this buffer into the waiting list.
+ */
+static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb) {
+ TU_LOG_DRV("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
- return drv_len;
-}
+ for (int i = 0; i < RECV_NTB_N; ++i) {
+ if (ncm_interface.recv_ready_ntb[i] == NULL) {
+ ncm_interface.recv_ready_ntb[i] = ready_ntb;
+ return;
+ }
+ }
+ TU_LOG_DRV("(EE) recv_put_ntb_into_ready_list: ready list full\n");// this should not happen
+} // recv_put_ntb_into_ready_list
-static void ncm_report(void)
-{
- uint8_t const rhport = 0;
- if (ncm_interface.report_state == REPORT_SPEED) {
- ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
- usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
- ncm_interface.report_state = REPORT_CONNECTED;
- ncm_interface.report_pending = true;
- } else if (ncm_interface.report_state == REPORT_CONNECTED) {
- ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
- usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
- ncm_interface.report_state = REPORT_DONE;
- ncm_interface.report_pending = true;
+/**
+ * If possible, start a new reception TinyUSB -> driver.
+ */
+static void recv_try_to_start_new_reception(uint8_t rhport) {
+ TU_LOG_DRV("recv_try_to_start_new_reception(%d)\n", rhport);
+
+ if (ncm_interface.itf_data_alt != 1) {
+ return;
+ }
+ if (ncm_interface.recv_tinyusb_ntb != NULL) {
+ return;
+ }
+ if (usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
+ return;
}
-}
-TU_ATTR_WEAK void tud_network_link_state_cb(bool state)
-{
- (void)state;
-}
+ ncm_interface.recv_tinyusb_ntb = recv_get_free_ntb();
+ if (ncm_interface.recv_tinyusb_ntb == NULL) {
+ return;
+ }
-// Handle class control request
-// return false to stall control endpoint (e.g unsupported request)
-bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
- if ( stage != CONTROL_STAGE_SETUP ) return true;
+ // initiate transfer
+ TU_LOG_DRV(" start reception\n");
+ bool r = usbd_edpt_xfer(rhport, ncm_interface.ep_out, ncm_interface.recv_tinyusb_ntb->data, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+ if (!r) {
+ recv_put_ntb_into_free_list(ncm_interface.recv_tinyusb_ntb);
+ ncm_interface.recv_tinyusb_ntb = NULL;
+ }
+} // recv_try_to_start_new_reception
- switch ( request->bmRequestType_bit.type )
- {
- case TUSB_REQ_TYPE_STANDARD:
- switch ( request->bRequest )
- {
- case TUSB_REQ_GET_INTERFACE:
- {
- uint8_t const req_itfnum = (uint8_t) request->wIndex;
- TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum);
+/**
+ * Validate incoming datagram.
+ * \return true if valid
+ *
+ * \note
+ * \a ndp16->wNextNdpIndex != 0 is not supported
+ */
+static bool recv_validate_datagram(const recv_ntb_t *ntb, uint32_t len) {
+ const nth16_t *nth16 = &(ntb->nth);
- tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
- }
- break;
+ TU_LOG_DRV("recv_validate_datagram(%p, %d)\n", ntb, (int) len);
- case TUSB_REQ_SET_INTERFACE:
- {
- uint8_t const req_itfnum = (uint8_t) request->wIndex;
- uint8_t const req_alt = (uint8_t) request->wValue;
+ // check header
+ if (nth16->wHeaderLength != sizeof(nth16_t)) {
+ TU_LOG_DRV("(EE) ill nth16 length: %d\n", nth16->wHeaderLength);
+ return false;
+ }
+ if (nth16->dwSignature != NTH16_SIGNATURE) {
+ TU_LOG_DRV("(EE) ill signature: 0x%08x\n", (unsigned) nth16->dwSignature);
+ return false;
+ }
+ if (len < sizeof(nth16_t) + sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)) {
+ TU_LOG_DRV("(EE) ill min len: %lu\n", len);
+ return false;
+ }
+ if (nth16->wBlockLength > len) {
+ TU_LOG_DRV("(EE) ill block length: %d > %lu\n", nth16->wBlockLength, len);
+ return false;
+ }
+ if (nth16->wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+ TU_LOG_DRV("(EE) ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+ return false;
+ }
+ if (nth16->wNdpIndex < sizeof(nth16) || nth16->wNdpIndex > len - (sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t))) {
+ TU_LOG_DRV("(EE) ill position of first ndp: %d (%lu)\n", nth16->wNdpIndex, len);
+ return false;
+ }
- // Only valid for Data Interface with Alternate is either 0 or 1
- TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2);
+ // check (first) NDP(16)
+ const ndp16_t *ndp16 = (const ndp16_t *) (ntb->data + nth16->wNdpIndex);
- if (req_alt != ncm_interface.itf_data_alt) {
- ncm_interface.itf_data_alt = req_alt;
+ if (ndp16->wLength < sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)) {
+ TU_LOG_DRV("(EE) ill ndp16 length: %d\n", ndp16->wLength);
+ return false;
+ }
+ if (ndp16->dwSignature != NDP16_SIGNATURE_NCM0 && ndp16->dwSignature != NDP16_SIGNATURE_NCM1) {
+ TU_LOG_DRV("(EE) ill signature: 0x%08x\n", (unsigned) ndp16->dwSignature);
+ return false;
+ }
+ if (ndp16->wNextNdpIndex != 0) {
+ TU_LOG_DRV("(EE) cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
+ return false;
+ }
- if (ncm_interface.itf_data_alt) {
- if (!usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
- tud_network_recv_renew(); // prepare for incoming datagrams
- }
- if (!ncm_interface.report_pending) {
- ncm_report();
- }
- }
+ const ndp16_datagram_t *ndp16_datagram = (const ndp16_datagram_t *) (ntb->data + nth16->wNdpIndex + sizeof(ndp16_t));
+ int ndx = 0;
+ uint16_t max_ndx = (uint16_t) ((ndp16->wLength - sizeof(ndp16_t)) / sizeof(ndp16_datagram_t));
- tud_network_link_state_cb(ncm_interface.itf_data_alt);
- }
+ if (max_ndx > 2) { // number of datagrams in NTB > 1
+ TU_LOG_DRV("<< %d (%d)\n", max_ndx - 1, ntb->nth.wBlockLength);
+ }
+ if (ndp16_datagram[max_ndx - 1].wDatagramIndex != 0 || ndp16_datagram[max_ndx - 1].wDatagramLength != 0) {
+ TU_LOG_DRV(" max_ndx != 0\n");
+ return false;
+ }
+ while (ndp16_datagram[ndx].wDatagramIndex != 0 && ndp16_datagram[ndx].wDatagramLength != 0) {
+ TU_LOG_DRV(" << %d %d\n", ndp16_datagram[ndx].wDatagramIndex, ndp16_datagram[ndx].wDatagramLength);
+ if (ndp16_datagram[ndx].wDatagramIndex > len) {
+ TU_LOG_DRV("(EE) ill start of datagram[%d]: %d (%lu)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
+ return false;
+ }
+ if (ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength > len) {
+ TU_LOG_DRV("(EE) ill end of datagram[%d]: %d (%lu)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
+ return false;
+ }
+ ++ndx;
+ }
- tud_control_status(rhport, request);
- }
- break;
+ #if CFG_TUD_NCM_LOG_LEVEL >= 3
+ TU_LOG_BUF(3, ntb->data[i], len);
+ #endif
- // unsupported request
- default: return false;
- }
- break;
+ // -> ntb contains a valid packet structure
+ // ok... I did not check for garbage within the datagram indices...
+ return true;
+} // recv_validate_datagram
- case TUSB_REQ_TYPE_CLASS:
- TU_VERIFY (ncm_interface.itf_num == request->wIndex);
+/**
+ * Transfer the next (pending) datagram to the glue logic and return receive buffer if empty.
+ */
+static void recv_transfer_datagram_to_glue_logic(void) {
+ TU_LOG_DRV("recv_transfer_datagram_to_glue_logic()\n");
+
+ if (ncm_interface.recv_glue_ntb == NULL) {
+ ncm_interface.recv_glue_ntb = recv_get_next_ready_ntb();
+ TU_LOG_DRV(" new buffer for glue logic: %p\n", ncm_interface.recv_glue_ntb);
+ ncm_interface.recv_glue_ntb_datagram_ndx = 0;
+ }
- if (NCM_GET_NTB_PARAMETERS == request->bRequest)
- {
- tud_control_xfer(rhport, request, (void*)(uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
+ if (ncm_interface.recv_glue_ntb != NULL) {
+ const ndp16_datagram_t *ndp16_datagram = (ndp16_datagram_t *) (ncm_interface.recv_glue_ntb->data + ncm_interface.recv_glue_ntb->nth.wNdpIndex + sizeof(ndp16_t));
+
+ if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex == 0) {
+ TU_LOG_DRV("(EE) SOMETHING WENT WRONG 1\n");
+ } else if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength == 0) {
+ TU_LOG_DRV("(EE) SOMETHING WENT WRONG 2\n");
+ } else {
+ uint16_t datagramIndex = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex;
+ uint16_t datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength;
+
+ TU_LOG_DRV(" recv[%d] - %d %d\n", ncm_interface.recv_glue_ntb_datagram_ndx, datagramIndex, datagramLength);
+ if (tud_network_recv_cb(ncm_interface.recv_glue_ntb->data + datagramIndex, datagramLength)) {
+ // send datagram successfully to glue logic
+ TU_LOG_DRV(" OK\n");
+ datagramIndex = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramIndex;
+ datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramLength;
+
+ if (datagramIndex != 0 && datagramLength != 0) {
+ // -> next datagram
+ ++ncm_interface.recv_glue_ntb_datagram_ndx;
+ } else {
+ // end of datagrams reached
+ recv_put_ntb_into_free_list(ncm_interface.recv_glue_ntb);
+ ncm_interface.recv_glue_ntb = NULL;
+ }
}
+ }
+ }
+} // recv_transfer_datagram_to_glue_logic
- break;
+//-----------------------------------------------------------------------------
+//
+// all the tud_network_*() stuff (glue logic -> driver)
+//
- // unsupported request
- default: return false;
- }
+/**
+ * Check if the glue logic is allowed to call tud_network_xmit().
+ * This function also fetches a next buffer if required, so that tud_network_xmit() is ready for copy
+ * and transmission operation.
+ */
+bool tud_network_can_xmit(uint16_t size) {
+ TU_LOG_DRV("tud_network_can_xmit(%d)\n", size);
- return true;
-}
+ TU_ASSERT(size <= CFG_TUD_NCM_OUT_NTB_MAX_SIZE - (sizeof(nth16_t) + sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)), false);
-static void handle_incoming_datagram(uint32_t len)
-{
- uint32_t size = len;
+ if (xmit_requested_datagram_fits_into_current_ntb(size) || xmit_setup_next_glue_ntb()) {
+ // -> everything is fine
+ return true;
+ }
+ xmit_start_if_possible(ncm_interface.rhport);
+ TU_LOG_DRV("(II) tud_network_can_xmit: request blocked\n");// could happen if all xmit buffers are full (but should happen rarely)
+ return false;
+} // tud_network_can_xmit
+
+/**
+ * Put a datagram into a waiting NTB.
+ * If currently no transmission is started, then initiate transmission.
+ */
+void tud_network_xmit(void *ref, uint16_t arg) {
+ TU_LOG_DRV("tud_network_xmit(%p, %d)\n", ref, arg);
- if (len == 0) {
+ if (ncm_interface.xmit_glue_ntb == NULL) {
+ TU_LOG_DRV("(EE) tud_network_xmit: no buffer\n");// must not happen (really)
return;
}
- TU_ASSERT(size >= sizeof(nth16_t), );
+ xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
- const nth16_t *hdr = (const nth16_t *)receive_ntb;
- TU_ASSERT(hdr->dwSignature == NTH16_SIGNATURE, );
- TU_ASSERT(hdr->wNdpIndex >= sizeof(nth16_t) && (hdr->wNdpIndex + sizeof(ndp16_t)) <= len, );
+ // copy new datagram to the end of the current NTB
+ uint16_t size = tud_network_xmit_cb(ntb->data + ntb->nth.wBlockLength, ref, arg);
- const ndp16_t *ndp = (const ndp16_t *)(receive_ntb + hdr->wNdpIndex);
- TU_ASSERT(ndp->dwSignature == NDP16_SIGNATURE_NCM0 || ndp->dwSignature == NDP16_SIGNATURE_NCM1, );
- TU_ASSERT(hdr->wNdpIndex + ndp->wLength <= len, );
+ // correct NTB internals
+ ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramIndex = ntb->nth.wBlockLength;
+ ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramLength = size;
+ ncm_interface.xmit_glue_ntb_datagram_ndx += 1;
- int num_datagrams = (ndp->wLength - 12) / 4;
- ncm_interface.current_datagram_index = 0;
- ncm_interface.num_datagrams = 0;
- ncm_interface.ndp = ndp;
- for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++)
- {
- ncm_interface.num_datagrams++;
+ ntb->nth.wBlockLength += (uint16_t) (size + XMIT_ALIGN_OFFSET(size));
+
+ if (ntb->nth.wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+ TU_LOG_DRV("(EE) tud_network_xmit: buffer overflow\n"); // must not happen (really)
+ return;
}
+ xmit_start_if_possible(ncm_interface.rhport);
+} // tud_network_xmit
+
+/**
+ * Keep the receive logic busy and transfer pending packets to the glue logic.
+ */
+void tud_network_recv_renew(void) {
+ TU_LOG_DRV("tud_network_recv_renew()\n");
+
+ recv_transfer_datagram_to_glue_logic();
+ recv_try_to_start_new_reception(ncm_interface.rhport);
+} // tud_network_recv_renew
+
+/**
+ * Same as tud_network_recv_renew() but knows \a rhport
+ */
+void tud_network_recv_renew_r(uint8_t rhport) {
+ TU_LOG_DRV("tud_network_recv_renew_r(%d)\n", rhport);
+
+ ncm_interface.rhport = rhport;
tud_network_recv_renew();
+} // tud_network_recv_renew
+
+//-----------------------------------------------------------------------------
+//
+// all the netd_*() stuff (interface TinyUSB -> driver)
+//
+/**
+ * Initialize the driver data structures.
+ * Might be called several times.
+ */
+void netd_init(void) {
+ TU_LOG_DRV("netd_init()\n");
+
+ memset(&ncm_interface, 0, sizeof(ncm_interface));
+
+ for (int i = 0; i < XMIT_NTB_N; ++i) {
+ ncm_interface.xmit_free_ntb[i] = ncm_interface.xmit_ntb + i;
+ }
+ for (int i = 0; i < RECV_NTB_N; ++i) {
+ ncm_interface.recv_free_ntb[i] = ncm_interface.recv_ntb + i;
+ }
+} // netd_init
+
+/**
+ * Deinit driver
+ */
+bool netd_deinit(void) {
+ return true;
}
-bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+/**
+ * Resets the port.
+ * In this driver this is the same as netd_init()
+ */
+void netd_reset(uint8_t rhport) {
(void) rhport;
- (void) result;
- /* new datagram receive_ntb */
- if (ep_addr == ncm_interface.ep_out )
- {
- handle_incoming_datagram(xferred_bytes);
- }
+ netd_init();
+} // netd_reset
- /* data transmission finished */
- if (ep_addr == ncm_interface.ep_in )
- {
- if (ncm_interface.transferring) {
- ncm_interface.transferring = false;
- }
+/**
+ * Open the USB interface.
+ * - parse the USB descriptor \a TUD_CDC_NCM_DESCRIPTOR for itfnum and endpoints
+ * - a specific order of elements in the descriptor is tested.
+ *
+ * \note
+ * Actually all of the information could be read directly from \a itf_desc, because the
+ * structure and the values are well known. But we do it this way.
+ *
+ * \post
+ * - \a itf_num set
+ * - \a ep_notif, \a ep_in and \a ep_out are set
+ * - USB interface is open
+ */
+uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+ TU_ASSERT(ncm_interface.ep_notif == 0, 0);// assure that the interface is only opened once
- // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now
- if (ncm_interface.datagram_count && ncm_interface.itf_data_alt == 1) {
- ncm_start_tx();
- }
- }
+ ncm_interface.itf_num = itf_desc->bInterfaceNumber;// management interface
- if (ep_addr == ncm_interface.ep_notif )
- {
- ncm_interface.report_pending = false;
- ncm_report();
+ // skip the two first entries and the following TUSB_DESC_CS_INTERFACE entries
+ uint16_t drv_len = sizeof(tusb_desc_interface_t);
+ uint8_t const *p_desc = tu_desc_next(itf_desc);
+ while (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && drv_len <= max_len) {
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
}
- return true;
-}
+ // get notification endpoint
+ TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
+ TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0);
+ ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
-// poll network driver for its ability to accept another packet to transmit
-bool tud_network_can_xmit(uint16_t size)
-{
- TU_VERIFY(ncm_interface.itf_data_alt == 1);
+ // skip the following TUSB_DESC_INTERFACE entries (which must be TUSB_CLASS_CDC_DATA)
+ while (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && drv_len <= max_len) {
+ tusb_desc_interface_t const *data_itf_desc = (tusb_desc_interface_t const *) p_desc;
+ TU_ASSERT(data_itf_desc->bInterfaceClass == TUSB_CLASS_CDC_DATA, 0);
- if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
- TU_LOG_DRV("NTB full [by count]\r\n");
- return false;
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
}
- size_t next_datagram_offset = ncm_interface.next_datagram_offset;
- if (next_datagram_offset + size > ncm_interface.ntb_in_size) {
- TU_LOG_DRV("ntb full [by size]\r\n");
- return false;
+ // a TUSB_DESC_ENDPOINT (actually two) must follow, open these endpoints
+ TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
+ TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in));
+ drv_len += 2 * sizeof(tusb_desc_endpoint_t);
+
+ return drv_len;
+} // netd_open
+
+/**
+ * Handle TinyUSB requests to process transfer events.
+ */
+bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
+ (void) result;
+
+ if (ep_addr == ncm_interface.ep_out) {
+ // new NTB received
+ // - make the NTB valid
+ // - if ready transfer datagrams to the glue logic for further processing
+ // - if there is a free receive buffer, initiate reception
+ if (!recv_validate_datagram(ncm_interface.recv_tinyusb_ntb, xferred_bytes)) {
+ // verification failed: ignore NTB and return it to free
+ TU_LOG_DRV("(EE) VALIDATION FAILED. WHAT CAN WE DO IN THIS CASE?\n");
+ } else {
+ // packet ok -> put it into ready list
+ recv_put_ntb_into_ready_list(ncm_interface.recv_tinyusb_ntb);
+ }
+ ncm_interface.recv_tinyusb_ntb = NULL;
+ tud_network_recv_renew_r(rhport);
+ } else if (ep_addr == ncm_interface.ep_in) {
+ // transmission of an NTB finished
+ // - free the transmitted NTB buffer
+ // - insert ZLPs when necessary
+ // - if there is another transmit NTB waiting, try to start transmission
+ xmit_put_ntb_into_free_list(ncm_interface.xmit_tinyusb_ntb);
+ ncm_interface.xmit_tinyusb_ntb = NULL;
+ if (!xmit_insert_required_zlp(rhport, xferred_bytes)) {
+ xmit_start_if_possible(rhport);
+ }
+ } else if (ep_addr == ncm_interface.ep_notif) {
+ // next transfer on notification channel
+ notification_xmit(rhport, true);
}
return true;
-}
+} // netd_xfer_cb
-void tud_network_xmit(void *ref, uint16_t arg)
-{
- transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
- size_t next_datagram_offset = ncm_interface.next_datagram_offset;
+/**
+ * Respond to TinyUSB control requests.
+ * At startup transmission of notification packets are done here.
+ */
+bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
+ if (stage != CONTROL_STAGE_SETUP) {
+ return true;
+ }
- uint16_t size = tud_network_xmit_cb(ntb->data + next_datagram_offset, ref, arg);
+ switch (request->bmRequestType_bit.type) {
+ case TUSB_REQ_TYPE_STANDARD:
- ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = ncm_interface.next_datagram_offset;
- ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = size;
+ switch (request->bRequest) {
+ case TUSB_REQ_GET_INTERFACE: {
+ TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex, false);
- ncm_interface.datagram_count++;
- next_datagram_offset += size;
+ tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
+ } break;
- // round up so the next datagram is aligned correctly
- next_datagram_offset += (CFG_TUD_NCM_ALIGNMENT - 1);
- next_datagram_offset -= (next_datagram_offset % CFG_TUD_NCM_ALIGNMENT);
+ case TUSB_REQ_SET_INTERFACE: {
+ TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex && request->wValue < 2, false);
- ncm_interface.next_datagram_offset = next_datagram_offset;
+ ncm_interface.itf_data_alt = (uint8_t) request->wValue;
- ncm_start_tx();
-}
+ if (ncm_interface.itf_data_alt == 1) {
+ tud_network_recv_renew_r(rhport);
+ notification_xmit(rhport, false);
+ }
+ tud_control_status(rhport, request);
+ } break;
-#endif
+ // unsupported request
+ default:
+ return false;
+ }
+ break;
+
+ case TUSB_REQ_TYPE_CLASS:
+ TU_VERIFY(ncm_interface.itf_num == request->wIndex, false);
+ switch (request->bRequest) {
+ case NCM_GET_NTB_PARAMETERS: {
+ // transfer NTB parameters to host.
+ tud_control_xfer(rhport, request, (void *) (uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
+ } break;
+
+ // unsupported request
+ default:
+ return false;
+ }
+ break;
+ // unsupported request
+ default:
+ return false;
+ }
+
+ return true;
+} // netd_control_xfer_cb
+
+#endif // ( CFG_TUD_ENABLED && CFG_TUD_NCM )
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index da1a7b1e8e..4c9a92f2d0 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -28,14 +28,13 @@
#ifndef _TUSB_NET_DEVICE_H_
#define _TUSB_NET_DEVICE_H_
+#include
#include "class/cdc/cdc.h"
#if CFG_TUD_ECM_RNDIS && CFG_TUD_NCM
#error "Cannot enable both ECM_RNDIS and NCM network drivers"
#endif
-#include "ncm.h"
-
/* declared here, NOT in usb_descriptors.c, so that the driver can intelligently ZLP as needed */
#define CFG_TUD_NET_ENDPOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
@@ -44,21 +43,13 @@
#define CFG_TUD_NET_MTU 1514
#endif
-#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
-#define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200
-#endif
-
-#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
-#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200
-#endif
-#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
-#define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB 8
-#endif
+// Table 4.3 Data Class Interface Protocol Codes
+typedef enum
+{
+ NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK = 0x01
+} ncm_data_interface_protocol_code_t;
-#ifndef CFG_TUD_NCM_ALIGNMENT
-#define CFG_TUD_NCM_ALIGNMENT 4
-#endif
#ifdef __cplusplus
extern "C" {
@@ -96,11 +87,6 @@ void tud_network_init_cb(void);
// TODO removed later since it is not part of tinyusb stack
extern uint8_t tud_network_mac_address[6];
-//------------- NCM -------------//
-
-// callback to client providing optional indication of internal state of network driver
-void tud_network_link_state_cb(bool state);
-
//--------------------------------------------------------------------+
// INTERNAL USBD-CLASS DRIVER API
//--------------------------------------------------------------------+
diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h
index 090ab3c4ab..327de087c7 100644
--- a/src/class/usbtmc/usbtmc.h
+++ b/src/class/usbtmc/usbtmc.h
@@ -183,6 +183,23 @@ typedef enum {
} usmtmc_request_type_enum;
+typedef enum {
+ // The last and first valid bNotify1 for use by the USBTMC class specification.
+ USBTMC_bNOTIFY1_USBTMC_FIRST = 0x00,
+ USBTMC_bNOTIFY1_USBTMC_LAST = 0x3F,
+
+ // The last and first valid bNotify1 for use by vendors.
+ USBTMC_bNOTIFY1_VENDOR_SPECIFIC_FIRST = 0x40,
+ USBTMC_bNOTIFY1_VENDOR_SPECIFIC_LAST = 0x7F,
+
+ // The last and first valid bNotify1 for use by USBTMC subclass specifications.
+ USBTMC_bNOTIFY1_SUBCLASS_FIRST = 0x80,
+ USBTMC_bNOTIFY1_SUBCLASS_LAST = 0xFF,
+
+ // From the USB488 Subclass Specification, Section 3.4.
+ USB488_bNOTIFY1_SRQ = 0x81,
+} usbtmc_int_in_payload_format;
+
typedef enum {
USBTMC_STATUS_SUCCESS = 0x01,
USBTMC_STATUS_PENDING = 0x02,
@@ -303,6 +320,14 @@ typedef struct TU_ATTR_PACKED
TU_VERIFY_STATIC(sizeof(usbtmc_read_stb_rsp_488_t) == 3u, "struct wrong length");
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bNotify1; // Must be USB488_bNOTIFY1_SRQ
+ uint8_t StatusByte;
+} usbtmc_srq_interrupt_488_t;
+
+TU_VERIFY_STATIC(sizeof(usbtmc_srq_interrupt_488_t) == 2u, "struct wrong length");
+
typedef struct TU_ATTR_PACKED
{
struct TU_ATTR_PACKED
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index f6cddfbd7d..129ff465de 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -86,6 +86,11 @@ tu_static char logMsg[150];
// imposes a minimum buffer size of 32 bytes.
#define USBTMCD_BUFFER_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+// Interrupt endpoint buffer size, default to 2 bytes as USB488 specification.
+#ifndef CFG_TUD_USBTMC_INT_EP_SIZE
+#define CFG_TUD_USBTMC_INT_EP_SIZE 2
+#endif
+
/*
* The state machine does not allow simultaneous reading and writing. This is
* consistent with USBTMC.
@@ -124,13 +129,15 @@ typedef struct
uint8_t ep_bulk_in;
uint8_t ep_bulk_out;
uint8_t ep_int_in;
+ uint32_t ep_bulk_in_wMaxPacketSize;
+ uint32_t ep_bulk_out_wMaxPacketSize;
// IN buffer is only used for first packet, not the remainder
// in order to deal with prepending header
CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_in_buf[USBTMCD_BUFFER_SIZE];
- uint32_t ep_bulk_in_wMaxPacketSize;
// OUT buffer receives one packet at a time
CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_out_buf[USBTMCD_BUFFER_SIZE];
- uint32_t ep_bulk_out_wMaxPacketSize;
+ // Buffer int msg to ensure alignment and placement correctness
+ CFG_TUSB_MEM_ALIGN uint8_t ep_int_in_buf[CFG_TUD_USBTMC_INT_EP_SIZE];
uint32_t transfer_size_remaining; // also used for requested length for bulk IN.
uint32_t transfer_size_sent; // To keep track of data bytes that have been queued in FIFO (not header bytes)
@@ -240,6 +247,19 @@ bool tud_usbtmc_transmit_dev_msg_data(
return true;
}
+bool tud_usbtmc_transmit_notification_data(const void * data, size_t len)
+{
+#ifndef NDEBUG
+ TU_ASSERT(len > 0);
+ TU_ASSERT(usbtmc_state.ep_int_in != 0);
+#endif
+ TU_VERIFY(usbd_edpt_busy(usbtmc_state.rhport, usbtmc_state.ep_int_in));
+
+ TU_VERIFY(tu_memcpy_s(usbtmc_state.ep_int_in_buf, sizeof(usbtmc_state.ep_int_in_buf), data, len) == 0);
+ TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, usbtmc_state.ep_int_in_buf, (uint16_t)len));
+ return true;
+}
+
void usbtmcd_init_cb(void)
{
usbtmc_state.capabilities = tud_usbtmc_get_capabilities_cb();
@@ -547,9 +567,10 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
case STATE_TX_INITIATED:
if(usbtmc_state.transfer_size_remaining >= sizeof(usbtmc_state.ep_bulk_in_buf))
{
- // FIXME! This removes const below!
+ // Copy buffer to ensure alignment correctness
+ memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf));
TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in,
- (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf)));
+ usbtmc_state.ep_bulk_in_buf, sizeof(usbtmc_state.ep_bulk_in_buf)));
usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf);
usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf);
usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf);
@@ -585,7 +606,9 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
}
}
else if (ep_addr == usbtmc_state.ep_int_in) {
- // Good?
+ if (tud_usbtmc_notification_complete_cb) {
+ TU_VERIFY(tud_usbtmc_notification_complete_cb());
+ }
return true;
}
return false;
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index 3299a36eb8..b85ef12b59 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -73,6 +73,10 @@ bool tud_usbtmc_check_abort_bulk_in_cb(usbtmc_check_abort_bulk_rsp_t *rsp);
bool tud_usbtmc_check_abort_bulk_out_cb(usbtmc_check_abort_bulk_rsp_t *rsp);
bool tud_usbtmc_check_clear_cb(usbtmc_get_clear_status_rsp_t *rsp);
+// The interrupt-IN endpoint buffer was transmitted to the host. Use
+// tud_usbtmc_transmit_notification_data to send another notification.
+TU_ATTR_WEAK bool tud_usbtmc_notification_complete_cb(void);
+
// Indicator pulse should be 0.5 to 1.0 seconds long
TU_ATTR_WEAK bool tud_usbtmc_indicator_pulse_cb(tusb_control_request_t const * msg, uint8_t *tmcResult);
@@ -82,17 +86,23 @@ TU_ATTR_WEAK bool tud_usbtmc_msg_trigger_cb(usbtmc_msg_generic_t* msg);
//TU_ATTR_WEAK bool tud_usbtmc_app_go_to_local_cb();
#endif
-/*******************************************
- * Called from app
- *
- * We keep a reference to the buffer, so it MUST not change until the app is
- * notified that the transfer is complete.
- ******************************************/
-
+// Called from app
+//
+// We keep a reference to the buffer, so it MUST not change until the app is
+// notified that the transfer is complete.
bool tud_usbtmc_transmit_dev_msg_data(
const void * data, size_t len,
bool endOfMessage, bool usingTermChar);
+// Buffers a notification to be sent to the host. The data starts
+// with the bNotify1 field, see the USBTMC Specification, Table 13.
+//
+// If the previous notification data has not yet been sent, this
+// returns false.
+//
+// Requires an interrupt endpoint in the interface.
+bool tud_usbtmc_transmit_notification_data(const void * data, size_t len);
+
bool tud_usbtmc_start_bus_read(void);
@@ -105,9 +115,4 @@ void usbtmcd_reset_cb(uint8_t rhport);
bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
-/************************************************************
- * USBTMC Descriptor Templates
- *************************************************************/
-
-
#endif /* CLASS_USBTMC_USBTMC_DEVICE_H_ */
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index e87ce39971..ca04d9a017 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -36,134 +36,103 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
uint8_t itf_num;
- uint8_t ep_in;
- uint8_t ep_out;
/*------------- From this point, data is not cleared by bus reset -------------*/
- tu_fifo_t rx_ff;
- tu_fifo_t tx_ff;
+ // Endpoint Transfer buffer
+ CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_VENDOR_EPSIZE];
+ CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
- uint8_t rx_ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE];
- uint8_t tx_ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE];
+ struct {
+ tu_edpt_stream_t stream;
+ #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+ uint8_t ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE];
+ #endif
+ }tx;
- OSAL_MUTEX_DEF(rx_ff_mutex);
- OSAL_MUTEX_DEF(tx_ff_mutex);
+ struct {
+ tu_edpt_stream_t stream;
+ #if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+ uint8_t ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE];
+ #endif
+ } rx;
- // Endpoint Transfer buffer
- CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_VENDOR_EPSIZE];
- CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
} vendord_interface_t;
-CFG_TUD_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
+CFG_TUD_MEM_SECTION static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
-#define ITF_MEM_RESET_SIZE offsetof(vendord_interface_t, rx_ff)
+#define ITF_MEM_RESET_SIZE (offsetof(vendord_interface_t, itf_num) + sizeof(((vendord_interface_t *)0)->itf_num))
+//--------------------------------------------------------------------
+// Application API
+//--------------------------------------------------------------------
-bool tud_vendor_n_mounted (uint8_t itf)
-{
- return _vendord_itf[itf].ep_in && _vendord_itf[itf].ep_out;
-}
-
-uint32_t tud_vendor_n_available (uint8_t itf)
-{
- return tu_fifo_count(&_vendord_itf[itf].rx_ff);
-}
-
-bool tud_vendor_n_peek(uint8_t itf, uint8_t* u8)
-{
- return tu_fifo_peek(&_vendord_itf[itf].rx_ff, u8);
+bool tud_vendor_n_mounted(uint8_t itf) {
+ TU_VERIFY(itf < CFG_TUD_VENDOR);
+ vendord_interface_t* p_itf = &_vendord_itf[itf];
+ return p_itf->rx.stream.ep_addr || p_itf->tx.stream.ep_addr;
}
//--------------------------------------------------------------------+
// Read API
//--------------------------------------------------------------------+
-static void _prep_out_transaction (vendord_interface_t* p_itf)
-{
- uint8_t const rhport = 0;
+uint32_t tud_vendor_n_available(uint8_t itf) {
+ TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
+ vendord_interface_t* p_itf = &_vendord_itf[itf];
- // claim endpoint
- TU_VERIFY(usbd_edpt_claim(rhport, p_itf->ep_out), );
+ return tu_edpt_stream_read_available(&p_itf->rx.stream);
+}
- // Prepare for incoming data but only allow what we can store in the ring buffer.
- uint16_t max_read = tu_fifo_remaining(&p_itf->rx_ff);
- if ( max_read >= CFG_TUD_VENDOR_EPSIZE )
- {
- usbd_edpt_xfer(rhport, p_itf->ep_out, p_itf->epout_buf, CFG_TUD_VENDOR_EPSIZE);
- }
- else
- {
- // Release endpoint since we don't make any transfer
- usbd_edpt_release(rhport, p_itf->ep_out);
- }
+bool tud_vendor_n_peek(uint8_t itf, uint8_t* u8) {
+ TU_VERIFY(itf < CFG_TUD_VENDOR);
+ vendord_interface_t* p_itf = &_vendord_itf[itf];
+
+ return tu_edpt_stream_peek(&p_itf->rx.stream, u8);
}
-uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize)
-{
+uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize) {
+ TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
vendord_interface_t* p_itf = &_vendord_itf[itf];
- uint32_t num_read = tu_fifo_read_n(&p_itf->rx_ff, buffer, (uint16_t) bufsize);
- _prep_out_transaction(p_itf);
- return num_read;
+ uint8_t const rhport = 0;
+
+ return tu_edpt_stream_read(rhport, &p_itf->rx.stream, buffer, bufsize);
}
-void tud_vendor_n_read_flush (uint8_t itf)
-{
+void tud_vendor_n_read_flush (uint8_t itf) {
+ TU_VERIFY(itf < CFG_TUD_VENDOR, );
vendord_interface_t* p_itf = &_vendord_itf[itf];
- tu_fifo_clear(&p_itf->rx_ff);
- _prep_out_transaction(p_itf);
+ uint8_t const rhport = 0;
+
+ tu_edpt_stream_clear(&p_itf->rx.stream);
+ tu_edpt_stream_read_xfer(rhport, &p_itf->rx.stream);
}
//--------------------------------------------------------------------+
// Write API
//--------------------------------------------------------------------+
-uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize)
-{
+uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize) {
+ TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
vendord_interface_t* p_itf = &_vendord_itf[itf];
- uint16_t ret = tu_fifo_write_n(&p_itf->tx_ff, buffer, (uint16_t) bufsize);
+ uint8_t const rhport = 0;
- // flush if queue more than packet size
- if (tu_fifo_count(&p_itf->tx_ff) >= CFG_TUD_VENDOR_EPSIZE) {
- tud_vendor_n_write_flush(itf);
- }
- return ret;
+ return tu_edpt_stream_write(rhport, &p_itf->tx.stream, buffer, (uint16_t) bufsize);
}
-uint32_t tud_vendor_n_write_flush (uint8_t itf)
-{
+uint32_t tud_vendor_n_write_flush (uint8_t itf) {
+ TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
vendord_interface_t* p_itf = &_vendord_itf[itf];
-
- // Skip if usb is not ready yet
- TU_VERIFY( tud_ready(), 0 );
-
- // No data to send
- if ( !tu_fifo_count(&p_itf->tx_ff) ) return 0;
-
uint8_t const rhport = 0;
- // Claim the endpoint
- TU_VERIFY( usbd_edpt_claim(rhport, p_itf->ep_in), 0 );
-
- // Pull data from FIFO
- uint16_t const count = tu_fifo_read_n(&p_itf->tx_ff, p_itf->epin_buf, sizeof(p_itf->epin_buf));
-
- if ( count )
- {
- TU_ASSERT( usbd_edpt_xfer(rhport, p_itf->ep_in, p_itf->epin_buf, count), 0 );
- return count;
- }else
- {
- // Release endpoint since we don't make any transfer
- // Note: data is dropped if terminal is not connected
- usbd_edpt_release(rhport, p_itf->ep_in);
- return 0;
- }
+ return tu_edpt_stream_write_xfer(rhport, &p_itf->tx.stream);
}
-uint32_t tud_vendor_n_write_available (uint8_t itf)
-{
- return tu_fifo_remaining(&_vendord_itf[itf].tx_ff);
+uint32_t tud_vendor_n_write_available (uint8_t itf) {
+ TU_VERIFY(itf < CFG_TUD_VENDOR, 0);
+ vendord_interface_t* p_itf = &_vendord_itf[itf];
+ uint8_t const rhport = 0;
+
+ return tu_edpt_stream_write_available(rhport, &p_itf->tx.stream);
}
//--------------------------------------------------------------------+
@@ -175,70 +144,61 @@ void vendord_init(void) {
for(uint8_t i=0; irx_ff, p_itf->rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, 1, false);
- tu_fifo_config(&p_itf->tx_ff, p_itf->tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, 1, false);
-
- #if OSAL_MUTEX_REQUIRED
- osal_mutex_t mutex_rd = osal_mutex_create(&p_itf->rx_ff_mutex);
- osal_mutex_t mutex_wr = osal_mutex_create(&p_itf->tx_ff_mutex);
- TU_ASSERT(mutex_rd && mutex_wr,);
-
- tu_fifo_config_mutex(&p_itf->rx_ff, NULL, mutex_rd);
- tu_fifo_config_mutex(&p_itf->tx_ff, mutex_wr, NULL);
- #endif
+ uint8_t* rx_ff_buf =
+ #if CFG_TUD_VENDOR_RX_BUFSIZE > 0
+ p_itf->rx.ff_buf;
+ #else
+ NULL;
+ #endif
+
+ tu_edpt_stream_init(&p_itf->rx.stream, false, false, false,
+ rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE,
+ p_itf->epout_buf, CFG_TUD_VENDOR_EPSIZE);
+
+ uint8_t* tx_ff_buf =
+ #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+ p_itf->tx.ff_buf;
+ #else
+ NULL;
+ #endif
+
+ tu_edpt_stream_init(&p_itf->tx.stream, false, true, false,
+ tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE,
+ p_itf->epin_buf, CFG_TUD_VENDOR_EPSIZE);
}
}
bool vendord_deinit(void) {
- #if OSAL_MUTEX_REQUIRED
for(uint8_t i=0; irx_ff.mutex_rd;
- osal_mutex_t mutex_wr = p_itf->tx_ff.mutex_wr;
-
- if (mutex_rd) {
- osal_mutex_delete(mutex_rd);
- tu_fifo_config_mutex(&p_itf->rx_ff, NULL, NULL);
- }
-
- if (mutex_wr) {
- osal_mutex_delete(mutex_wr);
- tu_fifo_config_mutex(&p_itf->tx_ff, NULL, NULL);
- }
+ tu_edpt_stream_deinit(&p_itf->rx.stream);
+ tu_edpt_stream_deinit(&p_itf->tx.stream);
}
- #endif
-
return true;
}
-void vendord_reset(uint8_t rhport)
-{
+void vendord_reset(uint8_t rhport) {
(void) rhport;
- for(uint8_t i=0; irx_ff);
- tu_fifo_clear(&p_itf->tx_ff);
+ tu_edpt_stream_clear(&p_itf->rx.stream);
+ tu_edpt_stream_clear(&p_itf->tx.stream);
+ tu_edpt_stream_close(&p_itf->rx.stream);
+ tu_edpt_stream_close(&p_itf->tx.stream);
}
}
-uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
-{
+uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len) {
TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0);
-
- uint8_t const * p_desc = tu_desc_next(desc_itf);
- uint8_t const * desc_end = p_desc + max_len;
+ const uint8_t* p_desc = tu_desc_next(desc_itf);
+ const uint8_t* desc_end = p_desc + max_len;
// Find available interface
vendord_interface_t* p_vendor = NULL;
- for(uint8_t i=0; iitf_num = desc_itf->bInterfaceNumber;
- if (desc_itf->bNumEndpoints)
- {
+ uint8_t found_ep = 0;
+ while (found_ep < desc_itf->bNumEndpoints) {
// skip non-endpoint descriptors
- while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (p_desc < desc_end) )
- {
+ while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (p_desc < desc_end) ) {
p_desc = tu_desc_next(p_desc);
}
+ if (p_desc >= desc_end) {
+ break;
+ }
- // Open endpoint pair with usbd helper
- TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0);
-
- p_desc += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+ const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc;
+ TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
+ found_ep++;
- // Prepare for incoming data
- if ( p_vendor->ep_out )
- {
- _prep_out_transaction(p_vendor);
+ if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+ tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep);
+ tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf));
+ } else {
+ tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep);
+ TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data
}
- if ( p_vendor->ep_in ) tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf));
+ p_desc = tu_desc_next(p_desc);
}
return (uint16_t) ((uintptr_t) p_desc - (uintptr_t) desc_itf);
}
-bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
- (void) rhport;
+bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
(void) result;
uint8_t itf = 0;
vendord_interface_t* p_itf = _vendord_itf;
- for ( ; ; itf++, p_itf++)
- {
- if (itf >= TU_ARRAY_SIZE(_vendord_itf)) return false;
-
- if ( ( ep_addr == p_itf->ep_out ) || ( ep_addr == p_itf->ep_in ) ) break;
+ for ( ; ; itf++, p_itf++) {
+ if (itf >= CFG_TUD_VENDOR) return false;
+ if ((ep_addr == p_itf->rx.stream.ep_addr) || (ep_addr == p_itf->tx.stream.ep_addr)) break;
}
- if ( ep_addr == p_itf->ep_out )
- {
- // Receive new data
- tu_fifo_write_n(&p_itf->rx_ff, p_itf->epout_buf, (uint16_t) xferred_bytes);
+ if ( ep_addr == p_itf->rx.stream.ep_addr ) {
+ // Received new data: put into stream's fifo
+ tu_edpt_stream_read_xfer_complete(&p_itf->rx.stream, xferred_bytes);
// Invoked callback if any
- if (tud_vendor_rx_cb) tud_vendor_rx_cb(itf);
+ if (tud_vendor_rx_cb) {
+ tud_vendor_rx_cb(itf, p_itf->epout_buf, (uint16_t) xferred_bytes);
+ }
- _prep_out_transaction(p_itf);
- }
- else if ( ep_addr == p_itf->ep_in )
- {
- if (tud_vendor_tx_cb) tud_vendor_tx_cb(itf, (uint16_t) xferred_bytes);
- // Send complete, try to send more if possible
- tud_vendor_n_write_flush(itf);
+ tu_edpt_stream_read_xfer(rhport, &p_itf->rx.stream);
+ } else if ( ep_addr == p_itf->tx.stream.ep_addr ) {
+ // Send complete
+ if (tud_vendor_tx_cb) {
+ tud_vendor_tx_cb(itf, (uint16_t) xferred_bytes);
+ }
+
+ #if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+ // try to send more if possible
+ if ( 0 == tu_edpt_stream_write_xfer(rhport, &p_itf->tx.stream) ) {
+ // If there is no data left, a ZLP should be sent if xferred_bytes is multiple of EP Packet size and not zero
+ tu_edpt_stream_write_zlp_if_needed(rhport, &p_itf->tx.stream, xferred_bytes);
+ }
+ #endif
}
return true;
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index cd69ec7c65..149ae2d564 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -33,15 +33,24 @@
#define CFG_TUD_VENDOR_EPSIZE 64
#endif
+// RX FIFO can be disabled by setting this value to 0
+#ifndef CFG_TUD_VENDOR_RX_BUFSIZE
+#define CFG_TUD_VENDOR_RX_BUFSIZE 64
+#endif
+
+// TX FIFO can be disabled by setting this value to 0
+#ifndef CFG_TUD_VENDOR_TX_BUFSIZE
+#define CFG_TUD_VENDOR_TX_BUFSIZE 64
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
//--------------------------------------------------------------------+
-// Application API (Multiple Interfaces)
+// Application API (Multiple Interfaces) i.e CFG_TUD_VENDOR > 1
//--------------------------------------------------------------------+
bool tud_vendor_n_mounted (uint8_t itf);
-
uint32_t tud_vendor_n_available (uint8_t itf);
uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize);
bool tud_vendor_n_peek (uint8_t itf, uint8_t* ui8);
@@ -51,89 +60,73 @@ uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t
uint32_t tud_vendor_n_write_flush (uint8_t itf);
uint32_t tud_vendor_n_write_available (uint8_t itf);
-static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str);
// backward compatible
#define tud_vendor_n_flush(itf) tud_vendor_n_write_flush(itf)
//--------------------------------------------------------------------+
-// Application API (Single Port)
+// Application API (Single Port) i.e CFG_TUD_VENDOR = 1
//--------------------------------------------------------------------+
-static inline bool tud_vendor_mounted (void);
-static inline uint32_t tud_vendor_available (void);
-static inline uint32_t tud_vendor_read (void* buffer, uint32_t bufsize);
-static inline bool tud_vendor_peek (uint8_t* ui8);
-static inline void tud_vendor_read_flush (void);
-static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize);
-static inline uint32_t tud_vendor_write_str (char const* str);
-static inline uint32_t tud_vendor_write_available (void);
-static inline uint32_t tud_vendor_write_flush (void);
-// backward compatible
-#define tud_vendor_flush() tud_vendor_write_flush()
-
-//--------------------------------------------------------------------+
-// Application Callback API (weak is optional)
-//--------------------------------------------------------------------+
-
-// Invoked when received new data
-TU_ATTR_WEAK void tud_vendor_rx_cb(uint8_t itf);
-// Invoked when last rx transfer finished
-TU_ATTR_WEAK void tud_vendor_tx_cb(uint8_t itf, uint32_t sent_bytes);
-
-//--------------------------------------------------------------------+
-// Inline Functions
-//--------------------------------------------------------------------+
-
-static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str)
-{
- return tud_vendor_n_write(itf, str, strlen(str));
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_n_write_str(uint8_t itf, char const* str) {
+ return tud_vendor_n_write(itf, str, strlen(str));
}
-static inline bool tud_vendor_mounted (void)
-{
- return tud_vendor_n_mounted(0);
+TU_ATTR_ALWAYS_INLINE static inline bool tud_vendor_mounted(void) {
+ return tud_vendor_n_mounted(0);
}
-static inline uint32_t tud_vendor_available (void)
-{
- return tud_vendor_n_available(0);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_available(void) {
+ return tud_vendor_n_available(0);
}
-static inline uint32_t tud_vendor_read (void* buffer, uint32_t bufsize)
-{
- return tud_vendor_n_read(0, buffer, bufsize);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_read(void* buffer, uint32_t bufsize) {
+ return tud_vendor_n_read(0, buffer, bufsize);
}
-static inline bool tud_vendor_peek (uint8_t* ui8)
-{
- return tud_vendor_n_peek(0, ui8);
+TU_ATTR_ALWAYS_INLINE static inline bool tud_vendor_peek(uint8_t* ui8) {
+ return tud_vendor_n_peek(0, ui8);
}
-static inline void tud_vendor_read_flush(void)
-{
- tud_vendor_n_read_flush(0);
+TU_ATTR_ALWAYS_INLINE static inline void tud_vendor_read_flush(void) {
+ tud_vendor_n_read_flush(0);
}
-static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize)
-{
- return tud_vendor_n_write(0, buffer, bufsize);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write(void const* buffer, uint32_t bufsize) {
+ return tud_vendor_n_write(0, buffer, bufsize);
}
-static inline uint32_t tud_vendor_write_flush (void)
-{
- return tud_vendor_n_write_flush(0);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_str(char const* str) {
+ return tud_vendor_n_write_str(0, str);
}
-static inline uint32_t tud_vendor_write_str (char const* str)
-{
- return tud_vendor_n_write_str(0, str);
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_flush(void) {
+ return tud_vendor_n_write_flush(0);
}
-static inline uint32_t tud_vendor_write_available (void)
-{
- return tud_vendor_n_write_available(0);
+#if CFG_TUD_VENDOR_TX_BUFSIZE > 0
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tud_vendor_write_available(void) {
+ return tud_vendor_n_write_available(0);
}
+#endif
+
+// backward compatible
+#define tud_vendor_flush() tud_vendor_write_flush()
+
+//--------------------------------------------------------------------+
+// Application Callback API (weak is optional)
+//--------------------------------------------------------------------+
+
+// Invoked when received new data
+TU_ATTR_WEAK void tud_vendor_rx_cb(uint8_t itf, uint8_t const* buffer, uint16_t bufsize);
+// Invoked when last rx transfer finished
+TU_ATTR_WEAK void tud_vendor_tx_cb(uint8_t itf, uint32_t sent_bytes);
+
+//--------------------------------------------------------------------+
+// Inline Functions
+//--------------------------------------------------------------------+
+
//--------------------------------------------------------------------+
// Internal Class Driver API
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 4218835aab..70dbb5b9e9 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -398,7 +398,7 @@ static inline void const *_find_desc_format(void const *beg, void const *end, ui
if ((fmt == VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED ||
fmt == VIDEO_CS_ITF_VS_FORMAT_MJPEG ||
fmt == VIDEO_CS_ITF_VS_FORMAT_DV ||
- fmt == VIDEO_CS_ITF_VS_FRAME_FRAME_BASED) &&
+ fmt == VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED) &&
fmtnum == p[3]) {
return cur;
}
@@ -707,7 +707,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
/* The first descriptor is a video control interface descriptor. */
uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
- TU_LOG_DRV(" cur %d\r\n", cur - beg);
+ TU_LOG_DRV(" cur %" PRId32 "\r\n", (int32_t) (cur - beg));
TU_VERIFY(cur < end);
tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 0d4082c031..d3e0cf888b 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -79,7 +79,7 @@
//--------------------------------------------------------------------+
// Optional API implemented by application if needed
-// TODO move to a more ovious place/file
+// TODO move to a more obvious place/file
//--------------------------------------------------------------------+
// flush data cache
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 0d5570b1c3..646c22b295 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -118,6 +118,14 @@
#define _TU_ARGS_APPLY_7(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7) _X(_a1) _s _TU_ARGS_APPLY_6(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7)
#define _TU_ARGS_APPLY_8(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7, _a8) _X(_a1) _s _TU_ARGS_APPLY_7(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7, _a8)
+//--------------------------------------------------------------------+
+// Macro for function default arguments
+//--------------------------------------------------------------------+
+#define TU_GET_3RD_ARG(arg1, arg2, arg3, ...) arg3
+
+// function expand with number of arguments
+#define TU_FUNC_OPTIONAL_ARG(func, ...) TU_XSTRCAT(func##_arg, TU_ARGS_NUM(__VA_ARGS__))(__VA_ARGS__)
+
//--------------------------------------------------------------------+
// Compiler porting with Attribute and Endian
//--------------------------------------------------------------------+
@@ -128,6 +136,7 @@
#define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name)))
#define TU_ATTR_PACKED __attribute__ ((packed))
#define TU_ATTR_WEAK __attribute__ ((weak))
+ // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))
#ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug
#define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline))
#endif
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 76696396b6..5f2dcabad5 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -62,7 +62,9 @@ TU_ATTR_ALWAYS_INLINE static inline void _ff_unlock(osal_mutex_t mutex)
typedef enum
{
TU_FIFO_COPY_INC, ///< Copy from/to an increasing source/destination address - default mode
+#ifdef TUP_MEM_CONST_ADDR
TU_FIFO_COPY_CST_FULL_WORDS, ///< Copy from/to a constant source/destination address - required for e.g. STM32 to write into USB hardware FIFO
+#endif
} tu_fifo_copy_mode_t;
bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable)
@@ -92,6 +94,7 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
// Pull & Push
//--------------------------------------------------------------------+
+#ifdef TUP_MEM_CONST_ADDR
// Intended to be used to read from hardware USB FIFO in e.g. STM32 where all data is read from a constant address
// Code adapted from dcd_synopsys.c
// TODO generalize with configurable 1 byte or 4 byte each read
@@ -140,6 +143,7 @@ static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t
*reg_tx = tmp32;
}
}
+#endif
// send one item to fifo WITHOUT updating write pointer
static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel)
@@ -179,7 +183,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
memcpy(f->buffer, ((uint8_t const*) app_buf) + lin_bytes, wrap_bytes);
}
break;
-
+#ifdef TUP_MEM_CONST_ADDR
case TU_FIFO_COPY_CST_FULL_WORDS:
// Intended for hardware buffers from which it can be read word by word only
if(n <= lin_count)
@@ -224,6 +228,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes);
}
break;
+#endif
default: break;
}
}
@@ -265,7 +270,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rd_ptr,
memcpy((uint8_t*) app_buf + lin_bytes, f->buffer, wrap_bytes);
}
break;
-
+#ifdef TUP_MEM_CONST_ADDR
case TU_FIFO_COPY_CST_FULL_WORDS:
if ( n <= lin_count )
{
@@ -311,7 +316,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rd_ptr,
if (wrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, wrap_bytes);
}
break;
-
+#endif
default: break;
}
}
@@ -727,10 +732,29 @@ uint16_t tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n)
return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_INC);
}
+#ifdef TUP_MEM_CONST_ADDR
+/******************************************************************************/
+/*!
+ @brief This function will read n elements from the array index specified by
+ the read pointer and increment the read index.
+ This function checks for an overflow and corrects read pointer if required.
+ The dest address will not be incremented which is useful for writing to registers.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] buffer
+ The pointer to data location
+ @param[in] n
+ Number of element that buffer can afford
+
+ @returns number of items read from the FIFO
+ */
+/******************************************************************************/
uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t* f, void * buffer, uint16_t n)
{
return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_CST_FULL_WORDS);
}
+#endif
/******************************************************************************/
/*!
@@ -839,6 +863,7 @@ uint16_t tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n)
return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_INC);
}
+#ifdef TUP_MEM_CONST_ADDR
/******************************************************************************/
/*!
@brief This function will write n elements into the array index specified by
@@ -858,6 +883,7 @@ uint16_t tu_fifo_write_n_const_addr_full_words(tu_fifo_t* f, const void * data,
{
return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_CST_FULL_WORDS);
}
+#endif
/******************************************************************************/
/*!
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 2d9f5e6671..879acda4fd 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -145,22 +145,26 @@ bool tu_fifo_clear(tu_fifo_t *f);
bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable);
#if OSAL_MUTEX_REQUIRED
- TU_ATTR_ALWAYS_INLINE static inline
- void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) {
- f->mutex_wr = wr_mutex;
- f->mutex_rd = rd_mutex;
- }
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) {
+ f->mutex_wr = wr_mutex;
+ f->mutex_rd = rd_mutex;
+}
#else
- #define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex)
+#define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex)
#endif
-bool tu_fifo_write (tu_fifo_t* f, void const * p_data);
-uint16_t tu_fifo_write_n (tu_fifo_t* f, void const * p_data, uint16_t n);
+bool tu_fifo_write (tu_fifo_t* f, void const * data);
+uint16_t tu_fifo_write_n (tu_fifo_t* f, void const * data, uint16_t n);
+#ifdef TUP_MEM_CONST_ADDR
uint16_t tu_fifo_write_n_const_addr_full_words (tu_fifo_t* f, const void * data, uint16_t n);
+#endif
-bool tu_fifo_read (tu_fifo_t* f, void * p_buffer);
-uint16_t tu_fifo_read_n (tu_fifo_t* f, void * p_buffer, uint16_t n);
+bool tu_fifo_read (tu_fifo_t* f, void * buffer);
+uint16_t tu_fifo_read_n (tu_fifo_t* f, void * buffer, uint16_t n);
+#ifdef TUP_MEM_CONST_ADDR
uint16_t tu_fifo_read_n_const_addr_full_words (tu_fifo_t* f, void * buffer, uint16_t n);
+#endif
bool tu_fifo_peek (tu_fifo_t* f, void * p_buffer);
uint16_t tu_fifo_peek_n (tu_fifo_t* f, void * p_buffer, uint16_t n);
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 0ae2573cd3..c77afecad0 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -138,21 +138,21 @@
#elif TU_CHECK_MCU(OPT_MCU_SAMG)
#define TUP_DCD_ENDPOINT_MAX 6
- #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+ #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
#elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
#define TUP_DCD_ENDPOINT_MAX 10
#define TUP_RHPORT_HIGHSPEED 1
- #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+ #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
#elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
#define TUP_DCD_ENDPOINT_MAX 8
- #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+ #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
#elif TU_CHECK_MCU(OPT_MCU_PIC32MX, OPT_MCU_PIC32MM, OPT_MCU_PIC32MK) || \
TU_CHECK_MCU(OPT_MCU_PIC24, OPT_MCU_DSPIC33)
#define TUP_DCD_ENDPOINT_MAX 16
- #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+ #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
//--------------------------------------------------------------------+
// ST
@@ -269,16 +269,23 @@
#define TUP_DCD_ENDPOINT_MAX 8
#elif TU_CHECK_MCU(OPT_MCU_STM32U5)
- #define TUP_USBIP_DWC2
- #define TUP_USBIP_DWC2_STM32
+ #if defined (STM32U535xx) || defined (STM32U545xx)
+ #define TUP_USBIP_FSDEV
+ #define TUP_USBIP_FSDEV_STM32
+ #define TUP_DCD_ENDPOINT_MAX 8
- // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
- #if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
- defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
- #define TUP_DCD_ENDPOINT_MAX 9
- #define TUP_RHPORT_HIGHSPEED 1
#else
- #define TUP_DCD_ENDPOINT_MAX 6
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_STM32
+
+ // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
+ #if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
+ defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
+ #define TUP_DCD_ENDPOINT_MAX 9
+ #define TUP_RHPORT_HIGHSPEED 1
+ #else
+ #define TUP_DCD_ENDPOINT_MAX 6
+ #endif
#endif
#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
@@ -286,13 +293,18 @@
#define TUP_USBIP_FSDEV_STM32
#define TUP_DCD_ENDPOINT_MAX 8
+#elif TU_CHECK_MCU(OPT_MCU_STM32U0)
+ #define TUP_USBIP_FSDEV
+ #define TUP_USBIP_FSDEV_STM32
+ #define TUP_DCD_ENDPOINT_MAX 8
+
//--------------------------------------------------------------------+
// Sony
//--------------------------------------------------------------------+
#elif TU_CHECK_MCU(OPT_MCU_CXD56)
#define TUP_DCD_ENDPOINT_MAX 7
#define TUP_RHPORT_HIGHSPEED 1
- #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+ #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
//--------------------------------------------------------------------+
// TI
@@ -301,6 +313,8 @@
#define TUP_DCD_ENDPOINT_MAX 8
#elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+ #define TUP_USBIP_MUSB
+ #define TUP_USBIP_MUSB_TI
#define TUP_DCD_ENDPOINT_MAX 8
//--------------------------------------------------------------------+
@@ -327,7 +341,20 @@
//--------------------------------------------------------------------+
#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
#define TUP_USBIP_DWC2
- #define TUP_DCD_ENDPOINT_MAX 6
+ #define TUP_USBIP_DWC2_ESP32
+ #define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN
+
+#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
+ #define TUP_USBIP_DWC2
+ #define TUP_USBIP_DWC2_ESP32
+ #define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS
+ #define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep
+
+#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
+ #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421))
+ #error "MCUs are only supported with CFG_TUH_MAX3421 enabled"
+ #endif
+ #define TUP_DCD_ENDPOINT_MAX 0
//--------------------------------------------------------------------+
// Dialog
@@ -385,10 +412,12 @@
#elif TU_CHECK_MCU(OPT_MCU_FT90X)
#define TUP_DCD_ENDPOINT_MAX 8
#define TUP_RHPORT_HIGHSPEED 1
+ #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
#elif TU_CHECK_MCU(OPT_MCU_FT93X)
#define TUP_DCD_ENDPOINT_MAX 16
#define TUP_RHPORT_HIGHSPEED 1
+ #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
//--------------------------------------------------------------------+
// Allwinner
@@ -396,16 +425,76 @@
#elif TU_CHECK_MCU(OPT_MCU_F1C100S)
#define TUP_DCD_ENDPOINT_MAX 4
-//------------- WCH -------------//
+//--------------------------------------------------------------------+
+// WCH
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_CH32F20X)
+ #define TUP_USBIP_WCH_USBHS
+ #define TUP_USBIP_WCH_USBFS
+
+ #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+ #define CFG_TUD_WCH_USBIP_USBFS 0
+ #endif
+
+ #if !defined(CFG_TUD_WCH_USBIP_USBHS)
+ #define CFG_TUD_WCH_USBIP_USBHS (CFG_TUD_WCH_USBIP_USBFS ? 0 : 1)
+ #endif
+
+ #define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS
+ #define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8)
+
+#elif TU_CHECK_MCU(OPT_MCU_CH32V103)
+ #define TUP_USBIP_WCH_USBFS
+
+ #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+ #define CFG_TUD_WCH_USBIP_USBFS 1
+ #endif
+
+ #define TUP_DCD_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(OPT_MCU_CH32V20X)
+ // v20x support both FSDEV (USBD) and USBFS, default to FSDEV
+ #define TUP_USBIP_WCH_USBFS
+ #define TUP_USBIP_FSDEV
+ #define TUP_USBIP_FSDEV_CH32
+
+ #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+ #define CFG_TUD_WCH_USBIP_USBFS 0
+ #endif
+
+ #if !defined(CFG_TUD_WCH_USBIP_FSDEV)
+ #define CFG_TUD_WCH_USBIP_FSDEV (CFG_TUD_WCH_USBIP_USBFS ? 0 : 1)
+ #endif
+
+ #define TUP_DCD_ENDPOINT_MAX 8
+
#elif TU_CHECK_MCU(OPT_MCU_CH32V307)
- #define TUP_DCD_ENDPOINT_MAX 16
- #define TUP_RHPORT_HIGHSPEED 1
+ // v307 support both FS and HS, default to HS
+ #define TUP_USBIP_WCH_USBHS
+ #define TUP_USBIP_WCH_USBFS
-#elif TU_CHECK_MCU(OPT_MCU_CH32F20X)
- #define TUP_DCD_ENDPOINT_MAX 16
+ #if !defined(CFG_TUD_WCH_USBIP_USBFS)
+ #define CFG_TUD_WCH_USBIP_USBFS 0
+ #endif
+
+ #if !defined(CFG_TUD_WCH_USBIP_USBHS)
+ #define CFG_TUD_WCH_USBIP_USBHS (CFG_TUD_WCH_USBIP_USBFS ? 0 : 1)
+ #endif
+
+ #define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS
+ #define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8)
+
+//--------------------------------------------------------------------+
+// Analog Devices
+//--------------------------------------------------------------------+
+#elif TU_CHECK_MCU(OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX32690, OPT_MCU_MAX78002)
+ #define TUP_USBIP_MUSB
+ #define TUP_USBIP_MUSB_ADI
+ #define TUP_DCD_ENDPOINT_MAX 12
#define TUP_RHPORT_HIGHSPEED 1
-#endif
+ #define TUD_ENDPOINT_ONE_DIRECTION_ONLY
+#endif
//--------------------------------------------------------------------+
// External USB controller
@@ -426,7 +515,7 @@
#define TUP_MCU_MULTIPLE_CORE 0
#endif
-#ifndef TUP_DCD_ENDPOINT_MAX
+#if !defined(TUP_DCD_ENDPOINT_MAX) && defined(CFG_TUD_ENABLED) && CFG_TUD_ENABLED
#warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
#define TUP_DCD_ENDPOINT_MAX 8
#endif
@@ -441,8 +530,13 @@
#define TU_ATTR_FAST_FUNC
#endif
-#if defined(TUP_USBIP_DWC2) || defined(TUP_USBIP_FSDEV)
+// USBIP that support ISO alloc & activate API
+#if defined(TUP_USBIP_DWC2) || defined(TUP_USBIP_FSDEV) || defined(TUP_USBIP_MUSB)
#define TUP_DCD_EDPT_ISO_ALLOC
#endif
+#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA == 0
+ #define TUP_MEM_CONST_ADDR
+#endif
+
#endif
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index 373a502564..8a479c0424 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -34,32 +34,24 @@
extern "C" {
#endif
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
volatile uint8_t busy : 1;
volatile uint8_t stalled : 1;
volatile uint8_t claimed : 1;
}tu_edpt_state_t;
typedef struct {
- bool is_host; // host or device most
- union {
- uint8_t daddr;
- uint8_t rhport;
- uint8_t hwid;
+ struct TU_ATTR_PACKED {
+ uint8_t is_host : 1; // 1: host, 0: device
+ uint8_t is_mps512 : 1; // 1: 512, 0: 64 since stream is used for Bulk only
};
uint8_t ep_addr;
- uint8_t ep_speed;
-
- uint16_t ep_packetsize;
uint16_t ep_bufsize;
- // TODO xfer_fifo can skip this buffer
- uint8_t* ep_buf;
-
+ uint8_t* ep_buf; // TODO xfer_fifo can skip this buffer
tu_fifo_t ff;
- // mutex: read if ep rx, write if e tx
+ // mutex: read if rx, otherwise write
OSAL_MUTEX_DEF(ff_mutexdef);
}tu_edpt_stream_t;
@@ -95,18 +87,15 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove
bool tu_edpt_stream_deinit(tu_edpt_stream_t* s);
// Open an stream for an endpoint
-// hwid is either device address (host mode) or rhport (device mode)
TU_ATTR_ALWAYS_INLINE static inline
-void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t const *desc_ep) {
+void tu_edpt_stream_open(tu_edpt_stream_t* s, tusb_desc_endpoint_t const *desc_ep) {
tu_fifo_clear(&s->ff);
- s->hwid = hwid;
s->ep_addr = desc_ep->bEndpointAddress;
- s->ep_packetsize = tu_edpt_packet_size(desc_ep);
+ s->is_mps512 = (tu_edpt_packet_size(desc_ep) == 512) ? 1 : 0;
}
TU_ATTR_ALWAYS_INLINE static inline
void tu_edpt_stream_close(tu_edpt_stream_t* s) {
- s->hwid = 0;
s->ep_addr = 0;
}
@@ -121,40 +110,40 @@ bool tu_edpt_stream_clear(tu_edpt_stream_t* s) {
//--------------------------------------------------------------------+
// Write to stream
-uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize);
+uint32_t tu_edpt_stream_write(uint8_t hwid, tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize);
// Start an usb transfer if endpoint is not busy
-uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s);
+uint32_t tu_edpt_stream_write_xfer(uint8_t hwid, tu_edpt_stream_t* s);
// Start an zero-length packet if needed
-bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes);
+bool tu_edpt_stream_write_zlp_if_needed(uint8_t hwid, tu_edpt_stream_t* s, uint32_t last_xferred_bytes);
-// Get the number of bytes available for writing
-TU_ATTR_ALWAYS_INLINE static inline
-uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) {
- return (uint32_t) tu_fifo_remaining(&s->ff);
-}
+// Get the number of bytes available for writing to FIFO
+// Note: if no fifo, return endpoint size if not busy, 0 otherwise
+uint32_t tu_edpt_stream_write_available(uint8_t hwid, tu_edpt_stream_t* s);
//--------------------------------------------------------------------+
// Stream Read
//--------------------------------------------------------------------+
// Read from stream
-uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize);
+uint32_t tu_edpt_stream_read(uint8_t hwid, tu_edpt_stream_t* s, void* buffer, uint32_t bufsize);
// Start an usb transfer if endpoint is not busy
-uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s);
+uint32_t tu_edpt_stream_read_xfer(uint8_t hwid, tu_edpt_stream_t* s);
// Must be called in the transfer complete callback
TU_ATTR_ALWAYS_INLINE static inline
void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes) {
- tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes);
+ if (tu_fifo_depth(&s->ff)) {
+ tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes);
+ }
}
// Same as tu_edpt_stream_read_xfer_complete but skip the first n bytes
TU_ATTR_ALWAYS_INLINE static inline
void tu_edpt_stream_read_xfer_complete_offset(tu_edpt_stream_t* s, uint32_t xferred_bytes, uint32_t skip_offset) {
- if (skip_offset < xferred_bytes) {
+ if (tu_fifo_depth(&s->ff) && (skip_offset < xferred_bytes)) {
tu_fifo_write_n(&s->ff, s->ep_buf + skip_offset, (uint16_t) (xferred_bytes - skip_offset));
}
}
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index b571f9b72c..53bb367cb1 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -39,11 +39,18 @@
/* CONSTANTS
*------------------------------------------------------------------*/
+typedef enum {
+ TUSB_ROLE_INVALID = 0,
+ TUSB_ROLE_DEVICE,
+ TUSB_ROLE_HOST,
+} tusb_role_t;
+
/// defined base on EHCI specs value for Endpoint Speed
typedef enum {
TUSB_SPEED_FULL = 0,
TUSB_SPEED_LOW = 1,
TUSB_SPEED_HIGH = 2,
+ TUSB_SPEED_AUTO = 0xaa,
TUSB_SPEED_INVALID = 0xff,
} tusb_speed_t;
@@ -214,6 +221,15 @@ enum {
#define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2)
+// USB 2.0 Spec Table 9-7: Test Mode Selectors
+typedef enum {
+ TUSB_FEATURE_TEST_J = 1,
+ TUSB_FEATURE_TEST_K,
+ TUSB_FEATURE_TEST_SE0_NAK,
+ TUSB_FEATURE_TEST_PACKET,
+ TUSB_FEATURE_TEST_FORCE_ENABLE,
+} tusb_feature_test_mode_t;
+
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
@@ -258,6 +274,14 @@ enum {
TUSB_INDEX_INVALID_8 = 0xFFu
};
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+typedef struct {
+ tusb_role_t role;
+ tusb_speed_t speed;
+} tusb_rhport_init_t;
+
//--------------------------------------------------------------------+
// USB Descriptors
//--------------------------------------------------------------------+
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 71406dacf2..3e0f1f1068 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -56,8 +56,8 @@
* #define TU_VERIFY(cond) if(cond) return false;
* #define TU_VERIFY(cond,ret) if(cond) return ret;
*
- * #define TU_ASSERT(cond) if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return false;}
- * #define TU_ASSERT(cond,ret) if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
+ * #define TU_ASSERT(cond) if(cond) {TU_MESS_FAILED(); TU_BREAKPOINT(), return false;}
+ * #define TU_ASSERT(cond,ret) if(cond) {TU_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
*------------------------------------------------------------------*/
#ifdef __cplusplus
@@ -70,21 +70,20 @@
#if CFG_TUSB_DEBUG
#include
- #define _MESS_FAILED() tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
+ #define TU_MESS_FAILED() tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
#else
- #define _MESS_FAILED() do {} while (0)
+ #define TU_MESS_FAILED() do {} while (0)
#endif
// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
- #define TU_BREAKPOINT() do \
- { \
+ #define TU_BREAKPOINT() do { \
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \
} while(0)
-#elif defined(__riscv)
+#elif defined(__riscv) && !TUP_MCU_ESPRESSIF
#define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
#elif defined(_mips)
@@ -94,9 +93,6 @@
#define TU_BREAKPOINT() do {} while (0)
#endif
-// Helper to implement optional parameter for TU_VERIFY Macro family
-#define _GET_3RD_ARG(arg1, arg2, arg3, ...) arg3
-
/*------------------------------------------------------------------*/
/* TU_VERIFY
* - TU_VERIFY_1ARGS : return false if failed
@@ -110,7 +106,7 @@
#define TU_VERIFY_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, false)
#define TU_VERIFY_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, _ret)
-#define TU_VERIFY(...) _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, _dummy)(__VA_ARGS__)
+#define TU_VERIFY(...) TU_GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, _dummy)(__VA_ARGS__)
/*------------------------------------------------------------------*/
/* ASSERT
@@ -120,14 +116,14 @@
*------------------------------------------------------------------*/
#define TU_ASSERT_DEFINE(_cond, _ret) \
do { \
- if ( !(_cond) ) { _MESS_FAILED(); TU_BREAKPOINT(); return _ret; } \
+ if ( !(_cond) ) { TU_MESS_FAILED(); TU_BREAKPOINT(); return _ret; } \
} while(0)
#define TU_ASSERT_1ARGS(_cond) TU_ASSERT_DEFINE(_cond, false)
#define TU_ASSERT_2ARGS(_cond, _ret) TU_ASSERT_DEFINE(_cond, _ret)
#ifndef TU_ASSERT
-#define TU_ASSERT(...) _GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_2ARGS, TU_ASSERT_1ARGS, _dummy)(__VA_ARGS__)
+#define TU_ASSERT(...) TU_GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_2ARGS, TU_ASSERT_1ARGS, _dummy)(__VA_ARGS__)
#endif
#ifdef __cplusplus
diff --git a/src/device/dcd.h b/src/device/dcd.h
index d4f105aa39..d01f82e01c 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -24,8 +24,8 @@
* This file is part of the TinyUSB stack.
*/
-#ifndef _TUSB_DCD_H_
-#define _TUSB_DCD_H_
+#ifndef TUSB_DCD_H_
+#define TUSB_DCD_H_
#include "common/tusb_common.h"
#include "osal/osal.h"
@@ -35,32 +35,20 @@
extern "C" {
#endif
-//--------------------------------------------------------------------+
-// Configuration
-//--------------------------------------------------------------------+
-
-#ifndef CFG_TUD_ENDPPOINT_MAX
- #define CFG_TUD_ENDPPOINT_MAX TUP_DCD_ENDPOINT_MAX
-#endif
-
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF PROTYPES
//--------------------------------------------------------------------+
typedef enum {
- DCD_EVENT_INVALID = 0,
- DCD_EVENT_BUS_RESET,
- DCD_EVENT_UNPLUGGED,
- DCD_EVENT_SOF,
- DCD_EVENT_SUSPEND, // TODO LPM Sleep L1 support
- DCD_EVENT_RESUME,
-
- DCD_EVENT_SETUP_RECEIVED,
- DCD_EVENT_XFER_COMPLETE,
-
- // Not an DCD event, just a convenient way to defer ISR function
- USBD_EVENT_FUNC_CALL,
-
+ DCD_EVENT_INVALID = 0, // 0
+ DCD_EVENT_BUS_RESET, // 1
+ DCD_EVENT_UNPLUGGED, // 2
+ DCD_EVENT_SOF, // 3
+ DCD_EVENT_SUSPEND, // 4 TODO LPM Sleep L1 support
+ DCD_EVENT_RESUME, // 5
+ DCD_EVENT_SETUP_RECEIVED, // 6
+ DCD_EVENT_XFER_COMPLETE, // 7
+ USBD_EVENT_FUNC_CALL, // 8 Not an DCD event, just a convenient way to defer ISR function
DCD_EVENT_COUNT
} dcd_eventid_t;
@@ -120,7 +108,7 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W
//--------------------------------------------------------------------+
// Initialize controller to device mode
-void dcd_init(uint8_t rhport);
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
// Deinitialize controller, unset device mode.
bool dcd_deinit(uint8_t rhport);
@@ -141,14 +129,18 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr);
void dcd_remote_wakeup(uint8_t rhport);
// Connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport) TU_ATTR_WEAK;
+void dcd_connect(uint8_t rhport);
// Disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK;
+void dcd_disconnect(uint8_t rhport);
// Enable/Disable Start-of-frame interrupt. Default is disabled
void dcd_sof_enable(uint8_t rhport, bool en);
+#if CFG_TUD_TEST_MODE
+// Put device into a test mode (needs power cycle to quit)
+void dcd_enter_test_mode(uint8_t rhport, tusb_feature_test_mode_t test_selector);
+#endif
//--------------------------------------------------------------------+
// Endpoint API
//--------------------------------------------------------------------+
@@ -165,10 +157,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc
// required for multiple configuration support.
void dcd_edpt_close_all (uint8_t rhport);
-// Close an endpoint.
-// Since it is weak, caller must TU_ASSERT this function's existence before calling it.
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK;
-
// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
@@ -183,12 +171,19 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr);
// This API never calls with control endpoints, since it is auto cleared when receiving setup packet
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
// Allocate packet buffer used by ISO endpoints
// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
-TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
// Configure and enable an ISO endpoint according to descriptor
-TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
+
+#else
+// Close an endpoint.
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr);
+
+#endif
//--------------------------------------------------------------------+
// Event API (implemented by stack)
@@ -199,38 +194,45 @@ extern void dcd_event_handler(dcd_event_t const * event, bool in_isr);
// helper to send bus signal event
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr) {
- dcd_event_t event = { .rhport = rhport, .event_id = eid };
+ dcd_event_t event;
+ event.rhport = rhport;
+ event.event_id = eid;
dcd_event_handler(&event, in_isr);
}
// helper to send bus reset event
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr) {
- dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
+ dcd_event_t event;
+ event.rhport = rhport;
+ event.event_id = DCD_EVENT_BUS_RESET;
event.bus_reset.speed = speed;
dcd_event_handler(&event, in_isr);
}
// helper to send setup received
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) {
- dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
+ dcd_event_t event;
+ event.rhport = rhport;
+ event.event_id = DCD_EVENT_SETUP_RECEIVED;
memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t));
-
dcd_event_handler(&event, in_isr);
}
// helper to send transfer complete event
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) {
- dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE };
-
+ dcd_event_t event;
+ event.rhport = rhport;
+ event.event_id = DCD_EVENT_XFER_COMPLETE;
event.xfer_complete.ep_addr = ep_addr;
event.xfer_complete.len = xferred_bytes;
event.xfer_complete.result = result;
-
dcd_event_handler(&event, in_isr);
}
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr) {
- dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF };
+ dcd_event_t event;
+ event.rhport = rhport;
+ event.event_id = DCD_EVENT_SOF;
event.sof.frame_count = frame_count;
dcd_event_handler(&event, in_isr);
}
@@ -239,4 +241,4 @@ TU_ATTR_ALWAYS_INLINE static inline void dcd_event_sof(uint8_t rhport, uint32_t
}
#endif
-#endif /* _TUSB_DCD_H_ */
+#endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index e51aa0fc49..a730b745b8 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -45,15 +45,60 @@
//--------------------------------------------------------------------+
// Weak stubs: invoked if no strong implementation is available
//--------------------------------------------------------------------+
+TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
+ (void) rhport;
+ (void) eventid;
+ (void) in_isr;
+}
+
+TU_ATTR_WEAK void tud_sof_cb(uint32_t frame_count) {
+ (void) frame_count;
+}
+
+TU_ATTR_WEAK uint8_t const* tud_descriptor_bos_cb(void) {
+ return NULL;
+}
+
+TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void) {
+ return NULL;
+}
+
+TU_ATTR_WEAK uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+ (void) index;
+ return NULL;
+}
+
+TU_ATTR_WEAK void tud_mount_cb(void) {
+}
+
+TU_ATTR_WEAK void tud_umount_cb(void) {
+}
+
+TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en) {
+ (void) remote_wakeup_en;
+}
+
+TU_ATTR_WEAK void tud_resume_cb(void) {
+}
+
+TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) {
+ (void) rhport;
+ (void) stage;
+ (void) request;
+ return false;
+}
+
TU_ATTR_WEAK bool dcd_deinit(uint8_t rhport) {
(void) rhport;
return false;
}
-TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
- (void)rhport;
- (void)eventid;
- (void)in_isr;
+TU_ATTR_WEAK void dcd_connect(uint8_t rhport) {
+ (void) rhport;
+}
+
+TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) {
+ (void) rhport;
}
//--------------------------------------------------------------------+
@@ -75,7 +120,7 @@ typedef struct {
};
volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
uint8_t speed;
- volatile uint8_t setup_count;
+ volatile uint8_t sof_consumer;
uint8_t itf2drv[CFG_TUD_INTERFACE_MAX]; // map interface number to driver (0xff is invalid)
uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ), can use only 4-bit each
@@ -85,21 +130,22 @@ typedef struct {
}usbd_device_t;
tu_static usbd_device_t _usbd_dev;
+static volatile uint8_t _usbd_queued_setup;
//--------------------------------------------------------------------+
// Class Driver
//--------------------------------------------------------------------+
#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
- #define DRIVER_NAME(_name) .name = _name,
+ #define DRIVER_NAME(_name) _name
#else
- #define DRIVER_NAME(_name)
+ #define DRIVER_NAME(_name) NULL
#endif
// Built-in class drivers
tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_CDC
{
- DRIVER_NAME("CDC")
+ .name = DRIVER_NAME("CDC"),
.init = cdcd_init,
.deinit = cdcd_deinit,
.reset = cdcd_reset,
@@ -112,7 +158,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_MSC
{
- DRIVER_NAME("MSC")
+ .name = DRIVER_NAME("MSC"),
.init = mscd_init,
.deinit = NULL,
.reset = mscd_reset,
@@ -125,7 +171,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_HID
{
- DRIVER_NAME("HID")
+ .name = DRIVER_NAME("HID"),
.init = hidd_init,
.deinit = hidd_deinit,
.reset = hidd_reset,
@@ -138,7 +184,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_AUDIO
{
- DRIVER_NAME("AUDIO")
+ .name = DRIVER_NAME("AUDIO"),
.init = audiod_init,
.deinit = audiod_deinit,
.reset = audiod_reset,
@@ -151,7 +197,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_VIDEO
{
- DRIVER_NAME("VIDEO")
+ .name = DRIVER_NAME("VIDEO"),
.init = videod_init,
.deinit = videod_deinit,
.reset = videod_reset,
@@ -164,7 +210,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_MIDI
{
- DRIVER_NAME("MIDI")
+ .name = DRIVER_NAME("MIDI"),
.init = midid_init,
.deinit = midid_deinit,
.open = midid_open,
@@ -177,7 +223,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_VENDOR
{
- DRIVER_NAME("VENDOR")
+ .name = DRIVER_NAME("VENDOR"),
.init = vendord_init,
.deinit = vendord_deinit,
.reset = vendord_reset,
@@ -190,7 +236,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_USBTMC
{
- DRIVER_NAME("TMC")
+ .name = DRIVER_NAME("TMC"),
.init = usbtmcd_init_cb,
.deinit = usbtmcd_deinit,
.reset = usbtmcd_reset_cb,
@@ -203,7 +249,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_DFU_RUNTIME
{
- DRIVER_NAME("DFU-RUNTIME")
+ .name = DRIVER_NAME("DFU-RUNTIME"),
.init = dfu_rtd_init,
.deinit = dfu_rtd_deinit,
.reset = dfu_rtd_reset,
@@ -216,7 +262,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_DFU
{
- DRIVER_NAME("DFU")
+ .name = DRIVER_NAME("DFU"),
.init = dfu_moded_init,
.deinit = dfu_moded_deinit,
.reset = dfu_moded_reset,
@@ -229,7 +275,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
{
- DRIVER_NAME("NET")
+ .name = DRIVER_NAME("NET"),
.init = netd_init,
.deinit = netd_deinit,
.reset = netd_reset,
@@ -242,7 +288,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
#if CFG_TUD_BTH
{
- DRIVER_NAME("BTH")
+ .name = DRIVER_NAME("BTH"),
.init = btd_init,
.deinit = btd_deinit,
.reset = btd_reset,
@@ -275,6 +321,7 @@ TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8
return driver;
}
+
//--------------------------------------------------------------------+
// DCD Event
//--------------------------------------------------------------------+
@@ -308,6 +355,16 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
static bool process_set_config(uint8_t rhport, uint8_t cfg_num);
static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const * p_request);
+#if CFG_TUD_TEST_MODE
+static bool process_test_mode_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) {
+ TU_VERIFY(CONTROL_STAGE_ACK == stage);
+ uint8_t const selector = tu_u16_high(request->wIndex);
+ TU_LOG_USBD(" Enter Test Mode (test selector index: %d)\r\n", selector);
+ dcd_enter_test_mode(rhport, (tusb_feature_test_mode_t) selector);
+ return true;
+}
+#endif
+
// from usbd_control.c
void usbd_control_reset(void);
void usbd_control_set_request(tusb_control_request_t const *request);
@@ -371,17 +428,19 @@ bool tud_remote_wakeup(void) {
}
bool tud_disconnect(void) {
- TU_VERIFY(dcd_disconnect);
dcd_disconnect(_usbd_rhport);
return true;
}
bool tud_connect(void) {
- TU_VERIFY(dcd_connect);
dcd_connect(_usbd_rhport);
return true;
}
+void tud_sof_cb_enable(bool en) {
+ usbd_sof_enable(_usbd_rhport, SOF_CONSUMER_USER, en);
+}
+
//--------------------------------------------------------------------+
// USBD Task
//--------------------------------------------------------------------+
@@ -389,17 +448,21 @@ bool tud_inited(void) {
return _usbd_rhport != RHPORT_INVALID;
}
-bool tud_init(uint8_t rhport) {
- // skip if already initialized
- if (tud_inited()) return true;
+bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ if (tud_inited()) {
+ return true; // skip if already initialized
+ }
+ TU_ASSERT(rh_init);
- TU_LOG_USBD("USBD init on controller %u\r\n", rhport);
+ TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport,
+ rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t));
TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t));
TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_edpt_stream_t));
tu_varclr(&_usbd_dev);
+ _usbd_queued_setup = 0;
#if OSAL_MUTEX_REQUIRED
// Init device mutex
@@ -427,15 +490,16 @@ bool tud_init(uint8_t rhport) {
_usbd_rhport = rhport;
// Init device controller driver
- dcd_init(rhport);
+ TU_ASSERT(dcd_init(rhport, rh_init));
dcd_int_enable(rhport);
return true;
}
bool tud_deinit(uint8_t rhport) {
- // skip if not initialized
- if (!tud_inited()) return true;
+ if (!tud_inited()) {
+ return true; // skip if not initialized
+ }
TU_LOG_USBD("USBD deinit on controller %u\r\n", rhport);
@@ -497,7 +561,7 @@ bool tud_task_event_ready(void) {
*
int main(void) {
application_init();
- tusb_init();
+ tusb_init(0, TUSB_ROLE_DEVICE);
while(1) { // the mainloop
application_code();
@@ -531,13 +595,14 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
case DCD_EVENT_UNPLUGGED:
TU_LOG_USBD("\r\n");
usbd_reset(event.rhport);
- if (tud_umount_cb) tud_umount_cb();
+ tud_umount_cb();
break;
case DCD_EVENT_SETUP_RECEIVED:
- _usbd_dev.setup_count--;
+ TU_ASSERT(_usbd_queued_setup > 0,);
+ _usbd_queued_setup--;
TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
- if (_usbd_dev.setup_count) {
+ if (_usbd_queued_setup) {
TU_LOG_USBD(" Skipped since there is other SETUP in queue\r\n");
break;
}
@@ -591,7 +656,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
// e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected
if (_usbd_dev.connected) {
TU_LOG_USBD(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
- if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
+ tud_suspend_cb(_usbd_dev.remote_wakeup_en);
} else {
TU_LOG_USBD(" Skipped\r\n");
}
@@ -600,7 +665,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
case DCD_EVENT_RESUME:
if (_usbd_dev.connected) {
TU_LOG_USBD("\r\n");
- if (tud_resume_cb) tud_resume_cb();
+ tud_resume_cb();
} else {
TU_LOG_USBD(" Skipped\r\n");
}
@@ -612,6 +677,12 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
break;
case DCD_EVENT_SOF:
+ if (tu_bit_test(_usbd_dev.sof_consumer, SOF_CONSUMER_USER)) {
+ TU_LOG_USBD("\r\n");
+ tud_sof_cb(event.sof.frame_count);
+ }
+ break;
+
default:
TU_BREAKPOINT();
break;
@@ -643,8 +714,6 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
// Vendor request
if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR ) {
- TU_VERIFY(tud_vendor_control_xfer_cb);
-
usbd_control_set_complete_callback(tud_vendor_control_xfer_cb);
return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request);
}
@@ -671,7 +740,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
}
if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) {
- // Non standard request is not supported
+ // Non-standard request is not supported
TU_BREAKPOINT();
return false;
}
@@ -702,6 +771,9 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
// already configured: need to clear all endpoints and driver first
TU_LOG_USBD(" Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
+ // disable SOF
+ dcd_sof_enable(rhport, false);
+
// close all non-control endpoints, cancel all pending transfers if any
dcd_edpt_close_all(rhport);
@@ -712,17 +784,23 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
_usbd_dev.speed = speed; // restore speed
}
+ _usbd_dev.cfg_num = cfg_num;
+
// Handle the new configuration and execute the corresponding callback
if ( cfg_num ) {
// switch to new configuration if not zero
- TU_ASSERT( process_set_config(rhport, cfg_num) );
- if ( tud_mount_cb ) tud_mount_cb();
+ if (!process_set_config(rhport, cfg_num)) {
+ TU_MESS_FAILED();
+ TU_BREAKPOINT();
+ _usbd_dev.cfg_num = 0;
+ return false;
+ }
+ tud_mount_cb();
} else {
- if ( tud_umount_cb ) tud_umount_cb();
+ tud_umount_cb();
}
}
- _usbd_dev.cfg_num = cfg_num;
tud_control_status(rhport, p_request);
}
break;
@@ -732,14 +810,31 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
break;
case TUSB_REQ_SET_FEATURE:
- // Only support remote wakeup for device feature
- TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
+ switch(p_request->wValue) {
+ case TUSB_REQ_FEATURE_REMOTE_WAKEUP:
+ TU_LOG_USBD(" Enable Remote Wakeup\r\n");
+ // Host may enable remote wake up before suspending especially HID device
+ _usbd_dev.remote_wakeup_en = true;
+ tud_control_status(rhport, p_request);
+ break;
- TU_LOG_USBD(" Enable Remote Wakeup\r\n");
+ #if CFG_TUD_TEST_MODE
+ case TUSB_REQ_FEATURE_TEST_MODE: {
+ // Only handle the test mode if supported and valid
+ TU_VERIFY(0 == tu_u16_low(p_request->wIndex));
- // Host may enable remote wake up before suspending especially HID device
- _usbd_dev.remote_wakeup_en = true;
- tud_control_status(rhport, p_request);
+ uint8_t const selector = tu_u16_high(p_request->wIndex);
+ TU_VERIFY(TUSB_FEATURE_TEST_J <= selector && selector <= TUSB_FEATURE_TEST_FORCE_ENABLE);
+
+ usbd_control_set_complete_callback(process_test_mode_cb);
+ tud_control_status(rhport, p_request);
+ break;
+ }
+ #endif /* CFG_TUD_TEST_MODE */
+
+ // Stall unsupported feature selector
+ default: return false;
+ }
break;
case TUSB_REQ_CLEAR_FEATURE:
@@ -969,39 +1064,34 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
switch(desc_type)
{
- case TUSB_DESC_DEVICE:
- {
+ case TUSB_DESC_DEVICE: {
TU_LOG_USBD(" Device\r\n");
void* desc_device = (void*) (uintptr_t) tud_descriptor_device_cb();
+ TU_ASSERT(desc_device);
// Only response with exactly 1 Packet if: not addressed and host requested more data than device descriptor has.
// This only happens with the very first get device descriptor and EP0 size = 8 or 16.
if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed &&
- ((tusb_control_request_t const*) p_request)->wLength > sizeof(tusb_desc_device_t))
- {
+ ((tusb_control_request_t const*) p_request)->wLength > sizeof(tusb_desc_device_t)) {
// Hack here: we modify the request length to prevent usbd_control response with zlp
// since we are responding with 1 packet & less data than wLength.
tusb_control_request_t mod_request = *p_request;
mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE;
return tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE);
- }else
- {
+ }else {
return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t));
}
}
// break; // unreachable
- case TUSB_DESC_BOS:
- {
+ case TUSB_DESC_BOS: {
TU_LOG_USBD(" BOS\r\n");
// requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
- if (!tud_descriptor_bos_cb) return false;
-
uintptr_t desc_bos = (uintptr_t) tud_descriptor_bos_cb();
- TU_ASSERT(desc_bos);
+ TU_VERIFY(desc_bos);
// Use offsetof to avoid pointer to the odd/misaligned address
uint16_t const total_len = tu_le16toh( tu_unaligned_read16((const void*) (desc_bos + offsetof(tusb_desc_bos_t, wTotalLength))) );
@@ -1011,24 +1101,20 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
// break; // unreachable
case TUSB_DESC_CONFIGURATION:
- case TUSB_DESC_OTHER_SPEED_CONFIG:
- {
+ case TUSB_DESC_OTHER_SPEED_CONFIG: {
uintptr_t desc_config;
- if ( desc_type == TUSB_DESC_CONFIGURATION )
- {
+ if ( desc_type == TUSB_DESC_CONFIGURATION ) {
TU_LOG_USBD(" Configuration[%u]\r\n", desc_index);
desc_config = (uintptr_t) tud_descriptor_configuration_cb(desc_index);
- }else
- {
+ TU_ASSERT(desc_config);
+ }else {
// Host only request this after getting Device Qualifier descriptor
TU_LOG_USBD(" Other Speed Configuration\r\n");
- TU_VERIFY( tud_descriptor_other_speed_configuration_cb );
desc_config = (uintptr_t) tud_descriptor_other_speed_configuration_cb(desc_index);
+ TU_VERIFY(desc_config);
}
- TU_ASSERT(desc_config);
-
// Use offsetof to avoid pointer to the odd/misaligned address
uint16_t const total_len = tu_le16toh( tu_unaligned_read16((const void*) (desc_config + offsetof(tusb_desc_configuration_t, wTotalLength))) );
@@ -1049,16 +1135,10 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
}
// break; // unreachable
- case TUSB_DESC_DEVICE_QUALIFIER:
- {
+ case TUSB_DESC_DEVICE_QUALIFIER: {
TU_LOG_USBD(" Device Qualifier\r\n");
-
- TU_VERIFY( tud_descriptor_device_qualifier_cb );
-
uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb();
TU_VERIFY(desc_qualifier);
-
- // first byte of descriptor is its size
return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_qualifier, tu_desc_len(desc_qualifier));
}
// break; // unreachable
@@ -1101,6 +1181,14 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr)
break;
case DCD_EVENT_SOF:
+ // SOF driver handler in ISR context
+ for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+ usbd_class_driver_t const* driver = get_driver(i);
+ if (driver && driver->sof) {
+ driver->sof(event->rhport, event->sof.frame_count);
+ }
+ }
+
// Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
// which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational
if (_usbd_dev.suspended) {
@@ -1110,19 +1198,14 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr)
queue_event(&event_resume, in_isr);
}
- // SOF driver handler in ISR context
- for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
- usbd_class_driver_t const* driver = get_driver(i);
- if (driver && driver->sof) {
- driver->sof(event->rhport, event->sof.frame_count);
- }
+ if (tu_bit_test(_usbd_dev.sof_consumer, SOF_CONSUMER_USER)) {
+ dcd_event_t const event_sof = {.rhport = event->rhport, .event_id = DCD_EVENT_SOF, .sof.frame_count = event->sof.frame_count};
+ queue_event(&event_sof, in_isr);
}
-
- // skip osal queue for SOF in usbd task
break;
case DCD_EVENT_SETUP_RECEIVED:
- _usbd_dev.setup_count++;
+ _usbd_queued_setup++;
send = true;
break;
@@ -1339,9 +1422,12 @@ bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) {
* In progress transfers on this EP may be delivered after this call.
*/
void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+ (void) rhport; (void) ep_addr;
+ // ISO alloc/activate Should be used instead
+#else
rhport = _usbd_rhport;
- TU_ASSERT(dcd_edpt_close, /**/);
TU_LOG_USBD(" CLOSING Endpoint: 0x%02X\r\n", ep_addr);
uint8_t const epnum = tu_edpt_number(ep_addr);
@@ -1351,34 +1437,47 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
_usbd_dev.ep_status[epnum][dir].stalled = 0;
_usbd_dev.ep_status[epnum][dir].busy = 0;
_usbd_dev.ep_status[epnum][dir].claimed = 0;
+#endif
return;
}
-void usbd_sof_enable(uint8_t rhport, bool en) {
+void usbd_sof_enable(uint8_t rhport, sof_consumer_t consumer, bool en) {
rhport = _usbd_rhport;
- // TODO: Check needed if all drivers including the user sof_cb does not need an active SOF ISR any more.
- // Only if all drivers switched off SOF calls the SOF interrupt may be disabled
- dcd_sof_enable(rhport, en);
+ uint8_t consumer_old = _usbd_dev.sof_consumer;
+ // Keep track how many class instances need the SOF interrupt
+ if (en) {
+ _usbd_dev.sof_consumer |= (uint8_t)(1 << consumer);
+ } else {
+ _usbd_dev.sof_consumer &= (uint8_t)(~(1 << consumer));
+ }
+
+ // Test logically unequal
+ if(!_usbd_dev.sof_consumer != !consumer_old) {
+ dcd_sof_enable(rhport, _usbd_dev.sof_consumer);
+ }
}
bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
rhport = _usbd_rhport;
- TU_ASSERT(dcd_edpt_iso_alloc);
TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX);
-
return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size);
+#else
+ (void) rhport; (void) ep_addr; (void) largest_packet_size;
+ return false;
+#endif
}
bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) {
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
rhport = _usbd_rhport;
uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress);
- TU_ASSERT(dcd_edpt_iso_activate);
TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX);
TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
@@ -1386,6 +1485,10 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep)
_usbd_dev.ep_status[epnum][dir].busy = 0;
_usbd_dev.ep_status[epnum][dir].claimed = 0;
return dcd_edpt_iso_activate(rhport, desc_ep);
+#else
+ (void) rhport; (void) desc_ep;
+ return false;
+#endif
}
#endif
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 0197628e2c..de6007fb39 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -37,8 +37,20 @@ extern "C" {
// Application API
//--------------------------------------------------------------------+
+// New API to replace tud_init() to init device stack on specific roothub port
+bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
+
// Init device stack on roothub port
-bool tud_init (uint8_t rhport);
+#if TUSB_VERSION_NUMBER > 2000 // 0.20.0
+TU_ATTR_DEPRECATED("Please use tusb_init(rhport, rh_init) instead")
+#endif
+TU_ATTR_ALWAYS_INLINE static inline bool tud_init (uint8_t rhport) {
+ const tusb_rhport_init_t rh_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL
+ };
+ return tud_rhport_init(rhport, &rh_init);
+}
// Deinit device stack on roothub port
bool tud_deinit(uint8_t rhport);
@@ -60,7 +72,7 @@ void tud_task (void) {
// Check if there is pending events need processing by tud_task()
bool tud_task_event_ready(void);
-#ifndef _TUSB_DCD_H_
+#ifndef TUSB_DCD_H_
extern void dcd_int_handler(uint8_t rhport);
#endif
@@ -97,6 +109,9 @@ bool tud_disconnect(void);
// Return false on unsupported MCUs
bool tud_connect(void);
+// Enable or disable the Start Of Frame callback support
+void tud_sof_cb_enable(bool en);
+
// Carry out Data and Status stage of control transfer
// - If len = 0, it is equivalent to sending status only
// - If len > wLength : it will be truncated
@@ -106,7 +121,7 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request);
//--------------------------------------------------------------------+
-// Application Callbacks (WEAK is optional)
+// Application Callbacks
//--------------------------------------------------------------------+
// Invoked when received GET DEVICE DESCRIPTOR request
@@ -123,37 +138,40 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid);
// Invoked when received GET BOS DESCRIPTOR request
// Application return pointer to descriptor
-TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void);
+uint8_t const * tud_descriptor_bos_cb(void);
// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
// device_qualifier descriptor describes information about a high-speed capable device that would
// change if the device were operating at the other speed. If not highspeed capable stall this request.
-TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void);
+uint8_t const* tud_descriptor_device_qualifier_cb(void);
// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
-TU_ATTR_WEAK uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index);
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index);
// Invoked when device is mounted (configured)
-TU_ATTR_WEAK void tud_mount_cb(void);
+void tud_mount_cb(void);
// Invoked when device is unmounted
-TU_ATTR_WEAK void tud_umount_cb(void);
+void tud_umount_cb(void);
// Invoked when usb bus is suspended
// Within 7ms, device must draw an average of current less than 2.5 mA from bus
-TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en);
+void tud_suspend_cb(bool remote_wakeup_en);
// Invoked when usb bus is resumed
-TU_ATTR_WEAK void tud_resume_cb(void);
+void tud_resume_cb(void);
// Invoked when there is a new usb event, which need to be processed by tud_task()/tud_task_ext()
void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
+// Invoked when a new (micro) frame started
+void tud_sof_cb(uint32_t frame_count);
+
// Invoked when received control request with VENDOR TYPE
-TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
//--------------------------------------------------------------------+
// Binary Device Object Store (BOS) Descriptor Templates
@@ -221,8 +239,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120),\
/* CDC Call */\
5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1),\
- /* CDC ACM: support line request */\
- 4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 2,\
+ /* CDC ACM: support line request + send break */\
+ 4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 6,\
/* CDC Union */\
5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
/* Endpoint Notification */\
@@ -428,8 +446,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
/* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */
#define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7
-#define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \
- TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_NO_SYNC | (uint8_t)TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
+#define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _epsize, _interval) \
+ TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_NO_SYNC | (uint8_t)TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(_epsize), _interval
// AUDIO simple descriptor (UAC2) for 1 microphone input
// - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source
@@ -547,7 +565,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
+ TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+ TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN)
-#define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epsize, _epfb) \
+#define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epoutsize, _epfb, _epfbsize) \
/* Standard Interface Association Descriptor (IAD) */\
TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
/* Standard AC Interface Descriptor(4.7.1) */\
@@ -561,7 +579,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
/* Output Terminal Descriptor(4.7.2.5) */\
TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_OUT_DESKTOP_SPEAKER, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
/* Feature Unit Descriptor(4.7.2.8) */\
- TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\
+ TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\
/* Standard AS Interface Descriptor(4.9.1) */\
/* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
@@ -573,11 +591,11 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
- TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
/* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
- TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_interval*/ 1)\
+ TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_epsize*/ _epfbsize, /*_interval*/ 1)
// Calculate wMaxPacketSize of Endpoints
#define TUD_AUDIO_EP_SIZE(_maxFrequency, _nBytesPerSample, _nChannels) \
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 35cce1f7ee..b1fd357aa3 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -137,7 +137,7 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi
void usbd_control_reset(void);
void usbd_control_set_request(tusb_control_request_t const* request);
void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp);
-bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
void usbd_control_reset(void) {
tu_varclr(&_ctrl_xfer);
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 47752f32cb..90f37db3ed 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -23,11 +23,12 @@
*
* This file is part of the TinyUSB stack.
*/
-#ifndef _TUSB_USBD_PVT_H_
-#define _TUSB_USBD_PVT_H_
+#ifndef TUSB_USBD_PVT_H_
+#define TUSB_USBD_PVT_H_
#include "osal/osal.h"
#include "common/tusb_fifo.h"
+#include "common/tusb_private.h"
#ifdef __cplusplus
extern "C" {
@@ -35,15 +36,21 @@
#define TU_LOG_USBD(...) TU_LOG(CFG_TUD_LOG_LEVEL, __VA_ARGS__)
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+typedef enum {
+ SOF_CONSUMER_USER = 0,
+ SOF_CONSUMER_AUDIO,
+} sof_consumer_t;
+
//--------------------------------------------------------------------+
// Class Driver API
//--------------------------------------------------------------------+
typedef struct {
- #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
char const* name;
- #endif
-
void (* init ) (void);
bool (* deinit ) (void);
void (* reset ) (uint8_t rhport);
@@ -111,7 +118,7 @@ bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) {
}
// Enable SOF interrupt
-void usbd_sof_enable(uint8_t rhport, bool en);
+void usbd_sof_enable(uint8_t rhport, sof_consumer_t consumer, bool en);
/*------------------------------------------------------------------*/
/* Helper
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 5547c7cc5c..6518e6fd29 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -53,26 +53,21 @@
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-typedef enum
-{
+typedef enum {
HCD_EVENT_DEVICE_ATTACH,
HCD_EVENT_DEVICE_REMOVE,
HCD_EVENT_XFER_COMPLETE,
- // Not an HCD event, just a convenient way to defer ISR function
- USBH_EVENT_FUNC_CALL,
-
+ USBH_EVENT_FUNC_CALL, // Not an HCD event
HCD_EVENT_COUNT
} hcd_eventid_t;
-typedef struct
-{
+typedef struct {
uint8_t rhport;
uint8_t event_id;
uint8_t dev_addr;
- union
- {
+ union {
// Attach, Remove
struct {
uint8_t hub_addr;
@@ -93,11 +88,9 @@ typedef struct
void* param;
}func_call;
};
-
} hcd_event_t;
-typedef struct
-{
+typedef struct {
uint8_t rhport;
uint8_t hub_addr;
uint8_t hub_port;
@@ -128,7 +121,7 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W
bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
// Initialize controller to host mode
-bool hcd_init(uint8_t rhport);
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
// De-initialize controller
bool hcd_deinit(uint8_t rhport);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 7a47f5056a..b5df29f501 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -352,11 +352,13 @@ bool tuh_inited(void) {
return _usbh_controller != TUSB_INDEX_INVALID_8;
}
-bool tuh_init(uint8_t rhport) {
- // skip if already initialized
- if (tuh_rhport_is_active(rhport)) return true;
+bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ if (tuh_rhport_is_active(rhport)) {
+ return true; // skip if already initialized
+ }
- TU_LOG_USBH("USBH init on controller %u\r\n", rhport);
+ TU_LOG_USBH("USBH init on controller %u, speed = %s\r\n", rhport,
+ rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full");
// Init host stack if not already
if (!tuh_inited()) {
@@ -402,8 +404,8 @@ bool tuh_init(uint8_t rhport) {
}
// Init host controller
- _usbh_controller = rhport;;
- TU_ASSERT(hcd_init(rhport));
+ _usbh_controller = rhport;
+ TU_ASSERT(hcd_init(rhport, rh_init));
hcd_int_enable(rhport);
return true;
@@ -459,7 +461,7 @@ bool tuh_task_event_ready(void) {
int main(void)
{
application_init();
- tusb_init();
+ tusb_init(0, TUSB_ROLE_HOST);
while(1) // the mainloop
{
@@ -1113,7 +1115,7 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
TU_LOG_USBH("Set Interface %u Alternate %u\r\n", itf_num, itf_alt);
tusb_control_request_t const request = {
.bmRequestType_bit = {
- .recipient = TUSB_REQ_RCPT_DEVICE,
+ .recipient = TUSB_REQ_RCPT_INTERFACE,
.type = TUSB_REQ_TYPE_STANDARD,
.direction = TUSB_DIR_OUT
},
@@ -1421,6 +1423,9 @@ static void process_enumeration(tuh_xfer_t* xfer) {
break;
case ENUM_GET_DEVICE_DESC: {
+ // Allow 2ms for address recovery time, Ref USB Spec 9.2.6.3
+ osal_task_delay(2);
+
uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue);
usbh_device_t* new_dev = get_device(new_addr);
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 359684169e..20fad284ee 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -81,7 +81,7 @@ enum {
};
typedef struct {
- uint8_t max_nak; // max NAK per endpoint per frame
+ uint8_t max_nak; // max NAK per endpoint per frame to save CPU/SPI bus usage
uint8_t cpuctl; // R16: CPU Control Register
uint8_t pinctl; // R17: Pin Control Register. FDUPSPI bit is ignored
} tuh_configure_max3421_t;
@@ -120,8 +120,20 @@ void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
// - cfg_param: configure data, structure depends on the ID
bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
+// New API to replace tuh_init() to init host stack on specific roothub port
+bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
+
// Init host stack
-bool tuh_init(uint8_t rhport);
+#if TUSB_VERSION_NUMBER > 2000 // 0.20.0
+TU_ATTR_DEPRECATED("Please use tusb_init(rhport, rh_init) instead")
+#endif
+TU_ATTR_ALWAYS_INLINE static inline bool tuh_init(uint8_t rhport) {
+ const tusb_rhport_init_t rh_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUH_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL,
+ };
+ return tuh_rhport_init(rhport, &rh_init);
+}
// Deinit host stack on rhport
bool tuh_deinit(uint8_t rhport);
@@ -149,12 +161,10 @@ extern void hcd_int_handler(uint8_t rhport, bool in_isr);
#endif
// Interrupt handler alias to HCD with in_isr as optional parameter
-// - tuh_int_handler(rhport) --> hcd_int_handler(rhport, true)
-// - tuh_int_handler(rhport, in_isr) --> hcd_int_handler(rhport, in_isr)
-// Note: this is similar to TU_VERIFY(), _GET_3RD_ARG() is defined in tusb_verify.h
-#define _tuh_int_handler_1arg(_rhport) hcd_int_handler(_rhport, true)
-#define _tuh_int_hanlder_2arg(_rhport, _in_isr) hcd_int_handler(_rhport, _in_isr)
-#define tuh_int_handler(...) _GET_3RD_ARG(__VA_ARGS__, _tuh_int_hanlder_2arg, _tuh_int_handler_1arg, _dummy)(__VA_ARGS__)
+#define _tuh_int_handler_arg0() TU_VERIFY_STATIC(false, "tuh_int_handler() must have 1 or 2 arguments")
+#define _tuh_int_handler_arg1(_rhport) hcd_int_handler(_rhport, true)
+#define _tuh_int_handler_arg2(_rhport, _in_isr) hcd_int_handler(_rhport, _in_isr)
+#define tuh_int_handler(...) TU_FUNC_OPTIONAL_ARG(_tuh_int_handler, __VA_ARGS__)
// Check if roothub port is initialized and active as a host
bool tuh_rhport_is_active(uint8_t rhport);
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index f1f05f353e..a3a0f3a3fe 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -78,7 +78,7 @@ typedef struct
// _int_set is not used with an RTOS
#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
static _type _name##_##buf[_depth];\
- osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, _OSAL_Q_NAME(_name) };
+ osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, _OSAL_Q_NAME(_name) }
//--------------------------------------------------------------------+
// TASK API
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 39afb7505e..c5e9242668 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -168,13 +168,14 @@ enum {
};
enum {
- MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame
+ MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame to save CPU/SPI bus usage
};
enum {
EP_STATE_IDLE = 0,
EP_STATE_COMPLETE = 1,
- EP_STATE_ATTEMPT_1 = 2, // pending 1st attempt
+ EP_STATE_ABORTING = 2,
+ EP_STATE_ATTEMPT_1 = 3, // Number of attempts to transfer in a frame. Incremented after each NAK
EP_STATE_ATTEMPT_MAX = 15
};
@@ -182,17 +183,20 @@ enum {
//
//--------------------------------------------------------------------+
+typedef struct TU_ATTR_PACKED {
+ uint8_t ep_num : 4;
+ uint8_t is_setup : 1;
+ uint8_t is_out : 1;
+ uint8_t is_iso : 1;
+} hxfr_bm_t;
+
+TU_VERIFY_STATIC(sizeof(hxfr_bm_t) == 1, "size is not correct");
+
typedef struct {
uint8_t daddr;
- union { ;
- struct TU_ATTR_PACKED {
- uint8_t ep_num : 4;
- uint8_t is_setup : 1;
- uint8_t is_out : 1;
- uint8_t is_iso : 1;
- }hxfr_bm;
-
+ union {
+ hxfr_bm_t hxfr_bm;
uint8_t hxfr;
};
@@ -218,7 +222,16 @@ typedef struct {
uint8_t hien;
uint8_t mode;
uint8_t peraddr;
- uint8_t hxfr;
+ union {
+ hxfr_bm_t hxfr_bm;
+ uint8_t hxfr;
+ };
+
+ // owner of data in SNDFIFO, for retrying NAKed without re-writing to FIFO
+ struct {
+ uint8_t daddr;
+ uint8_t hxfr;
+ }sndfifo_owner;
atomic_flag busy; // busy transferring
@@ -316,33 +329,9 @@ bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_is
return ret;
}
-static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) {
- uint8_t hirq;
- reg |= CMDBYTE_WRITE;
-
- max3421_spi_lock(rhport, in_isr);
-
- tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1);
- _hcd_data.hirq = hirq;
- tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
-
- max3421_spi_unlock(rhport, in_isr);
-}
-
-static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
- uint8_t hirq;
- uint8_t const reg = RCVVFIFO_ADDR;
-
- max3421_spi_lock(rhport, in_isr);
-
- tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1);
- _hcd_data.hirq = hirq;
- tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
-
- max3421_spi_unlock(rhport, in_isr);
-}
-
-//------------- register write helper -------------//
+//--------------------------------------------------------------------
+// Register helper
+//--------------------------------------------------------------------
TU_ATTR_ALWAYS_INLINE static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
reg_write(rhport, HIRQ_ADDR, data, in_isr);
// HIRQ write 1 is clear
@@ -376,6 +365,47 @@ TU_ATTR_ALWAYS_INLINE static inline void sndbc_write(uint8_t rhport, uint8_t dat
reg_write(rhport, SNDBC_ADDR, data, in_isr);
}
+//--------------------------------------------------------------------
+// FIFO access (receive, send, setup)
+//--------------------------------------------------------------------
+static void hwfifo_write(uint8_t rhport, uint8_t reg, const uint8_t* buffer, uint8_t len, bool in_isr) {
+ uint8_t hirq;
+ reg |= CMDBYTE_WRITE;
+
+ max3421_spi_lock(rhport, in_isr);
+
+ tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1);
+ _hcd_data.hirq = hirq;
+ tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
+
+ max3421_spi_unlock(rhport, in_isr);
+}
+
+// Write to SNDFIFO if len > 0 and update SNDBC
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_send(uint8_t rhport, const uint8_t* buffer, uint8_t len, bool in_isr) {
+ if (len) {
+ hwfifo_write(rhport, SNDFIFO_ADDR, buffer, len, in_isr);
+ }
+ sndbc_write(rhport, len, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_setup(uint8_t rhport, const uint8_t* buffer, bool in_isr) {
+ hwfifo_write(rhport, SUDFIFO_ADDR, buffer, 8, in_isr);
+}
+
+static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
+ uint8_t hirq;
+ uint8_t const reg = RCVVFIFO_ADDR;
+
+ max3421_spi_lock(rhport, in_isr);
+
+ tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1);
+ _hcd_data.hirq = hirq;
+ tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
+
+ max3421_spi_unlock(rhport, in_isr);
+}
+
//--------------------------------------------------------------------+
// Endpoint helper
//--------------------------------------------------------------------+
@@ -416,7 +446,7 @@ static void free_ep(uint8_t daddr) {
}
}
-// Check if endpoint has an queued transfer and not reach max NAK
+// Check if endpoint has a queued transfer and not reach max NAK in this frame
TU_ATTR_ALWAYS_INLINE static inline bool is_ep_pending(max3421_ep_t const * ep) {
uint8_t const state = ep->state;
return ep->packet_size && (state >= EP_STATE_ATTEMPT_1) &&
@@ -459,12 +489,13 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
_tuh_cfg = cfg->max3421;
+ _tuh_cfg.max_nak = tu_min8(_tuh_cfg.max_nak, EP_STATE_ATTEMPT_MAX-EP_STATE_ATTEMPT_1);
return true;
}
// Initialize controller to host mode
-bool hcd_init(uint8_t rhport) {
- (void) rhport;
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
tuh_max3421_int_api(rhport, false);
@@ -479,13 +510,16 @@ bool hcd_init(uint8_t rhport) {
_hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
#endif
+ // NOTE: driver does not seem to work without nRST pin signal
+
// full duplex, interrupt negative edge
reg_write(rhport, PINCTL_ADDR, _tuh_cfg.pinctl | PINCTL_FDUPSPI, false);
// v1 is 0x01, v2 is 0x12, v3 is 0x13
+ // Note: v1 and v2 has host OUT errata whose workaround is not implemented in this driver
uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
- TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
TU_LOG2_HEX(revision);
+ TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
// reset
reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
@@ -611,22 +645,45 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
return true;
}
+/* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes.
+ * Then the microcontroller writes the SNDBC register, which this does three things:
+ * 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send.
+ * 2. Connects the SNDFIFO and SNDBC register to the USB logic for USB transmission.
+ * 3. Clears the SNDBAVIRQ interrupt flag. If the second FIFO is available for µC loading, the SNDBAVIRQ immediately re-asserts.
+
+ +-----------+
+ --->| SNDBC-A |
+ / | SNDFIFO-A |
+ / +-----------+
+ +------+ +-------------+ / +----------+
+ | MCU |------>| R2: SNDFIFO |---- << Write R7 Flip >> ---| MAX3241E |
+ |(hcd) | | R7: SNDBC | / | SIE |
+ +------+ +-------------+ / +----------+
+ +-----------+ /
+ | SNDBC-B | /
+ | SNDFIFO-B |<---
+ +-----------+
+ Note: xact_out() is called when starting a new transfer, continue a transfer (isr) or retry a transfer (NAK)
+ For NAK retry, we do not need to write to FIFO or SNDBC register again.
+*/
static void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
// Page 12: Programming BULK-OUT Transfers
- // TODO double buffered
+ // TODO: double buffering for ISO transfer
if (switch_ep) {
peraddr_write(rhport, ep->daddr, in_isr);
-
- uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+ const uint8_t hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
reg_write(rhport, HCTL_ADDR, hctl, in_isr);
}
- uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
- TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
- if (xact_len) {
- fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
+ // Only write to sndfifo and sdnbc register if it is not a NAKed retry
+ if (!(ep->daddr == _hcd_data.sndfifo_owner.daddr && ep->hxfr == _hcd_data.sndfifo_owner.hxfr)) {
+ // skip SNDBAV IRQ check, overwrite sndfifo if needed
+ const uint8_t xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+ hwfifo_send(rhport, ep->buf, xact_len, in_isr);
}
- sndbc_write(rhport, xact_len, in_isr);
+ _hcd_data.sndfifo_owner.daddr = ep->daddr;
+ _hcd_data.sndfifo_owner.hxfr = ep->hxfr;
+
hxfr_write(rhport, ep->hxfr, in_isr);
}
@@ -644,7 +701,7 @@ static void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_is
static void xact_setup(uint8_t rhport, max3421_ep_t *ep, bool in_isr) {
peraddr_write(rhport, ep->daddr, in_isr);
- fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr);
+ hwfifo_setup(rhport, ep->buf, in_isr);
hxfr_write(rhport, HXFR_SETUP, in_isr);
}
@@ -658,7 +715,7 @@ static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool
// status
if (ep->buf == NULL || ep->total_len == 0) {
- uint8_t const hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN));
+ const uint8_t hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN));
peraddr_write(rhport, ep->daddr, in_isr);
hxfr_write(rhport, hxfr, in_isr);
return;
@@ -676,7 +733,6 @@ static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool
bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
uint8_t const ep_num = tu_edpt_number(ep_addr);
uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
-
max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
TU_VERIFY(ep);
@@ -700,14 +756,19 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
return true;
}
-// Abort a queued transfer. Note: it can only abort transfer that has not been started
-// Return true if a queued transfer is aborted, false if there is no transfer to abort
-bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
- (void) rhport;
- (void) dev_addr;
- (void) ep_addr;
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
+ max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
+ TU_VERIFY(ep);
- return false;
+ if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) {
+ hcd_int_disable(rhport);
+ ep->state = EP_STATE_ABORTING;
+ hcd_int_enable(rhport);
+ }
+
+ return true;
}
// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
@@ -815,46 +876,41 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
}
static void handle_xfer_done(uint8_t rhport, bool in_isr) {
- uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
- uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
-
- uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
- uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
- uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
+ const uint8_t hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
+ const uint8_t hresult = hrsl & HRSL_RESULT_MASK;
+ const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num;
+ const uint8_t hxfr_type = _hcd_data.hxfr & 0xf0;
+ const uint8_t ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
TU_VERIFY(ep, );
xfer_result_t xfer_result;
switch(hresult) {
- case HRSL_SUCCESS:
- xfer_result = XFER_RESULT_SUCCESS;
- break;
-
- case HRSL_STALL:
- xfer_result = XFER_RESULT_STALLED;
- break;
-
case HRSL_NAK:
- if (ep_num == 0) {
- // control endpoint -> retry immediately
- hxfr_write(rhport, _hcd_data.hxfr, in_isr);
+ if (ep->state == EP_STATE_ABORTING) {
+ ep->state = EP_STATE_IDLE;
} else {
- if (ep->state < EP_STATE_ATTEMPT_MAX) {
+ if (ep_num == 0) {
+ // control endpoint -> retry immediately and return
+ hxfr_write(rhport, _hcd_data.hxfr, in_isr);
+ return;
+ }
+ if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) {
ep->state++;
}
+ }
- max3421_ep_t * next_ep = find_next_pending_ep(ep);
- if (ep == next_ep) {
- // this endpoint is only one pending -> retry immediately
- hxfr_write(rhport, _hcd_data.hxfr, in_isr);
- } else if (next_ep) {
- // switch to next pending endpoint TODO could have issue with double buffered if not clear previously out data
- xact_generic(rhport, next_ep, true, in_isr);
- } else {
- // no more pending in this frame -> clear busy
- atomic_flag_clear(&_hcd_data.busy);
- }
+ max3421_ep_t * next_ep = find_next_pending_ep(ep);
+ if (ep == next_ep) {
+ // this endpoint is only one pending -> retry immediately
+ hxfr_write(rhport, _hcd_data.hxfr, in_isr);
+ } else if (next_ep) {
+ // switch to next pending endpoint
+ xact_generic(rhport, next_ep, true, in_isr);
+ } else {
+ // no more pending in this frame -> clear busy
+ atomic_flag_clear(&_hcd_data.busy);
}
return;
@@ -862,6 +918,14 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
// occurred when initialized without any pending transfer. Skip for now
return;
+ case HRSL_SUCCESS:
+ xfer_result = XFER_RESULT_SUCCESS;
+ break;
+
+ case HRSL_STALL:
+ xfer_result = XFER_RESULT_STALLED;
+ break;
+
default:
TU_LOG3("HRSL: %02X\r\n", hrsl);
xfer_result = XFER_RESULT_FAILED;
@@ -885,11 +949,15 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
if (ep->state == EP_STATE_COMPLETE) {
xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
}else {
- // more to transfer
- hxfr_write(rhport, _hcd_data.hxfr, in_isr);
+ hxfr_write(rhport, _hcd_data.hxfr, in_isr); // more to transfer
}
} else {
// SETUP or OUT transfer
+
+ // clear sndfifo owner since data is sent
+ _hcd_data.sndfifo_owner.daddr = 0xff;
+ _hcd_data.sndfifo_owner.hxfr = 0xff;
+
uint8_t xact_len;
if (hxfr_type & HXFR_SETUP) {
@@ -906,8 +974,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
} else {
- // more to transfer
- xact_out(rhport, ep, false, in_isr);
+ xact_out(rhport, ep, false, in_isr); // more to transfer
}
}
}
@@ -940,9 +1007,8 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
if (hirq & HIRQ_FRAME_IRQ) {
_hcd_data.frame_count++;
+ // reset all endpoints nak counter, retry with 1st pending ep.
max3421_ep_t* ep_retry = NULL;
-
- // reset all endpoints attempt counter
for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
max3421_ep_t* ep = &_hcd_data.ep[i];
if (ep->packet_size && ep->state > EP_STATE_ATTEMPT_1) {
@@ -968,16 +1034,16 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
// not call this handler again. So we need to loop until all IRQ are cleared
while (hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ)) {
if (hirq & HIRQ_RCVDAV_IRQ) {
- uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+ const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num;
max3421_ep_t* ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
uint8_t xact_len = 0;
// RCVDAV_IRQ can trigger 2 times (dual buffered)
while (hirq & HIRQ_RCVDAV_IRQ) {
- uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr);
+ const uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr);
xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
if (xact_len) {
- fifo_read(rhport, ep->buf, xact_len, in_isr);
+ hwfifo_receive(rhport, ep->buf, xact_len, in_isr);
ep->buf += xact_len;
ep->xferred_len += xact_len;
}
@@ -1002,7 +1068,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
// clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
hirq &= (uint8_t) ~HIRQ_SNDBAV_IRQ;
- if ( hirq ) {
+ if (hirq) {
hirq_write(rhport, hirq, in_isr);
}
}
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index f02415904f..34a8be3b66 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -517,8 +517,8 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
*------------------------------------------------------------------*/
// Initialize controller to device mode
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
TU_LOG2("FT9xx initialisation\r\n");
_dcd_ft9xx_attach();
@@ -526,6 +526,7 @@ void dcd_init(uint8_t rhport)
interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft9xx_usbd_ISR);
dcd_connect(rhport);
+ return true;
}
// Enable device interrupt
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
index 02f813ab5b..11ddb683f3 100644
--- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -267,9 +267,9 @@ static void process_bus_resume(uint8_t rhport)
/*------------------------------------------------------------------*/
/* Device API
*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
// save crystal-less setting (if available)
#if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
@@ -296,6 +296,7 @@ void dcd_init(uint8_t rhport)
dcd_connect(rhport);
// NVIC_ClearPendingIRQ(CIFS_IRQN);
+ return true;
}
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index f9ec666e5a..430a0aad10 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -234,13 +234,13 @@ static void bus_reset(uint8_t rhport)
dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
}
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
tu_memclr(&_dcd_data, sizeof(dcd_data_t));
ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
- TU_ASSERT(ci_ep_count(dcd_reg) <= TUP_DCD_ENDPOINT_MAX, );
+ TU_ASSERT(ci_ep_count(dcd_reg) <= TUP_DCD_ENDPOINT_MAX);
// Reset controller
dcd_reg->USBCMD |= USBCMD_RESET;
@@ -268,6 +268,8 @@ void dcd_init(uint8_t rhport)
usbcmd |= USBCMD_RUN_STOP; // run
dcd_reg->USBCMD = usbcmd;
+
+ return true;
}
void dcd_int_enable(uint8_t rhport)
@@ -309,10 +311,12 @@ void dcd_disconnect(uint8_t rhport)
void dcd_sof_enable(uint8_t rhport, bool en)
{
- (void) rhport;
- (void) en;
-
- // TODO implement later
+ ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
+ if (en) {
+ dcd_reg->USBINTR |= INTR_SOF;
+ } else {
+ dcd_reg->USBINTR &= ~INTR_SOF;
+ }
}
//--------------------------------------------------------------------+
@@ -679,7 +683,8 @@ void dcd_int_handler(uint8_t rhport)
if (int_status & INTR_SOF)
{
- dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+ const uint32_t frame = dcd_reg->FRINDEX;
+ dcd_event_sof(rhport, frame, true);
}
}
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 462cbd3013..14f8acb45e 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -70,7 +70,8 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
// Controller API
//--------------------------------------------------------------------+
-bool hcd_init(uint8_t rhport) {
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
ci_hs_regs_t *hcd_reg = CI_HS_REG(rhport);
// Reset controller
@@ -82,7 +83,9 @@ bool hcd_init(uint8_t rhport) {
// LPC18XX/43XX need to set VBUS Power Select to HIGH
// RHPORT1 is fullspeed only (need external PHY for Highspeed)
hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
- if ( rhport == 1 ) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+ if (rhport == 1) {
+ hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+ }
#else
hcd_reg->USBMODE = USBMODE_CM_HOST;
#endif
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index d1e85c2df1..887f59588d 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -804,15 +804,16 @@ static void handle_ep0_nak(void)
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
_dcd.init_called = true;
- if (_dcd.vbus_present)
- {
+ if (_dcd.vbus_present) {
dcd_connect(rhport);
}
+
+ return true;
}
void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index bfc0baa567..1b6aae026b 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -31,7 +31,8 @@
#if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) || (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && CFG_TUD_ENABLED)
// Espressif
-#include "xtensa_api.h"
+#include "xtensa/xtensa_api.h"
+
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "soc/dport_reg.h"
@@ -171,8 +172,8 @@ static void enum_done_processing(void)
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
ESP_LOGV(TAG, "DCD init - Start");
// A. Disconnect
@@ -206,9 +207,11 @@ void dcd_init(uint8_t rhport)
USB_USBRSTMSK_M |
USB_ENUMDONEMSK_M |
USB_RESETDETMSK_M |
+ USB_WKUPINT_M |
USB_DISCONNINTMSK_M; // host most only
dcd_connect(rhport);
+ return true;
}
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index a817c5d6e8..4fce08dd9a 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -2,6 +2,7 @@
* The MIT License (MIT)
*
* Copyright (c) 2021 Koji KITAYAMA
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -26,8 +27,10 @@
#include "tusb_option.h"
-#if CFG_TUD_ENABLED && \
- TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_MUSB)
+
+#define MUSB_DEBUG 2
+#define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport])
#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
/* GCC warns that an address may be unaligned, even though
@@ -35,48 +38,30 @@
_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
#endif
+#include "musb_type.h"
#include "device/dcd.h"
-#if TU_CHECK_MCU(OPT_MCU_MSP432E4)
- #include "musb_msp432e.h"
-
-#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129)
- #include "musb_tm4c.h"
-
- // HACK generalize later
- #include "musb_type.h"
- #define FIFO0_WORD FIFO0
- #define FIFO1_WORD FIFO1
-
+// Following symbols must be defined by port header
+// - musb_dcd_int_enable/disable/clear/get_enable
+// - musb_dcd_int_handler_enter/exit
+#if defined(TUP_USBIP_MUSB_TI)
+ #include "musb_ti.h"
+#elif defined(TUP_USBIP_MUSB_ADI)
+ #include "musb_max32.h"
#else
- #error "Unsupported MCUs"
+ #error "Unsupported MCU"
#endif
/*------------------------------------------------------------------
* MACRO TYPEDEF CONSTANT ENUM DECLARATION
*------------------------------------------------------------------*/
-#define REQUEST_TYPE_INVALID (0xFFu)
-typedef struct {
- uint_fast16_t beg; /* offset of including first element */
- uint_fast16_t end; /* offset of excluding the last element */
-} free_block_t;
-
-typedef struct TU_ATTR_PACKED {
- uint16_t TXMAXP;
- uint8_t TXCSRL;
- uint8_t TXCSRH;
- uint16_t RXMAXP;
- uint8_t RXCSRL;
- uint8_t RXCSRH;
- uint16_t RXCOUNT;
- uint16_t RESERVED[3];
-} hw_endpoint_t;
+#define REQUEST_TYPE_INVALID (0xFFu)
typedef union {
- uint8_t u8;
- uint16_t u16;
- uint32_t u32;
+ volatile uint8_t u8;
+ volatile uint16_t u16;
+ volatile uint32_t u32;
} hw_fifo_t;
typedef struct TU_ATTR_PACKED
@@ -92,134 +77,97 @@ typedef struct
uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
int8_t status_out;
pipe_state_t pipe0;
- pipe_state_t pipe[2][7]; /* pipe[direction][endpoint number - 1] */
+ pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX-1]; /* pipe[direction][endpoint number - 1] */
uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */
} dcd_data_t;
-/*------------------------------------------------------------------
- * INTERNAL OBJECT & FUNCTION DECLARATION
- *------------------------------------------------------------------*/
static dcd_data_t _dcd;
+//--------------------------------------------------------------------
+// HW FIFO Helper
+// Note: Index register is already set by caller
+//--------------------------------------------------------------------
-static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
-{
- free_block_t *cur = beg;
- for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ;
- return cur;
-}
+#if MUSB_CFG_DYNAMIC_FIFO
-static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size)
-{
- free_block_t *p = find_containing_block(blks, blks + num, addr);
- TU_ASSERT(p != blks + num, -2);
- if (p->beg == addr) {
- /* Shrink block */
- p->beg = addr + size;
- if (p->beg != p->end) return 0;
- /* remove block */
- free_block_t *end = blks + num;
- while (p + 1 < end) {
- *p = *(p + 1);
- ++p;
- }
- return -1;
- } else {
- /* Split into 2 blocks */
- free_block_t tmp = {
- .beg = addr + size,
- .end = p->end
- };
- p->end = addr;
- if (p->beg == p->end) {
- if (tmp.beg != tmp.end) {
- *p = tmp;
- return 0;
- }
- /* remove block */
- free_block_t *end = blks + num;
- while (p + 1 < end) {
- *p = *(p + 1);
- ++p;
- }
- return -1;
- }
- if (tmp.beg == tmp.end) return 0;
- blks[num] = tmp;
- return 1;
+// musb is configured to use dynamic FIFO sizing.
+// FF Size is encodded: 1 << (fifo_size[3:0] + 3) = 8 << fifo_size[3:0]
+// FF Address is 8*ff_addr[12:0]
+// First 64 bytes are reserved for EP0
+static uint32_t alloced_fifo_bytes;
+
+// ffsize is log2(mps) - 3 (round up)
+TU_ATTR_ALWAYS_INLINE static inline uint8_t hwfifo_byte2size(uint16_t nbytes) {
+ uint8_t ffsize = 28 - tu_min8(28, __builtin_clz(nbytes));
+ if ((8u << ffsize) < nbytes) {
+ ++ffsize;
}
+ return ffsize;
}
-static inline unsigned free_block_size(free_block_t const *blk)
-{
- return blk->end - blk->beg;
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned is_rx) {
+ (void) epnum;
+ musb->fifo_size[is_rx] = 0;
+ musb->fifo_addr[is_rx] = 0;
}
-#if 0
-static inline void print_block_list(free_block_t const *blk, unsigned num)
-{
- TU_LOG1("*************\r\n");
- for (unsigned i = 0; i < num; ++i) {
- TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end);
- ++blk;
+TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned is_rx, unsigned mps,
+ bool double_packet) {
+ (void) epnum;
+ uint8_t ffsize = hwfifo_byte2size(mps);
+ mps = 8 << ffsize; // round up to the next power of 2
+
+ if (double_packet) {
+ ffsize |= MUSB_FIFOSZ_DOUBLE_PACKET;
+ mps <<= 1;
}
+
+ TU_ASSERT(alloced_fifo_bytes + mps <= MUSB_CFG_DYNAMIC_FIFO_SIZE);
+ musb->fifo_addr[is_rx] = alloced_fifo_bytes / 8;
+ musb->fifo_size[is_rx] = ffsize;
+
+ alloced_fifo_bytes += mps;
+ return true;
}
+
#else
-#define print_block_list(a,b)
-#endif
-static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
-{
- free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)];
- unsigned num_blocks = 1;
-
- /* Initialize free memory block list */
- free_blocks[0].beg = 64 / 8;
- free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
- for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
- uint_fast16_t addr;
- int num;
- USB0->EPIDX = i;
- addr = USB0->TXFIFOADD;
- if (addr) {
- unsigned sz = USB0->TXFIFOSZ;
- unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0);
- num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
- TU_ASSERT(-2 < num, 0);
- num_blocks += num;
- print_block_list(free_blocks, num_blocks);
- }
- addr = USB0->RXFIFOADD;
- if (addr) {
- unsigned sz = USB0->RXFIFOSZ;
- unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0);
- num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
- TU_ASSERT(-2 < num, 0);
- num_blocks += num;
- print_block_list(free_blocks, num_blocks);
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned is_rx) {
+ (void) musb; (void) epnum; (void) is_rx;
+ // nothing to do for static FIFO
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned is_rx, unsigned mps,
+ bool double_packet) {
+ (void) epnum; (void) mps;
+ if (!double_packet) {
+ #if defined(TUP_USBIP_MUSB_ADI)
+ musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx);
+ #else
+ if (is_rx) {
+ musb->rx_doulbe_packet_disable |= 1u << epnum;
+ } else {
+ musb->tx_double_packet_disable |= 1u << epnum;
}
+ #endif
}
- print_block_list(free_blocks, num_blocks);
- /* Find the best fit memory block */
- uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3;
- free_block_t const *min = NULL;
- uint_fast16_t min_sz = 0xFFFFu;
- free_block_t const *end = &free_blocks[num_blocks];
- for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) {
- uint_fast16_t sz = free_block_size(cur);
- if (sz < size_in_8byte_unit) continue;
- if (size_in_8byte_unit == sz) return cur->beg;
- if (sz < min_sz) min = cur;
- }
- TU_ASSERT(min, 0);
- return min->beg;
+ return true;
}
-static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1)
-{
- volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1);
- return regs + epnum_minus1;
+#endif
+
+// Flush FIFO and clear data toggle
+TU_ATTR_ALWAYS_INLINE static inline void hwfifo_flush(musb_regs_t* musb, unsigned epnum, unsigned is_rx, bool clear_dtog) {
+ (void) epnum;
+ const uint8_t csrl_dtog = clear_dtog ? MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx) : 0;
+ musb_ep_maxp_csr_t* maxp_csr = &musb->indexed_csr.maxp_csr[is_rx];
+ // may need to flush twice for double packet
+ for (unsigned i=0; i<2; i++) {
+ if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) {
+ maxp_csr->csrl = MUSB_CSRL_FLUSH_FIFO(is_rx) | csrl_dtog;
+ }
+ }
}
static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -284,11 +232,14 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
ops[dir].tu_fifo_advance(f, total_len - rem);
}
-static void process_setup_packet(uint8_t rhport)
-{
+static void process_setup_packet(uint8_t rhport) {
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+
+ // Read setup packet
uint32_t *p = (void*)&_dcd.setup_packet;
- p[0] = USB0->FIFO0_WORD;
- p[1] = USB0->FIFO0_WORD;
+ volatile uint32_t *fifo_ptr = &musb_regs->fifo[0];
+ p[0] = *fifo_ptr;
+ p[1] = *fifo_ptr;
_dcd.pipe0.buf = NULL;
_dcd.pipe0.length = 0;
@@ -299,12 +250,16 @@ static void process_setup_packet(uint8_t rhport)
_dcd.remaining_ctrl = len;
const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType);
/* Clear RX FIFO and reverse the transaction direction */
- if (len && dir_in) USB0->CSRL0 = USB_CSRL0_RXRDYC;
+ if (len && dir_in) {
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
+ ep_csr->csr0l = MUSB_CSRL0_RXRDYC;
+ }
}
-static bool handle_xfer_in(uint_fast8_t ep_addr)
+static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr)
{
- unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+ unsigned epnum = tu_edpt_number(ep_addr);
+ unsigned epnum_minus1 = epnum - 1;
pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
const unsigned rem = pipe->remaining;
@@ -313,44 +268,49 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
return true;
}
- volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
- const unsigned mps = regs->TXMAXP;
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum);
+ const unsigned mps = ep_csr->tx_maxp;
const unsigned len = TU_MIN(mps, rem);
void *buf = pipe->buf;
+ volatile void *fifo_ptr = &musb_regs->fifo[epnum];
// TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem);
if (len) {
if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
- pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN);
+ pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN);
} else {
- pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
+ pipe_write_packet(buf, fifo_ptr, len);
pipe->buf = buf + len;
}
pipe->remaining = rem - len;
}
- regs->TXCSRL = USB_TXCSRL1_TXRDY;
- // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+ ep_csr->tx_csrl = MUSB_TXCSRL1_TXRDY;
+ // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum, ep_csr->tx_csrl, rem - len);
return false;
}
-static bool handle_xfer_out(uint_fast8_t ep_addr)
+static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr)
{
- unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+ unsigned epnum = tu_edpt_number(ep_addr);
+ unsigned epnum_minus1 = epnum - 1;
pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
- volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
- // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL);
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum);
+ // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, ep_csr->rx_csrl);
- TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY);
+ TU_ASSERT(ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY);
- const unsigned mps = regs->RXMAXP;
+ const unsigned mps = ep_csr->rx_maxp;
const unsigned rem = pipe->remaining;
- const unsigned vld = regs->RXCOUNT;
+ const unsigned vld = ep_csr->rx_count;
const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
void *buf = pipe->buf;
+ volatile void *fifo_ptr = &musb_regs->fifo[epnum];
if (len) {
if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) {
- pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_OUT);
+ pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT);
} else {
- pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
+ pipe_read_packet(buf, fifo_ptr, len);
pipe->buf = buf + len;
}
pipe->remaining = rem - len;
@@ -359,15 +319,14 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
pipe->buf = NULL;
return NULL != buf;
}
- regs->RXCSRL = 0; /* Clear RXRDY bit */
+ ep_csr->rx_csrl = 0; /* Clear RXRDY bit */
return false;
}
static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
{
- (void)rhport;
-
- unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+ unsigned epnum = tu_edpt_number(ep_addr);
+ unsigned epnum_minus1 = epnum - 1;
unsigned dir_in = tu_edpt_dir(ep_addr);
pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1];
@@ -376,10 +335,11 @@ static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16
pipe->remaining = total_bytes;
if (dir_in) {
- handle_xfer_in(ep_addr);
+ handle_xfer_in(rhport, ep_addr);
} else {
- volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
- if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0;
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum);
+ if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) ep_csr->rx_csrl = 0;
}
return true;
}
@@ -388,7 +348,8 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
{
(void)rhport;
TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */
-
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
const unsigned req = _dcd.setup_packet.bmRequestType;
TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0);
@@ -399,7 +360,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
* may have already finished and received the next setup packet
* without calling this function, so we have no choice but to
* invoke the callback function of status packet here. */
- // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0);
+ // TU_LOG1(" STATUS OUT ep_csr->csr0l = %x\r\n", ep_csr->csr0l);
_dcd.status_out = 0;
if (req == REQUEST_TYPE_INVALID) {
dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
@@ -415,8 +376,9 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
TU_ASSERT(total_bytes <= _dcd.remaining_ctrl);
const unsigned rem = _dcd.remaining_ctrl;
const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes);
+ volatile void *fifo_ptr = &musb_regs->fifo[0];
if (dir_in) {
- pipe_write_packet(buffer, &USB0->FIFO0_WORD, len);
+ pipe_write_packet(buffer, fifo_ptr, len);
_dcd.pipe0.buf = buffer + len;
_dcd.pipe0.length = len;
@@ -427,45 +389,48 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */
_dcd.status_out = 1;
/* Flush TX FIFO and reverse the transaction direction. */
- USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
+ ep_csr->csr0l = MUSB_CSRL0_TXRDY | MUSB_CSRL0_DATAEND;
} else {
- USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
+ ep_csr->csr0l = MUSB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
}
- // TU_LOG1(" IN USB0->CSRL0 = %x\r\n", USB0->CSRL0);
+ // TU_LOG1(" IN ep_csr->csr0l = %x\r\n", ep_csr->csr0l);
} else {
- // TU_LOG1(" OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0);
+ // TU_LOG1(" OUT ep_csr->csr0l = %x\r\n", ep_csr->csr0l);
_dcd.pipe0.buf = buffer;
_dcd.pipe0.length = len;
_dcd.pipe0.remaining = len;
- USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
+ ep_csr->csr0l = MUSB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
}
} else if (dir_in) {
- // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\r\n", USB0->CSRL0);
+ // TU_LOG1(" STATUS IN ep_csr->csr0l = %x\r\n", ep_csr->csr0l);
_dcd.pipe0.buf = NULL;
_dcd.pipe0.length = 0;
_dcd.pipe0.remaining = 0;
/* Clear RX FIFO and reverse the transaction direction */
- USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
+ ep_csr->csr0l = MUSB_CSRL0_RXRDYC | MUSB_CSRL0_DATAEND;
}
return true;
}
static void process_ep0(uint8_t rhport)
{
- uint_fast8_t csrl = USB0->CSRL0;
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
+ uint_fast8_t csrl = ep_csr->csr0l;
- // TU_LOG1(" EP0 USB0->CSRL0 = %x\r\n", csrl);
+ // TU_LOG1(" EP0 ep_csr->csr0l = %x\r\n", csrl);
+ // 21.1.5: endpoint 0 service routine as peripheral
- if (csrl & USB_CSRL0_STALLED) {
+ if (csrl & MUSB_CSRL0_STALLED) {
/* Returned STALL packet to HOST. */
- USB0->CSRL0 = 0; /* Clear STALL */
+ ep_csr->csr0l = 0; /* Clear STALL */
return;
}
unsigned req = _dcd.setup_packet.bmRequestType;
- if (csrl & USB_CSRL0_SETEND) {
+ if (csrl & MUSB_CSRL0_SETEND) {
TU_LOG1(" ABORT by the next packets\r\n");
- USB0->CSRL0 = USB_CSRL0_SETENDC;
+ ep_csr->csr0l = MUSB_CSRL0_SETENDC;
if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
/* DATA stage was aborted by receiving STATUS or SETUP packet. */
_dcd.pipe0.buf = NULL;
@@ -476,23 +441,24 @@ static void process_ep0(uint8_t rhport)
XFER_RESULT_SUCCESS, true);
}
req = REQUEST_TYPE_INVALID;
- if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */
+ if (!(csrl & MUSB_CSRL0_RXRDY)) return; /* Received SETUP packet */
}
- if (csrl & USB_CSRL0_RXRDY) {
+ if (csrl & MUSB_CSRL0_RXRDY) {
/* Received SETUP or DATA OUT packet */
if (req == REQUEST_TYPE_INVALID) {
/* SETUP */
- TU_ASSERT(sizeof(tusb_control_request_t) == USB0->COUNT0,);
+ TU_ASSERT(sizeof(tusb_control_request_t) == ep_csr->count0,);
process_setup_packet(rhport);
return;
}
if (_dcd.pipe0.buf) {
/* DATA OUT */
- const unsigned vld = USB0->COUNT0;
+ const unsigned vld = ep_csr->count0;
const unsigned rem = _dcd.pipe0.remaining;
const unsigned len = TU_MIN(TU_MIN(rem, 64), vld);
- pipe_read_packet(_dcd.pipe0.buf, &USB0->FIFO0_WORD, len);
+ volatile void *fifo_ptr = &musb_regs->fifo[0];
+ pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len);
_dcd.pipe0.remaining = rem - len;
_dcd.remaining_ctrl -= len;
@@ -512,7 +478,7 @@ static void process_ep0(uint8_t rhport)
/* STATUS IN */
if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) {
/* The address must be changed on completion of the control transfer. */
- USB0->FADDR = (uint8_t)_dcd.setup_packet.wValue;
+ musb_regs->faddr = (uint8_t)_dcd.setup_packet.wValue;
}
_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
dcd_event_xfer_complete(rhport,
@@ -534,118 +500,149 @@ static void process_ep0(uint8_t rhport)
static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
{
bool completed;
- const unsigned dir_in = tu_edpt_dir(ep_addr);
- const unsigned epn_minus1 = tu_edpt_number(ep_addr) - 1;
+ const unsigned dir_in = tu_edpt_dir(ep_addr);
+ const unsigned epn = tu_edpt_number(ep_addr);
+ const unsigned epn_minus1 = epn - 1;
- volatile hw_endpoint_t *regs = edpt_regs(epn_minus1);
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
if (dir_in) {
- // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL);
- if (regs->TXCSRL & USB_TXCSRL1_STALLED) {
- regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN);
+ // TU_LOG1(" TX CSRL%d = %x\r\n", epn, ep_csr->tx_csrl);
+ if (ep_csr->tx_csrl & MUSB_TXCSRL1_STALLED) {
+ ep_csr->tx_csrl &= ~(MUSB_TXCSRL1_STALLED | MUSB_TXCSRL1_UNDRN);
return;
}
- completed = handle_xfer_in(ep_addr);
+ completed = handle_xfer_in(rhport, ep_addr);
} else {
- // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL);
- if (regs->RXCSRL & USB_RXCSRL1_STALLED) {
- regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER);
+ // TU_LOG1(" RX CSRL%d = %x\r\n", epn, ep_csr->rx_csrl);
+ if (ep_csr->rx_csrl & MUSB_RXCSRL1_STALLED) {
+ ep_csr->rx_csrl &= ~(MUSB_RXCSRL1_STALLED | MUSB_RXCSRL1_OVER);
return;
}
- completed = handle_xfer_out(ep_addr);
+ completed = handle_xfer_out(rhport, ep_addr);
}
if (completed) {
- pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1];
+ pipe_state_t *pipe = &_dcd.pipe[dir_in][epn_minus1];
dcd_event_xfer_complete(rhport, ep_addr,
pipe->length - pipe->remaining,
XFER_RESULT_SUCCESS, true);
}
}
-static void process_bus_reset(uint8_t rhport)
-{
- /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF),
- * a control transfer state is SETUP or STATUS stage. */
+// Upon BUS RESET is detected, hardware havs already done:
+// faddr = 0, index = 0, flushes all ep fifos, clears all ep csr, enabled all ep interrupts
+static void process_bus_reset(uint8_t rhport) {
+ musb_regs_t* musb = MUSB_REGS(rhport);
+
+#if MUSB_CFG_DYNAMIC_FIFO
+ alloced_fifo_bytes = CFG_TUD_ENDPOINT0_SIZE;
+#endif
+
+ /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), a control transfer state is SETUP or STATUS stage. */
_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
_dcd.status_out = 0;
/* When pipe0.buf has not NULL, DATA stage works in progress. */
_dcd.pipe0.buf = NULL;
- USB0->TXIE = 1; /* Enable only EP0 */
- USB0->RXIE = 0;
+ musb->intr_txen = 1; /* Enable only EP0 */
+ musb->intr_rxen = 0;
/* Clear FIFO settings */
for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
- USB0->EPIDX = i;
- USB0->TXFIFOSZ = 0;
- USB0->TXFIFOADD = 0;
- USB0->RXFIFOSZ = 0;
- USB0->RXFIFOADD = 0;
+ musb->index = i;
+ hwfifo_reset(musb, i, 0);
+ hwfifo_reset(musb, i, 1);
}
- dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+ dcd_event_bus_reset(rhport, (musb->power & MUSB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true);
}
/*------------------------------------------------------------------
* Device API
*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
- (void)rhport;
- USB0->IE |= USB_IE_SUSPND;
- NVIC_ClearPendingIRQ(USB0_IRQn);
+#if CFG_TUSB_DEBUG >= MUSB_DEBUG
+void print_musb_info(musb_regs_t* musb_regs) {
+ // print version, epinfo, raminfo, config_data0, fifo_size
+ TU_LOG1("musb version = %u.%u\r\n", musb_regs->hwvers_bit.major, musb_regs->hwvers_bit.minor);
+ TU_LOG1("Number of endpoints: %u TX, %u RX\r\n", musb_regs->epinfo_bit.tx_ep_num, musb_regs->epinfo_bit.rx_ep_num);
+ TU_LOG1("RAM Info: %u DMA Channel, %u RAM address width\r\n", musb_regs->raminfo_bit.dma_channel, musb_regs->raminfo_bit.ram_bits);
+
+ musb_regs->index = 0;
+ TU_LOG1("config_data0 = 0x%x\r\n", musb_regs->indexed_csr.config_data0);
+#if MUSB_CFG_DYNAMIC_FIFO
+ TU_LOG1("Dynamic FIFO configuration\r\n");
+#else
+ for (uint8_t i=1; i <= musb_regs->epinfo_bit.tx_ep_num; i++) {
+ musb_regs->index = i;
+ TU_LOG1("FIFO %u Size: TX %u RX %u\r\n", i, musb_regs->indexed_csr.fifo_size_bit.tx, musb_regs->indexed_csr.fifo_size_bit.rx);
+ }
+#endif
+}
+#endif
+
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+
+#if CFG_TUSB_DEBUG >= MUSB_DEBUG
+ print_musb_info(musb_regs);
+#endif
+
+ musb_regs->intr_usben |= MUSB_IE_SUSPND;
+ musb_dcd_int_clear(rhport);
+ musb_dcd_phy_init(rhport);
dcd_connect(rhport);
+ return true;
}
-void dcd_int_enable(uint8_t rhport)
-{
- (void)rhport;
- NVIC_EnableIRQ(USB0_IRQn);
+void dcd_int_enable(uint8_t rhport) {
+ musb_dcd_int_enable(rhport);
}
-void dcd_int_disable(uint8_t rhport)
-{
- (void)rhport;
- NVIC_DisableIRQ(USB0_IRQn);
+void dcd_int_disable(uint8_t rhport) {
+ musb_dcd_int_disable(rhport);
}
// Receive Set Address request, mcu port must also include status IN response
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
- (void)rhport;
(void)dev_addr;
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0);
+
_dcd.pipe0.buf = NULL;
_dcd.pipe0.length = 0;
_dcd.pipe0.remaining = 0;
/* Clear RX FIFO to return ACK. */
- USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
+ ep_csr->csr0l = MUSB_CSRL0_RXRDYC | MUSB_CSRL0_DATAEND;
}
// Wake up host
-void dcd_remote_wakeup(uint8_t rhport)
-{
- (void)rhport;
- USB0->POWER |= USB_POWER_RESUME;
+void dcd_remote_wakeup(uint8_t rhport) {
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_regs->power |= MUSB_POWER_RESUME;
unsigned cnt = SystemCoreClock / 1000;
while (cnt--) __NOP();
- USB0->POWER &= ~USB_POWER_RESUME;
+ musb_regs->power &= ~MUSB_POWER_RESUME;
}
// Connect by enabling internal pull-up resistor on D+/D-
void dcd_connect(uint8_t rhport)
{
- (void)rhport;
- USB0->POWER |= USB_POWER_SOFTCONN;
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_regs->power |= TUD_OPT_HIGH_SPEED ? MUSB_POWER_HSENAB : 0;
+ musb_regs->power |= MUSB_POWER_SOFTCONN;
}
// Disconnect by disabling internal pull-up resistor on D+/D-
void dcd_disconnect(uint8_t rhport)
{
- (void)rhport;
- USB0->POWER &= ~USB_POWER_SOFTCONN;
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_regs->power &= ~MUSB_POWER_SOFTCONN;
}
void dcd_sof_enable(uint8_t rhport, bool en)
@@ -659,129 +656,119 @@ void dcd_sof_enable(uint8_t rhport, bool en)
//--------------------------------------------------------------------+
// Endpoint API
//--------------------------------------------------------------------+
+// static void edpt_setup(musb_regs_t* musb, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_size){
+// const unsigned epn = tu_edpt_number(ep_addr);
+// const unsigned dir_in = tu_edpt_dir(ep_addr);
+// }
// Configure endpoint's registers according to descriptor
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
-{
- (void) rhport;
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) {
+ const unsigned ep_addr = ep_desc->bEndpointAddress;
+ const unsigned epn = tu_edpt_number(ep_addr);
+ const unsigned dir_in = tu_edpt_dir(ep_addr);
+ const unsigned mps = tu_edpt_packet_size(ep_desc);
+
+ pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
+ pipe->buf = NULL;
+ pipe->length = 0;
+ pipe->remaining = 0;
+ musb_regs_t* musb = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn);
+ const uint8_t is_rx = 1 - dir_in;
+ musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx];
+
+ maxp_csr->maxp = mps;
+ maxp_csr->csrh = 0;
+#if MUSB_CFG_SHARED_FIFO
+ if (dir_in) {
+ maxp_csr->csrh |= MUSB_CSRH_TX_MODE;
+ }
+#endif
+
+ hwfifo_flush(musb, epn, is_rx, true);
+
+ TU_ASSERT(hwfifo_config(musb, epn, is_rx, mps, false));
+ musb->intren_ep[is_rx] |= TU_BIT(epn);
+
+ return true;
+}
+
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+ const unsigned epn = tu_edpt_number(ep_addr);
+ const unsigned dir_in = tu_edpt_dir(ep_addr);
+ musb_regs_t* musb = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn);
+ const uint8_t is_rx = 1 - dir_in;
+ ep_csr->maxp_csr[is_rx].csrh = 0;
+ return hwfifo_config(musb, epn, is_rx, largest_packet_size, true);
+}
+
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc ) {
const unsigned ep_addr = ep_desc->bEndpointAddress;
const unsigned epn = tu_edpt_number(ep_addr);
const unsigned dir_in = tu_edpt_dir(ep_addr);
- const unsigned xfer = ep_desc->bmAttributes.xfer;
const unsigned mps = tu_edpt_packet_size(ep_desc);
- TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX);
+ unsigned const ie = musb_dcd_get_int_enable(rhport);
+ musb_dcd_int_disable(rhport);
pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
pipe->buf = NULL;
pipe->length = 0;
pipe->remaining = 0;
- volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
- if (dir_in) {
- regs->TXMAXP = mps;
- regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0;
- if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
- regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
- else
- regs->TXCSRL = USB_TXCSRL1_CLRDT;
- USB0->TXIE |= TU_BIT(epn);
- } else {
- regs->RXMAXP = mps;
- regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0;
- if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
- regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
- else
- regs->RXCSRL = USB_RXCSRL1_CLRDT;
- USB0->RXIE |= TU_BIT(epn);
- }
-
- /* Setup FIFO */
- int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps));
- if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3;
- unsigned addr = find_free_memory(size_in_log2_minus3);
- TU_ASSERT(addr);
-
- USB0->EPIDX = epn;
+ musb_regs_t* musb = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn);
+ const uint8_t is_rx = 1 - dir_in;
+ musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx];
+
+ maxp_csr->maxp = mps;
+ maxp_csr->csrh |= MUSB_CSRH_ISO;
+#if MUSB_CFG_SHARED_FIFO
if (dir_in) {
- USB0->TXFIFOADD = addr;
- USB0->TXFIFOSZ = size_in_log2_minus3;
- } else {
- USB0->RXFIFOADD = addr;
- USB0->RXFIFOSZ = size_in_log2_minus3;
+ maxp_csr->csrh |= MUSB_CSRH_TX_MODE;
}
+#endif
+
+ hwfifo_flush(musb, epn, is_rx, true);
+
+#if MUSB_CFG_DYNAMIC_FIFO
+ // fifo space is already allocated, keep the address and just change packet size
+ musb->fifo_size[is_rx] = hwfifo_byte2size(mps) | MUSB_FIFOSZ_DOUBLE_PACKET;
+#endif
+
+ musb->intren_ep[is_rx] |= TU_BIT(epn);
+
+ if (ie) musb_dcd_int_enable(rhport);
return true;
}
void dcd_edpt_close_all(uint8_t rhport)
{
- (void) rhport;
- volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1;
- unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
- NVIC_DisableIRQ(USB0_IRQn);
- USB0->TXIE = 1; /* Enable only EP0 */
- USB0->RXIE = 0;
+ musb_regs_t* musb = MUSB_REGS(rhport);
+ unsigned const ie = musb_dcd_get_int_enable(rhport);
+ musb_dcd_int_disable(rhport);
+
+ musb->intr_txen = 1; /* Enable only EP0 */
+ musb->intr_rxen = 0;
for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
- regs->TXMAXP = 0;
- regs->TXCSRH = 0;
- if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
- regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
- else
- regs->TXCSRL = USB_TXCSRL1_CLRDT;
-
- regs->RXMAXP = 0;
- regs->RXCSRH = 0;
- if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
- regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
- else
- regs->RXCSRL = USB_RXCSRL1_CLRDT;
-
- USB0->EPIDX = i;
- USB0->TXFIFOSZ = 0;
- USB0->TXFIFOADD = 0;
- USB0->RXFIFOSZ = 0;
- USB0->RXFIFOADD = 0;
- }
- if (ie) NVIC_EnableIRQ(USB0_IRQn);
-}
-
-void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
- (void)rhport;
- unsigned const epn = tu_edpt_number(ep_addr);
- unsigned const dir_in = tu_edpt_dir(ep_addr);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb, i);
+ for (unsigned d = 0; d < 2; d++) {
+ musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[d];
+ hwfifo_flush(musb, i, d, true);
+ hwfifo_reset(musb, i, d);
+ maxp_csr->maxp = 0;
+ maxp_csr->csrh = 0;
+ }
+ }
- hw_endpoint_t volatile *regs = edpt_regs(epn - 1);
- unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
- NVIC_DisableIRQ(USB0_IRQn);
- if (dir_in) {
- USB0->TXIE &= ~TU_BIT(epn);
- regs->TXMAXP = 0;
- regs->TXCSRH = 0;
- if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
- regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
- else
- regs->TXCSRL = USB_TXCSRL1_CLRDT;
-
- USB0->EPIDX = epn;
- USB0->TXFIFOSZ = 0;
- USB0->TXFIFOADD = 0;
- } else {
- USB0->RXIE &= ~TU_BIT(epn);
- regs->RXMAXP = 0;
- regs->RXCSRH = 0;
- if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
- regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
- else
- regs->RXCSRL = USB_RXCSRL1_CLRDT;
+#if MUSB_CFG_DYNAMIC_FIFO
+ alloced_fifo_bytes = CFG_TUD_ENDPOINT0_SIZE;
+#endif
- USB0->EPIDX = epn;
- USB0->RXFIFOSZ = 0;
- USB0->RXFIFOADD = 0;
- }
- if (ie) NVIC_EnableIRQ(USB0_IRQn);
+ if (ie) musb_dcd_int_enable(rhport);
}
// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
@@ -791,18 +778,22 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
bool ret;
// TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
unsigned const epnum = tu_edpt_number(ep_addr);
- unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
- NVIC_DisableIRQ(USB0_IRQn);
+ unsigned const ie = musb_dcd_get_int_enable(rhport);
+ musb_dcd_int_disable(rhport);
+
if (epnum) {
_dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1);
ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes);
- } else
+ } else {
ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
- if (ie) NVIC_EnableIRQ(USB0_IRQn);
+ }
+
+ if (ie) musb_dcd_int_enable(rhport);
return ret;
}
-// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
+// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack
+// - optional, however, must be listed in usbd.c
bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
{
(void)rhport;
@@ -810,99 +801,104 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
// TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
unsigned const epnum = tu_edpt_number(ep_addr);
TU_ASSERT(epnum);
- unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
- NVIC_DisableIRQ(USB0_IRQn);
+ unsigned const ie = musb_dcd_get_int_enable(rhport);
+ musb_dcd_int_disable(rhport);
_dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1);
ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes);
- if (ie) NVIC_EnableIRQ(USB0_IRQn);
+ if (ie) musb_dcd_int_enable(rhport);
return ret;
}
// Stall endpoint
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
- (void)rhport;
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+ unsigned const ie = musb_dcd_get_int_enable(rhport);
+ musb_dcd_int_disable(rhport);
+
unsigned const epn = tu_edpt_number(ep_addr);
- unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
- NVIC_DisableIRQ(USB0_IRQn);
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
+
if (0 == epn) {
if (!ep_addr) { /* Ignore EP80 */
_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
_dcd.pipe0.buf = NULL;
- USB0->CSRL0 = USB_CSRL0_STALL;
+ ep_csr->csr0l = MUSB_CSRL0_STALL;
}
} else {
- volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
- if (tu_edpt_dir(ep_addr)) { /* IN */
- regs->TXCSRL = USB_TXCSRL1_STALL;
- } else { /* OUT */
- TU_ASSERT(!(regs->RXCSRL & USB_RXCSRL1_RXRDY),);
- regs->RXCSRL = USB_RXCSRL1_STALL;
- }
+ const uint8_t is_rx = 1 - tu_edpt_dir(ep_addr);
+ ep_csr->maxp_csr[is_rx].csrl = MUSB_CSRL_SEND_STALL(is_rx);
}
- if (ie) NVIC_EnableIRQ(USB0_IRQn);
+
+ if (ie) musb_dcd_int_enable(rhport);
}
// clear stall, data toggle is also reset to DATA0
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
{
(void)rhport;
+ unsigned const ie = musb_dcd_get_int_enable(rhport);
+ musb_dcd_int_disable(rhport);
+
unsigned const epn = tu_edpt_number(ep_addr);
- hw_endpoint_t volatile *regs = edpt_regs(epn - 1);
- unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
- NVIC_DisableIRQ(USB0_IRQn);
- if (tu_edpt_dir(ep_addr)) { /* IN */
- regs->TXCSRL = USB_TXCSRL1_CLRDT;
- } else { /* OUT */
- regs->RXCSRL = USB_RXCSRL1_CLRDT;
- }
- if (ie) NVIC_EnableIRQ(USB0_IRQn);
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn);
+ const uint8_t is_rx = 1 - tu_edpt_dir(ep_addr);
+
+ ep_csr->maxp_csr[is_rx].csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx);
+
+ if (ie) musb_dcd_int_enable(rhport);
}
/*-------------------------------------------------------------------
* ISR
*-------------------------------------------------------------------*/
-void dcd_int_handler(uint8_t rhport)
-{
- uint_fast8_t is, txis, rxis;
+void dcd_int_handler(uint8_t rhport) {
+ musb_regs_t* musb_regs = MUSB_REGS(rhport);
+ const uint8_t saved_index = musb_regs->index; // save endpoint index
+
+ //Part specific ISR setup/entry
+ musb_dcd_int_handler_enter(rhport);
- is = USB0->IS; /* read and clear interrupt status */
- txis = USB0->TXIS; /* read and clear interrupt status */
- rxis = USB0->RXIS; /* read and clear interrupt status */
+ uint_fast8_t intr_usb = musb_regs->intr_usb; // a read will clear this interrupt status
+ uint_fast8_t intr_tx = musb_regs->intr_tx; // a read will clear this interrupt status
+ uint_fast8_t intr_rx = musb_regs->intr_rx; // a read will clear this interrupt status
// TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis);
- is &= USB0->IE; /* Clear disabled interrupts */
- if (is & USB_IS_DISCON) {
+ intr_usb &= musb_regs->intr_usben; /* Clear disabled interrupts */
+ if (intr_usb & MUSB_IS_DISCON) {
}
- if (is & USB_IS_SOF) {
+ if (intr_usb & MUSB_IS_SOF) {
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
}
- if (is & USB_IS_RESET) {
+ if (intr_usb & MUSB_IS_RESET) {
process_bus_reset(rhport);
}
- if (is & USB_IS_RESUME) {
+ if (intr_usb & MUSB_IS_RESUME) {
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
}
- if (is & USB_IS_SUSPEND) {
+ if (intr_usb & MUSB_IS_SUSPEND) {
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
}
- txis &= USB0->TXIE; /* Clear disabled interrupts */
- if (txis & USB_TXIE_EP0) {
+ intr_tx &= musb_regs->intr_txen; /* Clear disabled interrupts */
+ if (intr_tx & TU_BIT(0)) {
process_ep0(rhport);
- txis &= ~TU_BIT(0);
+ intr_tx &= ~TU_BIT(0);
}
- while (txis) {
- unsigned const num = __builtin_ctz(txis);
+ while (intr_tx) {
+ unsigned const num = __builtin_ctz(intr_tx);
process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN));
- txis &= ~TU_BIT(num);
+ intr_tx &= ~TU_BIT(num);
}
- rxis &= USB0->RXIE; /* Clear disabled interrupts */
- while (rxis) {
- unsigned const num = __builtin_ctz(rxis);
+
+ intr_rx &= musb_regs->intr_rxen; /* Clear disabled interrupts */
+ while (intr_rx) {
+ unsigned const num = __builtin_ctz(intr_rx);
process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT));
- rxis &= ~TU_BIT(num);
+ intr_rx &= ~TU_BIT(num);
}
+
+ musb_regs->index = saved_index; // restore endpoint index
}
#endif
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 5312c2812c..1c0740193a 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -37,16 +37,10 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
#include "host/hcd.h"
-#if TU_CHECK_MCU(OPT_MCU_MSP432E4)
- #include "musb_msp432e.h"
-
-#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129)
- #include "musb_tm4c.h"
-
- // HACK generalize later
- #include "musb_type.h"
- #define FIFO0_WORD FIFO0
+#include "musb_type.h"
+#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+ #include "musb_ti.h"
#else
#error "Unsupported MCUs"
#endif
@@ -562,9 +556,9 @@ static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum)
* Host API
*------------------------------------------------------------------*/
-bool hcd_init(uint8_t rhport)
-{
- (void)rhport;
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rhport;
+ (void) rh_init;
NVIC_ClearPendingIRQ(USB0_IRQn);
_hcd.bmRequestType = REQUEST_TYPE_INVALID;
diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h
new file mode 100644
index 0000000000..35849b5f83
--- /dev/null
+++ b/src/portable/mentor/musb/musb_max32.h
@@ -0,0 +1,150 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_MUSB_MAX32_H_
+#define TUSB_MUSB_MAX32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mxc_device.h"
+#include "usbhs_regs.h"
+
+#define MUSB_CFG_SHARED_FIFO 1 // shared FIFO for TX and RX endpoints
+#define MUSB_CFG_DYNAMIC_FIFO 0 // dynamic EP FIFO sizing
+
+const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS };
+
+#if CFG_TUD_ENABLED
+#define USBHS_M31_CLOCK_RECOVERY
+
+// Mapping of IRQ numbers to port. Currently just 1.
+static const IRQn_Type musb_irqs[] = {
+ USB_IRQn
+};
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_enable(uint8_t rhport) {
+ NVIC_EnableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_disable(uint8_t rhport) {
+ NVIC_DisableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) {
+ #ifdef NVIC_GetEnableIRQ // only defined in CMSIS 5
+ return NVIC_GetEnableIRQ(musb_irqs[rhport]);
+ #else
+ uint32_t IRQn = (uint32_t) musb_irqs[rhport];
+ return ((NVIC->ISER[IRQn >> 5UL] & (1UL << (IRQn & 0x1FUL))) != 0UL) ? 1UL : 0UL;
+ #endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_clear(uint8_t rhport) {
+ NVIC_ClearPendingIRQ(musb_irqs[rhport]);
+}
+
+static inline void musb_dcd_int_handler_enter(uint8_t rhport) {
+ mxc_usbhs_regs_t* hs_phy = MXC_USBHS;
+ uint32_t mxm_int, mxm_int_en, mxm_is;
+
+ //Handle PHY specific events
+ mxm_int = hs_phy->mxm_int;
+ mxm_int_en = hs_phy->mxm_int_en;
+ mxm_is = mxm_int & mxm_int_en;
+ hs_phy->mxm_int = mxm_is;
+
+ if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) {
+ dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+ }
+}
+
+static inline void musb_dcd_phy_init(uint8_t rhport) {
+ (void) rhport;
+ mxc_usbhs_regs_t* hs_phy = MXC_USBHS;
+
+ // Interrupt for VBUS disconnect
+ hs_phy->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS;
+
+ musb_dcd_int_clear(rhport);
+
+ // Unsuspend the MAC
+ hs_phy->mxm_suspend = 0;
+
+ // Configure PHY
+ hs_phy->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11);
+ hs_phy->m31_phy_xcfgi_63_32 = 0;
+ hs_phy->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64);
+ hs_phy->m31_phy_xcfgi_127_96 = 0;
+
+ #ifdef USBHS_M31_CLOCK_RECOVERY
+ hs_phy->m31_phy_noncry_rstb = 1;
+ hs_phy->m31_phy_noncry_en = 1;
+ hs_phy->m31_phy_outclksel = 0;
+ hs_phy->m31_phy_coreclkin = 0;
+ hs_phy->m31_phy_xtlsel = 2; /* Select 25 MHz clock */
+ #else
+ hs_phy->m31_phy_noncry_rstb = 0;
+ hs_phy->m31_phy_noncry_en = 0;
+ hs_phy->m31_phy_outclksel = 1;
+ hs_phy->m31_phy_coreclkin = 1;
+ hs_phy->m31_phy_xtlsel = 3; /* Select 30 MHz clock */
+ #endif
+ hs_phy->m31_phy_pll_en = 1;
+ hs_phy->m31_phy_oscouten = 1;
+
+ /* Reset PHY */
+ hs_phy->m31_phy_ponrst = 0;
+ hs_phy->m31_phy_ponrst = 1;
+}
+
+// static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) {
+// (void) mps;
+//
+// //Most likely the caller has already grabbed the right register block. But
+// //as a precaution save and restore the register bank anyways
+// unsigned saved_index = musb_periph_inst[rhport]->index;
+//
+// musb_periph_inst[rhport]->index = epnum;
+//
+// //Disable double buffering
+// if (dir_in) {
+// musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE);
+// } else {
+// musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS);
+// }
+//
+// musb_periph_inst[rhport]->index = saved_index;
+// }
+
+#endif // CFG_TUD_ENABLED
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // TUSB_MUSB_MAX32_H_
diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h
new file mode 100644
index 0000000000..d17e836ee9
--- /dev/null
+++ b/src/portable/mentor/musb/musb_ti.h
@@ -0,0 +1,91 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_MUSB_TI_H_
+#define TUSB_MUSB_TI_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_TM4C123
+ #include "TM4C123.h"
+ #define FIFO0_WORD FIFO0
+ #define FIFO1_WORD FIFO1
+//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129
+#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4
+ #include "msp.h"
+#else
+ #error "Unsupported MCUs"
+#endif
+
+#define MUSB_CFG_SHARED_FIFO 0
+#define MUSB_CFG_DYNAMIC_FIFO 1
+#define MUSB_CFG_DYNAMIC_FIFO_SIZE 4096
+
+const uintptr_t MUSB_BASES[] = { USB0_BASE };
+
+// Header supports both device and host modes. Only include what's necessary
+#if CFG_TUD_ENABLED
+
+// Mapping of IRQ numbers to port. Currently just 1.
+static const IRQn_Type musb_irqs[] = {
+ USB0_IRQn
+};
+
+static inline void musb_dcd_phy_init(uint8_t rhport){
+ (void)rhport;
+ //Nothing to do for this part
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_enable(uint8_t rhport) {
+ NVIC_EnableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_disable(uint8_t rhport) {
+ NVIC_DisableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) {
+ return NVIC_GetEnableIRQ(musb_irqs[rhport]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_clear(uint8_t rhport) {
+ NVIC_ClearPendingIRQ(musb_irqs[rhport]);
+}
+
+static inline void musb_dcd_int_handler_enter(uint8_t rhport) {
+ (void)rhport;
+ //Nothing to do for this part
+}
+
+#endif // CFG_TUD_ENABLED
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif // TUSB_MUSB_TI_H_
diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h
index 8f83305a52..4e448c0eda 100644
--- a/src/portable/mentor/musb/musb_type.h
+++ b/src/portable/mentor/musb/musb_type.h
@@ -1,3 +1,29 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
/******************************************************************************
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
@@ -32,2590 +58,696 @@
*
*******************************************************************************/
-#ifndef _TUSB_MUSB_TYPE_H_
-#define _TUSB_MUSB_TYPE_H_
+#ifndef TUSB_MUSB_TYPE_H_
+#define TUSB_MUSB_TYPE_H_
+
+#include "stdint.h"
#ifdef __cplusplus
extern "C" {
#endif
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FADDR register.
-//
-//*****************************************************************************
-#define USB_FADDR_M 0x0000007F // Function Address
-#define USB_FADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_POWER register.
-//
-//*****************************************************************************
-#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
-#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
-#define USB_POWER_HSENAB 0x00000020 // High Speed Enable
-#define USB_POWER_HSMODE 0x00000010 // High Speed Enable
-#define USB_POWER_RESET 0x00000008 // RESET Signaling
-#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
-#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
-#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXIS register.
-//
-//*****************************************************************************
-#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
-#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
-#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
-#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
-#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
-#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
-#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
-#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXIS register.
-//
-//*****************************************************************************
-#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
-#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
-#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
-#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
-#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
-#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
-#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXIE register.
-//
-//*****************************************************************************
-#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
-#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
-#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
-#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
-#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
-#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
-#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
-#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
- // Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXIE register.
-//
-//*****************************************************************************
-#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
-#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
-#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
-#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
-#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
-#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
-#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IS register.
-//
-//*****************************************************************************
-#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only)
-#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only)
-#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only)
-#define USB_IS_CONN 0x00000010 // Session Connect
-#define USB_IS_SOF 0x00000008 // Start of Frame
-#define USB_IS_BABBLE 0x00000004 // Babble Detected
-#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
-#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
-#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IE register.
-//
-//*****************************************************************************
-#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG
- // only)
-#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG
- // only)
-#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
-#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt
-#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
-#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt
-#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
-#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
-#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FRAME register.
-//
-//*****************************************************************************
-#define USB_FRAME_M 0x000007FF // Frame Number
-#define USB_FRAME_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPIDX register.
-//
-//*****************************************************************************
-#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
-#define USB_EPIDX_EPIDX_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TEST register.
-//
-//*****************************************************************************
-#define USB_TEST_FORCEH 0x00000080 // Force Host Mode
-#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
-#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
-#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode
-#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable
-#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable
-#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable
-#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO0 register.
-//
-//*****************************************************************************
-#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO0_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO1 register.
-//
-//*****************************************************************************
-#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO1_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO2 register.
-//
-//*****************************************************************************
-#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO2_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO3 register.
-//
-//*****************************************************************************
-#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO3_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO4 register.
-//
-//*****************************************************************************
-#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO4_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO5 register.
-//
-//*****************************************************************************
-#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO5_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO6 register.
-//
-//*****************************************************************************
-#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO6_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO7 register.
-//
-//*****************************************************************************
-#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO7_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DEVCTL register.
-//
-//*****************************************************************************
-#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only)
-#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected
-#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected
-#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only)
-#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
-#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
-#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid
-#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid
-#define USB_DEVCTL_HOST 0x00000004 // Host Mode
-#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only)
-#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only)
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CCONF register.
-//
-//*****************************************************************************
-#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable
-#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
-//
-//*****************************************************************************
-#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
-#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
-#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
-#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
-#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
-#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
-#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
-#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
-#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
-#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
-#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
-//
-//*****************************************************************************
-#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
-#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
-#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
-#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
-#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
-#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
-#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
-#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
-#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
-#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
-#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFIFOADD
-// register.
-//
-//*****************************************************************************
-#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
-#define USB_TXFIFOADD_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFIFOADD
-// register.
-//
-//*****************************************************************************
-#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
-#define USB_RXFIFOADD_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
-// register.
-//
-//*****************************************************************************
-#define USB_ULPIVBUSCTL_USEEXTVBUSIND \
- 0x00000002 // Use External VBUS Indicator
-#define USB_ULPIVBUSCTL_USEEXTVBUS \
- 0x00000001 // Use External VBUS
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_ULPIREGDATA
-// register.
-//
-//*****************************************************************************
-#define USB_ULPIREGDATA_REGDATA_M \
- 0x000000FF // Register Data
-#define USB_ULPIREGDATA_REGDATA_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_ULPIREGADDR
-// register.
-//
-//*****************************************************************************
-#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address
-#define USB_ULPIREGADDR_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_ULPIREGCTL
-// register.
-//
-//*****************************************************************************
-#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control
-#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete
-#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPINFO register.
-//
-//*****************************************************************************
-#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints
-#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints
-#define USB_EPINFO_RXEP_S 4
-#define USB_EPINFO_TXEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RAMINFO register.
-//
-//*****************************************************************************
-#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels
-#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width
-#define USB_RAMINFO_DMACHAN_S 4
-#define USB_RAMINFO_RAMBITS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CONTIM register.
-//
-//*****************************************************************************
-#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
-#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
-#define USB_CONTIM_WTCON_S 4
-#define USB_CONTIM_WTID_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VPLEN register.
-//
-//*****************************************************************************
-#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length
-#define USB_VPLEN_VPLEN_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_HSEOF register.
-//
-//*****************************************************************************
-#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap
-#define USB_HSEOF_HSEOFG_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FSEOF register.
-//
-//*****************************************************************************
-#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
-#define USB_FSEOF_FSEOFG_S 0
+#ifndef __IO
+ #define __IO volatile
+#endif
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LSEOF register.
-//
-//*****************************************************************************
-#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
-#define USB_LSEOF_LSEOFG_S 0
+#ifndef __I
+ #define __I volatile const
+#endif
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address
-#define USB_TXFUNCADDR0_ADDR_S 0
+#ifndef __O
+ #define __O volatile
+#endif
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR0
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address
-#define USB_TXHUBADDR0_ADDR_S 0
+#ifndef __R
+ #define __R volatile const
+#endif
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT0
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port
-#define USB_TXHUBPORT0_PORT_S 0
+typedef struct TU_ATTR_PACKED {
+ __IO uint16_t maxp; // 0x00, 0x04: MAXP
+ __IO uint8_t csrl; // 0x02, 0x06: CSRL
+ __IO uint8_t csrh; // 0x03, 0x07: CSRH
+}musb_ep_maxp_csr_t;
+
+// 0: TX (device IN, host OUT)
+// 1: RX (device OUT, host IN)
+typedef struct TU_ATTR_PACKED {
+ union {
+ struct {
+ __IO uint16_t tx_maxp; // 0x00: TXMAXP
+ union {
+ __IO uint8_t csr0l; // 0x02: CSR0
+ __IO uint8_t tx_csrl; // 0x02: TX CSRL
+ };
+ union {
+ __IO uint8_t csr0h; // 0x03: CSR0H
+ __IO uint8_t tx_csrh; // 0x03: TX CSRH
+ };
+
+ __IO uint16_t rx_maxp; // 0x04: RX MAXP
+ __IO uint8_t rx_csrl; // 0x06: RX CSRL
+ __IO uint8_t rx_csrh; // 0x07: RX CSRH
+ };
+
+ musb_ep_maxp_csr_t maxp_csr[2];
+ };
+
+ union {
+ __IO uint16_t count0; // 0x08: COUNT0
+ __IO uint16_t rx_count; // 0x08: RX COUNT
+ };
+ union {
+ __IO uint8_t type0; // 0x0A: TYPE0 (host only)
+ __IO uint8_t tx_type; // 0x0A: TX TYPE
+ };
+ __IO uint8_t tx_interval; // 0x0B: TX INTERVAL
+ __IO uint8_t rx_type; // 0x0C: RX TYPE
+ __IO uint8_t rx_interval; // 0x0D: RX INTERVAL
+ __IO uint8_t reserved_0x0e; // 0x0E: Reserved
+ union {
+ __IO uint8_t config_data0; // 0x0F: CONFIG DATA
+ struct {
+ __IO uint8_t utmi_data_width : 1; // [0] UTMI Data Width
+ __IO uint8_t softconn_en : 1; // [1] Soft Connect Enable
+ __IO uint8_t dynamic_fifo : 1; // [2] Dynamic FIFO Sizing
+ __IO uint8_t hb_tx_en : 1; // [3] High Bandwidth TX ISO Enable
+ __IO uint8_t hb_rx_en : 1; // [4] High Bandwidth RX ISO Enable
+ __IO uint8_t big_endian : 1; // [5] Big Endian
+ __IO uint8_t mp_tx_en : 1; // [6] Auto splitting BULK TX Enable
+ __IO uint8_t mp_rx_en : 1; // [7] Auto amalgamation BULK RX Enable
+ } config_data0_bit;
+
+ __IO uint8_t fifo_size; // 0x0F: FIFO_SIZE
+ struct {
+ __IO uint8_t tx : 4; // [3:0] TX FIFO Size
+ __IO uint8_t rx : 4; // [7:4] RX FIFO Size
+ }fifo_size_bit;
+ };
+} musb_ep_csr_t;
+
+TU_VERIFY_STATIC(sizeof(musb_ep_csr_t) == 16, "size is not correct");
+
+typedef struct TU_ATTR_PACKED {
+ //------------- Common -------------//
+ __IO uint8_t faddr; // 0x00: FADDR
+ union {
+ __IO uint8_t power; // 0x01: POWER
+ struct {
+ __IO uint8_t suspend_mode_en : 1; // [0] SUSPEND Mode Enable
+ __IO uint8_t suspend_mode : 1; // [1] SUSPEND Mode
+ __IO uint8_t resume_mode : 1; // [2] RESUME
+ __IO uint8_t reset : 1; // [3] RESET
+ __IO uint8_t highspeed_mode : 1; // [4] High Speed Mode
+ __IO uint8_t highspeed_en : 1; // [5] High Speed Enable
+ __IO uint8_t soft_conn : 1; // [6] Soft Connect/Disconnect
+ __IO uint8_t iso_update : 1; // [7] Isochronous Update
+ } power_bit;
+ };
+
+ union {
+ struct {
+ __IO uint16_t intr_tx; // 0x02: INTR_TX
+ __IO uint16_t intr_rx; // 0x04: INTR_RX
+ };
+
+ __IO uint16_t intr_ep[2]; // 0x02-0x05: INTR_EP0-1
+ };
+
+ union {
+ struct {
+ __IO uint16_t intr_txen; // 0x06: INTR_TXEN
+ __IO uint16_t intr_rxen; // 0x08: INTR_RXEN
+ };
+
+ __IO uint16_t intren_ep[2]; // 0x06-0x09: INTREN_EP0-1
+ };
+
+ __IO uint8_t intr_usb; // 0x0A: INTRUSB
+ __IO uint8_t intr_usben; // 0x0B: INTRUSBEN
+
+ __IO uint16_t frame; // 0x0C: FRAME
+ __IO uint8_t index; // 0x0E: INDEX
+ __IO uint8_t testmode; // 0x0F: TESTMODE
+
+ //------------- Endpoint CSR (indexed) -------------//
+ musb_ep_csr_t indexed_csr; // 0x10-0x1F: Indexed CSR 0-15
+
+ //------------- FIFOs -------------//
+ __IO uint32_t fifo[16]; // 0x20-0x5C: FIFO 0-15
+
+ // Common (2)
+ __IO uint8_t devctl; // 0x60: DEVCTL
+ __IO uint8_t misc; // 0x61: MISC
+
+ //------------- Dynammic FIFO (indexed) -------------//
+ union {
+ struct {
+ __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ
+ __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ
+ };
+ __IO uint8_t fifo_size[2];
+ };
+
+ union {
+ struct {
+ __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR
+ __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR
+ };
+ __IO uint16_t fifo_addr[2];
+ };
+
+ //------------- Additional Control and Configuration -------------//
+ union {
+ __O uint32_t vcontrol; // 0x68: PHY VCONTROL
+ __IO uint32_t vstatus; // 0x68: PHY VSTATUS
+ };
+ union {
+ __IO uint16_t hwvers; // 0x6C: HWVERS
+ struct {
+ __IO uint16_t minor : 10; // [9:0] Minor
+ __IO uint16_t major : 5; // [14:10] Major
+ __IO uint16_t rc : 1; // [15] Release Candidate
+ } hwvers_bit;
+ };
+ __R uint16_t rsv_0x6e_0x77[5]; // 0x6E-0x77: Reserved
+
+ //------------- Additional Configuration -------------//
+ union {
+ __IO uint8_t epinfo; // 0x78: EPINFO
+ struct {
+ __IO uint8_t tx_ep_num : 4; // [3:0] TX Endpoints
+ __IO uint8_t rx_ep_num : 4; // [7:4] RX Endpoints
+ } epinfo_bit;
+ };
+ union {
+ __IO uint8_t raminfo; // 0x79: RAMINFO
+ struct {
+ __IO uint8_t ram_bits : 4; // [3:0] RAM Address Bus Width
+ __IO uint8_t dma_channel : 4; // [7:4] DMA Channels
+ }raminfo_bit;
+ };
+ union {
+ __IO uint8_t link_info; // 0x7A: LINK_INFO
+ __IO uint8_t adi_softreset; // 0x7A: AnalogDevice SOFTRESET
+ };
+ __IO uint8_t vplen; // 0x7B: VPLEN
+ __IO uint8_t hs_eof1; // 0x7C: HS_EOF1
+ __IO uint8_t fs_eof1; // 0x7D: FS_EOF1
+ __IO uint8_t ls_eof1; // 0x7E: LS_EOF1
+ __IO uint8_t soft_rst; // 0x7F: SOFT_RST
+
+ //------------- Target Endpoints (multipoint option) -------------//
+ __IO uint16_t ctuch; // 0x80: CTUCH
+ __IO uint16_t cthsrtn; // 0x82: CTHSRTN
+ __R uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved
+
+ //------------- Non-Indexed Endpoint CSRs -------------//
+ // TI tm4c can access this directly, but should use indexed_csr for portability
+ musb_ep_csr_t abs_csr[16]; // 0x100-0x1FF: EP0-15 CSR
+
+ //------------- DMA -------------//
+ __IO uint8_t dma_intr; // 0x200: DMA_INTR
+ __R uint8_t rsv_0x201_0x203[3]; // 0x201-0x203: Reserved
+ struct {
+ __IO uint16_t cntl; // 0x204: DMA_CNTL
+ __IO uint16_t rsv_0x206; // 0x206: Reserved
+ __IO uint32_t addr; // 0x208: DMA_ADDR
+ __IO uint32_t count; // 0x20C: DMA_COUNT
+ __IO uint32_t rsv_0x210; // 0x210: Reserved
+ }dma[8];
+ __R uint32_t rsv_0x284_0x2FF[31]; // 0x284-0x2FF: Reserved
+
+ //------------- Extended -------------//
+ __R uint32_t rsv_0x300; // 0x300: Reserved
+ struct {
+ __IO uint16_t count; // 0x304: REQ_PACKET_COUNT
+ __R uint16_t rsv_0x306; // 0x306: Reserved
+ }req_packet[15];
+
+ __IO uint16_t rx_doulbe_packet_disable; // 0x340: RX_DOUBLE_PACKET_DISABLE
+ __IO uint16_t tx_double_packet_disable; // 0x342: TX_DOUBLE_PACKET_DISABLE
+
+ __IO uint16_t chirp_timeout; // 0x344: CHIRP_TIMEOUT
+ __IO uint16_t hs_to_utm; // 0x346: HS_TO_UTM delay
+ __IO uint16_t hs_timeout_adder; // 0x348: HS_TIMEOUT_ADDER
+
+ __R uint8_t rsv_34A_34f[6]; // 0x34A-0x34F: Reserved
+} musb_regs_t;
+
+TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x350, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Helper
+//--------------------------------------------------------------------+
+TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_regs, unsigned epnum) {
+ musb_regs->index = epnum;
+ return &musb_regs->indexed_csr;
+}
+
+//--------------------------------------------------------------------+
+// Register Bit Field
+//--------------------------------------------------------------------+
+
+// 0x01: Power
+#define MUSB_POWER_ISOUP 0x0080 // Isochronous Update
+#define MUSB_POWER_SOFTCONN 0x0040 // Soft Connect/Disconnect
+#define MUSB_POWER_HSENAB 0x0020 // High Speed Enable
+#define MUSB_POWER_HSMODE 0x0010 // High Speed Enable
+#define MUSB_POWER_RESET 0x0008 // RESET Signaling
+#define MUSB_POWER_RESUME 0x0004 // RESUME Signaling
+#define MUSB_POWER_SUSPEND 0x0002 // SUSPEND Mode
+#define MUSB_POWER_PWRDNPHY 0x0001 // Power Down PHY
+
+// Interrupt TX/RX Status and Enable: each bit is for an endpoint
+
+// 0x6c: HWVERS
+#define MUSB_HWVERS_RC_SHIFT 15
+#define MUSB_HWVERS_RC_MASK 0x8000
+#define MUSB_HWVERS_MAJOR_SHIFT 10
+#define MUSB_HWVERS_MAJOR_MASK 0x7C00
+#define MUSB_HWVERS_MINOR_SHIFT 0
+#define MUSB_HWVERS_MINOR_MASK 0x03FF
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address
-#define USB_TXFUNCADDR1_ADDR_S 0
+// 0x12, 0x16: TX/RX CSRL
+#define MUSB_CSRL_PACKET_READY(_rx) (1u << 0)
+#define MUSB_CSRL_FLUSH_FIFO(_rx) (1u << ((_rx) ? 4 : 3))
+#define MUSB_CSRL_SEND_STALL(_rx) (1u << ((_rx) ? 5 : 4))
+#define MUSB_CSRL_STALLED(_rx) (1u << ((_rx) ? 6 : 5))
+#define MUSB_CSRL_CLEAR_DATA_TOGGLE(_rx) (1u << ((_rx) ? 7 : 6))
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address
-#define USB_TXHUBADDR1_ADDR_S 0
+// 0x13, 0x17: TX/RX CSRH
+#define MUSB_CSRH_DISABLE_DOUBLE_PACKET(_rx) (1u << 1)
+#define MUSB_CSRH_TX_MODE (1u << 5) // 1 = TX, 0 = RX. only relevant for SHARED FIFO
+#define MUSB_CSRH_ISO (1u << 6)
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT1
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port
-#define USB_TXHUBPORT1_PORT_S 0
+// 0x62, 0x63: TXFIFO_SZ, RXFIFO_SZ
+#define MUSB_FIFOSZ_DOUBLE_PACKET (1u << 4)
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address
-#define USB_RXFUNCADDR1_ADDR_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR1
-// register.
+// The following are defines for the bit fields in the MUSB_O_IS register.
//
//*****************************************************************************
-#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address
-#define USB_RXHUBADDR1_ADDR_S 0
+#define MUSB_IS_VBUSERR 0x0080 // VBUS Error (OTG only)
+#define MUSB_IS_SESREQ 0x0040 // SESSION REQUEST (OTG only)
+#define MUSB_IS_DISCON 0x0020 // Session Disconnect (OTG only)
+#define MUSB_IS_CONN 0x0010 // Session Connect
+#define MUSB_IS_SOF 0x0008 // Start of Frame
+#define MUSB_IS_BABBLE 0x0004 // Babble Detected
+#define MUSB_IS_RESET 0x0004 // RESET Signaling Detected
+#define MUSB_IS_RESUME 0x0002 // RESUME Signaling Detected
+#define MUSB_IS_SUSPEND 0x0001 // SUSPEND Signaling Detected
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT1
-// register.
+// The following are defines for the bit fields in the MUSB_O_IE register.
//
//*****************************************************************************
-#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port
-#define USB_RXHUBPORT1_PORT_S 0
+#define MUSB_IE_VBUSERR 0x0080 // Enable VBUS Error Interrupt (OTG only)
+#define MUSB_IE_SESREQ 0x0040 // Enable Session Request (OTG only)
+#define MUSB_IE_DISCON 0x0020 // Enable Disconnect Interrupt
+#define MUSB_IE_CONN 0x0010 // Enable Connect Interrupt
+#define MUSB_IE_SOF 0x0008 // Enable Start-of-Frame Interrupt
+#define MUSB_IE_BABBLE 0x0004 // Enable Babble Interrupt
+#define MUSB_IE_RESET 0x0004 // Enable RESET Interrupt
+#define MUSB_IE_RESUME 0x0002 // Enable RESUME Interrupt
+#define MUSB_IE_SUSPND 0x0001 // Enable SUSPEND Interrupt
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
-// register.
+// The following are defines for the bit fields in the MUSB_O_FRAME register.
//
//*****************************************************************************
-#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address
-#define USB_TXFUNCADDR2_ADDR_S 0
+#define MUSB_FRAME_M 0x07FF // Frame Number
+#define MUSB_FRAME_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR2
-// register.
+// The following are defines for the bit fields in the MUSB_O_TEST register.
//
//*****************************************************************************
-#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address
-#define USB_TXHUBADDR2_ADDR_S 0
+#define MUSB_TEST_FORCEH 0x0080 // Force Host Mode
+#define MUSB_TEST_FIFOACC 0x0040 // FIFO Access
+#define MUSB_TEST_FORCEFS 0x0020 // Force Full-Speed Mode
+#define MUSB_TEST_FORCEHS 0x0010 // Force High-Speed Mode
+#define MUSB_TEST_TESTPKT 0x0008 // Test Packet Mode Enable
+#define MUSB_TEST_TESTK 0x0004 // Test_K Mode Enable
+#define MUSB_TEST_TESTJ 0x0002 // Test_J Mode Enable
+#define MUSB_TEST_TESTSE0NAK 0x0001 // Test_SE0_NAK Test Mode Enable
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT2
-// register.
+// The following are defines for the bit fields in the MUSB_O_DEVCTL register.
//
//*****************************************************************************
-#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port
-#define USB_TXHUBPORT2_PORT_S 0
+#define MUSB_DEVCTL_DEV 0x0080 // Device Mode (OTG only)
+#define MUSB_DEVCTL_FSDEV 0x0040 // Full-Speed Device Detected
+#define MUSB_DEVCTL_LSDEV 0x0020 // Low-Speed Device Detected
+#define MUSB_DEVCTL_VBUS_M 0x0018 // VBUS Level (OTG only)
+#define MUSB_DEVCTL_VBUS_NONE 0x0000 // Below SessionEnd
+#define MUSB_DEVCTL_VBUS_SEND 0x0008 // Above SessionEnd, below AValid
+#define MUSB_DEVCTL_VBUS_AVALID 0x0010 // Above AValid, below VBUSValid
+#define MUSB_DEVCTL_VBUS_VALID 0x0018 // Above VBUSValid
+#define MUSB_DEVCTL_HOST 0x0004 // Host Mode
+#define MUSB_DEVCTL_HOSTREQ 0x0002 // Host Request (OTG only)
+#define MUSB_DEVCTL_SESSION 0x0001 // Session Start/End (OTG only)
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
-// register.
+// The following are defines for the bit fields in the MUSB_O_CCONF register.
//
//*****************************************************************************
-#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address
-#define USB_RXFUNCADDR2_ADDR_S 0
+#define MUSB_CCONF_TXEDMA 0x0002 // TX Early DMA Enable
+#define MUSB_CCONF_RXEDMA 0x0001 // TX Early DMA Enable
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// The following are defines for the bit fields in the MUSB_O_ULPIVBUSCTL
// register.
//
//*****************************************************************************
-#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address
-#define USB_RXHUBADDR2_ADDR_S 0
+#define MUSB_ULPIVBUSCTL_USEEXTVBUSIND 0x0002 // Use External VBUS Indicator
+#define MUSB_ULPIVBUSCTL_USEEXTVBUS 0x0001 // Use External VBUS
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// The following are defines for the bit fields in the MUSB_O_ULPIREGDATA
// register.
//
//*****************************************************************************
-#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port
-#define USB_RXHUBPORT2_PORT_S 0
-
+#define MUSB_ULPIREGDATA_REGDATA_M 0x00FF // Register Data
+#define MUSB_ULPIREGDATA_REGDATA_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// The following are defines for the bit fields in the MUSB_O_ULPIREGADDR
// register.
//
//*****************************************************************************
-#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address
-#define USB_TXFUNCADDR3_ADDR_S 0
+#define MUSB_ULPIREGADDR_ADDR_M 0x00FF // Register Address
+#define MUSB_ULPIREGADDR_ADDR_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// The following are defines for the bit fields in the MUSB_O_ULPIREGCTL
// register.
//
//*****************************************************************************
-#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address
-#define USB_TXHUBADDR3_ADDR_S 0
+#define MUSB_ULPIREGCTL_RDWR 0x0004 // Read/Write Control
+#define MUSB_ULPIREGCTL_REGCMPLT 0x0002 // Register Access Complete
+#define MUSB_ULPIREGCTL_REGACC 0x0001 // Initiate Register Access
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT3
-// register.
+// The following are defines for the bit fields in the MUSB_O_EPINFO register.
//
//*****************************************************************************
-#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port
-#define USB_TXHUBPORT3_PORT_S 0
+#define MUSB_EPINFO_RXEP_M 0x00F0 // RX Endpoints
+#define MUSB_EPINFO_TXEP_M 0x000F // TX Endpoints
+#define MUSB_EPINFO_RXEP_S 4
+#define MUSB_EPINFO_TXEP_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
-// register.
+// The following are defines for the bit fields in the MUSB_O_RAMINFO register.
//
//*****************************************************************************
-#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address
-#define USB_RXFUNCADDR3_ADDR_S 0
+#define MUSB_RAMINFO_DMACHAN_M 0x00F0 // DMA Channels
+#define MUSB_RAMINFO_RAMBITS_M 0x000F // RAM Address Bus Width
+#define MUSB_RAMINFO_DMACHAN_S 4
+#define MUSB_RAMINFO_RAMBITS_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR3
-// register.
+// The following are defines for the bit fields in the MUSB_O_CONTIM register.
//
//*****************************************************************************
-#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address
-#define USB_RXHUBADDR3_ADDR_S 0
+#define MUSB_CONTIM_WTCON_M 0x00F0 // Connect Wait
+#define MUSB_CONTIM_WTID_M 0x000F // Wait ID
+#define MUSB_CONTIM_WTCON_S 4
+#define MUSB_CONTIM_WTID_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT3
-// register.
+// The following are defines for the bit fields in the MUSB_O_VPLEN register.
//
//*****************************************************************************
-#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port
-#define USB_RXHUBPORT3_PORT_S 0
+#define MUSB_VPLEN_VPLEN_M 0x00FF // VBUS Pulse Length
+#define MUSB_VPLEN_VPLEN_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
-// register.
+// The following are defines for the bit fields in the MUSB_O_HSEOF register.
//
//*****************************************************************************
-#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address
-#define USB_TXFUNCADDR4_ADDR_S 0
+#define MUSB_HSEOF_HSEOFG_M 0x00FF // HIgh-Speed End-of-Frame Gap
+#define MUSB_HSEOF_HSEOFG_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR4
-// register.
+// The following are defines for the bit fields in the MUSB_O_FSEOF register.
//
//*****************************************************************************
-#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address
-#define USB_TXHUBADDR4_ADDR_S 0
+#define MUSB_FSEOF_FSEOFG_M 0x00FF // Full-Speed End-of-Frame Gap
+#define MUSB_FSEOF_FSEOFG_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT4
-// register.
+// The following are defines for the bit fields in the MUSB_O_LSEOF register.
//
//*****************************************************************************
-#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port
-#define USB_TXHUBPORT4_PORT_S 0
+#define MUSB_LSEOF_LSEOFG_M 0x00FF // Low-Speed End-of-Frame Gap
+#define MUSB_LSEOF_LSEOFG_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
-// register.
+// The following are defines for the bit fields in the MUSB_O_CSRL0 register.
//
//*****************************************************************************
-#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address
-#define USB_RXFUNCADDR4_ADDR_S 0
+#define MUSB_CSRL0_NAKTO 0x0080 // NAK Timeout
+#define MUSB_CSRL0_SETENDC 0x0080 // Setup End Clear
+#define MUSB_CSRL0_STATUS 0x0040 // STATUS Packet
+#define MUSB_CSRL0_RXRDYC 0x0040 // RXRDY Clear
+#define MUSB_CSRL0_REQPKT 0x0020 // Request Packet
+#define MUSB_CSRL0_STALL 0x0020 // Send Stall
+#define MUSB_CSRL0_SETEND 0x0010 // Setup End
+#define MUSB_CSRL0_ERROR 0x0010 // Error
+#define MUSB_CSRL0_DATAEND 0x0008 // Data End
+#define MUSB_CSRL0_SETUP 0x0008 // Setup Packet
+#define MUSB_CSRL0_STALLED 0x0004 // Endpoint Stalled
+#define MUSB_CSRL0_TXRDY 0x0002 // Transmit Packet Ready
+#define MUSB_CSRL0_RXRDY 0x0001 // Receive Packet Ready
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR4
-// register.
+// The following are defines for the bit fields in the MUSB_O_CSRH0 register.
//
//*****************************************************************************
-#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address
-#define USB_RXHUBADDR4_ADDR_S 0
+#define MUSB_CSRH0_DISPING 0x0008 // PING Disable
+#define MUSB_CSRH0_DTWE 0x0004 // Data Toggle Write Enable
+#define MUSB_CSRH0_DT 0x0002 // Data Toggle
+#define MUSB_CSRH0_FLUSH 0x0001 // Flush FIFO
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT4
-// register.
+// The following are defines for the bit fields in the MUSB_O_TYPE0 register.
//
//*****************************************************************************
-#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port
-#define USB_RXHUBPORT4_PORT_S 0
+#define MUSB_TYPE0_SPEED_M 0x00C0 // Operating Speed
+#define MUSB_TYPE0_SPEED_HIGH 0x0040 // High
+#define MUSB_TYPE0_SPEED_FULL 0x0080 // Full
+#define MUSB_TYPE0_SPEED_LOW 0x00C0 // Low
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
-// register.
+// The following are defines for the bit fields in the MUSB_O_NAKLMT register.
//
//*****************************************************************************
-#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address
-#define USB_TXFUNCADDR5_ADDR_S 0
+#define MUSB_NAKLMT_NAKLMT_M 0x001F // EP0 NAK Limit
+#define MUSB_NAKLMT_NAKLMT_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR5
-// register.
+// The following are defines for the bit fields in the MUSB_O_TXCSRL1 register.
//
//*****************************************************************************
-#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address
-#define USB_TXHUBADDR5_ADDR_S 0
+#define MUSB_TXCSRL1_NAKTO 0x0080 // NAK Timeout
+#define MUSB_TXCSRL1_CLRDT 0x0040 // Clear Data Toggle
+#define MUSB_TXCSRL1_STALLED 0x0020 // Endpoint Stalled
+#define MUSB_TXCSRL1_STALL 0x0010 // Send STALL
+#define MUSB_TXCSRL1_SETUP 0x0010 // Setup Packet
+#define MUSB_TXCSRL1_FLUSH 0x0008 // Flush FIFO
+#define MUSB_TXCSRL1_ERROR 0x0004 // Error
+#define MUSB_TXCSRL1_UNDRN 0x0004 // Underrun
+#define MUSB_TXCSRL1_FIFONE 0x0002 // FIFO Not Empty
+#define MUSB_TXCSRL1_TXRDY 0x0001 // Transmit Packet Ready
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT5
-// register.
+// The following are defines for the bit fields in the MUSB_O_TXCSRH1 register.
//
//*****************************************************************************
-#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port
-#define USB_TXHUBPORT5_PORT_S 0
+#define MUSB_TXCSRH1_AUTOSET 0x0080 // Auto Set
+#define MUSB_TXCSRH1_ISO 0x0040 // Isochronous Transfers
+#define MUSB_TXCSRH1_MODE 0x0020 // Mode
+#define MUSB_TXCSRH1_DMAEN 0x0010 // DMA Request Enable
+#define MUSB_TXCSRH1_FDT 0x0008 // Force Data Toggle
+#define MUSB_TXCSRH1_DMAMOD 0x0004 // DMA Request Mode
+#define MUSB_TXCSRH1_DTWE 0x0002 // Data Toggle Write Enable
+#define MUSB_TXCSRH1_DT 0x0001 // Data Toggle
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
-// register.
+// The following are defines for the bit fields in the MUSB_O_RXCSRL1 register.
//
//*****************************************************************************
-#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address
-#define USB_RXFUNCADDR5_ADDR_S 0
+#define MUSB_RXCSRL1_CLRDT 0x0080 // Clear Data Toggle
+#define MUSB_RXCSRL1_STALLED 0x0040 // Endpoint Stalled
+#define MUSB_RXCSRL1_STALL 0x0020 // Send STALL
+#define MUSB_RXCSRL1_REQPKT 0x0020 // Request Packet
+#define MUSB_RXCSRL1_FLUSH 0x0010 // Flush FIFO
+#define MUSB_RXCSRL1_DATAERR 0x0008 // Data Error
+#define MUSB_RXCSRL1_NAKTO 0x0008 // NAK Timeout
+#define MUSB_RXCSRL1_OVER 0x0004 // Overrun
+#define MUSB_RXCSRL1_ERROR 0x0004 // Error
+#define MUSB_RXCSRL1_FULL 0x0002 // FIFO Full
+#define MUSB_RXCSRL1_RXRDY 0x0001 // Receive Packet Ready
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR5
-// register.
+// The following are defines for the bit fields in the MUSB_O_RXCSRH1 register.
//
//*****************************************************************************
-#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address
-#define USB_RXHUBADDR5_ADDR_S 0
+#define MUSB_RXCSRH1_AUTOCL 0x0080 // Auto Clear
+#define MUSB_RXCSRH1_AUTORQ 0x0040 // Auto Request
+#define MUSB_RXCSRH1_ISO 0x0040 // Isochronous Transfers
+#define MUSB_RXCSRH1_DMAEN 0x0020 // DMA Request Enable
+#define MUSB_RXCSRH1_DISNYET 0x0010 // Disable NYET
+#define MUSB_RXCSRH1_PIDERR 0x0010 // PID Error
+#define MUSB_RXCSRH1_DMAMOD 0x0008 // DMA Request Mode
+#define MUSB_RXCSRH1_DTWE 0x0004 // Data Toggle Write Enable
+#define MUSB_RXCSRH1_DT 0x0002 // Data Toggle
+#define MUSB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission Status
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT5
-// register.
+// The following are defines for the bit fields in the MUSB_O_TXTYPE1 register.
//
//*****************************************************************************
-#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port
-#define USB_RXHUBPORT5_PORT_S 0
+#define MUSB_TXTYPE1_SPEED_M 0x00C0 // Operating Speed
+#define MUSB_TXTYPE1_SPEED_DFLT 0x0000 // Default
+#define MUSB_TXTYPE1_SPEED_HIGH 0x0040 // High
+#define MUSB_TXTYPE1_SPEED_FULL 0x0080 // Full
+#define MUSB_TXTYPE1_SPEED_LOW 0x00C0 // Low
+#define MUSB_TXTYPE1_PROTO_M 0x0030 // Protocol
+#define MUSB_TXTYPE1_PROTO_CTRL 0x0000 // Control
+#define MUSB_TXTYPE1_PROTO_ISOC 0x0010 // Isochronous
+#define MUSB_TXTYPE1_PROTO_BULK 0x0020 // Bulk
+#define MUSB_TXTYPE1_PROTO_INT 0x0030 // Interrupt
+#define MUSB_TXTYPE1_TEP_M 0x000F // Target Endpoint Number
+#define MUSB_TXTYPE1_TEP_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// The following are defines for the bit fields in the MUSB_O_TXINTERVAL1
// register.
//
//*****************************************************************************
-#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address
-#define USB_TXFUNCADDR6_ADDR_S 0
+#define MUSB_TXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit
+#define MUSB_TXINTERVAL1_TXPOLL_M 0x00FF // TX Polling
+#define MUSB_TXINTERVAL1_TXPOLL_S 0
+#define MUSB_TXINTERVAL1_NAKLMT_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR6
-// register.
+// The following are defines for the bit fields in the MUSB_O_RXTYPE1 register.
//
//*****************************************************************************
-#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address
-#define USB_TXHUBADDR6_ADDR_S 0
+#define MUSB_RXTYPE1_SPEED_M 0x00C0 // Operating Speed
+#define MUSB_RXTYPE1_SPEED_DFLT 0x0000 // Default
+#define MUSB_RXTYPE1_SPEED_HIGH 0x0040 // High
+#define MUSB_RXTYPE1_SPEED_FULL 0x0080 // Full
+#define MUSB_RXTYPE1_SPEED_LOW 0x00C0 // Low
+#define MUSB_RXTYPE1_PROTO_M 0x0030 // Protocol
+#define MUSB_RXTYPE1_PROTO_CTRL 0x0000 // Control
+#define MUSB_RXTYPE1_PROTO_ISOC 0x0010 // Isochronous
+#define MUSB_RXTYPE1_PROTO_BULK 0x0020 // Bulk
+#define MUSB_RXTYPE1_PROTO_INT 0x0030 // Interrupt
+#define MUSB_RXTYPE1_TEP_M 0x000F // Target Endpoint Number
+#define MUSB_RXTYPE1_TEP_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// The following are defines for the bit fields in the MUSB_O_RXINTERVAL1
// register.
//
//*****************************************************************************
-#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port
-#define USB_TXHUBPORT6_PORT_S 0
+#define MUSB_RXINTERVAL1_TXPOLL_M 0x00FF // RX Polling
+#define MUSB_RXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit
+#define MUSB_RXINTERVAL1_TXPOLL_S 0
+#define MUSB_RXINTERVAL1_NAKLMT_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
-// register.
+// The following are defines for the bit fields in the MUSB_O_DMACTL0 register.
//
//*****************************************************************************
-#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address
-#define USB_RXFUNCADDR6_ADDR_S 0
+#define MUSB_DMACTL0_BRSTM_M 0x0600 // Burst Mode
+#define MUSB_DMACTL0_BRSTM_ANY 0x0000 // Bursts of unspecified length
+#define MUSB_DMACTL0_BRSTM_INC4 0x0200 // INCR4 or unspecified length
+#define MUSB_DMACTL0_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified
+ // length
+#define MUSB_DMACTL0_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define MUSB_DMACTL0_ERR 0x0100 // Bus Error Bit
+#define MUSB_DMACTL0_EP_M 0x00F0 // Endpoint number
+#define MUSB_DMACTL0_IE 0x0008 // DMA Interrupt Enable
+#define MUSB_DMACTL0_MODE 0x0004 // DMA Transfer Mode
+#define MUSB_DMACTL0_DIR 0x0002 // DMA Direction
+#define MUSB_DMACTL0_ENABLE 0x0001 // DMA Transfer Enable
+#define MUSB_DMACTL0_EP_S 4
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR6
-// register.
+// The following are defines for the bit fields in the MUSB_O_DMAADDR0 register.
//
//*****************************************************************************
-#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address
-#define USB_RXHUBADDR6_ADDR_S 0
+#define MUSB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address
+#define MUSB_DMAADDR0_ADDR_S 2
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// The following are defines for the bit fields in the MUSB_O_DMACOUNT0
// register.
//
//*****************************************************************************
-#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port
-#define USB_RXHUBPORT6_PORT_S 0
+#define MUSB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count
+#define MUSB_DMACOUNT0_COUNT_S 2
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
-// register.
+// The following are defines for the bit fields in the MUSB_O_CTO register.
//
//*****************************************************************************
-#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address
-#define USB_TXFUNCADDR7_ADDR_S 0
+#define MUSB_CTO_CCTV_M 0xFFFF // Configurable Chirp Timeout Value
+#define MUSB_CTO_CCTV_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR7
-// register.
+// The following are defines for the bit fields in the MUSB_O_HHSRTN register.
//
//*****************************************************************************
-#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address
-#define USB_TXHUBADDR7_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT7
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port
-#define USB_TXHUBPORT7_PORT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address
-#define USB_RXFUNCADDR7_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address
-#define USB_RXHUBADDR7_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT7
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port
-#define USB_RXHUBPORT7_PORT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CSRL0 register.
-//
-//*****************************************************************************
-#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
-#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
-#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
-#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
-#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
-#define USB_CSRL0_STALL 0x00000020 // Send Stall
-#define USB_CSRL0_SETEND 0x00000010 // Setup End
-#define USB_CSRL0_ERROR 0x00000010 // Error
-#define USB_CSRL0_DATAEND 0x00000008 // Data End
-#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
-#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
-#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
-#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CSRH0 register.
-//
-//*****************************************************************************
-#define USB_CSRH0_DISPING 0x00000008 // PING Disable
-#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable
-#define USB_CSRH0_DT 0x00000002 // Data Toggle
-#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_COUNT0 register.
-//
-//*****************************************************************************
-#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
-#define USB_COUNT0_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TYPE0 register.
-//
-//*****************************************************************************
-#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed
-#define USB_TYPE0_SPEED_HIGH 0x00000040 // High
-#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
-#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_NAKLMT register.
-//
-//*****************************************************************************
-#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit
-#define USB_NAKLMT_NAKLMT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP1_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
-#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet
-#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL1_ERROR 0x00000004 // Error
-#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH1_MODE 0x00000020 // Mode
-#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
-#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable
-#define USB_TXCSRH1_DT 0x00000001 // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP1_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet
-#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout
-#define USB_RXCSRL1_OVER 0x00000004 // Overrun
-#define USB_RXCSRL1_ERROR 0x00000004 // Error
-#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request
-#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
-#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable
-#define USB_RXCSRH1_DT 0x00000002 // Data Toggle
-#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT1_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed
-#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
-#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High
-#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
-#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
-#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol
-#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
-#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
-#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
-#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_TXTYPE1_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL1
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL1_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_TXINTERVAL1_TXPOLL_M \
- 0x000000FF // TX Polling
-#define USB_TXINTERVAL1_TXPOLL_S \
- 0
-#define USB_TXINTERVAL1_NAKLMT_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed
-#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
-#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High
-#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
-#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
-#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol
-#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
-#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
-#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
-#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_RXTYPE1_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL1
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL1_TXPOLL_M \
- 0x000000FF // RX Polling
-#define USB_RXINTERVAL1_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_RXINTERVAL1_TXPOLL_S \
- 0
-#define USB_RXINTERVAL1_NAKLMT_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP2_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
-#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet
-#define USB_TXCSRL2_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL2_ERROR 0x00000004 // Error
-#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH2_MODE 0x00000020 // Mode
-#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
-#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable
-#define USB_TXCSRH2_DT 0x00000001 // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP2_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet
-#define USB_RXCSRL2_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout
-#define USB_RXCSRL2_ERROR 0x00000004 // Error
-#define USB_RXCSRL2_OVER 0x00000004 // Overrun
-#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request
-#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
-#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable
-#define USB_RXCSRH2_DT 0x00000002 // Data Toggle
-#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT2_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed
-#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
-#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High
-#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
-#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
-#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol
-#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
-#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
-#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
-#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_TXTYPE2_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL2
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL2_TXPOLL_M \
- 0x000000FF // TX Polling
-#define USB_TXINTERVAL2_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_TXINTERVAL2_NAKLMT_S \
- 0
-#define USB_TXINTERVAL2_TXPOLL_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed
-#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
-#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High
-#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
-#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
-#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol
-#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
-#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
-#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
-#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_RXTYPE2_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL2
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL2_TXPOLL_M \
- 0x000000FF // RX Polling
-#define USB_RXINTERVAL2_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_RXINTERVAL2_TXPOLL_S \
- 0
-#define USB_RXINTERVAL2_NAKLMT_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP3_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
-#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet
-#define USB_TXCSRL3_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL3_ERROR 0x00000004 // Error
-#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH3_MODE 0x00000020 // Mode
-#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
-#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable
-#define USB_TXCSRH3_DT 0x00000001 // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP3_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL3_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet
-#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout
-#define USB_RXCSRL3_ERROR 0x00000004 // Error
-#define USB_RXCSRL3_OVER 0x00000004 // Overrun
-#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request
-#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
-#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable
-#define USB_RXCSRH3_DT 0x00000002 // Data Toggle
-#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT3_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed
-#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
-#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High
-#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
-#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
-#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol
-#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
-#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
-#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
-#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_TXTYPE3_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL3
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL3_TXPOLL_M \
- 0x000000FF // TX Polling
-#define USB_TXINTERVAL3_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_TXINTERVAL3_TXPOLL_S \
- 0
-#define USB_TXINTERVAL3_NAKLMT_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed
-#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
-#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High
-#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
-#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
-#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol
-#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
-#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
-#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
-#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_RXTYPE3_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL3
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL3_TXPOLL_M \
- 0x000000FF // RX Polling
-#define USB_RXINTERVAL3_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_RXINTERVAL3_TXPOLL_S \
- 0
-#define USB_RXINTERVAL3_NAKLMT_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP4_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
-#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet
-#define USB_TXCSRL4_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL4_ERROR 0x00000004 // Error
-#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH4_MODE 0x00000020 // Mode
-#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
-#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable
-#define USB_TXCSRH4_DT 0x00000001 // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP4_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL4_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet
-#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout
-#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL4_OVER 0x00000004 // Overrun
-#define USB_RXCSRL4_ERROR 0x00000004 // Error
-#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request
-#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
-#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable
-#define USB_RXCSRH4_DT 0x00000002 // Data Toggle
-#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT4_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed
-#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
-#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High
-#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
-#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
-#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol
-#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
-#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
-#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
-#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_TXTYPE4_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL4
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL4_TXPOLL_M \
- 0x000000FF // TX Polling
-#define USB_TXINTERVAL4_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_TXINTERVAL4_NAKLMT_S \
- 0
-#define USB_TXINTERVAL4_TXPOLL_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed
-#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
-#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High
-#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
-#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
-#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol
-#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
-#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
-#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
-#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_RXTYPE4_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL4
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL4_TXPOLL_M \
- 0x000000FF // RX Polling
-#define USB_RXINTERVAL4_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_RXINTERVAL4_NAKLMT_S \
- 0
-#define USB_RXINTERVAL4_TXPOLL_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP5_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
-#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet
-#define USB_TXCSRL5_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL5_ERROR 0x00000004 // Error
-#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH5_MODE 0x00000020 // Mode
-#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
-#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable
-#define USB_TXCSRH5_DT 0x00000001 // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP5_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL5_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet
-#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout
-#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL5_ERROR 0x00000004 // Error
-#define USB_RXCSRL5_OVER 0x00000004 // Overrun
-#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request
-#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
-#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable
-#define USB_RXCSRH5_DT 0x00000002 // Data Toggle
-#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT5_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed
-#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
-#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High
-#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
-#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
-#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol
-#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
-#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
-#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
-#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_TXTYPE5_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL5
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL5_TXPOLL_M \
- 0x000000FF // TX Polling
-#define USB_TXINTERVAL5_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_TXINTERVAL5_NAKLMT_S \
- 0
-#define USB_TXINTERVAL5_TXPOLL_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed
-#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
-#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High
-#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
-#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
-#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol
-#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
-#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
-#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
-#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_RXTYPE5_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL5
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL5_TXPOLL_M \
- 0x000000FF // RX Polling
-#define USB_RXINTERVAL5_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_RXINTERVAL5_TXPOLL_S \
- 0
-#define USB_RXINTERVAL5_NAKLMT_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP6_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
-#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL6_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet
-#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL6_ERROR 0x00000004 // Error
-#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH6_MODE 0x00000020 // Mode
-#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
-#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable
-#define USB_TXCSRH6_DT 0x00000001 // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP6_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet
-#define USB_RXCSRL6_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout
-#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL6_ERROR 0x00000004 // Error
-#define USB_RXCSRL6_OVER 0x00000004 // Overrun
-#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request
-#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
-#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable
-#define USB_RXCSRH6_DT 0x00000002 // Data Toggle
-#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT6_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed
-#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
-#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High
-#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
-#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
-#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol
-#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
-#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
-#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
-#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_TXTYPE6_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL6
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL6_TXPOLL_M \
- 0x000000FF // TX Polling
-#define USB_TXINTERVAL6_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_TXINTERVAL6_TXPOLL_S \
- 0
-#define USB_TXINTERVAL6_NAKLMT_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed
-#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
-#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High
-#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
-#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
-#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol
-#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
-#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
-#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
-#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_RXTYPE6_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL6
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL6_TXPOLL_M \
- 0x000000FF // RX Polling
-#define USB_RXINTERVAL6_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_RXINTERVAL6_NAKLMT_S \
- 0
-#define USB_RXINTERVAL6_TXPOLL_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP7_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
-#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL7_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet
-#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL7_ERROR 0x00000004 // Error
-#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH7_MODE 0x00000020 // Mode
-#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
-#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable
-#define USB_TXCSRH7_DT 0x00000001 // Data Toggle
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP7_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet
-#define USB_RXCSRL7_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout
-#define USB_RXCSRL7_ERROR 0x00000004 // Error
-#define USB_RXCSRL7_OVER 0x00000004 // Overrun
-#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request
-#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
-#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable
-#define USB_RXCSRH7_DT 0x00000002 // Data Toggle
-#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT7_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
-//
-//*****************************************************************************
-#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed
-#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
-#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High
-#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
-#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
-#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol
-#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
-#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
-#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
-#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_TXTYPE7_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXINTERVAL7
-// register.
-//
-//*****************************************************************************
-#define USB_TXINTERVAL7_TXPOLL_M \
- 0x000000FF // TX Polling
-#define USB_TXINTERVAL7_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_TXINTERVAL7_NAKLMT_S \
- 0
-#define USB_TXINTERVAL7_TXPOLL_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
-//
-//*****************************************************************************
-#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed
-#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
-#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High
-#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
-#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
-#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol
-#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
-#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
-#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
-#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
-#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
-#define USB_RXTYPE7_TEP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXINTERVAL7
-// register.
-//
-//*****************************************************************************
-#define USB_RXINTERVAL7_TXPOLL_M \
- 0x000000FF // RX Polling
-#define USB_RXINTERVAL7_NAKLMT_M \
- 0x000000FF // NAK Limit
-#define USB_RXINTERVAL7_NAKLMT_S \
- 0
-#define USB_RXINTERVAL7_TXPOLL_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAINTR register.
-//
-//*****************************************************************************
-#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt
-#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt
-#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt
-#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt
-#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt
-#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt
-#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt
-#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL0 register.
-//
-//*****************************************************************************
-#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode
-#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length
-#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
-#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
- // length
-#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
- // unspecified length
-#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit
-#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number
-#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable
-#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode
-#define USB_DMACTL0_DIR 0x00000002 // DMA Direction
-#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable
-#define USB_DMACTL0_EP_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR0 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address
-#define USB_DMAADDR0_ADDR_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT0
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count
-#define USB_DMACOUNT0_COUNT_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL1 register.
-//
-//*****************************************************************************
-#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode
-#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length
-#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
-#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
- // length
-#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
- // unspecified length
-#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit
-#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number
-#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable
-#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode
-#define USB_DMACTL1_DIR 0x00000002 // DMA Direction
-#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable
-#define USB_DMACTL1_EP_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR1 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address
-#define USB_DMAADDR1_ADDR_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT1
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count
-#define USB_DMACOUNT1_COUNT_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL2 register.
-//
-//*****************************************************************************
-#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode
-#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length
-#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
-#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
- // length
-#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
- // unspecified length
-#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit
-#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number
-#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable
-#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode
-#define USB_DMACTL2_DIR 0x00000002 // DMA Direction
-#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable
-#define USB_DMACTL2_EP_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR2 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address
-#define USB_DMAADDR2_ADDR_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT2
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count
-#define USB_DMACOUNT2_COUNT_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL3 register.
-//
-//*****************************************************************************
-#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode
-#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length
-#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
-#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
- // length
-#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
- // unspecified length
-#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit
-#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number
-#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable
-#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode
-#define USB_DMACTL3_DIR 0x00000002 // DMA Direction
-#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable
-#define USB_DMACTL3_EP_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR3 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address
-#define USB_DMAADDR3_ADDR_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT3
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count
-#define USB_DMACOUNT3_COUNT_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL4 register.
-//
-//*****************************************************************************
-#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode
-#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length
-#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
-#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
- // length
-#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
- // unspecified length
-#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit
-#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number
-#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable
-#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode
-#define USB_DMACTL4_DIR 0x00000002 // DMA Direction
-#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable
-#define USB_DMACTL4_EP_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR4 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address
-#define USB_DMAADDR4_ADDR_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT4
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count
-#define USB_DMACOUNT4_COUNT_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL5 register.
-//
-//*****************************************************************************
-#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode
-#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length
-#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
-#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
- // length
-#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
- // unspecified length
-#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit
-#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number
-#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable
-#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode
-#define USB_DMACTL5_DIR 0x00000002 // DMA Direction
-#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable
-#define USB_DMACTL5_EP_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR5 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address
-#define USB_DMAADDR5_ADDR_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT5
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count
-#define USB_DMACOUNT5_COUNT_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL6 register.
-//
-//*****************************************************************************
-#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode
-#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length
-#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
-#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
- // length
-#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
- // unspecified length
-#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit
-#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number
-#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable
-#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode
-#define USB_DMACTL6_DIR 0x00000002 // DMA Direction
-#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable
-#define USB_DMACTL6_EP_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR6 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address
-#define USB_DMAADDR6_ADDR_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT6
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count
-#define USB_DMACOUNT6_COUNT_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACTL7 register.
-//
-//*****************************************************************************
-#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode
-#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length
-#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
-#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
- // length
-#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
- // unspecified length
-#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit
-#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number
-#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable
-#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode
-#define USB_DMACTL7_DIR 0x00000002 // DMA Direction
-#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable
-#define USB_DMACTL7_EP_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMAADDR7 register.
-//
-//*****************************************************************************
-#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address
-#define USB_DMAADDR7_ADDR_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMACOUNT7
-// register.
-//
-//*****************************************************************************
-#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count
-#define USB_DMACOUNT7_COUNT_S 2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count
-#define USB_RQPKTCOUNT1_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count
-#define USB_RQPKTCOUNT2_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count
-#define USB_RQPKTCOUNT3_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count
-#define USB_RQPKTCOUNT4_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count
-#define USB_RQPKTCOUNT5_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count
-#define USB_RQPKTCOUNT6_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count
-#define USB_RQPKTCOUNT7_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
- // Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
- // Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CTO register.
-//
-//*****************************************************************************
-#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value
-#define USB_CTO_CCTV_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_HHSRTN register.
-//
-//*****************************************************************************
-#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating
+#define MUSB_HHSRTN_HHSRTN_M 0xFFFF // HIgh Speed to UTM Operating
// Delay
-#define USB_HHSRTN_HHSRTN_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_HSBT register.
-//
-//*****************************************************************************
-#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder
-#define USB_HSBT_HSBT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMATTR register.
-//
-//*****************************************************************************
-#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint
-#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake
-#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration
-#define USB_LPMATTR_LS_M 0x0000000F // Link State
-#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1)
-#define USB_LPMATTR_ENDPT_S 12
-#define USB_LPMATTR_HIRD_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMCNTRL register.
-//
-//*****************************************************************************
-#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK
-#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable
-#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions
- // are not supported. In this case,
- // the USB does not respond to LPM
- // transactions and LPM
- // transactions cause a timeout
-#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but
- // extended transactions are
- // supported. In this case, the USB
- // does respond to an LPM
- // transaction with a STALL
-#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended
- // transactions. In this case, the
- // USB responds with a NYET or an
- // ACK as determined by the value
- // of TXLPM and other conditions
-#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume
-#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMIM register.
-//
-//*****************************************************************************
-#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask
-#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask
-#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask
-#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask
-#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask
-#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMRIS register.
-//
-//*****************************************************************************
-#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status
-#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status
-#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status
-#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status
-#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status
-#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LPMFADDR register.
-//
-//*****************************************************************************
-#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address
-#define USB_LPMFADDR_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPC register.
-//
-//*****************************************************************************
-#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action
-#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
-#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
-#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
-#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
-#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable
-#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense
-#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable
-#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable
-#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
- // Configuration
-#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
-#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
-#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
- // (OTG only)
-#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
- // (OTG only)
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCRIS register.
-//
-//*****************************************************************************
-#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCIM register.
-//
-//*****************************************************************************
-#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCISC register.
-//
-//*****************************************************************************
-#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
- // and Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRRIS register.
-//
-//*****************************************************************************
-#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRIM register.
-//
-//*****************************************************************************
-#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRISC register.
-//
-//*****************************************************************************
-#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
- // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_GPCS register.
-//
-//*****************************************************************************
-#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode
-#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin
-#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low
-#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high
-#define USB_GPCS_DEVMOD_HOSTVBUS \
- 0x00000004 // Use USB0VBUS and force USB0ID
- // low
-#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID
- // high
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDC register.
-//
-//*****************************************************************************
-#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCRIS register.
-//
-//*****************************************************************************
-#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCIM register.
-//
-//*****************************************************************************
-#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCISC register.
-//
-//*****************************************************************************
-#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
- // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_PP register.
-//
-//*****************************************************************************
-#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
-#define USB_PP_USB_M 0x000000C0 // USB Capability
-#define USB_PP_USB_DEVICE 0x00000040 // DEVICE
-#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
-#define USB_PP_USB_OTG 0x000000C0 // OTG
-#define USB_PP_ULPI 0x00000020 // ULPI Present
-#define USB_PP_PHY 0x00000010 // PHY Present
-#define USB_PP_TYPE_M 0x0000000F // Controller Type
-#define USB_PP_TYPE_0 0x00000000 // The first-generation USB
- // controller
-#define USB_PP_TYPE_1 0x00000001 // The second-generation USB
- // controller revision
-#define USB_PP_ECNT_S 8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_PC register.
-//
-//*****************************************************************************
-#define USB_PC_ULPIEN 0x00010000 // ULPI Enable
+#define MUSB_HHSRTN_HHSRTN_S 0
//*****************************************************************************
//
-// The following are defines for the bit fields in the USB_O_CC register.
+// The following are defines for the bit fields in the MUSB_O_HSBT register.
//
//*****************************************************************************
-#define USB_CC_CLKEN 0x00000200 // USB Clock Enable
-#define USB_CC_CSD 0x00000100 // Clock Source/Direction
-#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor
-#define USB_CC_CLKDIV_S 0
+#define MUSB_HSBT_HSBT_M 0x000F // High Speed Timeout Adder
+#define MUSB_HSBT_HSBT_S 0
#ifdef __cplusplus
}
diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c
index ccc27c3c9e..d40c4794a8 100644
--- a/src/portable/microchip/pic/dcd_pic.c
+++ b/src/portable/microchip/pic/dcd_pic.c
@@ -470,8 +470,8 @@ static void process_bus_resume(uint8_t rhport)
/*------------------------------------------------------------------*/
/* Device API
*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
intr_disable(rhport);
intr_clear(rhport);
@@ -502,6 +502,7 @@ void dcd_init(uint8_t rhport)
U1IE = _U1IE_URSTIE_MASK;
dcd_connect(rhport);
+ return true;
}
void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c
index 9ad755670f..8709baf671 100644
--- a/src/portable/microchip/pic32mz/dcd_pic32mz.c
+++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c
@@ -120,8 +120,8 @@ static ep0_stage_t ep0_get_stage(void)
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
// Disable endpoint interrupts for now
USB_REGS->INTRRXEbits.w = 0;
USB_REGS->INTRTXEbits.w = 0;
@@ -129,6 +129,7 @@ void dcd_init(uint8_t rhport)
USB_REGS->INTRUSBEbits.w = 7;
dcd_connect(rhport);
+ return true;
}
void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 976d3dfd02..0c96f6ac42 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -78,9 +78,9 @@ static void bus_reset(void)
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
-void dcd_init (uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
// Reset to get in a clean state.
USB->DEVICE.CTRLA.bit.SWRST = true;
@@ -102,6 +102,8 @@ void dcd_init (uint8_t rhport)
USB->DEVICE.INTFLAG.reg |= USB->DEVICE.INTFLAG.reg; // clear pending
USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST;
+
+ return true;
}
#if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X
@@ -183,9 +185,12 @@ void dcd_connect(uint8_t rhport)
void dcd_sof_enable(uint8_t rhport, bool en)
{
(void) rhport;
- (void) en;
- // TODO implement later
+ if (en) {
+ USB->DEVICE.INTENSET.bit.SOF = 1;
+ } else {
+ USB->DEVICE.INTENCLR.bit.SOF = 1;
+ }
}
/*------------------------------------------------------------------*/
@@ -374,7 +379,9 @@ void dcd_int_handler (uint8_t rhport)
if ( int_status & USB_DEVICE_INTFLAG_SOF )
{
USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
- dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+ const uint32_t frame = USB->DEVICE.FNUM.bit.FNUM;
+ dcd_event_sof(0, frame, true);
+ //dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
}
// SAMD doesn't distinguish between Suspend and Disconnect state.
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
index e3fa51e316..c88b315144 100644
--- a/src/portable/microchip/samg/dcd_samg.c
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -155,10 +155,13 @@ static void bus_reset(void)
}
// Initialize controller to device mode
-void dcd_init (uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rhport;
+ (void) rh_init;
+
tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
dcd_connect(rhport);
+ return true;
}
// Enable device interrupt
@@ -277,6 +280,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
return true;
}
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport; (void) ep_addr;
+ // TODO implement dcd_edpt_close()
+}
+
void dcd_edpt_close_all (uint8_t rhport)
{
(void) rhport;
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 9586df84d9..8aec1568d0 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -104,9 +104,10 @@ TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, in
//------------------------------------------------------------------
// Initialize controller to device mode
-void dcd_init (uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
dcd_connect(rhport);
+ return true;
}
// Enable device interrupt
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index c3d0c7297e..1ce3da27ee 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -245,9 +245,9 @@ static void process_bus_active(uint8_t rhport)
/*------------------------------------------------------------------*/
/* Device API
*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
tu_memclr(&_dcd, sizeof(_dcd));
USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >> 8);
@@ -256,6 +256,7 @@ void dcd_init(uint8_t rhport)
dcd_connect(rhport);
NVIC_ClearPendingIRQ(USB_FS_IRQn);
+ return true;
}
#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
void dcd_int_enable(uint8_t rhport)
@@ -283,7 +284,18 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
/* Response with status first before changing device address */
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
}
+
+#ifdef __GNUC__ // caused by extra declaration of SystemCoreClock in freeRTOSConfig.h
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
extern u32 SystemCoreClock;
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
void dcd_remote_wakeup(uint8_t rhport)
{
(void) rhport;
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 2fe721d6b3..3f53ee26e5 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -120,6 +120,9 @@ static struct {
// nRF can only carry one DMA at a time, this is used to guard the access to EasyDMA
atomic_flag dma_running;
+
+ // Track whether sof has been manually enabled
+ bool sof_enabled;
} _dcd;
/*------------------------------------------------------------------*/
@@ -147,7 +150,7 @@ static void start_dma(volatile uint32_t* reg_startep) {
static void edpt_dma_start(volatile uint32_t* reg_startep) {
if (atomic_flag_test_and_set(&_dcd.dma_running)) {
- usbd_defer_func((osal_task_func_t)(uintptr_t ) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
+ usbd_defer_func((osal_task_func_t)(uintptr_t ) edpt_dma_start, (void*) (uintptr_t) reg_startep, is_in_isr());
} else {
start_dma(reg_startep);
}
@@ -227,9 +230,11 @@ static void xact_in_dma(uint8_t epnum) {
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+
-void dcd_init(uint8_t rhport) {
- TU_LOG2("dcd init\r\n");
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
+ TU_LOG2("dcd init\r\n");
+ return true;
}
void dcd_int_enable(uint8_t rhport) {
@@ -283,9 +288,13 @@ void dcd_connect(uint8_t rhport) {
void dcd_sof_enable(uint8_t rhport, bool en) {
(void) rhport;
- (void) en;
-
- // TODO implement later
+ if (en) {
+ _dcd.sof_enabled = true;
+ NRF_USBD->INTENSET = USBD_INTENSET_SOF_Msk;
+ } else {
+ _dcd.sof_enabled = false;
+ NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
+ }
}
//--------------------------------------------------------------------+
@@ -434,11 +443,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));
if (control_status) {
- // Status Phase also requires EasyDMA has to be available as well !!!!
- edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
-
// The nRF doesn't interrupt on status transmit so we queue up a success response.
dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr());
+
+ // Status Phase also requires EasyDMA has to be available as well !!!!
+ edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
} else if (dir == TUSB_DIR_OUT) {
xfer->started = true;
if (epnum == 0) {
@@ -607,13 +616,16 @@ void dcd_int_handler(uint8_t rhport) {
}
}
- if (!iso_enabled) {
- // ISO endpoint is not used, SOF is only enabled one-time for remote wakeup
- // so we disable it now
- NRF_USBD->INTENCLR = USBD_INTENSET_SOF_Msk;
+ if (!iso_enabled && !_dcd.sof_enabled) {
+ // SOF interrupt not manually enabled and ISO endpoint is not used,
+ // SOF is only enabled one-time for remote wakeup so we disable it now
+
+ NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
}
- dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+ const uint32_t frame = NRF_USBD->FRAMECNTR;
+ dcd_event_sof(0, frame, true);
+ //dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
}
if (int_status & USBD_INTEN_USBEVENT_Msk) {
@@ -897,9 +909,9 @@ void tusb_hal_nrf_power_event(uint32_t event) {
USB_EVT_READY = 2
};
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= 3
const char* const power_evt_str[] = {"Detected", "Removed", "Ready"};
- TU_LOG(2, "Power USB event: %s\r\n", power_evt_str[event]);
+ TU_LOG(3, "Power USB event: %s\r\n", power_evt_str[event]);
#endif
switch (event) {
diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
index fb12122e01..b0b6fe8576 100644
--- a/src/portable/nuvoton/nuc120/dcd_nuc120.c
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -201,9 +201,9 @@ static const uint32_t enabled_irqs = USBD_INTSTS_FLDET_STS_Msk | USBD_INTSTS_BUS
NUC100/NUC120 TinyUSB API driver implementation
*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
USBD->ATTR = 0x7D0;
@@ -215,6 +215,8 @@ void dcd_init(uint8_t rhport)
USBD->INTSTS = enabled_irqs;
USBD->INTEN = enabled_irqs;
+
+ return true;
}
void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 873b1b7efa..f4af97ca75 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -209,9 +209,9 @@ enum {
NUC121/NUC125/NUC126 TinyUSB API driver implementation
*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
#ifdef SUPPORT_LPM
USBD->ATTR = 0x7D0 | USBD_LPMACK;
@@ -227,6 +227,8 @@ void dcd_init(uint8_t rhport)
USBD->INTSTS = ENABLED_IRQS;
USBD->INTEN = ENABLED_IRQS;
+
+ return true;
}
void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index 3a92c97946..1c98a0a493 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -279,9 +279,9 @@ static const uint32_t enabled_irqs = USBD_GINTEN_USBIEN_Msk | \
NUC505 TinyUSB API driver implementation
*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
/* configure interrupts in their initial state; BUSINTEN and CEPINTEN will be subsequently and dynamically re-written as needed */
USBD->GINTEN = enabled_irqs;
@@ -291,6 +291,8 @@ void dcd_init(uint8_t rhport)
bus_reset();
usb_attach();
+
+ return true;
}
void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index dc71117b36..8398b09bf8 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -265,9 +265,9 @@ static void process_bus_resume(uint8_t rhport)
/*------------------------------------------------------------------*/
/* Device API
*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
// save crystal-less setting (if available)
#if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
@@ -294,6 +294,8 @@ void dcd_init(uint8_t rhport)
dcd_connect(rhport);
NVIC_ClearPendingIRQ(USB0_IRQn);
+
+ return true;
}
void dcd_int_enable(uint8_t rhport)
@@ -540,7 +542,7 @@ void dcd_int_handler(uint8_t rhport)
}
if (is & USB_ISTAT_SLEEP_MASK) {
- // TU_LOG2("Suspend: "); TU_LOG2_HEX(is);
+ // TU_LOG3("Suspend: "); TU_LOG2_HEX(is);
// Note Host usually has extra delay after bus reset (without SOF), which could falsely
// detected as Sleep event. Though usbd has debouncing logic so we are good
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 57684b2594..f5ca73c18e 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -368,10 +368,9 @@ static void process_bus_reset(uint8_t rhport)
/*------------------------------------------------------------------*/
/* Host API
*------------------------------------------------------------------*/
-bool hcd_init(uint8_t rhport)
-{
- (void)rhport;
-
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rhport;
+ (void) rh_init;
KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index b880c28709..855c59cd1c 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -167,9 +167,9 @@ static void bus_reset(void)
tu_memclr(&_dcd, sizeof(dcd_data_t));
}
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
//------------- user manual 11.13 usb device controller initialization -------------//
// step 6 : set up control endpoint
@@ -186,6 +186,8 @@ void dcd_init(uint8_t rhport)
// Clear pending IRQ
NVIC_ClearPendingIRQ(USB_IRQn);
+
+ return true;
}
void dcd_int_enable(uint8_t rhport)
@@ -335,6 +337,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
return true;
}
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport; (void) ep_addr;
+ // TODO implement dcd_edpt_close()
+}
+
void dcd_edpt_close_all (uint8_t rhport)
{
(void) rhport;
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 022904a3ab..7d5cfb5b0f 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -42,7 +42,18 @@
#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
// LPCOpen
+ #ifdef __GNUC__
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wunused-parameter"
+ #pragma GCC diagnostic ignored "-Wstrict-prototypes"
+ #endif
+
#include "chip.h"
+
+ #ifdef __GNUC__
+ #pragma GCC diagnostic pop
+ #endif
+
#else
// SDK
#include "fsl_device_registers.h"
@@ -278,8 +289,8 @@ static void edpt_reset_all(uint8_t rhport)
}
prepare_setup_packet(rhport);
}
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
edpt_reset_all(rhport);
dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -292,6 +303,8 @@ void dcd_init(uint8_t rhport)
DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum);
+
+ return true;
}
void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index c59d4755ed..ce35eab706 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -178,9 +178,9 @@ TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address)
}
// Initialization according to 5.1.1.4
-bool hcd_init(uint8_t rhport)
-{
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
//------------- Data Structure init -------------//
tu_memclr(&ohci_data, sizeof(ohci_data_t));
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index e6daf68272..60afbd4352 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -50,12 +50,13 @@ static usb_descriptor_buffers_t desc;
*------------------------------------------------------------------*/
// Initialize controller to device mode
-void dcd_init (uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
-
+ (void) rh_init;
static pio_usb_configuration_t config = PIO_USB_DEFAULT_CONFIG;
usb_device = pio_usb_device_init(&config, &desc);
+
+ return true;
}
// Enable device interrupt
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index f4de3c51da..6422afff1a 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -55,8 +55,9 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) {
return true;
}
-bool hcd_init(uint8_t rhport) {
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
// To run USB SOF interrupt in core1, call this init in core1
pio_usb_host_init(&pio_host_cfg);
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index bc0deee328..2e177d5cbf 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -369,7 +369,8 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff
#endif
-void dcd_init(uint8_t rhport) {
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
assert(rhport == 0);
TU_LOG(2, "Chip Version B%u\r\n", rp2040_chip_version());
@@ -405,6 +406,7 @@ void dcd_init(uint8_t rhport) {
(FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS);
dcd_connect(rhport);
+ return true;
}
bool dcd_deinit(uint8_t rhport) {
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 222dbbbf03..2c0a3fd49e 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -375,9 +375,9 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
//--------------------------------------------------------------------+
// HCD API
//--------------------------------------------------------------------+
-bool hcd_init(uint8_t rhport)
-{
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
pico_trace("hcd_init %d\n", rhport);
assert(rhport == 0);
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 1ca711c778..43f48da396 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -53,6 +53,14 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) {
//--------------------------------------------------------------------+
// Implementation
//--------------------------------------------------------------------+
+// Provide own byte by byte memcpy as not all copies are aligned
+static void unaligned_memcpy(void *dst, const void *src, size_t n) {
+ uint8_t *dst_byte = (uint8_t*)dst;
+ const uint8_t *src_byte = (const uint8_t*)src;
+ while (n--) {
+ *dst_byte++ = *src_byte++;
+ }
+}
void rp2040_usb_init(void) {
// Reset usb controller
@@ -67,7 +75,6 @@ void rp2040_usb_init(void) {
#pragma GCC diagnostic ignored "-Wstringop-overflow"
#endif
#endif
- memset(usb_hw, 0, sizeof(*usb_hw));
memset(usb_dpram, 0, sizeof(*usb_dpram));
#ifdef __GNUC__
#pragma GCC diagnostic pop
@@ -125,7 +132,7 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint* ep,
if (!ep->rx) {
// Copy data from user buffer to hw buffer
- memcpy(ep->hw_data_buf + buf_id * 64, ep->user_buf, buflen);
+ unaligned_memcpy(ep->hw_data_buf + buf_id * 64, ep->user_buf, buflen);
ep->user_buf += buflen;
// Mark as full
@@ -230,7 +237,7 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint* ep, uin
// we have received AFTER we have copied it to the user buffer at the appropriate offset
assert(buf_ctrl & USB_BUF_CTRL_FULL);
- memcpy(ep->user_buf, ep->hw_data_buf + buf_id * 64, xferred_bytes);
+ unaligned_memcpy(ep->user_buf, ep->hw_data_buf + buf_id * 64, xferred_bytes);
ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
ep->user_buf += xferred_bytes;
}
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 50400d1f5f..ecd28973c7 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -29,10 +29,6 @@
#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#define USE_SOF 0
-
#include "device/dcd.h"
#include "rusb2_type.h"
@@ -74,6 +70,8 @@ typedef struct
{
pipe_state_t pipe[PIPE_COUNT];
uint8_t ep[2][16]; /* a lookup table for a pipe index from an endpoint address */
+ // Track whether sof has been manually enabled
+ bool sof_enabled;
} dcd_data_t;
static dcd_data_t _dcd;
@@ -659,11 +657,15 @@ static void enable_interrupt(uint32_t pswi)
}
#endif
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
rusb2_reg_t* rusb = RUSB2_REG(rhport);
rusb2_module_start(rhport, true);
+ // We disable SOF for now until needed later on.
+ // Since TinyUSB doesn't use SOF for now, and this interrupt often (1ms interval)
+ _dcd.sof_enabled = false;
+
#ifdef RUSB2_SUPPORT_HIGHSPEED
if ( rusb2_is_highspeed_rhport(rhport) ) {
rusb->SYSCFG_b.HSE = 1;
@@ -708,7 +710,7 @@ void dcd_init(uint8_t rhport)
rusb->INTSTS0 = 0;
rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
- RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
+ RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (_dcd.sof_enabled ? RUSB2_INTSTS0_SOFR_Msk : 0) |
RUSB2_INTSTS0_RESM_Msk;
rusb->BEMPENB = 1;
rusb->BRDYENB = 1;
@@ -717,6 +719,8 @@ void dcd_init(uint8_t rhport)
if (rusb->INTSTS0_b.VBSTS) {
dcd_connect(rhport);
}
+
+ return true;
}
void dcd_int_enable(uint8_t rhport) {
@@ -756,10 +760,9 @@ void dcd_disconnect(uint8_t rhport)
void dcd_sof_enable(uint8_t rhport, bool en)
{
- (void) rhport;
- (void) en;
-
- // TODO implement later
+ rusb2_reg_t* rusb = RUSB2_REG(rhport);
+ _dcd.sof_enabled = en;
+ rusb->INTENB0_b.SOFE = en ? 1: 0;
}
//--------------------------------------------------------------------+
@@ -949,18 +952,19 @@ void dcd_int_handler(uint8_t rhport)
// Resumed
if ( is0 & RUSB2_INTSTS0_RESM_Msk ) {
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-#if (0 == USE_SOF)
- rusb->INTENB0_b.SOFE = 0;
-#endif
+ if (!_dcd.sof_enabled) {
+ rusb->INTENB0_b.SOFE = 0;
+ }
}
// SOF received
if ( (is0 & RUSB2_INTSTS0_SOFR_Msk) && rusb->INTENB0_b.SOFE ) {
// USBD will exit suspended mode when SOF event is received
- dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-#if (0 == USE_SOF)
- rusb->INTENB0_b.SOFE = 0;
-#endif
+ const uint32_t frame = rusb->FRMNUM_b.FRNM;
+ dcd_event_sof(rhport, frame, true);
+ if (!_dcd.sof_enabled) {
+ rusb->INTENB0_b.SOFE = 0;
+ }
}
// Device state changes
@@ -979,9 +983,9 @@ void dcd_int_handler(uint8_t rhport)
case RUSB2_INTSTS0_DVSQ_STATE_SUSP2:
case RUSB2_INTSTS0_DVSQ_STATE_SUSP3:
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-#if (0 == USE_SOF)
- rusb->INTENB0_b.SOFE = 1;
-#endif
+ if (!_dcd.sof_enabled) {
+ rusb->INTENB0_b.SOFE = 1;
+ }
default: break;
}
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index f140da6909..4c81b05be8 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -466,8 +466,8 @@ static void enable_interrupt(uint32_t pswi)
}
#endif
-bool hcd_init(uint8_t rhport)
-{
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
rusb2_reg_t* rusb = RUSB2_REG(rhport);
rusb2_module_start(rhport, true);
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index 41814370ea..b16509c6fb 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -201,9 +201,9 @@ static void _dcd_resume(FAR struct usbdevclass_driver_s *driver, FAR struct usbd
dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
}
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
usbdcd_driver.usbdevclass_driver.speed = USB_SPEED_HIGH;
usbdcd_driver.usbdevclass_driver.ops = &g_driverops;
@@ -211,6 +211,8 @@ void dcd_init(uint8_t rhport)
usbdcd_driver.setup_queue = osal_queue_create(&_setup_queue_def);
usbdev_register(&usbdcd_driver.usbdevclass_driver);
+
+ return true;
}
// Enable device interrupt
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index a26c668929..d921429e29 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -4,7 +4,6 @@
* Copyright (c) 2019 Nathan Conrad
*
* Portions:
- * Copyright (c) 2016 STMicroelectronics
* Copyright (c) 2019 Ha Thach (tinyusb.org)
* Copyright (c) 2022 Simon Küppers (skuep)
* Copyright (c) 2022 HiFiPhile
@@ -37,14 +36,20 @@
* It also should work with minimal changes for any ST MCU with an "USB A"/"PCD"/"HCD" peripheral. This
* covers:
*
- * F04x, F072, F078, 070x6/B 1024 byte buffer
+ * F04x, F072, F078, F070x6/B 1024 byte buffer
* F102, F103 512 byte buffer; no internal D+ pull-up (maybe many more changes?)
* F302xB/C, F303xB/C, F373 512 byte buffer; no internal D+ pull-up
* F302x6/8, F302xD/E2, F303xD/E 1024 byte buffer; no internal D+ pull-up
+ * G0 2048 byte buffer; 32-bit bus; host mode
+ * G4 1024 byte buffer
+ * H5 2048 byte buffer; 32-bit bus; host mode
* L0x2, L0x3 1024 byte buffer
* L1 512 byte buffer
* L4x2, L4x3 1024 byte buffer
- * G0 2048 byte buffer
+ * L5 1024 byte buffer
+ * U0 1024 byte buffer; 32-bit bus
+ * U535, U545 2048 byte buffer; 32-bit bus; host mode
+ * WB35, WB55 1024 byte buffer
*
* To use this driver, you must:
* - If you are using a device with crystal-less USB, set up the clock recovery system (CRS)
@@ -102,43 +107,20 @@
#include "tusb_option.h"
-#if CFG_TUD_ENABLED && defined(TUP_USBIP_FSDEV)
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_FSDEV) && \
+ !(defined(TUP_USBIP_FSDEV_CH32) && CFG_TUD_WCH_USBIP_FSDEV == 0)
#include "device/dcd.h"
-#ifdef TUP_USBIP_FSDEV_STM32
-// Undefine to reduce the dependence on HAL
-#undef USE_HAL_DRIVER
-#include "portable/st/stm32_fsdev/dcd_stm32_fsdev.h"
-#endif
-
-/*****************************************************
- * Configuration
- *****************************************************/
-
-// HW supports max of 8 bidirectional endpoints, but this can be reduced to save RAM
-// (8u here would mean 8 IN and 8 OUT)
-#ifndef MAX_EP_COUNT
-#define MAX_EP_COUNT 8U
-#endif
-
-// If sharing with CAN, one can set this to be non-zero to give CAN space where it wants it
-// Both of these MUST be a multiple of 2, and are in byte units.
-#ifndef DCD_STM32_BTABLE_BASE
-#define DCD_STM32_BTABLE_BASE 0U
-#endif
-
-#ifndef DCD_STM32_BTABLE_SIZE
-#define DCD_STM32_BTABLE_SIZE (FSDEV_PMA_SIZE - DCD_STM32_BTABLE_BASE)
+#if defined(TUP_USBIP_FSDEV_STM32)
+ #include "fsdev_stm32.h"
+#elif defined(TUP_USBIP_FSDEV_CH32)
+ #include "fsdev_ch32.h"
+#else
+ #error "Unknown USB IP"
#endif
-/***************************************************
- * Checks, structs, defines, function definitions, etc.
- */
-
-TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware");
-TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_SIZE)) <= (FSDEV_PMA_SIZE), "BTABLE does not fit in PMA RAM");
-TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
+#include "fsdev_type.h"
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
@@ -162,12 +144,8 @@ typedef struct {
bool allocated[2];
} ep_alloc_t;
-static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
-
-static ep_alloc_t ep_alloc_status[STFSDEV_EP_COUNT];
-
-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
-
+static xfer_ctl_t xfer_status[CFG_TUD_ENDPPOINT_MAX][2];
+static ep_alloc_t ep_alloc_status[FSDEV_EP_COUNT];
static uint8_t remoteWakeCountdown; // When wake is requested
//--------------------------------------------------------------------+
@@ -175,253 +153,93 @@ static uint8_t remoteWakeCountdown; // When wake is requested
//--------------------------------------------------------------------+
// into the stack.
-static void dcd_handle_bus_reset(void);
+static void handle_bus_reset(uint8_t rhport);
static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix);
-static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr);
-static void dcd_ep_ctr_handler(void);
+static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir);
// PMA allocation/access
static uint16_t ep_buf_ptr; ///< Points to first free memory location
-static uint32_t dcd_pma_alloc(uint16_t length, bool dbuf);
+static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf);
static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
-static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes);
-static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes);
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t nbytes);
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t nbytes);
static bool dcd_write_packet_memory_ff(tu_fifo_t *ff, uint16_t dst, uint16_t wNBytes);
static bool dcd_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes);
+static void edpt0_open(uint8_t rhport);
+
+TU_ATTR_ALWAYS_INLINE static inline void edpt0_prepare_setup(void) {
+ btable_set_rx_bufsize(0, BTABLE_BUF_RX, 8);
+}
+
//--------------------------------------------------------------------+
// Inline helper
//--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint32_t ep_addr)
-{
- uint8_t epnum = tu_edpt_number(ep_addr);
- uint8_t dir = tu_edpt_dir(ep_addr);
- // Fix -Werror=null-dereference
- TU_ASSERT(epnum < MAX_EP_COUNT, &xfer_status[0][0]);
-
+TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint8_t epnum, uint8_t dir) {
return &xfer_status[epnum][dir];
}
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+
-
-void dcd_init(uint8_t rhport)
-{
- /* Clocks should already be enabled */
- /* Use __HAL_RCC_USB_CLK_ENABLE(); to enable the clocks before calling this function */
-
- /* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL.
- * Here, the RM is followed. */
-
- for (uint32_t i = 0; i < 200; i++) { // should be a few us
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
+ // Follow the RM mentions to use a special ordering of PDWN and FRES
+ for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
+
// Perform USB peripheral reset
- USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
- for (uint32_t i = 0; i < 200; i++) { // should be a few us
+ FSDEV_REG->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
+ for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
- USB->CNTR &= ~USB_CNTR_PDWN;
+ FSDEV_REG->CNTR &= ~USB_CNTR_PDWN;
// Wait startup time, for F042 and F070, this is <= 1 us.
- for (uint32_t i = 0; i < 200; i++) { // should be a few us
+ for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us
asm("NOP");
}
- USB->CNTR = 0; // Enable USB
+ FSDEV_REG->CNTR = 0; // Enable USB
-#if !defined(STM32G0) && !defined(STM32H5) // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
- USB->BTABLE = DCD_STM32_BTABLE_BASE;
+#if !defined(FSDEV_BUS_32BIT)
+ // BTABLE register does not exist any more on 32-bit bus devices
+ FSDEV_REG->BTABLE = FSDEV_BTABLE_BASE;
#endif
- USB->ISTR = 0; // Clear pending interrupts
+
+ FSDEV_REG->ISTR = 0; // Clear pending interrupts
// Reset endpoints to disabled
- for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) {
+ for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) {
// This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.
- pcd_set_endpoint(USB, i, 0u);
+ ep_write(i, 0u, false);
}
- USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
- dcd_handle_bus_reset();
+ FSDEV_REG->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM |
+ USB_CNTR_SUSPM | USB_CNTR_WKUPM | USB_CNTR_PMAOVRM;
+ handle_bus_reset(rhport);
// Enable pull-up if supported
- if (dcd_connect) {
- dcd_connect(rhport);
- }
-}
-
-// Define only on MCU with internal pull-up. BSP can define on MCU without internal PU.
-#if defined(USB_BCDR_DPPU)
-
-// Disable internal D+ PU
-void dcd_disconnect(uint8_t rhport)
-{
- (void)rhport;
- USB->BCDR &= ~(USB_BCDR_DPPU);
-}
-
-// Enable internal D+ PU
-void dcd_connect(uint8_t rhport)
-{
- (void)rhport;
- USB->BCDR |= USB_BCDR_DPPU;
-}
+ dcd_connect(rhport);
-#elif defined(SYSCFG_PMC_USB_PU) // works e.g. on STM32L151
-// Disable internal D+ PU
-void dcd_disconnect(uint8_t rhport)
-{
- (void)rhport;
- SYSCFG->PMC &= ~(SYSCFG_PMC_USB_PU);
+ return true;
}
-// Enable internal D+ PU
-void dcd_connect(uint8_t rhport)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
(void)rhport;
- SYSCFG->PMC |= SYSCFG_PMC_USB_PU;
-}
-#endif
-
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
- (void)rhport;
- (void)en;
if (en) {
- USB->CNTR |= USB_CNTR_SOFM;
+ FSDEV_REG->CNTR |= USB_CNTR_SOFM;
} else {
- USB->CNTR &= ~USB_CNTR_SOFM;
+ FSDEV_REG->CNTR &= ~USB_CNTR_SOFM;
}
}
-// Enable device interrupt
-void dcd_int_enable(uint8_t rhport)
-{
- (void)rhport;
- // Member here forces write to RAM before allowing ISR to execute
- __DSB();
- __ISB();
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || CFG_TUSB_MCU == OPT_MCU_STM32L4
- NVIC_EnableIRQ(USB_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
- NVIC_EnableIRQ(USB_LP_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
-// Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
-// shared USB/CAN IRQs to separate CAN and USB IRQs.
-// This dynamically checks if this remap is active to enable the right IRQs.
-#ifdef SYSCFG_CFGR1_USB_IT_RMP
- if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
- NVIC_EnableIRQ(USB_HP_IRQn);
- NVIC_EnableIRQ(USB_LP_IRQn);
- NVIC_EnableIRQ(USBWakeUp_RMP_IRQn);
- } else
-#endif
- {
- NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn);
- NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
- NVIC_EnableIRQ(USBWakeUp_IRQn);
- }
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
- NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn);
- NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
- NVIC_EnableIRQ(USBWakeUp_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
- NVIC_EnableIRQ(USB_HP_IRQn);
- NVIC_EnableIRQ(USB_LP_IRQn);
- NVIC_EnableIRQ(USBWakeUp_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-#ifdef STM32G0B0xx
- NVIC_EnableIRQ(USB_IRQn);
-#else
- NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
-#endif
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
- NVIC_EnableIRQ(USB_DRD_FS_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
- NVIC_EnableIRQ(USB_HP_IRQn);
- NVIC_EnableIRQ(USB_LP_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
- NVIC_EnableIRQ(USB_FS_IRQn);
-
-#else
-#error Unknown arch in USB driver
-#endif
-}
-
-// Disable device interrupt
-void dcd_int_disable(uint8_t rhport)
-{
- (void)rhport;
-
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || CFG_TUSB_MCU == OPT_MCU_STM32L4
- NVIC_DisableIRQ(USB_IRQn);
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
- NVIC_DisableIRQ(USB_LP_IRQn);
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
-// Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
-// shared USB/CAN IRQs to separate CAN and USB IRQs.
-// This dynamically checks if this remap is active to disable the right IRQs.
-#ifdef SYSCFG_CFGR1_USB_IT_RMP
- if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
- NVIC_DisableIRQ(USB_HP_IRQn);
- NVIC_DisableIRQ(USB_LP_IRQn);
- NVIC_DisableIRQ(USBWakeUp_RMP_IRQn);
- } else
-#endif
- {
- NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn);
- NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn);
- NVIC_DisableIRQ(USBWakeUp_IRQn);
- }
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
- NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);
- NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
- NVIC_DisableIRQ(USBWakeUp_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
- NVIC_DisableIRQ(USB_HP_IRQn);
- NVIC_DisableIRQ(USB_LP_IRQn);
- NVIC_DisableIRQ(USBWakeUp_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-#ifdef STM32G0B0xx
- NVIC_DisableIRQ(USB_IRQn);
-#else
- NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
-#endif
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
- NVIC_DisableIRQ(USB_DRD_FS_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
- NVIC_DisableIRQ(USB_HP_IRQn);
- NVIC_DisableIRQ(USB_LP_IRQn);
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
- NVIC_DisableIRQ(USB_FS_IRQn);
-
-#else
-#error Unknown arch in USB driver
-#endif
-
- // CMSIS has a membar after disabling interrupts
-}
-
// Receive Set Address request, mcu port must also include status IN response
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
- (void)rhport;
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
(void)dev_addr;
// Respond with status
@@ -431,37 +249,17 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
// do it at dcd_edpt0_status_complete()
}
-void dcd_remote_wakeup(uint8_t rhport)
-{
+void dcd_remote_wakeup(uint8_t rhport) {
(void)rhport;
- USB->CNTR |= USB_CNTR_RESUME;
+ FSDEV_REG->CNTR |= USB_CNTR_RESUME;
remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
}
-static const tusb_desc_endpoint_t ep0OUT_desc = {
- .bLength = sizeof(tusb_desc_endpoint_t),
- .bDescriptorType = TUSB_DESC_ENDPOINT,
- .bEndpointAddress = 0x00,
- .bmAttributes = {.xfer = TUSB_XFER_CONTROL},
- .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
- .bInterval = 0
-};
-
-static const tusb_desc_endpoint_t ep0IN_desc = {
- .bLength = sizeof(tusb_desc_endpoint_t),
- .bDescriptorType = TUSB_DESC_ENDPOINT,
- .bEndpointAddress = 0x80,
- .bmAttributes = {.xfer = TUSB_XFER_CONTROL},
- .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
- .bInterval = 0
-};
-
-static void dcd_handle_bus_reset(void)
-{
- USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
+static void handle_bus_reset(uint8_t rhport) {
+ FSDEV_REG->DADDR = 0u; // disable USB Function
- for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) {
+ for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) {
// Clear EP allocation status
ep_alloc_status[i].ep_num = 0xFF;
ep_alloc_status[i].ep_type = 0xFF;
@@ -470,35 +268,21 @@ static void dcd_handle_bus_reset(void)
}
// Reset PMA allocation
- ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8 * MAX_EP_COUNT;
+ ep_buf_ptr = FSDEV_BTABLE_BASE + 8 * FSDEV_EP_COUNT;
- dcd_edpt_open(0, &ep0OUT_desc);
- dcd_edpt_open(0, &ep0IN_desc);
+ edpt0_open(rhport); // open control endpoint (both IN & OUT)
- USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
+ FSDEV_REG->DADDR = USB_DADDR_EF; // Enable USB Function
}
// Handle CTR interrupt for the TX/IN direction
-//
-// Upon call, (wIstr & USB_ISTR_DIR) == 0U
-static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
-{
- uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
- uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
- uint8_t ep_addr = (wEPRegVal & USB_EPADDR_FIELD) | TUSB_DIR_IN_MASK;
-
- // Verify the CTR_TX bit is set. This was in the ST Micro code,
- // but I'm not sure it's actually necessary?
- if ((wEPRegVal & USB_EP_CTR_TX) == 0U) {
- return;
- }
-
- /* clear int flag */
- pcd_clear_tx_ep_ctr(USB, EPindex);
+static void handle_ctr_tx(uint32_t ep_id) {
+ uint32_t ep_reg = ep_read(ep_id) | USB_EP_CTR_TX | USB_EP_CTR_RX;
- xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
+ uint8_t const ep_num = ep_reg & USB_EPADDR_FIELD;
+ xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_IN);
- if ((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
+ if (ep_is_iso(ep_reg)) {
// Ignore spurious interrupts that we don't schedule
// host can send IN token while there is no data to send, since ISO does not have NAK
// this will result to zero length packet --> trigger interrupt (which cannot be masked)
@@ -506,190 +290,106 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
return;
}
xfer->iso_in_sending = false;
-
- if (wEPRegVal & USB_EP_DTOG_TX) {
- pcd_set_ep_tx_dbuf0_cnt(USB, EPindex, 0);
- } else {
- pcd_set_ep_tx_dbuf1_cnt(USB, EPindex, 0);
- }
+ uint8_t buf_id = (ep_reg & USB_EP_DTOG_TX) ? 0 : 1;
+ btable_set_count(ep_id, buf_id, 0);
}
- if ((xfer->total_len != xfer->queued_len)) {
- dcd_transmit_packet(xfer, EPindex);
+ if (xfer->total_len != xfer->queued_len) {
+ dcd_transmit_packet(xfer, ep_id);
} else {
- dcd_event_xfer_complete(0, ep_addr, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ dcd_event_xfer_complete(0, ep_num | TUSB_DIR_IN_MASK, xfer->queued_len, XFER_RESULT_SUCCESS, true);
}
}
-// Handle CTR interrupt for the RX/OUT direction
-// Upon call, (wIstr & USB_ISTR_DIR) == 0U
-static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
-{
-#ifdef FSDEV_BUS_32BIT
- /* https://www.st.com/resource/en/errata_sheet/es0561-stm32h503cbebkbrb-device-errata-stmicroelectronics.pdf
- * From STM32H503 errata 2.15.1: Buffer description table update completes after CTR interrupt triggers
- * Description:
- * - During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
- * have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
- * Workaround:
- * - Software should ensure that a small delay is included before accessing the SRAM contents. This delay
- * should be 800 ns in Full Speed mode and 6.4 μs in Low Speed mode
- * - Since H5 can run up to 250Mhz -> 1 cycle = 4ns. Per errata, we need to wait 200 cycles. Though executing code
- * also takes time, so we'll wait 60 cycles (count = 20).
- * - Since Low Speed mode is not supported/popular, we will ignore it for now.
- *
- * Note: this errata also seems to apply to G0, U5, H5 etc.
- */
- volatile uint32_t cycle_count = 20; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
- while (cycle_count > 0U) {
- cycle_count--; // each count take 3 cycles (1 for sub, jump, and compare)
- }
-#endif
-
- uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
- uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
- uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD;
+static void handle_ctr_setup(uint32_t ep_id) {
+ uint16_t rx_count = btable_get_count(ep_id, BTABLE_BUF_RX);
+ uint16_t rx_addr = btable_get_addr(ep_id, BTABLE_BUF_RX);
+ uint8_t setup_packet[8] TU_ATTR_ALIGNED(4);
- xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
+ dcd_read_packet_memory(setup_packet, rx_addr, rx_count);
- // Verify the CTR_RX bit is set. This was in the ST Micro code,
- // but I'm not sure it's actually necessary?
- if ((wEPRegVal & USB_EP_CTR_RX) == 0U) {
- return;
- }
+ // Clear CTR RX if another setup packet arrived before this, it will be discarded
+ ep_write_clear_ctr(ep_id, TUSB_DIR_OUT);
- if ((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) {
- /* Setup packet */
- uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex);
- // Setup packet should always be 8 bytes. If not, ignore it, and try again.
- if (count == 8) {
- // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
- pcd_set_ep_rx_status(USB, 0u, USB_EP_RX_NAK);
- pcd_set_ep_tx_status(USB, 0u, USB_EP_TX_NAK);
-#ifdef FSDEV_BUS_32BIT
- dcd_event_setup_received(0, (uint8_t *)(USB_PMAADDR + pcd_get_ep_rx_address(USB, EPindex)), true);
-#else
- // The setup_received function uses memcpy, so this must first copy the setup data into
- // user memory, to allow for the 32-bit access that memcpy performs.
- uint8_t userMemBuf[8];
- dcd_read_packet_memory(userMemBuf, pcd_get_ep_rx_address(USB, EPindex), 8);
- dcd_event_setup_received(0, (uint8_t *)userMemBuf, true);
-#endif
- }
+ // Setup packet should always be 8 bytes. If not, we probably missed the packet
+ if (rx_count == 8) {
+ dcd_event_setup_received(0, (uint8_t*) setup_packet, true);
+ // Hardware should reset EP0 RX/TX to NAK and both toggle to 1
} else {
- // Clear RX CTR interrupt flag
- if (ep_addr != 0u) {
- pcd_clear_rx_ep_ctr(USB, EPindex);
- }
-
- uint32_t count;
- uint16_t addr;
- /* Read from correct register when ISOCHRONOUS (double buffered) */
- if ((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
- if (wEPRegVal & USB_EP_DTOG_RX) {
- count = pcd_get_ep_dbuf0_cnt(USB, EPindex);
- addr = pcd_get_ep_dbuf0_address(USB, EPindex);
- } else {
- count = pcd_get_ep_dbuf1_cnt(USB, EPindex);
- addr = pcd_get_ep_dbuf1_address(USB, EPindex);
- }
- } else {
- count = pcd_get_ep_rx_cnt(USB, EPindex);
- addr = pcd_get_ep_rx_address(USB, EPindex);
- }
-
- TU_ASSERT(count <= xfer->max_packet_size, /**/);
-
- if (count != 0U) {
- if (xfer->ff) {
- dcd_read_packet_memory_ff(xfer->ff, addr, count);
- } else {
- dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), addr, count);
- }
+ // Missed setup packet !!!
+ TU_BREAKPOINT();
+ edpt0_prepare_setup();
+ }
+}
- xfer->queued_len = (uint16_t)(xfer->queued_len + count);
- }
+// Handle CTR interrupt for the RX/OUT direction
+static void handle_ctr_rx(uint32_t ep_id) {
+ uint32_t ep_reg = ep_read(ep_id) | USB_EP_CTR_TX | USB_EP_CTR_RX;
+ uint8_t const ep_num = ep_reg & USB_EPADDR_FIELD;
+ bool const is_iso = ep_is_iso(ep_reg);
+ xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_OUT);
- if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
- // all bytes received or short packet
- dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
- } else {
- /* Set endpoint active again for receiving more data.
- * Note that isochronous endpoints stay active always */
- if ((wEPRegVal & USB_EP_TYPE_MASK) != USB_EP_ISOCHRONOUS) {
- uint16_t remaining = xfer->total_len - xfer->queued_len;
- uint16_t cnt = tu_min16(remaining, xfer->max_packet_size);
- pcd_set_ep_rx_cnt(USB, EPindex, cnt);
- }
- pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
- }
+ uint8_t buf_id;
+ if (is_iso) {
+ buf_id = (ep_reg & USB_EP_DTOG_RX) ? 0 : 1; // ISO are double buffered
+ } else {
+ buf_id = BTABLE_BUF_RX;
}
+ uint16_t const rx_count = btable_get_count(ep_id, buf_id);
+ uint16_t pma_addr = (uint16_t) btable_get_addr(ep_id, buf_id);
- // For EP0, prepare to receive another SETUP packet.
- // Clear CTR last so that a new packet does not overwrite the packing being read.
- // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared)
- if (ep_addr == 0u) {
- // Always be prepared for a status packet...
- pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
- pcd_clear_rx_ep_ctr(USB, EPindex);
+ if (xfer->ff) {
+ dcd_read_packet_memory_ff(xfer->ff, pma_addr, rx_count);
+ } else {
+ dcd_read_packet_memory(xfer->buffer + xfer->queued_len, pma_addr, rx_count);
}
-}
+ xfer->queued_len += rx_count;
-static void dcd_ep_ctr_handler(void)
-{
- uint32_t wIstr;
+ if ((rx_count < xfer->max_packet_size) || (xfer->queued_len >= xfer->total_len)) {
+ // all bytes received or short packet
- /* stay in loop while pending interrupts */
- while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U) {
- if ((wIstr & USB_ISTR_DIR) == 0U) {
- /* TX/IN */
- dcd_ep_ctr_tx_handler(wIstr);
- } else {
- /* RX/OUT*/
- dcd_ep_ctr_rx_handler(wIstr);
+ // For ch32v203: reset rx bufsize to mps to prevent race condition to cause PMAOVR (occurs with msc write10)
+ btable_set_rx_bufsize(ep_id, BTABLE_BUF_RX, xfer->max_packet_size);
+
+ dcd_event_xfer_complete(0, ep_num, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+
+ // ch32 seems to unconditionally accept ZLP on EP0 OUT, which can incorrectly use queued_len of previous
+ // transfer. So reset total_len and queued_len to 0.
+ xfer->total_len = xfer->queued_len = 0;
+ } else {
+ // Set endpoint active again for receiving more data. Note that isochronous endpoints stay active always
+ if (!is_iso) {
+ uint16_t const cnt = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
+ btable_set_rx_bufsize(ep_id, BTABLE_BUF_RX, cnt);
}
+ ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(TUSB_DIR_OUT); // will change RX Status, reserved other toggle bits
+ ep_change_status(&ep_reg, TUSB_DIR_OUT, EP_STAT_VALID);
+ ep_write(ep_id, ep_reg, false);
}
}
-void dcd_int_handler(uint8_t rhport)
-{
-
- (void)rhport;
-
- uint32_t int_status = USB->ISTR;
- // const uint32_t handled_ints = USB_ISTR_CTR | USB_ISTR_RESET | USB_ISTR_WKUP
- // | USB_ISTR_SUSP | USB_ISTR_SOF | USB_ISTR_ESOF;
- // unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_L1REQ )
-
- // The ST driver loops here on the CTR bit, but that loop has been moved into the
- // dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't
- // be triggered repeatedly.
+void dcd_int_handler(uint8_t rhport) {
+ uint32_t int_status = FSDEV_REG->ISTR;
/* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
if (int_status & USB_ISTR_SOF) {
- USB->ISTR = (fsdev_bus_t)~USB_ISTR_SOF;
- dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
+ FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_SOF;
+ dcd_event_sof(0, FSDEV_REG->FNR & USB_FNR_FN, true);
}
if (int_status & USB_ISTR_RESET) {
// USBRST is start of reset.
- USB->ISTR = (fsdev_bus_t)~USB_ISTR_RESET;
- dcd_handle_bus_reset();
+ FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_RESET;
+ handle_bus_reset(rhport);
dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
return; // Don't do the rest of the things here; perhaps they've been cleared?
}
- if (int_status & USB_ISTR_CTR) {
- /* servicing of the endpoint correct transfer interrupt */
- /* clear of the CTR flag into the sub */
- dcd_ep_ctr_handler();
- }
-
if (int_status & USB_ISTR_WKUP) {
- USB->CNTR &= ~USB_CNTR_LPMODE;
- USB->CNTR &= ~USB_CNTR_FSUSP;
+ FSDEV_REG->CNTR &= ~USB_CNTR_LPMODE;
+ FSDEV_REG->CNTR &= ~USB_CNTR_FSUSP;
- USB->ISTR = (fsdev_bus_t)~USB_ISTR_WKUP;
+ FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_WKUP;
dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
}
@@ -698,22 +398,70 @@ void dcd_int_handler(uint8_t rhport)
* these events cannot be differentiated, so we only trigger suspend. */
/* Force low-power mode in the macrocell */
- USB->CNTR |= USB_CNTR_FSUSP;
- USB->CNTR |= USB_CNTR_LPMODE;
+ FSDEV_REG->CNTR |= USB_CNTR_FSUSP;
+ FSDEV_REG->CNTR |= USB_CNTR_LPMODE;
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
- USB->ISTR = (fsdev_bus_t)~USB_ISTR_SUSP;
+ FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_SUSP;
dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
}
if (int_status & USB_ISTR_ESOF) {
if (remoteWakeCountdown == 1u) {
- USB->CNTR &= ~USB_CNTR_RESUME;
+ FSDEV_REG->CNTR &= ~USB_CNTR_RESUME;
}
if (remoteWakeCountdown > 0u) {
remoteWakeCountdown--;
}
- USB->ISTR = (fsdev_bus_t)~USB_ISTR_ESOF;
+ FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_ESOF;
+ }
+
+ // loop to handle all pending CTR interrupts
+ while (FSDEV_REG->ISTR & USB_ISTR_CTR) {
+ // skip DIR bit, and use CTR TX/RX instead, since there is chance we have both TX/RX completed in one interrupt
+ uint32_t const ep_id = FSDEV_REG->ISTR & USB_ISTR_EP_ID;
+ uint32_t const ep_reg = ep_read(ep_id);
+
+ if (ep_reg & USB_EP_CTR_RX) {
+ #ifdef FSDEV_BUS_32BIT
+ /* https://www.st.com/resource/en/errata_sheet/es0561-stm32h503cbebkbrb-device-errata-stmicroelectronics.pdf
+ * https://www.st.com/resource/en/errata_sheet/es0587-stm32u535xx-and-stm32u545xx-device-errata-stmicroelectronics.pdf
+ * From H503/U535 errata: Buffer description table update completes after CTR interrupt triggers
+ * Description:
+ * - During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
+ * have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
+ * Workaround:
+ * - Software should ensure that a small delay is included before accessing the SRAM contents. This delay
+ * should be 800 ns in Full Speed mode and 6.4 μs in Low Speed mode
+ * - Since H5 can run up to 250Mhz -> 1 cycle = 4ns. Per errata, we need to wait 200 cycles. Though executing code
+ * also takes time, so we'll wait 60 cycles (count = 20).
+ * - Since Low Speed mode is not supported/popular, we will ignore it for now.
+ *
+ * Note: this errata may also apply to G0, U5, H5 etc.
+ */
+ volatile uint32_t cycle_count = 20; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
+ while (cycle_count > 0U) {
+ cycle_count--; // each count take 3 cycles (1 for sub, jump, and compare)
+ }
+ #endif
+
+ if (ep_reg & USB_EP_SETUP) {
+ handle_ctr_setup(ep_id); // CTR will be clear after copied setup packet
+ } else {
+ ep_write_clear_ctr(ep_id, TUSB_DIR_OUT);
+ handle_ctr_rx(ep_id);
+ }
+ }
+
+ if (ep_reg & USB_EP_CTR_TX) {
+ ep_write_clear_ctr(ep_id, TUSB_DIR_IN);
+ handle_ctr_tx(ep_id);
+ }
+ }
+
+ if (int_status & USB_ISTR_PMAOVR) {
+ TU_BREAKPOINT();
+ FSDEV_REG->ISTR = (fsdev_bus_t)~USB_ISTR_PMAOVR;
}
}
@@ -723,19 +471,17 @@ void dcd_int_handler(uint8_t rhport)
// Invoked when a control transfer's status stage is complete.
// May help DCD to prepare for next control transfer, this API is optional.
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request)
-{
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
(void)rhport;
if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
request->bRequest == TUSB_REQ_SET_ADDRESS) {
uint8_t const dev_addr = (uint8_t)request->wValue;
-
- // Setting new address after the whole request is complete
- USB->DADDR &= ~USB_DADDR_ADD;
- USB->DADDR |= dev_addr; // leave the enable bit set
+ FSDEV_REG->DADDR = (USB_DADDR_EF | dev_addr);
}
+
+ edpt0_prepare_setup();
}
/***
@@ -743,21 +489,19 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *req
* In case of double buffering, high 16bit is the address of 2nd buffer
* During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually.
*/
-static uint32_t dcd_pma_alloc(uint16_t length, bool dbuf)
+static uint32_t dcd_pma_alloc(uint16_t len, bool dbuf)
{
- // Ensure allocated buffer is aligned
-#ifdef FSDEV_BUS_32BIT
- length = (length + 3) & ~0x03;
-#else
- length = (length + 1) & ~0x01;
-#endif
+ uint8_t blsize, num_block;
+ uint16_t aligned_len = pma_align_buffer_size(len, &blsize, &num_block);
+ (void) blsize;
+ (void) num_block;
uint32_t addr = ep_buf_ptr;
- ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
+ ep_buf_ptr = (uint16_t)(ep_buf_ptr + aligned_len); // increment buffer pointer
if (dbuf) {
addr |= ((uint32_t)ep_buf_ptr) << 16;
- ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
+ ep_buf_ptr = (uint16_t)(ep_buf_ptr + aligned_len); // increment buffer pointer
}
// Verify packet buffer is not overflowed
@@ -774,7 +518,7 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
- for (uint8_t i = 0; i < STFSDEV_EP_COUNT; i++) {
+ for (uint8_t i = 0; i < FSDEV_EP_COUNT; i++) {
// Check if already allocated
if (ep_alloc_status[i].allocated[dir] &&
ep_alloc_status[i].ep_type == ep_type &&
@@ -804,34 +548,53 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
TU_ASSERT(0);
}
-// The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
-// so I'm using the #define from HAL here, instead.
+void edpt0_open(uint8_t rhport) {
+ (void) rhport;
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
-{
+ dcd_ep_alloc(0x0, TUSB_XFER_CONTROL);
+ dcd_ep_alloc(0x80, TUSB_XFER_CONTROL);
+
+ xfer_status[0][0].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
+ xfer_status[0][0].ep_idx = 0;
+
+ xfer_status[0][1].max_packet_size = CFG_TUD_ENDPOINT0_SIZE;
+ xfer_status[0][1].ep_idx = 0;
+
+ uint16_t pma_addr0 = dcd_pma_alloc(CFG_TUD_ENDPOINT0_SIZE, false);
+ uint16_t pma_addr1 = dcd_pma_alloc(CFG_TUD_ENDPOINT0_SIZE, false);
+
+ btable_set_addr(0, BTABLE_BUF_RX, pma_addr0);
+ btable_set_addr(0, BTABLE_BUF_TX, pma_addr1);
+
+ uint32_t ep_reg = ep_read(0) & ~USB_EPREG_MASK; // only get toggle bits
+ ep_reg |= USB_EP_CONTROL;
+ ep_change_status(&ep_reg, TUSB_DIR_IN, EP_STAT_NAK);
+ ep_change_status(&ep_reg, TUSB_DIR_OUT, EP_STAT_NAK);
+ // no need to explicitly set DTOG bits since we aren't masked DTOG bit
+
+ edpt0_prepare_setup(); // prepare for setup packet
+ ep_write(0, ep_reg, false);
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
(void)rhport;
- uint8_t const ep_addr = p_endpoint_desc->bEndpointAddress;
- uint8_t const ep_idx = dcd_ep_alloc(ep_addr, p_endpoint_desc->bmAttributes.xfer);
- uint8_t const dir = tu_edpt_dir(ep_addr);
- const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
- const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
- uint16_t pma_addr;
- uint32_t wType;
+ uint8_t const ep_addr = desc_ep->bEndpointAddress;
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+ const uint16_t packet_size = tu_edpt_packet_size(desc_ep);
+ uint8_t const ep_idx = dcd_ep_alloc(ep_addr, desc_ep->bmAttributes.xfer);
+ TU_ASSERT(ep_idx < FSDEV_EP_COUNT);
- TU_ASSERT(ep_idx < STFSDEV_EP_COUNT);
- TU_ASSERT(buffer_size <= 64);
+ uint32_t ep_reg = ep_read(ep_idx) & ~USB_EPREG_MASK;
+ ep_reg |= tu_edpt_number(ep_addr) | USB_EP_CTR_TX | USB_EP_CTR_RX;
// Set type
- switch (p_endpoint_desc->bmAttributes.xfer) {
- case TUSB_XFER_CONTROL:
- wType = USB_EP_CONTROL;
- break;
+ switch (desc_ep->bmAttributes.xfer) {
case TUSB_XFER_BULK:
- wType = USB_EP_CONTROL;
+ ep_reg |= USB_EP_BULK;
break;
-
case TUSB_XFER_INTERRUPT:
- wType = USB_EP_INTERRUPT;
+ ep_reg |= USB_EP_INTERRUPT;
break;
default:
@@ -839,35 +602,35 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
TU_ASSERT(false);
}
- pcd_set_eptype(USB, ep_idx, wType);
- pcd_set_ep_address(USB, ep_idx, tu_edpt_number(ep_addr));
-
/* Create a packet memory buffer area. */
- pma_addr = dcd_pma_alloc(buffer_size, false);
+ uint16_t pma_addr = dcd_pma_alloc(packet_size, false);
+ btable_set_addr(ep_idx, dir == TUSB_DIR_IN ? BTABLE_BUF_TX : BTABLE_BUF_RX, pma_addr);
+
+ xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
+ xfer->max_packet_size = packet_size;
+ xfer->ep_idx = ep_idx;
+
+ ep_change_status(&ep_reg, dir, EP_STAT_NAK);
+ ep_change_dtog(&ep_reg, dir, 0);
+ // reserve other direction toggle bits
if (dir == TUSB_DIR_IN) {
- pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
- pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
- pcd_clear_tx_dtog(USB, ep_idx);
+ ep_reg &= ~(USB_EPRX_STAT | USB_EP_DTOG_RX);
} else {
- pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
- pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
- pcd_clear_rx_dtog(USB, ep_idx);
+ ep_reg &= ~(USB_EPTX_STAT | USB_EP_DTOG_TX);
}
- xfer_ctl_ptr(ep_addr)->max_packet_size = packet_size;
- xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
+ ep_write(ep_idx, ep_reg, true);
return true;
}
-void dcd_edpt_close_all(uint8_t rhport)
-{
- (void)rhport;
+void dcd_edpt_close_all(uint8_t rhport) {
+ dcd_int_disable(rhport);
- for (uint32_t i = 1; i < STFSDEV_EP_COUNT; i++) {
+ for (uint32_t i = 1; i < FSDEV_EP_COUNT; i++) {
// Reset endpoint
- pcd_set_endpoint(USB, i, 0);
+ ep_write(i, 0, false);
// Clear EP allocation status
ep_alloc_status[i].ep_num = 0xFF;
ep_alloc_status[i].ep_type = 0xFF;
@@ -875,508 +638,340 @@ void dcd_edpt_close_all(uint8_t rhport)
ep_alloc_status[i].allocated[1] = false;
}
+ dcd_int_enable(rhport);
+
// Reset PMA allocation
- ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8 * MAX_EP_COUNT + 2 * CFG_TUD_ENDPOINT0_SIZE;
+ ep_buf_ptr = FSDEV_BTABLE_BASE + 8 * CFG_TUD_ENDPPOINT_MAX + 2 * CFG_TUD_ENDPOINT0_SIZE;
}
-/**
- * Close an endpoint.
- *
- * This function may be called with interrupts enabled or disabled.
- *
- * This also clears transfers in progress, should there be any.
- */
-void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
(void)rhport;
- xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
- uint8_t const ep_idx = xfer->ep_idx;
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
-
- if (dir == TUSB_DIR_IN) {
- pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
- } else {
- pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
- }
-}
-
-bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
-{
- (void)rhport;
-
uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
- const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size);
/* Create a packet memory buffer area. Enable double buffering for devices with 2048 bytes PMA,
for smaller devices double buffering occupy too much space. */
#if FSDEV_PMA_SIZE > 1024u
- uint32_t pma_addr = dcd_pma_alloc(buffer_size, true);
+ uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, true);
uint16_t pma_addr2 = pma_addr >> 16;
#else
- uint32_t pma_addr = dcd_pma_alloc(buffer_size, true);
+ uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, false);
uint16_t pma_addr2 = pma_addr;
#endif
- pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
- pcd_set_ep_rx_address(USB, ep_idx, pma_addr2);
- pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
+ btable_set_addr(ep_idx, 0, pma_addr);
+ btable_set_addr(ep_idx, 1, pma_addr2);
- xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
+ xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, dir);
+ xfer->ep_idx = ep_idx;
return true;
}
-bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
-{
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
(void)rhport;
- uint8_t const ep_addr = p_endpoint_desc->bEndpointAddress;
- uint8_t const ep_idx = xfer_ctl_ptr(ep_addr)->ep_idx;
- uint8_t const dir = tu_edpt_dir(ep_addr);
- const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
+ uint8_t const ep_addr = desc_ep->bEndpointAddress;
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+ xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, dir);
- pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
- pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
-
- pcd_set_ep_address(USB, ep_idx, tu_edpt_number(ep_addr));
+ uint8_t const ep_idx = xfer->ep_idx;
- pcd_clear_tx_dtog(USB, ep_idx);
- pcd_clear_rx_dtog(USB, ep_idx);
+ xfer->max_packet_size = tu_edpt_packet_size(desc_ep);
- if (dir == TUSB_DIR_IN) {
- pcd_rx_dtog(USB, ep_idx);
- } else {
- pcd_tx_dtog(USB, ep_idx);
- }
+ uint32_t ep_reg = ep_read(ep_idx) & ~USB_EPREG_MASK;
+ ep_reg |= tu_edpt_number(ep_addr) | USB_EP_ISOCHRONOUS | USB_EP_CTR_TX | USB_EP_CTR_RX;
+ ep_change_status(&ep_reg, TUSB_DIR_IN, EP_STAT_DISABLED);
+ ep_change_status(&ep_reg, TUSB_DIR_OUT, EP_STAT_DISABLED);
+ ep_change_dtog(&ep_reg, dir, 0);
+ ep_change_dtog(&ep_reg, (tusb_dir_t)(1 - dir), 1);
- xfer_ctl_ptr(ep_addr)->max_packet_size = packet_size;
+ ep_write(ep_idx, ep_reg, true);
return true;
}
// Currently, single-buffered, and only 64 bytes at a time (max)
+static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) {
+ uint16_t len = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
+ uint32_t ep_reg = ep_read(ep_ix) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR
-static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix)
-{
- uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
- if (len > xfer->max_packet_size) {
- len = xfer->max_packet_size;
- }
-
- uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix);
- bool const is_iso = (ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS;
- uint16_t addr_ptr;
+ bool const is_iso = ep_is_iso(ep_reg);
+ uint8_t buf_id;
if (is_iso) {
- if (ep_reg & USB_EP_DTOG_TX) {
- addr_ptr = pcd_get_ep_dbuf1_address(USB, ep_ix);
- pcd_set_ep_tx_dbuf1_cnt(USB, ep_ix, len);
- } else {
- addr_ptr = pcd_get_ep_dbuf0_address(USB, ep_ix);
- pcd_set_ep_tx_dbuf0_cnt(USB, ep_ix, len);
- }
+ buf_id = (ep_reg & USB_EP_DTOG_TX) ? 1 : 0;
} else {
- addr_ptr = pcd_get_ep_tx_address(USB, ep_ix);
- pcd_set_ep_tx_cnt(USB, ep_ix, len);
+ buf_id = BTABLE_BUF_TX;
}
+ uint16_t addr_ptr = (uint16_t) btable_get_addr(ep_ix, buf_id);
if (xfer->ff) {
dcd_write_packet_memory_ff(xfer->ff, addr_ptr, len);
} else {
dcd_write_packet_memory(addr_ptr, &(xfer->buffer[xfer->queued_len]), len);
}
- xfer->queued_len = (uint16_t)(xfer->queued_len + len);
+ xfer->queued_len += len;
+
+ btable_set_count(ep_ix, buf_id, len);
+ ep_change_status(&ep_reg, TUSB_DIR_IN, EP_STAT_VALID);
- dcd_int_disable(0);
- pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
if (is_iso) {
xfer->iso_in_sending = true;
}
- dcd_int_enable(0);
+ ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(TUSB_DIR_IN); // only change TX Status, reserve other toggle bits
+ ep_write(ep_ix, ep_reg, true);
}
-static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
-{
- (void)rhport;
+static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, tusb_dir_t dir) {
+ (void) rhport;
- xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
+ xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
uint8_t const ep_idx = xfer->ep_idx;
- uint8_t const dir = tu_edpt_dir(ep_addr);
if (dir == TUSB_DIR_IN) {
dcd_transmit_packet(xfer, ep_idx);
} else {
- // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
- // buffer for the control endpoint.
- if (ep_idx == 0 && xfer->buffer == NULL) {
- xfer->buffer = (uint8_t *)_setup_packet;
- }
+ uint32_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR
+ ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir);
- uint32_t cnt = (uint32_t ) tu_min16(xfer->total_len, xfer->max_packet_size);
- uint16_t ep_reg = pcd_get_endpoint(USB, ep_idx);
+ uint16_t cnt = tu_min16(xfer->total_len, xfer->max_packet_size);
- if ((ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
- pcd_set_ep_rx_dbuf0_cnt(USB, ep_idx, cnt);
- pcd_set_ep_rx_dbuf1_cnt(USB, ep_idx, cnt);
+ if (ep_is_iso(ep_reg)) {
+ btable_set_rx_bufsize(ep_idx, 0, cnt);
+ btable_set_rx_bufsize(ep_idx, 1, cnt);
} else {
- pcd_set_ep_rx_cnt(USB, ep_idx, cnt);
+ btable_set_rx_bufsize(ep_idx, BTABLE_BUF_RX, cnt);
}
- pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_VALID);
+ ep_change_status(&ep_reg, dir, EP_STAT_VALID);
+ ep_write(ep_idx, ep_reg, true);
}
return true;
}
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
-{
- xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) {
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+ xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
xfer->buffer = buffer;
xfer->ff = NULL;
xfer->total_len = total_bytes;
xfer->queued_len = 0;
- return edpt_xfer(rhport, ep_addr);
+ return edpt_xfer(rhport, ep_num, dir);
}
-bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes)
-{
- xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) {
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+ xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
+
xfer->buffer = NULL;
xfer->ff = ff;
xfer->total_len = total_bytes;
xfer->queued_len = 0;
- return edpt_xfer(rhport, ep_addr);
+ return edpt_xfer(rhport, ep_num, dir);
}
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
(void)rhport;
-
- xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+ xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
uint8_t const ep_idx = xfer->ep_idx;
- uint8_t const dir = tu_edpt_dir(ep_addr);
- if (dir == TUSB_DIR_IN) {
- pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_STALL);
- } else {
- pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_STALL);
- }
+ uint32_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR bits
+ ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir);
+ ep_change_status(&ep_reg, dir, EP_STAT_STALL);
+
+ ep_write(ep_idx, ep_reg, true);
}
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
(void)rhport;
- xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+ xfer_ctl_t *xfer = xfer_ctl_ptr(ep_num, dir);
uint8_t const ep_idx = xfer->ep_idx;
- uint8_t const dir = tu_edpt_dir(ep_addr);
- if (dir == TUSB_DIR_IN) { // IN
- if (pcd_get_eptype(USB, ep_idx) != USB_EP_ISOCHRONOUS) {
- pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
- }
+ uint32_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX | USB_EP_CTR_RX; // reserve CTR bits
+ ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir) | EP_DTOG_MASK(dir);
- /* Reset to DATA0 if clearing stall condition. */
- pcd_clear_tx_dtog(USB, ep_idx);
- } else { // OUT
- if (pcd_get_eptype(USB, ep_idx) != USB_EP_ISOCHRONOUS) {
- pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
- }
- /* Reset to DATA0 if clearing stall condition. */
- pcd_clear_rx_dtog(USB, ep_idx);
+ if (!ep_is_iso(ep_reg)) {
+ ep_change_status(&ep_reg, dir, EP_STAT_NAK);
}
+ ep_change_dtog(&ep_reg, dir, 0); // Reset to DATA0
+ ep_write(ep_idx, ep_reg, true);
}
-#ifdef FSDEV_BUS_32BIT
-static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes)
-{
- const uint8_t *srcVal = src;
- volatile uint32_t *dst32 = (volatile uint32_t *)(USB_PMAADDR + dst);
+//--------------------------------------------------------------------+
+// PMA read/write
+//--------------------------------------------------------------------+
- for (uint32_t n = wNBytes / 4; n > 0; --n) {
- *dst32++ = tu_unaligned_read32(srcVal);
- srcVal += 4;
- }
+// Write to packet memory area (PMA) from user memory
+// - Packet memory must be either strictly 16-bit or 32-bit depending on FSDEV_BUS_32BIT
+// - Uses unaligned for RAM (since M0 cannot access unaligned address)
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t nbytes) {
+ if (nbytes == 0) return true;
+ uint32_t n_write = nbytes / FSDEV_BUS_SIZE;
- wNBytes = wNBytes & 0x03;
- if (wNBytes) {
- uint32_t wrVal = *srcVal;
- wNBytes--;
+ fsdev_pma_buf_t* pma_buf = PMA_BUF_AT(dst);
+ const uint8_t *src8 = src;
- if (wNBytes) {
- wrVal |= *++srcVal << 8;
- wNBytes--;
+ while (n_write--) {
+ pma_buf->value = fsdevbus_unaligned_read(src8);
+ src8 += FSDEV_BUS_SIZE;
+ pma_buf++;
+ }
- if (wNBytes) {
- wrVal |= *++srcVal << 16;
- }
+ // odd bytes e.g 1 for 16-bit or 1-3 for 32-bit
+ uint16_t odd = nbytes & (FSDEV_BUS_SIZE - 1);
+ if (odd) {
+ fsdev_bus_t temp = 0;
+ for(uint16_t i = 0; i < odd; i++) {
+ temp |= *src8++ << (i * 8);
}
-
- *dst32 = wrVal;
+ pma_buf->value = temp;
}
return true;
}
-#else
-// Packet buffer access can only be 8- or 16-bit.
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA).
- * This uses byte-access for user memory (so support non-aligned buffers)
- * and 16-bit access for packet memory.
- * @param dst, byte address in PMA; must be 16-bit aligned
- * @param src pointer to user memory area.
- * @param wPMABufAddr address into PMA.
- * @param wNBytes no. of bytes to be copied.
- * @retval None
- */
-static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes)
-{
- uint32_t n = (uint32_t)wNBytes >> 1U;
- uint16_t temp1, temp2;
- const uint8_t *srcVal;
-
- // The GCC optimizer will combine access to 32-bit sizes if we let it. Force
- // it volatile so that it won't do that.
- __IO uint16_t *pdwVal;
-
- srcVal = src;
- pdwVal = &pma[FSDEV_PMA_STRIDE * (dst >> 1)];
-
- while (n--) {
- temp1 = (uint16_t)*srcVal;
- srcVal++;
- temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U));
- *pdwVal = temp2;
- pdwVal += FSDEV_PMA_STRIDE;
- srcVal++;
+
+// Read from packet memory area (PMA) to user memory.
+// - Packet memory must be either strictly 16-bit or 32-bit depending on FSDEV_BUS_32BIT
+// - Uses unaligned for RAM (since M0 cannot access unaligned address)
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t nbytes) {
+ if (nbytes == 0) return true;
+ uint32_t n_read = nbytes / FSDEV_BUS_SIZE;
+
+ fsdev_pma_buf_t* pma_buf = PMA_BUF_AT(src);
+ uint8_t *dst8 = (uint8_t *)dst;
+
+ while (n_read--) {
+ fsdevbus_unaligned_write(dst8, (fsdev_bus_t ) pma_buf->value);
+ dst8 += FSDEV_BUS_SIZE;
+ pma_buf++;
}
- if (wNBytes) {
- temp1 = *srcVal;
- *pdwVal = temp1;
+ // odd bytes e.g 1 for 16-bit or 1-3 for 32-bit
+ uint16_t odd = nbytes & (FSDEV_BUS_SIZE - 1);
+ if (odd) {
+ fsdev_bus_t temp = pma_buf->value;
+ while (odd--) {
+ *dst8++ = (uint8_t) (temp & 0xfful);
+ temp >>= 8;
+ }
}
return true;
}
-#endif
-/**
- * @brief Copy from FIFO to packet memory area (PMA).
- * Uses byte-access of system memory and 16-bit access of packet memory
- * @param wNBytes no. of bytes to be copied.
- * @retval None
- */
-static bool dcd_write_packet_memory_ff(tu_fifo_t *ff, uint16_t dst, uint16_t wNBytes)
-{
+// Write to PMA from FIFO
+static bool dcd_write_packet_memory_ff(tu_fifo_t *ff, uint16_t dst, uint16_t wNBytes) {
+ if (wNBytes == 0) return true;
+
// Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
tu_fifo_buffer_info_t info;
tu_fifo_get_read_info(ff, &info);
- uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin);
- uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
+ uint16_t cnt_lin = tu_min16(wNBytes, info.len_lin);
+ uint16_t cnt_wrap = tu_min16(wNBytes - cnt_lin, info.len_wrap);
+ uint16_t const cnt_total = cnt_lin + cnt_wrap;
// We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
- // last lin byte will be combined with wrapped part
- // To ensure PMA is always access aligned (dst aligned to 16 or 32 bit)
-#ifdef FSDEV_BUS_32BIT
- if ((cnt_lin & 0x03) && cnt_wrap) {
- // Copy first linear part
- dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin & ~0x03);
- dst += cnt_lin & ~0x03;
-
- // Copy last linear bytes & first wrapped bytes to buffer
- uint32_t i;
- uint8_t tmp[4];
- for (i = 0; i < (cnt_lin & 0x03); i++) {
- tmp[i] = ((uint8_t *)info.ptr_lin)[(cnt_lin & ~0x03) + i];
- }
- uint32_t wCnt = cnt_wrap;
- for (; i < 4 && wCnt > 0; i++, wCnt--) {
- tmp[i] = *(uint8_t *)info.ptr_wrap;
- info.ptr_wrap = (uint8_t *)info.ptr_wrap + 1;
+ // last lin byte will be combined with wrapped part To ensure PMA is always access aligned
+ uint16_t lin_even = cnt_lin & ~(FSDEV_BUS_SIZE - 1);
+ uint16_t lin_odd = cnt_lin & (FSDEV_BUS_SIZE - 1);
+ uint8_t const *src8 = (uint8_t const*) info.ptr_lin;
+
+ // write even linear part
+ dcd_write_packet_memory(dst, src8, lin_even);
+ dst += lin_even;
+ src8 += lin_even;
+
+ if (lin_odd == 0) {
+ src8 = (uint8_t const*) info.ptr_wrap;
+ } else {
+ // Combine last linear bytes + first wrapped bytes to form fsdev bus width data
+ fsdev_bus_t temp = 0;
+ uint16_t i;
+ for(i = 0; i < lin_odd; i++) {
+ temp |= *src8++ << (i * 8);
}
- // Write unaligned buffer
- dcd_write_packet_memory(dst, &tmp, 4);
- dst += 4;
-
- // Copy rest of wrapped byte
- if (wCnt)
- dcd_write_packet_memory(dst, info.ptr_wrap, wCnt);
- }
-#else
- if ((cnt_lin & 0x01) && cnt_wrap) {
- // Copy first linear part
- dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin & ~0x01);
- dst += cnt_lin & ~0x01;
-
- // Copy last linear byte & first wrapped byte
- uint16_t tmp = ((uint8_t *)info.ptr_lin)[cnt_lin - 1] | ((uint16_t)(((uint8_t *)info.ptr_wrap)[0]) << 8U);
- dcd_write_packet_memory(dst, &tmp, 2);
- dst += 2;
-
- // Copy rest of wrapped byte
- dcd_write_packet_memory(dst, ((uint8_t *)info.ptr_wrap) + 1, cnt_wrap - 1);
- }
-#endif
- else {
- // Copy linear part
- dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin);
- dst += info.len_lin;
-
- if (info.len_wrap) {
- // Copy wrapped byte
- dcd_write_packet_memory(dst, info.ptr_wrap, cnt_wrap);
+ src8 = (uint8_t const*) info.ptr_wrap;
+ for(; i < FSDEV_BUS_SIZE && cnt_wrap > 0; i++, cnt_wrap--) {
+ temp |= *src8++ << (i * 8);
}
- }
- tu_fifo_advance_read_pointer(ff, cnt_lin + cnt_wrap);
-
- return true;
-}
-
-#ifdef FSDEV_BUS_32BIT
-static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes)
-{
- uint8_t *dstVal = dst;
- volatile uint32_t *src32 = (volatile uint32_t *)(USB_PMAADDR + src);
-
- for (uint32_t n = wNBytes / 4; n > 0; --n) {
- tu_unaligned_write32(dstVal, *src32++);
- dstVal += 4;
+ dcd_write_packet_memory(dst, &temp, FSDEV_BUS_SIZE);
+ dst += FSDEV_BUS_SIZE;
}
- wNBytes = wNBytes & 0x03;
- if (wNBytes) {
- uint32_t rdVal = *src32;
-
- *dstVal = tu_u32_byte0(rdVal);
- wNBytes--;
-
- if (wNBytes) {
- *++dstVal = tu_u32_byte1(rdVal);
- wNBytes--;
-
- if (wNBytes) {
- *++dstVal = tu_u32_byte2(rdVal);
- }
- }
- }
+ // write the rest of the wrapped part
+ dcd_write_packet_memory(dst, src8, cnt_wrap);
+ tu_fifo_advance_read_pointer(ff, cnt_total);
return true;
}
-#else
-/**
- * @brief Copy a buffer from packet memory area (PMA) to user memory area.
- * Uses byte-access of system memory and 16-bit access of packet memory
- * @param wNBytes no. of bytes to be copied.
- * @retval None
- */
-static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes)
-{
- uint32_t n = (uint32_t)wNBytes >> 1U;
- // The GCC optimizer will combine access to 32-bit sizes if we let it. Force
- // it volatile so that it won't do that.
- __IO const uint16_t *pdwVal;
- uint32_t temp;
-
- pdwVal = &pma[FSDEV_PMA_STRIDE * (src >> 1)];
- uint8_t *dstVal = (uint8_t *)dst;
-
- while (n--) {
- temp = *pdwVal;
- pdwVal += FSDEV_PMA_STRIDE;
- *dstVal++ = ((temp >> 0) & 0xFF);
- *dstVal++ = ((temp >> 8) & 0xFF);
- }
- if (wNBytes & 0x01) {
- temp = *pdwVal;
- pdwVal += FSDEV_PMA_STRIDE;
- *dstVal++ = ((temp >> 0) & 0xFF);
- }
- return true;
-}
-#endif
+// Read from PMA to FIFO
+static bool dcd_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes) {
+ if (wNBytes == 0) return true;
-/**
- * @brief Copy a buffer from user packet memory area (PMA) to FIFO.
- * Uses byte-access of system memory and 16-bit access of packet memory
- * @param wNBytes no. of bytes to be copied.
- * @retval None
- */
-static bool dcd_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes)
-{
// Since we copy into a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
// Check for first linear part
tu_fifo_buffer_info_t info;
tu_fifo_get_write_info(ff, &info); // We want to read from the FIFO
- uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin);
- uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
-
- // We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part,
- // last lin byte will be combined with wrapped part
- // To ensure PMA is always access aligned (src aligned to 16 or 32 bit)
-#ifdef FSDEV_BUS_32BIT
- if ((cnt_lin & 0x03) && cnt_wrap) {
- // Copy first linear part
- dcd_read_packet_memory(info.ptr_lin, src, cnt_lin & ~0x03);
- src += cnt_lin & ~0x03;
-
- // Copy last linear bytes & first wrapped bytes
- uint8_t tmp[4];
- dcd_read_packet_memory(tmp, src, 4);
- src += 4;
-
- uint32_t i;
- for (i = 0; i < (cnt_lin & 0x03); i++) {
- ((uint8_t *)info.ptr_lin)[(cnt_lin & ~0x03) + i] = tmp[i];
- }
- uint32_t wCnt = cnt_wrap;
- for (; i < 4 && wCnt > 0; i++, wCnt--) {
- *(uint8_t *)info.ptr_wrap = tmp[i];
- info.ptr_wrap = (uint8_t *)info.ptr_wrap + 1;
- }
+ uint16_t cnt_lin = tu_min16(wNBytes, info.len_lin);
+ uint16_t cnt_wrap = tu_min16(wNBytes - cnt_lin, info.len_wrap);
+ uint16_t cnt_total = cnt_lin + cnt_wrap;
- // Copy rest of wrapped byte
- if (wCnt)
- dcd_read_packet_memory(info.ptr_wrap, src, wCnt);
- }
-#else
- if ((cnt_lin & 0x01) && cnt_wrap) {
- // Copy first linear part
- dcd_read_packet_memory(info.ptr_lin, src, cnt_lin & ~0x01);
- src += cnt_lin & ~0x01;
+ // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
+ // last lin byte will be combined with wrapped part To ensure PMA is always access aligned
- // Copy last linear byte & first wrapped byte
- uint8_t tmp[2];
- dcd_read_packet_memory(tmp, src, 2);
- src += 2;
+ uint16_t lin_even = cnt_lin & ~(FSDEV_BUS_SIZE - 1);
+ uint16_t lin_odd = cnt_lin & (FSDEV_BUS_SIZE - 1);
+ uint8_t *dst8 = (uint8_t *) info.ptr_lin;
- ((uint8_t *)info.ptr_lin)[cnt_lin - 1] = tmp[0];
- ((uint8_t *)info.ptr_wrap)[0] = tmp[1];
+ // read even linear part
+ dcd_read_packet_memory(dst8, src, lin_even);
+ dst8 += lin_even;
+ src += lin_even;
- // Copy rest of wrapped byte
- dcd_read_packet_memory(((uint8_t *)info.ptr_wrap) + 1, src, cnt_wrap - 1);
- }
-#endif
- else {
- // Copy linear part
- dcd_read_packet_memory(info.ptr_lin, src, cnt_lin);
- src += cnt_lin;
-
- if (info.len_wrap) {
- // Copy wrapped byte
- dcd_read_packet_memory(info.ptr_wrap, src, cnt_wrap);
+ if (lin_odd == 0) {
+ dst8 = (uint8_t *) info.ptr_wrap;
+ } else {
+ // Combine last linear bytes + first wrapped bytes to form fsdev bus width data
+ fsdev_bus_t temp;
+ dcd_read_packet_memory(&temp, src, FSDEV_BUS_SIZE);
+ src += FSDEV_BUS_SIZE;
+
+ uint16_t i;
+ for (i = 0; i < lin_odd; i++) {
+ *dst8++ = (uint8_t) (temp & 0xfful);
+ temp >>= 8;
+ }
+
+ dst8 = (uint8_t *) info.ptr_wrap;
+ for (; i < FSDEV_BUS_SIZE && cnt_wrap > 0; i++, cnt_wrap--) {
+ *dst8++ = (uint8_t) (temp & 0xfful);
+ temp >>= 8;
}
}
- tu_fifo_advance_write_pointer(ff, cnt_lin + cnt_wrap);
+ // read the rest of the wrapped part
+ dcd_read_packet_memory(dst8, src, cnt_wrap);
+ tu_fifo_advance_write_pointer(ff, cnt_total);
return true;
}
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
deleted file mode 100644
index 7992f34a13..0000000000
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
+++ /dev/null
@@ -1,551 +0,0 @@
-/*
- * Copyright(c) 2016 STMicroelectronics
- * Copyright(c) N Conrad
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-// This file contains source copied from ST's HAL, and thus should have their copyright statement.
-
-// FSDEV_PMA_SIZE is PMA buffer size in bytes.
-// On 512-byte devices, access with a stride of two words (use every other 16-bit address)
-// On 1024-byte devices, access with a stride of one word (use every 16-bit address)
-
-#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
-#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
-
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0
- #include "stm32f0xx.h"
- #define FSDEV_PMA_SIZE (1024u)
- // F0x2 models are crystal-less
- // All have internal D+ pull-up
- // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support
- // PMA dedicated to USB (no sharing with CAN)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
- #include "stm32f1xx.h"
- #define FSDEV_PMA_SIZE (512u)
- // NO internal Pull-ups
- // *B, and *C: 2 x 16 bits/word
-
- // F1 names this differently from the rest
- #define USB_CNTR_LPMODE USB_CNTR_LP_MODE
-
-#elif defined(STM32F302xB) || defined(STM32F302xC) || \
- defined(STM32F303xB) || defined(STM32F303xC) || \
- defined(STM32F373xC)
- #include "stm32f3xx.h"
- #define FSDEV_PMA_SIZE (512u)
- // NO internal Pull-ups
- // *B, and *C: 1 x 16 bits/word
- // PMA dedicated to USB (no sharing with CAN)
-
-#elif defined(STM32F302x6) || defined(STM32F302x8) || \
- defined(STM32F302xD) || defined(STM32F302xE) || \
- defined(STM32F303xD) || defined(STM32F303xE)
- #include "stm32f3xx.h"
- #define FSDEV_PMA_SIZE (1024u)
- // NO internal Pull-ups
- // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support
- // When CAN clock is enabled, USB can use first 768 bytes ONLY.
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
- #include "stm32l0xx.h"
- #define FSDEV_PMA_SIZE (1024u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
- #include "stm32l1xx.h"
- #define FSDEV_PMA_SIZE (512u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
- #include "stm32g4xx.h"
- #define FSDEV_PMA_SIZE (1024u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
- #include "stm32g0xx.h"
- #define FSDEV_BUS_32BIT
- #define FSDEV_PMA_SIZE (2048u)
- #undef USB_PMAADDR
- #define USB_PMAADDR USB_DRD_PMAADDR
- #define USB_TypeDef USB_DRD_TypeDef
- #define EP0R CHEP0R
- #define USB_EP_CTR_RX USB_EP_VTRX
- #define USB_EP_CTR_TX USB_EP_VTTX
- #define USB_EP_T_FIELD USB_CHEP_UTYPE
- #define USB_EPREG_MASK USB_CHEP_REG_MASK
- #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
- #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
- #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
- #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
- #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
- #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
- #define USB_EPRX_STAT USB_CH_RX_VALID
- #define USB_EPKIND_MASK USB_EP_KIND_MASK
- #define USB USB_DRD_FS
- #define USB_CNTR_FRES USB_CNTR_USBRST
- #define USB_CNTR_RESUME USB_CNTR_L2RES
- #define USB_ISTR_EP_ID USB_ISTR_IDN
- #define USB_EPADDR_FIELD USB_CHEP_ADDR
- #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
- #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
- #include "stm32h5xx.h"
- #define FSDEV_BUS_32BIT
-
- #if !defined(USB_DRD_BASE) && defined(USB_DRD_FS_BASE)
- #define USB_DRD_BASE USB_DRD_FS_BASE
- #endif
-
- #define FSDEV_PMA_SIZE (2048u)
- #undef USB_PMAADDR
- #define USB_PMAADDR USB_DRD_PMAADDR
- #define USB_TypeDef USB_DRD_TypeDef
- #define EP0R CHEP0R
- #define USB_EP_CTR_RX USB_EP_VTRX
- #define USB_EP_CTR_TX USB_EP_VTTX
- #define USB_EP_T_FIELD USB_CHEP_UTYPE
- #define USB_EPREG_MASK USB_CHEP_REG_MASK
- #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
- #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
- #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
- #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
- #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
- #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
- #define USB_EPRX_STAT USB_CH_RX_VALID
- #define USB_EPKIND_MASK USB_EP_KIND_MASK
- #define USB USB_DRD_FS
- #define USB_CNTR_FRES USB_CNTR_USBRST
- #define USB_CNTR_RESUME USB_CNTR_L2RES
- #define USB_ISTR_EP_ID USB_ISTR_IDN
- #define USB_EPADDR_FIELD USB_CHEP_ADDR
- #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
- #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
- #include "stm32wbxx.h"
- #define FSDEV_PMA_SIZE (1024u)
- /* ST provided header has incorrect value */
- #undef USB_PMAADDR
- #define USB_PMAADDR USB1_PMAADDR
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
- #include "stm32l4xx.h"
- #define FSDEV_PMA_SIZE (1024u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
- #include "stm32l5xx.h"
- #define FSDEV_PMA_SIZE (1024u)
-
- #ifndef USB_PMAADDR
- #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
- #endif
-
-#else
- #error You are using an untested or unimplemented STM32 variant. Please update the driver.
- // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
-#endif
-
-// For purposes of accessing the packet
-#if ((FSDEV_PMA_SIZE) == 512u)
- #define FSDEV_PMA_STRIDE (2u)
-#elif ((FSDEV_PMA_SIZE) == 1024u)
- #define FSDEV_PMA_STRIDE (1u)
-#endif
-
-// The fsdev_bus_t type can be used for both register and PMA access necessities
-// For type-safety create a new macro for the volatile address of PMAADDR
-// The compiler should warn us if we cast it to a non-volatile type?
-#ifdef FSDEV_BUS_32BIT
-typedef uint32_t fsdev_bus_t;
-static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR;
-
-#else
-typedef uint16_t fsdev_bus_t;
-// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
-static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
-
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) {
- size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
- total_word_offset *= FSDEV_PMA_STRIDE;
- return &(pma[total_word_offset]);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) {
- return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) {
- return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u);
-}
-#endif
-
-/* Aligned buffer size according to hardware */
-TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) {
- /* The STM32 full speed USB peripheral supports only a limited set of
- * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
- uint16_t blocksize = (size > 62) ? 32 : 2;
-
- // Round up while dividing requested size by blocksize
- uint16_t numblocks = (size + blocksize - 1) / blocksize ;
-
- return numblocks * blocksize;
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4);
- *reg = wRegValue;
-#else
- __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
- *reg = (uint16_t)wRegValue;
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4);
-#else
- __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
-#endif
- return *reg;
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= (uint32_t)USB_EP_T_MASK;
- regVal |= wType;
- regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high
- pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EP_T_FIELD;
- return regVal;
-}
-
-/**
- * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpIdx Endpoint Number.
- * @retval None
- */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EPREG_MASK;
- regVal &= ~USB_EP_CTR_RX;
- regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0)
- pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EPREG_MASK;
- regVal &= ~USB_EP_CTR_TX;
- regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0)
- pcd_set_endpoint(USBx, bEpIdx,regVal);
-}
-
-/**
- * @brief gets counter of the tx buffer.
- * @param USBx USB peripheral instance register address.
- * @param bEpIdx Endpoint Number.
- * @retval Counter value
- */
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- return (pma32[2*bEpIdx] & 0x03FF0000) >> 16;
-#else
- __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
- return *regPtr & 0x3ffU;
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
-#else
- __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
- return *regPtr & 0x3ffU;
-#endif
-}
-
-#define pcd_get_ep_dbuf0_cnt pcd_get_ep_tx_cnt
-#define pcd_get_ep_dbuf1_cnt pcd_get_ep_rx_cnt
-
-/**
- * @brief Sets address in an endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpIdx Endpoint Number.
- * @param bAddr Address.
- * @retval None
- */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t bAddr) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EPREG_MASK;
- regVal |= bAddr;
- regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
- pcd_set_endpoint(USBx, bEpIdx,regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- return pma32[2*bEpIdx] & 0x0000FFFFu ;
-#else
- return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u);
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- return pma32[2*bEpIdx + 1] & 0x0000FFFFu;
-#else
- return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u);
-#endif
-}
-
-#define pcd_get_ep_dbuf0_address pcd_get_ep_tx_address
-#define pcd_get_ep_dbuf1_address pcd_get_ep_rx_address
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
-#else
- *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr;
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
-#else
- *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr;
-#endif
-}
-
-#define pcd_set_ep_dbuf0_address pcd_set_ep_tx_address
-#define pcd_set_ep_dbuf1_address pcd_set_ep_rx_address
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
-#else
- __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
- *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
-#endif
-}
-
-#define pcd_set_ep_tx_dbuf0_cnt pcd_set_ep_tx_cnt
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_dbuf1_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
-#else
- __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
- *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx,
- uint32_t blocksize, uint32_t numblocks) {
- /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
-#ifdef FSDEV_BUS_32BIT
- (void) USBx;
- pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26);
-#else
- __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u);
- *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10);
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) {
- wCount = pcd_aligned_buffer_size(wCount);
-
- /* We assume that the buffer size is already aligned to hardware requirements. */
- uint16_t blocksize = (wCount > 62) ? 1 : 0;
- uint16_t numblocks = wCount / (blocksize ? 32 : 2);
-
- /* There should be no remainder in the above calculation */
- TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
-
- /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
- pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_dbuf0_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
- pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
- pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount);
-}
-
-#define pcd_set_ep_rx_dbuf1_cnt pcd_set_ep_rx_cnt
-
-/**
- * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
- * @param USBx USB peripheral instance register address.
- * @param bEpIdx Endpoint Number.
- * @param wState new state
- * @retval None
- */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EPTX_DTOGMASK;
-
- /* toggle first bit ? */
- if((USB_EPTX_DTOG1 & (wState))!= 0U)
- {
- regVal ^= USB_EPTX_DTOG1;
- }
- /* toggle second bit ? */
- if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)
- {
- regVal ^= USB_EPTX_DTOG2;
- }
-
- regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
- pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-/**
- * @brief sets the status for rx transfer (bits STAT_TX[1:0])
- * @param USBx USB peripheral instance register address.
- * @param bEpIdx Endpoint Number.
- * @param wState new state
- * @retval None
- */
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wState) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EPRX_DTOGMASK;
-
- /* toggle first bit ? */
- if((USB_EPRX_DTOG1 & wState)!= 0U) {
- regVal ^= USB_EPRX_DTOG1;
- }
- /* toggle second bit ? */
- if((USB_EPRX_DTOG2 & wState)!= 0U) {
- regVal ^= USB_EPRX_DTOG2;
- }
-
- regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
- pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- return (regVal & USB_EPRX_STAT) >> (12u);
-}
-
-
-/**
- * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpIdx Endpoint Number.
- * @retval None
- */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EPREG_MASK;
- regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
- pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EPREG_MASK;
- regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
- pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-/**
- * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param USBx USB peripheral instance register address.
- * @param bEpIdx Endpoint Number.
- * @retval None
- */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- if((regVal & USB_EP_DTOG_RX) != 0) {
- pcd_rx_dtog(USBx,bEpIdx);
- }
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- if((regVal & USB_EP_DTOG_TX) != 0) {
- pcd_tx_dtog(USBx,bEpIdx);
- }
-}
-
-/**
- * @brief set & clear EP_KIND bit.
- * @param USBx USB peripheral instance register address.
- * @param bEpIdx Endpoint Number.
- * @retval None
- */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal |= USB_EP_KIND;
- regVal &= USB_EPREG_MASK;
- regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
- pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) {
- uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
- regVal &= USB_EPKIND_MASK;
- regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
- pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-// This checks if the device has "LPM"
-#if defined(USB_ISTR_L1REQ)
-#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)
-#else
-#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U)
-#endif
-
-#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
- USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
-
-// Number of endpoints in hardware
-// TODO should use TUP_DCD_ENDPOINT_MAX
-#define STFSDEV_EP_COUNT (8u)
-
-#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */
diff --git a/src/portable/st/stm32_fsdev/fsdev_ch32.h b/src/portable/st/stm32_fsdev/fsdev_ch32.h
new file mode 100644
index 0000000000..518197c477
--- /dev/null
+++ b/src/portable/st/stm32_fsdev/fsdev_ch32.h
@@ -0,0 +1,206 @@
+/*
+* The MIT License (MIT)
+ *
+ * Copyright (c) 2024, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+/** © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ */
+
+#ifndef TUSB_FSDEV_CH32_H
+#define TUSB_FSDEV_CH32_H
+
+#include "common/tusb_compiler.h"
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_CH32F20X
+ #include
+#elif CFG_TUSB_MCU == OPT_MCU_CH32V20X
+ #include
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#define FSDEV_PMA_SIZE (512u)
+#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL)
+#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL)
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
+
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
+
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
+
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
+
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04U) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08U) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0CU) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10U) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14U) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18U) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1CU) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_MCU == OPT_MCU_CH32V20X
+static const IRQn_Type fsdev_irq[] = {
+ USB_HP_CAN1_TX_IRQn,
+ USB_LP_CAN1_RX0_IRQn,
+ USBWakeUp_IRQn
+};
+enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
+#else
+ #error "Unsupported MCU"
+#endif
+
+void dcd_int_enable(uint8_t rhport) {
+ (void)rhport;
+ for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
+ NVIC_EnableIRQ(fsdev_irq[i]);
+ }
+}
+
+void dcd_int_disable(uint8_t rhport) {
+ (void)rhport;
+ for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
+ NVIC_DisableIRQ(fsdev_irq[i]);
+ }
+}
+
+void dcd_disconnect(uint8_t rhport) {
+ (void) rhport;
+ EXTEN->EXTEN_CTR &= ~EXTEN_USBD_PU_EN;
+}
+
+void dcd_connect(uint8_t rhport) {
+ (void) rhport;
+ EXTEN->EXTEN_CTR |= EXTEN_USBD_PU_EN;
+}
+
+#endif
diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h
new file mode 100644
index 0000000000..03ea4c67e0
--- /dev/null
+++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h
@@ -0,0 +1,356 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright(c) N Conrad
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_FSDEV_STM32_H
+#define TUSB_FSDEV_STM32_H
+
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0
+ #include "stm32f0xx.h"
+ #define FSDEV_PMA_SIZE (1024u)
+ #define FSDEV_REG_BASE USB_BASE
+ // F0x2 models are crystal-less
+ // All have internal D+ pull-up
+ // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support
+ // PMA dedicated to USB (no sharing with CAN)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
+ #include "stm32f1xx.h"
+ #define FSDEV_PMA_SIZE (512u)
+ // NO internal Pull-ups
+ // *B, and *C: 2 x 16 bits/word
+
+ // F1 names this differently from the rest
+ #define USB_CNTR_LPMODE USB_CNTR_LP_MODE
+
+#elif defined(STM32F302xB) || defined(STM32F302xC) || \
+ defined(STM32F303xB) || defined(STM32F303xC) || \
+ defined(STM32F373xC)
+ #include "stm32f3xx.h"
+ #define FSDEV_PMA_SIZE (512u)
+ // NO internal Pull-ups
+ // *B, and *C: 1 x 16 bits/word
+ // PMA dedicated to USB (no sharing with CAN)
+
+#elif defined(STM32F302x6) || defined(STM32F302x8) || \
+ defined(STM32F302xD) || defined(STM32F302xE) || \
+ defined(STM32F303xD) || defined(STM32F303xE)
+ #include "stm32f3xx.h"
+ #define FSDEV_PMA_SIZE (1024u)
+ // NO internal Pull-ups
+ // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support
+ // When CAN clock is enabled, USB can use first 768 bytes ONLY.
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
+ #include "stm32l0xx.h"
+ #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
+ #include "stm32l1xx.h"
+ #define FSDEV_PMA_SIZE (512u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
+ #include "stm32g4xx.h"
+ #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+ #include "stm32g0xx.h"
+ #define FSDEV_PMA_SIZE (2048u)
+ #define USB USB_DRD_FS
+
+ #define USB_EP_CTR_RX USB_EP_VTRX
+ #define USB_EP_CTR_TX USB_EP_VTTX
+ #define USB_EP_T_FIELD USB_CHEP_UTYPE
+ #define USB_EPREG_MASK USB_CHEP_REG_MASK
+ #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+ #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+ #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+ #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+ #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+ #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+ #define USB_EPRX_STAT USB_CH_RX_VALID
+ #define USB_EPKIND_MASK USB_EP_KIND_MASK
+ #define USB_CNTR_FRES USB_CNTR_USBRST
+ #define USB_CNTR_RESUME USB_CNTR_L2RES
+ #define USB_ISTR_EP_ID USB_ISTR_IDN
+ #define USB_EPADDR_FIELD USB_CHEP_ADDR
+ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+ #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+ #include "stm32h5xx.h"
+ #define FSDEV_PMA_SIZE (2048u)
+ #define USB USB_DRD_FS
+
+ #define USB_EP_CTR_RX USB_EP_VTRX
+ #define USB_EP_CTR_TX USB_EP_VTTX
+ #define USB_EP_T_FIELD USB_CHEP_UTYPE
+ #define USB_EPREG_MASK USB_CHEP_REG_MASK
+ #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+ #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+ #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+ #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+ #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+ #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+ #define USB_EPRX_STAT USB_CH_RX_VALID
+ #define USB_EPKIND_MASK USB_EP_KIND_MASK
+ #define USB_CNTR_FRES USB_CNTR_USBRST
+ #define USB_CNTR_RESUME USB_CNTR_L2RES
+ #define USB_ISTR_EP_ID USB_ISTR_IDN
+ #define USB_EPADDR_FIELD USB_CHEP_ADDR
+ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+ #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+ #include "stm32wbxx.h"
+ #define FSDEV_PMA_SIZE (1024u)
+ /* ST provided header has incorrect value of USB_PMAADDR */
+ #define FSDEV_PMA_BASE USB1_PMAADDR
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
+ #include "stm32l4xx.h"
+ #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+ #include "stm32l5xx.h"
+ #define FSDEV_PMA_SIZE (1024u)
+
+ #ifndef USB_PMAADDR
+ #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
+ #endif
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
+ #include "stm32u5xx.h"
+ #define FSDEV_PMA_SIZE (2048u)
+ #define USB USB_DRD_FS
+
+ #define USB_EP_CTR_RX USB_EP_VTRX
+ #define USB_EP_CTR_TX USB_EP_VTTX
+ #define USB_EP_T_FIELD USB_CHEP_UTYPE
+ #define USB_EPREG_MASK USB_CHEP_REG_MASK
+ #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+ #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+ #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+ #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+ #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+ #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+ #define USB_EPRX_STAT USB_CH_RX_VALID
+ #define USB_EPKIND_MASK USB_EP_KIND_MASK
+ #define USB_CNTR_FRES USB_CNTR_USBRST
+ #define USB_CNTR_RESUME USB_CNTR_L2RES
+ #define USB_ISTR_EP_ID USB_ISTR_IDN
+ #define USB_EPADDR_FIELD USB_CHEP_ADDR
+ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+ #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U0
+ #include "stm32u0xx.h"
+ #define FSDEV_PMA_SIZE (2048u)
+ #define USB USB_DRD_FS
+
+ #define USB_EP_CTR_RX USB_EP_VTRX
+ #define USB_EP_CTR_TX USB_EP_VTTX
+ #define USB_EP_T_FIELD USB_CHEP_UTYPE
+ #define USB_EPREG_MASK USB_CHEP_REG_MASK
+ #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+ #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+ #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+ #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+ #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+ #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+ #define USB_EPRX_STAT USB_CH_RX_VALID
+ #define USB_EPKIND_MASK USB_EP_KIND_MASK
+ #define USB_CNTR_FRES USB_CNTR_USBRST
+ #define USB_CNTR_RESUME USB_CNTR_L2RES
+ #define USB_ISTR_EP_ID USB_ISTR_IDN
+ #define USB_EPADDR_FIELD USB_CHEP_ADDR
+ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+ #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#else
+ #error You are using an untested or unimplemented STM32 variant. Please update the driver.
+ // This includes U0
+#endif
+
+//--------------------------------------------------------------------+
+// Register and PMA Base Address
+//--------------------------------------------------------------------+
+#ifndef FSDEV_REG_BASE
+#if defined(USB_BASE)
+ #define FSDEV_REG_BASE USB_BASE
+#elif defined(USB_DRD_BASE)
+ #define FSDEV_REG_BASE USB_DRD_BASE
+#elif defined(USB_DRD_FS_BASE)
+ #define FSDEV_REG_BASE USB_DRD_FS_BASE
+#else
+ #error "FSDEV_REG_BASE not defined"
+#endif
+#endif
+
+#ifndef FSDEV_PMA_BASE
+#if defined(USB_PMAADDR)
+ #define FSDEV_PMA_BASE USB_PMAADDR
+#elif defined(USB_DRD_PMAADDR)
+ #define FSDEV_PMA_BASE USB_DRD_PMAADDR
+#else
+ #error "FSDEV_PMA_BASE not defined"
+#endif
+#endif
+
+// This checks if the device has "LPM"
+#if defined(USB_ISTR_L1REQ)
+#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)
+#else
+#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U)
+#endif
+
+#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
+ USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+#if TU_CHECK_MCU(OPT_MCU_STM32L1) && !defined(USBWakeUp_IRQn)
+ #define USBWakeUp_IRQn USB_FS_WKUP_IRQn
+#endif
+
+static const IRQn_Type fsdev_irq[] = {
+ #if TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32L0, OPT_MCU_STM32L4)
+ USB_IRQn,
+ #elif CFG_TUSB_MCU == OPT_MCU_STM32F1
+ USB_HP_CAN1_TX_IRQn,
+ USB_LP_CAN1_RX0_IRQn,
+ USBWakeUp_IRQn,
+ #elif CFG_TUSB_MCU == OPT_MCU_STM32F3
+ // USB remap handles dcd functions
+ USB_HP_CAN_TX_IRQn,
+ USB_LP_CAN_RX0_IRQn,
+ USBWakeUp_IRQn,
+ #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+ #ifdef STM32G0B0xx
+ USB_IRQn,
+ #else
+ USB_UCPD1_2_IRQn,
+ #endif
+ #elif TU_CHECK_MCU(OPT_MCU_STM32G4, OPT_MCU_STM32L1)
+ USB_HP_IRQn,
+ USB_LP_IRQn,
+ USBWakeUp_IRQn,
+ #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+ USB_DRD_FS_IRQn,
+ #elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+ USB_FS_IRQn,
+ #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+ USB_HP_IRQn,
+ USB_LP_IRQn,
+ #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
+ USB_IRQn,
+ #elif CFG_TUSB_MCU == OPT_MCU_STM32U0
+ USB_DRD_FS_IRQn,
+ #else
+ #error Unknown arch in USB driver
+ #endif
+};
+enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
+
+void dcd_int_enable(uint8_t rhport) {
+ (void)rhport;
+
+ // forces write to RAM before allowing ISR to execute
+ __DSB(); __ISB();
+
+ #if CFG_TUSB_MCU == OPT_MCU_STM32F3 && defined(SYSCFG_CFGR1_USB_IT_RMP)
+ // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
+ // shared USB/CAN IRQs to separate CAN and USB IRQs.
+ // This dynamically checks if this remap is active to enable the right IRQs.
+ if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
+ NVIC_EnableIRQ(USB_HP_IRQn);
+ NVIC_EnableIRQ(USB_LP_IRQn);
+ NVIC_EnableIRQ(USBWakeUp_RMP_IRQn);
+ } else
+ #endif
+ {
+ for (uint8_t i = 0; i < FSDEV_IRQ_NUM; i++) {
+ NVIC_EnableIRQ(fsdev_irq[i]);
+ }
+ }
+}
+
+void dcd_int_disable(uint8_t rhport) {
+ (void)rhport;
+
+ #if CFG_TUSB_MCU == OPT_MCU_STM32F3 && defined(SYSCFG_CFGR1_USB_IT_RMP)
+ // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
+ // shared USB/CAN IRQs to separate CAN and USB IRQs.
+ // This dynamically checks if this remap is active to enable the right IRQs.
+ if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
+ NVIC_DisableIRQ(USB_HP_IRQn);
+ NVIC_DisableIRQ(USB_LP_IRQn);
+ NVIC_DisableIRQ(USBWakeUp_RMP_IRQn);
+ } else
+ #endif
+ {
+ for (uint8_t i = 0; i < FSDEV_IRQ_NUM; i++) {
+ NVIC_DisableIRQ(fsdev_irq[i]);
+ }
+ }
+
+ // CMSIS has a membar after disabling interrupts
+}
+
+// Define only on MCU with internal pull-up. BSP can define on MCU without internal PU.
+#if defined(USB_BCDR_DPPU)
+
+void dcd_disconnect(uint8_t rhport) {
+ (void)rhport;
+ USB->BCDR &= ~(USB_BCDR_DPPU);
+}
+
+void dcd_connect(uint8_t rhport) {
+ (void)rhport;
+ USB->BCDR |= USB_BCDR_DPPU;
+}
+
+#elif defined(SYSCFG_PMC_USB_PU) // works e.g. on STM32L151
+
+void dcd_disconnect(uint8_t rhport) {
+ (void)rhport;
+ SYSCFG->PMC &= ~(SYSCFG_PMC_USB_PU);
+}
+
+void dcd_connect(uint8_t rhport) {
+ (void)rhport;
+ SYSCFG->PMC |= SYSCFG_PMC_USB_PU;
+}
+#endif
+
+
+#endif /* TUSB_FSDEV_STM32_H */
diff --git a/src/portable/st/stm32_fsdev/fsdev_type.h b/src/portable/st/stm32_fsdev/fsdev_type.h
new file mode 100644
index 0000000000..cf36576bb6
--- /dev/null
+++ b/src/portable/st/stm32_fsdev/fsdev_type.h
@@ -0,0 +1,307 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright(c) N Conrad
+ * Copyright(c) 2024, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_FSDEV_TYPE_H
+#define TUSB_FSDEV_TYPE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stdint.h"
+
+// If sharing with CAN, one can set this to be non-zero to give CAN space where it wants it
+// Both of these MUST be a multiple of 2, and are in byte units.
+#ifndef FSDEV_BTABLE_BASE
+#define FSDEV_BTABLE_BASE 0U
+#endif
+
+TU_VERIFY_STATIC(FSDEV_BTABLE_BASE % 8 == 0, "BTABLE base must be aligned to 8 bytes");
+
+// FSDEV_PMA_SIZE is PMA buffer size in bytes.
+// - 512-byte devices, access with a stride of two words (use every other 16-bit address)
+// - 1024-byte devices, access with a stride of one word (use every 16-bit address)
+// - 2048-byte devices, access with 32-bit address
+
+// For purposes of accessing the packet
+#if FSDEV_PMA_SIZE == 512
+ // 1x16 bit / word access scheme
+ #define FSDEV_PMA_STRIDE 2
+ #define pma_access_scheme TU_ATTR_ALIGNED(4)
+#elif FSDEV_PMA_SIZE == 1024
+ // 2x16 bit / word access scheme
+ #define FSDEV_PMA_STRIDE 1
+ #define pma_access_scheme
+#elif FSDEV_PMA_SIZE == 2048
+ // 32 bit access scheme
+ #define FSDEV_BUS_32BIT
+ #define FSDEV_PMA_STRIDE 1
+ #define pma_access_scheme
+#endif
+
+// The fsdev_bus_t type can be used for both register and PMA access necessities
+#ifdef FSDEV_BUS_32BIT
+ typedef uint32_t fsdev_bus_t;
+ #define fsdevbus_unaligned_read(_addr) tu_unaligned_read32(_addr)
+ #define fsdevbus_unaligned_write(_addr, _value) tu_unaligned_write32(_addr, _value)
+#else
+ typedef uint16_t fsdev_bus_t;
+ #define fsdevbus_unaligned_read(_addr) tu_unaligned_read16(_addr)
+ #define fsdevbus_unaligned_write(_addr, _value) tu_unaligned_write16(_addr, _value)
+#endif
+
+enum {
+ FSDEV_BUS_SIZE = sizeof(fsdev_bus_t),
+};
+
+//--------------------------------------------------------------------+
+// BTable Typedef
+//--------------------------------------------------------------------+
+enum {
+ BTABLE_BUF_TX = 0,
+ BTABLE_BUF_RX = 1
+};
+
+// hardware limit endpoint
+#define FSDEV_EP_COUNT 8
+
+// Buffer Table is located in Packet Memory Area (PMA) and therefore its address access is forced to either
+// 16-bit or 32-bit depending on FSDEV_BUS_32BIT.
+// 0: TX (IN), 1: RX (OUT)
+typedef union {
+ // data is strictly 16-bit access (address could be 32-bit aligned)
+ struct {
+ volatile pma_access_scheme uint16_t addr;
+ volatile pma_access_scheme uint16_t count;
+ } ep16[FSDEV_EP_COUNT][2];
+
+ // strictly 32-bit access
+ struct {
+ volatile uint32_t count_addr;
+ } ep32[FSDEV_EP_COUNT][2];
+} fsdev_btable_t;
+
+TU_VERIFY_STATIC(sizeof(fsdev_btable_t) == FSDEV_EP_COUNT*8*FSDEV_PMA_STRIDE, "size is not correct");
+TU_VERIFY_STATIC(FSDEV_BTABLE_BASE + FSDEV_EP_COUNT*8 <= FSDEV_PMA_SIZE, "BTABLE does not fit in PMA RAM");
+
+#define FSDEV_BTABLE ((volatile fsdev_btable_t*) (FSDEV_PMA_BASE + FSDEV_PMA_STRIDE*(FSDEV_BTABLE_BASE)))
+
+typedef struct {
+ volatile pma_access_scheme fsdev_bus_t value;
+} fsdev_pma_buf_t;
+
+#define PMA_BUF_AT(_addr) ((fsdev_pma_buf_t*) (FSDEV_PMA_BASE + FSDEV_PMA_STRIDE*(_addr)))
+
+//--------------------------------------------------------------------+
+// Registers Typedef
+//--------------------------------------------------------------------+
+
+// volatile 32-bit aligned
+#define _va32 volatile TU_ATTR_ALIGNED(4)
+
+typedef struct {
+ struct {
+ _va32 fsdev_bus_t reg;
+ }ep[FSDEV_EP_COUNT];
+
+ _va32 uint32_t RESERVED7[8]; // Reserved
+ _va32 fsdev_bus_t CNTR; // 40: Control register
+ _va32 fsdev_bus_t ISTR; // 44: Interrupt status register
+ _va32 fsdev_bus_t FNR; // 48: Frame number register
+ _va32 fsdev_bus_t DADDR; // 4C: Device address register
+ _va32 fsdev_bus_t BTABLE; // 50: Buffer Table address register (16-bit only)
+ _va32 fsdev_bus_t LPMCSR; // 54: LPM Control and Status Register (32-bit only)
+ _va32 fsdev_bus_t BCDR; // 58: Battery Charging Detector Register (32-bit only)
+} fsdev_regs_t;
+
+TU_VERIFY_STATIC(offsetof(fsdev_regs_t, CNTR) == 0x40, "Wrong offset");
+TU_VERIFY_STATIC(sizeof(fsdev_regs_t) == 0x5C, "Size is not correct");
+
+#define FSDEV_REG ((fsdev_regs_t*) FSDEV_REG_BASE)
+
+
+#ifndef USB_EPTX_STAT
+#define USB_EPTX_STAT 0x0030U
+#endif
+
+#ifndef USB_EPRX_STAT
+#define USB_EPRX_STAT 0x3000U
+#endif
+
+#ifndef USB_EPTX_STAT_Pos
+#define USB_EPTX_STAT_Pos 4u
+#endif
+
+#ifndef USB_EP_DTOG_TX_Pos
+#define USB_EP_DTOG_TX_Pos 6u
+#endif
+
+#ifndef USB_EP_CTR_TX_Pos
+#define USB_EP_CTR_TX_Pos 7u
+#endif
+
+typedef enum {
+ EP_STAT_DISABLED = 0,
+ EP_STAT_STALL = 1,
+ EP_STAT_NAK = 2,
+ EP_STAT_VALID = 3
+}ep_stat_t;
+
+#define EP_STAT_MASK(_dir) (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
+#define EP_DTOG_MASK(_dir) (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
+
+//--------------------------------------------------------------------+
+// Endpoint Helper
+// - CTR is write 0 to clear
+// - DTOG and STAT are write 1 to toggle
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_read(uint32_t ep_id) {
+ return FSDEV_REG->ep[ep_id].reg;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void ep_write(uint32_t ep_id, uint32_t value, bool need_exclusive) {
+ if (need_exclusive) {
+ dcd_int_disable(0);
+ }
+
+ FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t) value;
+
+ if (need_exclusive) {
+ dcd_int_enable(0);
+ }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void ep_write_clear_ctr(uint32_t ep_id, tusb_dir_t dir) {
+ uint32_t reg = FSDEV_REG->ep[ep_id].reg;
+ reg |= USB_EP_CTR_TX | USB_EP_CTR_RX;
+ reg &= USB_EPREG_MASK;
+ reg &= ~(1 << (USB_EP_CTR_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
+ ep_write(ep_id, reg, false);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void ep_change_status(uint32_t* reg, tusb_dir_t dir, ep_stat_t state) {
+ *reg ^= (state << (USB_EPTX_STAT_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void ep_change_dtog(uint32_t* reg, tusb_dir_t dir, uint8_t state) {
+ *reg ^= (state << (USB_EP_DTOG_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(uint32_t reg) {
+ return (reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS;
+}
+
+//--------------------------------------------------------------------+
+// BTable Helper
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t btable_get_addr(uint32_t ep_id, uint8_t buf_id) {
+#ifdef FSDEV_BUS_32BIT
+ return FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr & 0x0000FFFFu;
+#else
+ return FSDEV_BTABLE->ep16[ep_id][buf_id].addr;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void btable_set_addr(uint32_t ep_id, uint8_t buf_id, uint16_t addr) {
+#ifdef FSDEV_BUS_32BIT
+ uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
+ count_addr = (count_addr & 0xFFFF0000u) | (addr & 0x0000FFFCu);
+ FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
+#else
+ FSDEV_BTABLE->ep16[ep_id][buf_id].addr = addr;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t btable_get_count(uint32_t ep_id, uint8_t buf_id) {
+ uint16_t count;
+#ifdef FSDEV_BUS_32BIT
+ count = (FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr >> 16);
+#else
+ count = FSDEV_BTABLE->ep16[ep_id][buf_id].count;
+#endif
+ return count & 0x3FFU;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void btable_set_count(uint32_t ep_id, uint8_t buf_id, uint16_t byte_count) {
+#ifdef FSDEV_BUS_32BIT
+ uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
+ count_addr = (count_addr & ~0x03FF0000u) | ((byte_count & 0x3FFu) << 16);
+ FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
+#else
+ uint16_t cnt = FSDEV_BTABLE->ep16[ep_id][buf_id].count;
+ cnt = (cnt & ~0x3FFU) | (byte_count & 0x3FFU);
+ FSDEV_BTABLE->ep16[ep_id][buf_id].count = cnt;
+#endif
+}
+
+/* Aligned buffer size according to hardware */
+TU_ATTR_ALWAYS_INLINE static inline uint16_t pma_align_buffer_size(uint16_t size, uint8_t* blsize, uint8_t* num_block) {
+ /* The STM32 full speed USB peripheral supports only a limited set of
+ * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
+ uint16_t block_in_bytes;
+ if (size > 62) {
+ block_in_bytes = 32;
+ *blsize = 1;
+ *num_block = tu_div_ceil(size, 32);
+ } else {
+ block_in_bytes = 2;
+ *blsize = 0;
+ *num_block = tu_div_ceil(size, 2);
+ }
+
+ return (*num_block) * block_in_bytes;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void btable_set_rx_bufsize(uint32_t ep_id, uint8_t buf_id, uint16_t wCount) {
+ uint8_t blsize, num_block;
+ (void) pma_align_buffer_size(wCount, &blsize, &num_block);
+
+ /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
+ uint16_t bl_nb = (blsize << 15) | ((num_block - blsize) << 10);
+ if (bl_nb == 0) {
+ // zlp but 0 is invalid value, set blsize to 1 (32 bytes)
+ // Note: lower value can cause PMAOVR on setup with ch32v203
+ bl_nb = 1 << 15;
+ }
+
+#ifdef FSDEV_BUS_32BIT
+ uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
+ count_addr = (bl_nb << 16) | (count_addr & 0x0000FFFFu);
+ FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
+#else
+ FSDEV_BTABLE->ep16[ep_id][buf_id].count = bl_nb;
+#endif
+
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 6cc1975a81..21f13b279d 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -35,7 +35,9 @@
#include
#include
#include "musb_def.h"
-#include "bsp/board.h"
+
+//#include "bsp/board_api.h"
+extern uint32_t board_millis(void); // TODO remove
typedef uint32_t u32;
typedef uint16_t u16;
@@ -58,7 +60,7 @@ typedef struct TU_ATTR_PACKED
typedef struct
{
- tusb_control_request_t setup_packet;
+ CFG_TUD_MEM_ALIGN tusb_control_request_t setup_packet;
uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
int8_t status_out;
pipe_state_t pipe0;
@@ -350,7 +352,7 @@ static void USBC_INT_DisableRxEp(u8 ep_index)
* INTERNAL FUNCTION DECLARATION
*------------------------------------------------------------------*/
-static dcd_data_t _dcd;
+CFG_TUD_MEM_ALIGN static dcd_data_t _dcd;
static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
{
@@ -560,7 +562,7 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
static void process_setup_packet(uint8_t rhport)
{
- uint32_t *p = (uint32_t*)&_dcd.setup_packet;
+ uint32_t *p = (uint32_t*)(uintptr_t) &_dcd.setup_packet;
p[0] = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
p[1] = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
@@ -594,7 +596,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
if (len) {
volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
- pipe_read_write_packet_ff((tu_fifo_t *)buf, addr, len, TUSB_DIR_IN);
+ pipe_read_write_packet_ff((tu_fifo_t *)(uintptr_t) buf, addr, len, TUSB_DIR_IN);
} else {
pipe_write_packet(buf, addr, len);
pipe->buf = buf + len;
@@ -622,7 +624,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
if (len) {
volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) {
- pipe_read_write_packet_ff((tu_fifo_t *)buf, addr, len, TUSB_DIR_OUT);
+ pipe_read_write_packet_ff((tu_fifo_t *)(uintptr_t )buf, addr, len, TUSB_DIR_OUT);
} else {
pipe_read_packet(buf, addr, len);
pipe->buf = buf + len;
@@ -865,8 +867,9 @@ static void usb_isr_handler(void) {
dcd_int_handler(0);
}
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
+
dcd_disconnect(rhport);
USBC_HardwareReset();
USBC_PhyConfig();
@@ -893,6 +896,8 @@ void dcd_init(uint8_t rhport)
f1c100s_intc_set_isr(F1C100S_IRQ_USBOTG, usb_isr_handler);
dcd_connect(rhport);
+
+ return true;
}
// Connect by enabling internal pull-up resistor on D+/D-
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 692096fc82..f30ec5ee39 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,6 +31,9 @@
#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
+// Debug level for DWC2
+#define DWC2_DEBUG 2
+
#include "device/dcd.h"
#include "dwc2_type.h"
@@ -43,7 +46,7 @@
#if defined(TUP_USBIP_DWC2_STM32)
#include "dwc2_stm32.h"
-#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#elif defined(TUP_USBIP_DWC2_ESP32)
#include "dwc2_esp32.h"
#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
#include "dwc2_gd32.h"
@@ -57,29 +60,26 @@
#error "Unsupported MCUs"
#endif
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
+enum {
+ DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
+};
// DWC2 registers
-#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
-
-// Debug level for DWC2
-#define DWC2_DEBUG 2
-
-#ifndef dcache_clean
-#define dcache_clean(_addr, _size)
-#endif
+//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
-#ifndef dcache_invalidate
-#define dcache_invalidate(_addr, _size)
-#endif
+TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
+ if (rhport >= DWC2_CONTROLLER_COUNT) {
+ // user mis-configured, ignore and use first controller
+ rhport = 0;
+ }
+ return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base;
+}
-#ifndef dcache_clean_invalidate
-#define dcache_clean_invalidate(_addr, _size)
-#endif
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
+static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
typedef struct {
uint8_t* buffer;
@@ -93,99 +93,230 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
// EP0 transfers are limited to 1 packet - larger sizes has to be split
-static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
+static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
+static uint16_t _dfifo_top; // top free location in FIFO RAM
-// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
-static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
+// Number of IN endpoints active
+static uint8_t _allocated_ep_in_count;
// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
static bool _sof_en;
-// Calculate the RX FIFO size according to minimum recommendations from reference manual
-// RxFIFO = (5 * number of control endpoints + 8) +
-// ((largest USB packet used / 4) + 1 for status information) +
-// (2 * number of OUT endpoints) + 1 for Global NAK
-// with number of control endpoints = 1 we have
-// RxFIFO = 15 + (largest USB packet used / 4) + 2 * number of OUT endpoints
-// we double the largest USB packet size to be able to hold up to 2 packets
-static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
- return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
+//--------------------------------------------------------------------
+// DMA
+//--------------------------------------------------------------------
+
+TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(const dwc2_regs_t* dwc2) {
+ #if !CFG_TUD_DWC2_DMA
+ (void) dwc2;
+ return false;
+ #else
+ // Internal DMA only
+ return (dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA);
+ #endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) {
+ // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
+ const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+ return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count;
+}
+
+static void dma_setup_prepare(uint8_t rhport) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) {
+ if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) {
+ return;
+ }
+ }
+
+ // Receive only 1 packet
+ dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos);
+ dwc2->epout[0].doepdma = (uintptr_t)_setup_packet;
+ dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP;
}
-TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) {
+//--------------------------------------------------------------------+
+// Data FIFO
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) {
// flush TX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos);
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
}
-TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_rx(dwc2_regs_t* dwc2) {
+TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) {
// flush RX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_RXFFLSH;
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
}
-static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
+/* USB Data FIFO Layout
+
+ The FIFO is split up into
+ - EPInfo: for storing DMA metadata, only required when use DMA. Maximum size is called
+ EP_LOC_CNT = ep_fifo_size - ghwcfg3.dfifo_depth. For value less than EP_LOC_CNT, gdfifocfg must be configured before
+ gahbcfg.dmaen is set
+ - Buffer mode: 1 word per endpoint direction
+ - Scatter/Gather DMA: 4 words per endpoint direction
+ - TX FIFO: one fifo for each IN endpoint. Size is dynamic depending on packet size, starting from top with EP0 IN.
+ - Shared RX FIFO: a shared fifo for all OUT endpoints. Typically, can hold up to 2 packets of the largest EP size.
+
+ We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is
+ possible since the free space is located between the RX and TX FIFOs.
+
+ ---------------- ep_fifo_size
+ | EPInfo |
+ | for DMA |
+ |-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth)
+ | IN FIFO 0 |
+ | control |
+ |-------------|
+ | IN FIFO 1 |
+ |-------------|
+ | . . . . |
+ |-------------|
+ | IN FIFO n |
+ |-------------|
+ | FREE |
+ |-------------|-- GRXFSIZ (expandable)
+ | OUT FIFO |
+ | ( Shared ) |
+ --------------- 0
+
+ According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
+ - Each EP IN needs at least max packet size
+ - All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula):
+ - 13 for setup packets + control words (up to 3 setup packets).
+ - 1 for global NAK (not required/used here).
+ - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1"
+ - 2 for each used OUT endpoint
+
+ Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum
+*/
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) {
+ return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count;
+}
+
+static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+ const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+ uint8_t const ep_count = dwc2_controller->ep_count;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
TU_ASSERT(epnum < ep_count);
uint16_t fifo_size = tu_div_ceil(packet_size, 4);
-
- // "USB Data FIFOs" section in reference manual
- // Peripheral FIFO architecture
- //
- // --------------- 320 or 1024 ( 1280 or 4096 bytes )
- // | IN FIFO 0 |
- // --------------- (320 or 1024) - 16
- // | IN FIFO 1 |
- // --------------- (320 or 1024) - 16 - x
- // | . . . . |
- // --------------- (320 or 1024) - 16 - x - y - ... - z
- // | IN FIFO MAX |
- // ---------------
- // | FREE |
- // --------------- GRXFSIZ
- // | OUT FIFO |
- // | ( Shared ) |
- // --------------- 0
- //
- // In FIFO is allocated by following rules:
- // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
if (dir == TUSB_DIR_OUT) {
// Calculate required size of RX FIFO
- uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
-
- // If size_rx needs to be extended check if possible and if so enlarge it
- if (dwc2->grxfsiz < sz) {
- TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
+ uint16_t const new_sz = calc_grxfsiz(4 * fifo_size, ep_count);
- // Enlarge RX FIFO
- dwc2->grxfsiz = sz;
+ // If size_rx needs to be extended check if there is enough free space
+ if (dwc2->grxfsiz < new_sz) {
+ TU_ASSERT(new_sz <= _dfifo_top);
+ dwc2->grxfsiz = new_sz; // Enlarge RX FIFO
}
} else {
- // Note if The TXFELVL is configured as half empty. In order
- // to be able to write a packet at that point, the fifo must be twice the max_size.
+ // Check IN endpoints concurrently active limit
+ if(_dwc2_controller->ep_in_count) {
+ TU_ASSERT(_allocated_ep_in_count < _dwc2_controller->ep_in_count);
+ _allocated_ep_in_count++;
+ }
+
+ // If The TXFELVL is configured as half empty, the fifo must be twice the max_size.
if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) {
fifo_size *= 2;
}
// Check if free space is available
- TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
- _allocated_fifo_words_tx += fifo_size;
- TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %" PRIu32, fifo_size * 4,
- _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
+ TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz);
+ _dfifo_top -= fifo_size;
+ TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top);
- // DIEPTXF starts at FIFO #1.
// Both TXFD and TXSA are in unit of 32-bit words.
- dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
- (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
+ if (epnum == 0) {
+ dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dfifo_top;
+ } else {
+ // DIEPTXF starts at FIFO #1.
+ dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dfifo_top;
+ }
}
return true;
}
+static void dfifo_init(uint8_t rhport) {
+ const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ dwc2->grxfsiz = calc_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count);
+
+ if(dma_enabled(dwc2)) {
+ // DMA use last DFIFO to store metadata
+ _dfifo_top = dma_cal_epfifo_base(rhport);
+ }else {
+ _dfifo_top = dwc2_controller->ep_fifo_size / 4;
+ }
+
+ // Allocate FIFO for EP0 IN
+ dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
+}
+
+// Read a single data packet from receive FIFO
+static void dfifo_read_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ volatile const uint32_t* rx_fifo = dwc2->fifo[0];
+
+ // Reading full available 32 bit words from fifo
+ uint16_t full_words = len >> 2;
+ while (full_words--) {
+ tu_unaligned_write32(dst, *rx_fifo);
+ dst += 4;
+ }
+
+ // Read the remaining 1-3 bytes from fifo
+ uint8_t const bytes_rem = len & 0x03;
+ if (bytes_rem != 0) {
+ uint32_t const tmp = *rx_fifo;
+ dst[0] = tu_u32_byte0(tmp);
+ if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
+ if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
+ }
+}
+
+// Write a single data packet to EPIN FIFO
+static void dfifo_write_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
+
+ // Pushing full available 32 bit words to fifo
+ uint16_t full_words = len >> 2;
+ while (full_words--) {
+ *tx_fifo = tu_unaligned_read32(src);
+ src += 4;
+ }
+
+ // Write the remaining 1-3 bytes into fifo
+ uint8_t const bytes_rem = len & 0x03;
+ if (bytes_rem) {
+ uint32_t tmp_word = src[0];
+ if (bytes_rem > 1) tmp_word |= (src[1] << 8);
+ if (bytes_rem > 2) tmp_word |= (src[2] << 16);
+
+ *tx_fifo = tmp_word;
+ }
+}
+
+//--------------------------------------------------------------------
+// Endpoint
+//--------------------------------------------------------------------
+
static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
@@ -196,53 +327,49 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin
xfer->interval = p_endpoint_desc->bInterval;
// USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints.
- uint32_t const dxepctl = (1 << DOEPCTL_USBAEP_Pos) |
- (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
- (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
- (xfer->max_size << DOEPCTL_MPSIZ_Pos);
-
- if (dir == TUSB_DIR_OUT) {
- dwc2->epout[epnum].doepctl = dxepctl;
- dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
- } else {
- dwc2->epin[epnum].diepctl = dxepctl | (epnum << DIEPCTL_TXFNUM_Pos);
- dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
+ uint32_t epctl = (1 << DOEPCTL_USBAEP_Pos) |
+ (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
+ (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
+ (xfer->max_size << DOEPCTL_MPSIZ_Pos);
+ if (dir == TUSB_DIR_IN) {
+ epctl |= (epnum << DIEPCTL_TXFNUM_Pos);
}
+
+ dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
+ dep->ctl = epctl;
+ dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir));
}
static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
+ const uint8_t epnum = tu_edpt_number(ep_addr);
+ const uint8_t dir = tu_edpt_dir(ep_addr);
+ dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
if (dir == TUSB_DIR_IN) {
- dwc2_epin_t* epin = dwc2->epin;
-
// Only disable currently enabled non-control endpoint
- if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) {
- epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+ if ((epnum == 0) || !(dep->diepctl & DIEPCTL_EPENA)) {
+ dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
} else {
// Stop transmitting packets and NAK IN xfers.
- epin[epnum].diepctl |= DIEPCTL_SNAK;
- while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {}
+ dep->diepctl |= DIEPCTL_SNAK;
+ while ((dep->diepint & DIEPINT_INEPNE) == 0) {}
// Disable the endpoint.
- epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
- while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {}
+ dep->diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+ while ((dep->diepint & DIEPINT_EPDISD_Msk) == 0) {}
- epin[epnum].diepint = DIEPINT_EPDISD;
+ dep->diepint = DIEPINT_EPDISD;
}
// Flush the FIFO, and wait until we have confirmed it cleared.
- fifo_flush_tx(dwc2, epnum);
+ dfifo_flush_tx(dwc2, epnum);
} else {
- dwc2_epout_t* epout = dwc2->epout;
-
// Only disable currently enabled non-control endpoint
- if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) {
- epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
+ if ((epnum == 0) || !(dep->doepctl & DOEPCTL_EPENA)) {
+ dep->doepctl |= stall ? DOEPCTL_STALL : 0;
} else {
// Asserting GONAK is required to STALL an OUT endpoint.
// Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
@@ -251,11 +378,11 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
dwc2->dctl |= DCTL_SGONAK;
while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
- // Ditto here- disable the endpoint.
- epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
- while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {}
+ // Ditto here disable the endpoint.
+ dep->doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+ while ((dep->doepint & DOEPINT_EPDISD_Msk) == 0) {}
- epout[epnum].doepint = DOEPINT_EPDISD;
+ dep->doepint = DOEPINT_EPDISD;
// Allow other OUT endpoints to keep receiving.
dwc2->dctl |= DCTL_CGONAK;
@@ -271,9 +398,7 @@ static void bus_reset(uint8_t rhport) {
tu_memclr(xfer_status, sizeof(xfer_status));
_sof_en = false;
-
- // clear device address
- dwc2->dcfg &= ~DCFG_DAD_Msk;
+ _allocated_ep_in_count = 1;
// 1. NAK for all OUT endpoints
for (uint8_t n = 0; n < ep_count; n++) {
@@ -287,79 +412,32 @@ static void bus_reset(uint8_t rhport) {
}
}
- fifo_flush_tx(dwc2, 0x10); // all tx fifo
- fifo_flush_rx(dwc2);
+ dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+ dfifo_flush_rx(dwc2);
- // 3. Set up interrupt mask
+ // 3. Set up interrupt mask for EP0
dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
- // "USB Data FIFOs" section in reference manual
- // Peripheral FIFO architecture
- //
- // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
- // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
- // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
- // configuration done below.
- //
- // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
- // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
- // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
- // opened when the host sends an additional command: setInterface. At this point in time
- // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
- // an additional memory
- //
- // --------------- 320 or 1024 ( 1280 or 4096 bytes )
- // | IN FIFO 0 |
- // --------------- (320 or 1024) - 16
- // | IN FIFO 1 |
- // --------------- (320 or 1024) - 16 - x
- // | . . . . |
- // --------------- (320 or 1024) - 16 - x - y - ... - z
- // | IN FIFO MAX |
- // ---------------
- // | FREE |
- // --------------- GRXFSIZ
- // | OUT FIFO |
- // | ( Shared ) |
- // --------------- 0
- //
- // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
- // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
- //
- // - All EP OUT shared a unique OUT FIFO which uses
- // - 13 for setup packets + control words (up to 3 setup packets).
- // - 1 for global NAK (not required/used here).
- // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1"
- // - 2 for each used OUT endpoint
- //
- // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
- // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x ep_count = 47 + 2 x ep_count
- // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x ep_count = 271 + 2 x ep_count
- //
- // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
- // of the overall picture yet. We will use the worst scenario: largest possible + ep_count
- //
- // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
- // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to
- // overwrite this.
-
- // EP0 out max is 64
- dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
-
- // Setup the control endpoint 0
- _allocated_fifo_words_tx = 16;
-
- // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
- dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
-
- // Fixed control EP0 size to 64 bytes
+ // 4. Set up DFIFO
+ dfifo_init(rhport);
+
+ // 5. Reset device address
+ dwc2->dcfg &= ~DCFG_DAD_Msk;
+
+ // Fixed both control EP0 size to 64 bytes
dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
+ dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos);
+
xfer_status[0][TUSB_DIR_OUT].max_size = 64;
xfer_status[0][TUSB_DIR_IN].max_size = 64;
- dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+ if(dma_enabled(dwc2)) {
+ dma_setup_prepare(rhport);
+ } else {
+ dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+ }
dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
}
@@ -369,68 +447,73 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
// EP0 is limited to one packet each xfer
// We use multiple transaction of xfer->max_size length to get a whole transfer done
if (epnum == 0) {
- xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
ep0_pending[dir] -= total_bytes;
}
// IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
- if (dir == TUSB_DIR_IN) {
- dwc2_epin_t* epin = dwc2->epin;
+ const uint8_t is_epout = 1 - dir;
+ dwc2_dep_t* dep = &dwc2->ep[is_epout][epnum];
+ if (dir == TUSB_DIR_IN) {
// A full IN transfer (multiple packets, possibly) triggers XFRC.
- epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
+ dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
- epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+ if(dma_enabled(dwc2)) {
+ dep->diepdma = (uintptr_t)xfer->buffer;
- // For ISO endpoint set correct odd/even bit for next frame.
- if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
- // Take odd/even bit from frame counter.
- uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
- epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
- }
- // Enable fifo empty interrupt only if there are something to put in the fifo.
- if (total_bytes != 0) {
- dwc2->diepempmsk |= (1 << epnum);
+ // For ISO endpoint set correct odd/even bit for next frame.
+ if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
+ // Take odd/even bit from frame counter.
+ uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
+ dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
+ }
+
+ dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+ } else {
+ dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+
+ // For ISO endpoint set correct odd/even bit for next frame.
+ if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
+ // Take odd/even bit from frame counter.
+ uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
+ dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
+ }
+ // Enable fifo empty interrupt only if there are something to put in the fifo.
+ if (total_bytes != 0) {
+ dwc2->diepempmsk |= (1 << epnum);
+ }
}
} else {
- dwc2_epout_t* epout = dwc2->epout;
-
// A full OUT transfer (multiple packets, possibly) triggers XFRC.
- epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
- epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
+ dep->doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
+ dep->doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
- epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
- if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
+ if ((dep->doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
XFER_CTL_BASE(epnum, dir)->interval == 1) {
// Take odd/even bit from frame counter.
uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
- epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
+ dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
}
+
+ if(dma_enabled(dwc2)) {
+ dep->doepdma = (uintptr_t)xfer->buffer;
+ }
+
+ dep->doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
}
}
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
-#if CFG_TUSB_DEBUG >= DWC2_DEBUG
-void print_dwc2_info(dwc2_regs_t* dwc2) {
- // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
- // use dwc2_info.py/md for bit-field value and comparison with other ports
- volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
- TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
- for (size_t i = 0; i < 5; i++) {
- TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 ", ", p[i]);
- }
- TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 "\r\n", p[5]);
-}
-#endif
static void reset_core(dwc2_regs_t* dwc2) {
// reset core
@@ -449,13 +532,10 @@ static void reset_core(dwc2_regs_t* dwc2) {
static bool phy_hs_supported(dwc2_regs_t* dwc2) {
(void) dwc2;
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
- // note: esp32 incorrect report its hs_phy_type as utmi
- return false;
-#elif !TUD_OPT_HIGH_SPEED
+#if !TUD_OPT_HIGH_SPEED
return false;
#else
- return dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
+ return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
#endif
}
@@ -466,7 +546,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
dwc2->gusbcfg |= GUSBCFG_PHYSEL;
// MCU specific PHY init before reset
- dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE);
+ dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
// Reset core after selecting PHY
reset_core(dwc2);
@@ -477,7 +557,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
// MCU specific PHY update post reset
- dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE);
+ dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
// set max speed
dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
@@ -489,7 +569,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// De-select FS PHY
gusbcfg &= ~GUSBCFG_PHYSEL;
- if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
+ if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
// Select ULPI
@@ -510,7 +590,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
// Set 16-bit interface if supported
- if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
+ if (dwc2->ghwcfg4_bm.phy_data_width) {
+ gusbcfg |= GUSBCFG_PHYIF16;
+ }
}
// Apply config
@@ -526,7 +608,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// - 9 if using 8-bit PHY interface
// - 5 if using 16-bit PHY interface
gusbcfg &= ~GUSBCFG_TRDT_Msk;
- gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+ gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
dwc2->gusbcfg = gusbcfg;
// MCU specific PHY update post reset
@@ -539,17 +621,26 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
- if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY;
+ if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
+ dcfg |= DCFG_XCVRDLY;
+ }
dwc2->dcfg = dcfg;
}
static bool check_dwc2(dwc2_regs_t* dwc2) {
#if CFG_TUSB_DEBUG >= DWC2_DEBUG
- print_dwc2_info(dwc2);
+ // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
+ // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports
+ volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
+ TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
+ for (size_t i = 0; i < 5; i++) {
+ TU_LOG1("0x%08" PRIX32 ", ", p[i]);
+ }
+ TU_LOG1("0x%08" PRIX32 "\r\n", p[5]);
#endif
- // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
+ // For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
(void) dwc2;
#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
@@ -559,18 +650,17 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
return true;
}
-void dcd_init(uint8_t rhport) {
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rhport;
+ (void) rh_init;
// Programming model begins in the last section of the chapter on the USB
// peripheral in each Reference Manual.
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
// Check Synopsys ID register, failed if controller clock/power is not enabled
- if (!check_dwc2(dwc2)) return;
+ TU_ASSERT(check_dwc2(dwc2));
dcd_disconnect(rhport);
- // max number of endpoints & total_fifo_size are:
- // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size
-
if (phy_hs_supported(dwc2)) {
phy_hs_init(dwc2); // Highspeed
} else {
@@ -600,8 +690,8 @@ void dcd_init(uint8_t rhport) {
// (non zero-length packet), send STALL back and discard.
dwc2->dcfg |= DCFG_NZLSOHSK;
- fifo_flush_tx(dwc2, 0x10); // all tx fifo
- fifo_flush_rx(dwc2);
+ dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+ dfifo_flush_rx(dwc2);
// Clear all interrupts
uint32_t int_mask = dwc2->gintsts;
@@ -610,12 +700,21 @@ void dcd_init(uint8_t rhport) {
dwc2->gotgint |= int_mask;
// Required as part of core initialization.
- dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_RXFLVLM |
- GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
+ dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
// Configure TX FIFO empty level for interrupt. Default is complete empty
dwc2->gahbcfg |= GAHBCFG_TXFELVL;
+ if (dma_enabled(dwc2)) {
+ const uint16_t epinfo_base = dma_cal_epfifo_base(rhport);
+ dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base;
+
+ // DMA seems to be only settable after a core reset
+ dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
+ }else {
+ dwc2->gintmsk |= GINTMSK_RXFLVLM;
+ }
+
// Enable global interrupt
dwc2->gahbcfg |= GAHBCFG_GINT;
@@ -628,6 +727,8 @@ void dcd_init(uint8_t rhport) {
// TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg);
dcd_connect(rhport);
+
+ return true;
}
void dcd_int_enable(uint8_t rhport) {
@@ -667,12 +768,34 @@ void dcd_remote_wakeup(uint8_t rhport) {
void dcd_connect(uint8_t rhport) {
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+#ifdef TUP_USBIP_DWC2_ESP32
+ usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+ conf.pad_pull_override = 0;
+ conf.dp_pullup = 0;
+ conf.dp_pulldown = 0;
+ conf.dm_pullup = 0;
+ conf.dm_pulldown = 0;
+ USB_WRAP.otg_conf = conf;
+#endif
+
dwc2->dctl &= ~DCTL_SDIS;
}
void dcd_disconnect(uint8_t rhport) {
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+#ifdef TUP_USBIP_DWC2_ESP32
+ usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+ conf.pad_pull_override = 1;
+ conf.dp_pullup = 0;
+ conf.dp_pulldown = 1;
+ conf.dm_pullup = 0;
+ conf.dm_pulldown = 1;
+ USB_WRAP.otg_conf = conf;
+#endif
+
dwc2->dctl |= DCTL_SDIS;
}
@@ -696,7 +819,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) {
*------------------------------------------------------------------*/
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
- TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
+ TU_ASSERT(dfifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
edpt_activate(rhport, desc_edpt);
return true;
}
@@ -706,43 +829,36 @@ void dcd_edpt_close_all(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+ _allocated_ep_in_count = 1;
+
// Disable non-control interrupt
dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
for (uint8_t n = 1; n < ep_count; n++) {
- // disable OUT endpoint
- if (dwc2->epout[n].doepctl & DOEPCTL_EPENA) {
- dwc2->epout[n].doepctl |= DOEPCTL_SNAK | DOEPCTL_EPDIS;
- }
- xfer_status[n][TUSB_DIR_OUT].max_size = 0;
-
- // disable IN endpoint
- if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
- dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+ for (uint8_t d = 0; d < 2; d++) {
+ dwc2_dep_t* dep = &dwc2->ep[d][n];
+ if (dep->ctl & EPCTL_EPENA) {
+ dep->ctl |= EPCTL_SNAK | EPCTL_EPDIS;
+ }
+ xfer_status[n][1-d].max_size = 0;
}
- xfer_status[n][TUSB_DIR_IN].max_size = 0;
}
- // reset allocated fifo OUT
- dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
- // reset allocated fifo IN
- _allocated_fifo_words_tx = 16;
+ dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+ dfifo_flush_rx(dwc2);
- fifo_flush_tx(dwc2, 0x10); // all tx fifo
- fifo_flush_rx(dwc2);
+ dfifo_init(rhport); // re-init dfifo
}
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
- TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size));
+ TU_ASSERT(dfifo_alloc(rhport, ep_addr, largest_packet_size));
return true;
}
bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
// Disable EP to clear potential incomplete transfers
edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false);
-
edpt_activate(rhport, p_endpoint_desc);
-
return true;
}
@@ -795,7 +911,9 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
uint16_t const short_packet_size = total_bytes % xfer->max_size;
// Zero-size packet is special case.
- if (short_packet_size > 0 || (total_bytes == 0)) num_packets++;
+ if (short_packet_size > 0 || (total_bytes == 0)) {
+ num_packets++;
+ }
// Schedule packets to be sent within interrupt
edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
@@ -809,100 +927,38 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
edpt_disable(rhport, ep_addr, true);
+ if((tu_edpt_number(ep_addr) == 0) && dma_enabled(DWC2_REG(rhport))) {
+ dma_setup_prepare(rhport);
+ }
}
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
- (void) rhport;
-
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
+ dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
// Clear stall and reset data toggle
- if (dir == TUSB_DIR_IN) {
- dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL;
- dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
- } else {
- dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL;
- dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
- }
+ dep->ctl &= ~EPCTL_STALL;;
+ dep->ctl |= EPCTL_SD0PID_SEVNFRM;
}
-/*------------------------------------------------------------------*/
-
-// Read a single data packet from receive FIFO
-static void read_fifo_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
- (void) rhport;
-
- dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- volatile const uint32_t* rx_fifo = dwc2->fifo[0];
-
- // Reading full available 32 bit words from fifo
- uint16_t full_words = len >> 2;
- while (full_words--) {
- tu_unaligned_write32(dst, *rx_fifo);
- dst += 4;
- }
-
- // Read the remaining 1-3 bytes from fifo
- uint8_t const bytes_rem = len & 0x03;
- if (bytes_rem != 0) {
- uint32_t const tmp = *rx_fifo;
- dst[0] = tu_u32_byte0(tmp);
- if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
- if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
- }
-}
-
-// Write a single data packet to EPIN FIFO
-static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
- (void) rhport;
-
- dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
-
- // Pushing full available 32 bit words to fifo
- uint16_t full_words = len >> 2;
- while (full_words--) {
- *tx_fifo = tu_unaligned_read32(src);
- src += 4;
- }
-
- // Write the remaining 1-3 bytes into fifo
- uint8_t const bytes_rem = len & 0x03;
- if (bytes_rem) {
- uint32_t tmp_word = src[0];
- if (bytes_rem > 1) tmp_word |= (src[1] << 8);
- if (bytes_rem > 2) tmp_word |= (src[2] << 16);
-
- *tx_fifo = tmp_word;
- }
-}
+//--------------------------------------------------------------------
+// Interrupt Handler
+//--------------------------------------------------------------------
+// Process shared receive FIFO, this interrupt is only used in Slave mode
static void handle_rxflvl_irq(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
volatile uint32_t const* rx_fifo = dwc2->fifo[0];
// Pop control word off FIFO
- uint32_t const ctl_word = dwc2->grxstsp;
- uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
- uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
- uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
-
+ uint32_t const grxstsp = dwc2->grxstsp;
+ uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
+ uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
+ uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
dwc2_epout_t* epout = &dwc2->epout[epnum];
-//#if CFG_TUSB_DEBUG >= DWC2_DEBUG
-// const char * pktsts_str[] =
-// {
-// "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)",
-// "Setup Complete (ISR)", "ASSERT", "Setup Data Received"
-// };
-// TU_LOG_LOCATION();
-// TU_LOG(DWC2_DEBUG, " EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]);
-// TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint);
-//#endif
-
switch (pktsts) {
// Global OUT NAK: do nothing
case GRXSTS_PKTSTS_GLOBALOUTNAK:
@@ -910,15 +966,14 @@ static void handle_rxflvl_irq(uint8_t rhport) {
case GRXSTS_PKTSTS_SETUPRX:
// Setup packet received
-
- // We can receive up to three setup packets in succession, but
- // only the last one is valid.
+ // We can receive up to three setup packets in succession, but only the last one is valid.
_setup_packet[0] = (*rx_fifo);
_setup_packet[1] = (*rx_fifo);
break;
case GRXSTS_PKTSTS_SETUPDONE:
- // Setup packet done (Interrupt)
+ // Setup packet done:
+ // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq()
epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
break;
@@ -932,7 +987,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
} else {
// Linear buffer
- read_fifo_packet(rhport, xfer->buffer, bcnt);
+ dfifo_read_packet(rhport, xfer->buffer, bcnt);
// Increment pointer to xfer data
xfer->buffer += bcnt;
@@ -946,34 +1001,16 @@ static void handle_rxflvl_irq(uint8_t rhport) {
ep0_pending[TUSB_DIR_OUT] = 0;
}
}
- }
break;
+ }
- // Out packet done (Interrupt)
case GRXSTS_PKTSTS_OUTDONE:
- // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a
- // May (or not) be 3.10a specific feature/bug or depending on MCU configuration
- // XFRC complete is additionally generated when
- // - setup packet is received
- // - complete the data stage of control write is complete
- if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
- uint32_t doepint = epout->doepint;
-
- if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) {
- // skip this "no-data" transfer complete event
- // Note: STPKTRX will be clear later by setup received handler
- uint32_t clear_flags = DOEPINT_XFRC;
-
- if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR;
-
- epout->doepint = clear_flags;
-
- // TU_LOG(DWC2_DEBUG, " FIX extra transfer complete on setup/data compete\r\n");
- }
- }
+ /* Out packet done
+ After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on
+ the specified OUT endpoint which will be handled by handle_epout_irq() */
break;
- default: // Invalid
+ default:
TU_BREAKPOINT();
break;
}
@@ -985,37 +1022,68 @@ static void handle_epout_irq(uint8_t rhport) {
// DAINT for a given EP clears when DOEPINTx is cleared.
// OEPINT will be cleared when DAINT's out bits are cleared.
- for (uint8_t n = 0; n < ep_count; n++) {
- if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n)) {
- dwc2_epout_t* epout = &dwc2->epout[n];
+ for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
+ if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + epnum)) {
+ dwc2_epout_t* epout = &dwc2->epout[epnum];
+ const uint32_t doepint = epout->doepint;
+ TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, );
+
+ // Setup and/or STPKTRX/STSPHSRX (from 3.00a) can be set along with XFRC, and also set independently.
+ if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) {
+ if (doepint & DOEPINT_STSPHSRX) {
+ // Status phase received for control write: In token received from Host
+ epout->doepint = DOEPINT_STSPHSRX;
+ }
- uint32_t const doepint = epout->doepint;
+ if (doepint & DOEPINT_STPKTRX) {
+ // New setup packet received, but wait for Setup done, since we can receive up to 3 setup consecutively
+ epout->doepint = DOEPINT_STPKTRX;
+ }
+ }
- // SETUP packet Setup Phase done.
- if (doepint & DOEPINT_STUP) {
- uint32_t clear_flag = DOEPINT_STUP;
+ if (doepint & DOEPINT_SETUP) {
+ epout->doepint = DOEPINT_SETUP;
- // STPKTRX is only available for version from 3_00a
- if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
- clear_flag |= DOEPINT_STPKTRX;
+ if(dma_enabled(dwc2)) {
+ dma_setup_prepare(rhport);
}
- epout->doepint = clear_flag;
dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
}
// OUT XFER complete
- if (epout->doepint & DOEPINT_XFRC) {
+ if (doepint & DOEPINT_XFRC) {
epout->doepint = DOEPINT_XFRC;
- xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
- // EP0 can only handle one packet
- if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
- // Schedule another packet to be received.
- edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
- } else {
- dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ // only handle data skip if it is setup or status related
+ // Normal OUT transfer complete
+ if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) {
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+
+ if(dma_enabled(dwc2)) {
+ if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ // EP0 can only handle one packet Schedule another packet to be received.
+ edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
+ } else {
+ // Fix packet length
+ uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
+ xfer->total_len -= remain;
+ // this is ZLP, so prepare EP0 for next setup
+ if(epnum == 0 && xfer->total_len == 0) {
+ dma_setup_prepare(rhport);
+ }
+
+ dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ }
+ } else {
+ // EP0 can only handle one packet
+ if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ // Schedule another packet to be received.
+ edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
+ } else {
+ dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ }
+ }
}
}
}
@@ -1042,6 +1110,9 @@ static void handle_epin_irq(uint8_t rhport) {
// Schedule another packet to be transmitted.
edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
} else {
+ if((n == 0) && dma_enabled(dwc2)) {
+ dma_setup_prepare(rhport);
+ }
dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
}
}
@@ -1071,7 +1142,7 @@ static void handle_epin_irq(uint8_t rhport) {
volatile uint32_t* tx_fifo = dwc2->fifo[n];
tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
} else {
- write_fifo_packet(rhport, n, xfer->buffer, packet_size);
+ dfifo_write_packet(rhport, n, xfer->buffer, packet_size);
// Increment pointer to xfer data
xfer->buffer += packet_size;
@@ -1087,6 +1158,29 @@ static void handle_epin_irq(uint8_t rhport) {
}
}
+/* Interrupt Hierarchy
+
+ DxEPMSK.XferComplMsk DxEPINTn.XferCompl
+ | |
+ +---------- AND --------+
+ |
+ DAINT.xEPnInt DAINTMSK.xEPnMsk
+ | |
+ +---------- AND --------+
+ |
+ GINTSTS.xEPInt GINTMSK.xEPIntMsk
+ | |
+ +---------- AND --------+
+ |
+ GAHBCFG.GblIntrMsk
+ |
+ IRQn
+
+ Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk
+ are combined to generate dedicated interrupt line for each endpoint.
+ */
+
+
void dcd_int_handler(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
@@ -1164,13 +1258,10 @@ void dcd_int_handler(uint8_t rhport) {
// RxFIFO non-empty interrupt handling.
if (int_status & GINTSTS_RXFLVL) {
// RXFLVL bit is read-only
+ dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading
- // Mask out RXFLVL while reading data from FIFO
- dwc2->gintmsk &= ~GINTMSK_RXFLVLM;
-
- // Loop until all available packets were handled
do {
- handle_rxflvl_irq(rhport);
+ handle_rxflvl_irq(rhport); // read all packets
} while(dwc2->gintsts & GINTSTS_RXFLVL);
dwc2->gintmsk |= GINTMSK_RXFLVLM;
@@ -1195,4 +1286,13 @@ void dcd_int_handler(uint8_t rhport) {
// }
}
+#if CFG_TUD_TEST_MODE
+void dcd_enter_test_mode(uint8_t rhport, tusb_feature_test_mode_t test_selector) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ // Enable the test mode
+ dwc2->dctl = (dwc2->dctl & ~DCTL_TCTL_Msk) | (((uint8_t) test_selector) << DCTL_TCTL_Pos);
+}
+#endif
+
#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index 732d96ae09..e5824606ad 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -39,7 +39,7 @@
static const dwc2_controller_t _dwc2_controller[] =
{
- { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 4096 }
+ { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 16384 }
};
#define dcache_clean(_addr, _size) data_clean(_addr, _size)
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index c50dd66b89..4cdbcdb7a0 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -32,60 +32,64 @@
extern "C" {
#endif
+#include "freertos/task.h"
+
#include "esp_intr_alloc.h"
#include "soc/periph_defs.h"
-//#include "soc/usb_periph.h"
+#include "soc/usb_wrap_struct.h"
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#define DWC2_FS_REG_BASE 0x60080000UL
+#define DWC2_EP_MAX 7
+
+static const dwc2_controller_t _dwc2_controller[] = {
+ { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }
+};
-#define DWC2_REG_BASE 0x60080000UL
-#define DWC2_EP_MAX 6 // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN)
+#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
+#define DWC2_FS_REG_BASE 0x50040000UL
+#define DWC2_HS_REG_BASE 0x50000000UL
+#define DWC2_EP_MAX 16
-static const dwc2_controller_t _dwc2_controller[] =
-{
- { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 }
+// On ESP32 for consistency we associate
+// - Port0 to OTG_FS, and Port1 to OTG_HS
+static const dwc2_controller_t _dwc2_controller[] = {
+{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
+{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
};
+#endif
-static intr_handle_t usb_ih;
+static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)];
-static void dcd_int_handler_wrap(void* arg)
-{
- (void) arg;
- dcd_int_handler(0);
+static void dcd_int_handler_wrap(void* arg) {
+ const uint8_t rhport = (uint8_t)(uintptr_t) arg;
+ dcd_int_handler(rhport);
}
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_enable (uint8_t rhport)
-{
- (void) rhport;
- esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih);
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
+ esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED,
+ dcd_int_handler_wrap, (void*)(uintptr_t) rhport, &usb_ih[rhport]);
}
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_disable (uint8_t rhport)
-{
- (void) rhport;
- esp_intr_free(usb_ih);
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
+ esp_intr_free(usb_ih[rhport]);
}
-static inline void dwc2_remote_wakeup_delay(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
vTaskDelay(pdMS_TO_TICKS(1));
}
// MCU specific PHY init, called BEFORE core reset
-static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
-{
- (void) dwc2;
- (void) hs_phy_type;
-
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+ (void)dwc2;
+ (void)hs_phy_type;
// nothing to do
}
// MCU specific PHY update, it is called AFTER init() and core reset
-static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
-{
- (void) dwc2;
- (void) hs_phy_type;
-
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+ (void)dwc2;
+ (void)hs_phy_type;
// nothing to do
}
@@ -93,4 +97,4 @@ static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
}
#endif
-#endif /* _DWC2_ESP32_H_ */
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
index 8690a07558..cfd0c81a89 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.md
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -1,55 +1,58 @@
-| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F429 Fullspeed | STM32F429 Highspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 |
-|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
-| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00001200 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
-| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
-| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 2.81a | 3.20a | 2.81a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a |
-| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
-| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
-| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |
-| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 |
-| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
-| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 |
-| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
-| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 |
-| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 |
-| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
-| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
-| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
-| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
-| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
-| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
-| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
-| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
-| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
-| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
-| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
-| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
-| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
-| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
-| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
-| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 |
-| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
-| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
-| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
-| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 |
-| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
-| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
-| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
-| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
-| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 |
-| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
-| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
-| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
-| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
-| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
-| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 |
-| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
-| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
+| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/767 FS | ST F723/L4P5 FS | ST F723 HS | ST F769 | ST H743/H750 | ST L476 FS | ST U5A5 HS | GD32VF103 | XMC4500 |
+|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:------------|:-------------|
+| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 |
+| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A |
+| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a |
+| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
+| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 |
+| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP |
+| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal |
+| - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
+| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a |
+| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated |
+| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 |
+| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 |
+| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
+| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
+| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 |
+| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 |
+| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 |
+| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 |
+| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 |
+| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
+| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
+| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
+| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
+| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
+| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 0 | 634 |
+| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 |
+| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
+| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit |
+| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 |
+| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
+| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
old mode 100644
new mode 100755
index 55bec3d233..d1793a0058
--- a/src/portable/synopsys/dwc2/dwc2_info.py
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -1,38 +1,41 @@
-import click
+#!/usr/bin/env python3
+
import ctypes
+import argparse
+import click
import pandas as pd
# hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
-dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4']
+# Note: FS is FullSpeed, HS is HighSpeed
+dwc2_reg_list = ['GUID', 'GSNPSID', 'GHWCFG1', 'GHWCFG2', 'GHWCFG3', 'GHWCFG4']
dwc2_reg_value = {
'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020],
- 'EFM32GG FullSpeed': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030],
- 'ESP32-S2': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030],
- 'STM32F407 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
- 'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
- 'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
- 'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
- 'STM32F429 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
- 'STM32F429 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
- 'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
- 'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030],
- 'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
- 'STM32H743 Highspeed': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores
- 'STM32L476 Fullspeed': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
- 'STM32U5A5 Highspeed': [0x00005000, 0x4F54411A, 0x00000000, 0x228FE052, 0x03B882E8, 0xE2103E30],
- 'GD32VF103 Fullspeed': [0x1000, 0, 0, 0, 0, 0],
- 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030]
+ 'EFM32GG': [0, 0x4F54330A, 0, 0x228F5910, 0x01F204E8, 0x1BF08030],
+ 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030],
+ 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030],
+ 'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030],
+ 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030],
+ 'ST F412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+ 'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+ 'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030],
+ 'ST F769': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030],
+ 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030],
+ 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030],
+ 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30],
+ 'GD32VF103': [0x1000, 0, 0, 0, 0, 0],
+ 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030]
+
}
# Combine dwc2_info with dwc2_reg_list
# dwc2_info = {
# 'BCM2711 (Pi4)': {
-# 'guid': 0x2708A000,
-# 'gsnpsid': 0x4F54280A,
-# 'ghwcfg1': 0,
-# 'ghwcfg2': 0x228DDD50,
-# 'ghwcfg3': 0xFF000E8,
-# 'ghwcfg4': 0x1FF00020
+# 'GUID': 0x2708A000,
+# 'GSNPSID': 0x4F54280A,
+# 'GHWCFG1': 0,
+# 'GHWCFG2': 0x228DDD50,
+# 'GHWCFG3': 0xFF000E8,
+# 'GHWCFG4': 0x1FF00020
# },
dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()}
@@ -41,18 +44,18 @@ class GHWCFG2(ctypes.LittleEndianStructure):
_fields_ = [
("op_mode", ctypes.c_uint32, 3),
("arch", ctypes.c_uint32, 2),
- ("point2point", ctypes.c_uint32, 1),
+ ("p2p (hub support)", ctypes.c_uint32, 1),
("hs_phy_type", ctypes.c_uint32, 2),
("fs_phy_type", ctypes.c_uint32, 2),
("num_dev_ep", ctypes.c_uint32, 4),
("num_host_ch", ctypes.c_uint32, 4),
("period_channel_support", ctypes.c_uint32, 1),
("enable_dynamic_fifo", ctypes.c_uint32, 1),
- ("mul_cpu_int", ctypes.c_uint32, 1),
+ ("mul_proc_intrpt", ctypes.c_uint32, 1),
("reserved21", ctypes.c_uint32, 1),
- ("nperiod_tx_q_depth", ctypes.c_uint32, 2),
- ("host_period_tx_q_depth", ctypes.c_uint32, 2),
- ("dev_token_q_depth", ctypes.c_uint32, 5),
+ ("nptx_q_depth", ctypes.c_uint32, 2),
+ ("ptx_q_depth", ctypes.c_uint32, 2),
+ ("token_q_depth", ctypes.c_uint32, 5),
("otg_enable_ic_usb", ctypes.c_uint32, 1)
]
@@ -70,90 +73,114 @@ class GHWCFG3(ctypes.LittleEndianStructure):
("otg_enable_hsic", ctypes.c_uint32, 1),
("battery_charger_support", ctypes.c_uint32, 1),
("lpm_mode", ctypes.c_uint32, 1),
- ("total_fifo_size", ctypes.c_uint32, 16)
+ ("dfifo_depth", ctypes.c_uint32, 16)
]
class GHWCFG4(ctypes.LittleEndianStructure):
_fields_ = [
("num_dev_period_in_ep", ctypes.c_uint32, 4),
- ("power_optimized", ctypes.c_uint32, 1),
+ ("partial_powerdown", ctypes.c_uint32, 1),
("ahb_freq_min", ctypes.c_uint32, 1),
("hibernation", ctypes.c_uint32, 1),
- ("reserved7", ctypes.c_uint32, 3),
- ("service_interval_mode", ctypes.c_uint32, 1),
- ("ipg_isoc_en", ctypes.c_uint32, 1),
- ("acg_enable", ctypes.c_uint32, 1),
- ("reserved13", ctypes.c_uint32, 1),
- ("utmi_phy_data_width", ctypes.c_uint32, 2),
- ("dev_ctrl_ep_num", ctypes.c_uint32, 4),
- ("iddg_filter_enabled", ctypes.c_uint32, 1),
- ("vbus_valid_filter_enabled", ctypes.c_uint32, 1),
- ("a_valid_filter_enabled", ctypes.c_uint32, 1),
- ("b_valid_filter_enabled", ctypes.c_uint32, 1),
+ ("extended_hibernation", ctypes.c_uint32, 1),
+ ("reserved8", ctypes.c_uint32, 1),
+ ("enhanced_lpm_support1", ctypes.c_uint32, 1),
+ ("service_interval_flow", ctypes.c_uint32, 1),
+ ("ipg_isoc_support", ctypes.c_uint32, 1),
+ ("acg_support", ctypes.c_uint32, 1),
+ ("enhanced_lpm_support", ctypes.c_uint32, 1),
+ ("phy_data_width", ctypes.c_uint32, 2),
+ ("ctrl_ep_num", ctypes.c_uint32, 4),
+ ("iddg_filter", ctypes.c_uint32, 1),
+ ("vbus_valid_filter", ctypes.c_uint32, 1),
+ ("a_valid_filter", ctypes.c_uint32, 1),
+ ("b_valid_filter", ctypes.c_uint32, 1),
+ ("session_end_filter", ctypes.c_uint32, 1),
("dedicated_fifos", ctypes.c_uint32, 1),
("num_dev_in_eps", ctypes.c_uint32, 4),
("dma_desc_enable", ctypes.c_uint32, 1),
- ("dma_dynamic", ctypes.c_uint32, 1)
+ ("dma_desc_dynamic", ctypes.c_uint32, 1)
]
+# mapping for specific fields in GHWCFG2
+GHWCFG2_field = {
+ 'op_mode': {
+ 0: "HNP SRP",
+ 1: "SRP",
+ 2: "noHNP noSRP",
+ 3: "SRP Device",
+ 4: "noOTG Device",
+ 5: "SRP Host",
+ 6: "noOTG Host"
+ },
+ 'arch': {
+ 0: "Slave only",
+ 1: "DMA external",
+ 2: "DMA internal"
+ },
+ 'hs_phy_type': {
+ 0: "n/a",
+ 1: "UTMI+",
+ 2: "ULPI",
+ 3: "UTMI+/ULPI"
+ },
+ 'fs_phy_type': {
+ 0: "n/a",
+ 1: "Dedicated",
+ 2: "Shared UTMI+",
+ 3: "Shared ULPI"
+ }
+}
-@click.group()
-def cli():
- pass
-
-
-@cli.command()
-@click.argument('mcus', nargs=-1)
-@click.option('-a', '--all', is_flag=True, help='Print all bit-field values')
-def info(mcus, all):
- """Print DWC2 register values for given MCU(s)"""
- if len(mcus) == 0:
- mcus = dwc2_info
-
- for mcu in mcus:
- for entry in dwc2_info:
- if mcu.lower() in entry.lower():
- print(f"## {entry}")
- for r_name, r_value in dwc2_info[entry].items():
- print(f"{r_name} = 0x{r_value:08X}")
- # Print bit-field values
- if all and r_name.upper() in globals():
- class_name = globals()[r_name.upper()]
- ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
- for field_name, field_type, _ in class_name._fields_:
- print(f" {field_name} = {getattr(ghwcfg, field_name)}")
+# mapping for specific fields in GHWCFG4
+GHWCFG4_field = {
+ 'phy_data_width': {
+ 0: "8 bit",
+ 1: "16 bit",
+ 2: "8/16 bit",
+ 3: "Reserved"
+ },
+ }
+
+def main():
+ """Render dwc2_info to Markdown table"""
+ parser = argparse.ArgumentParser()
+ args = parser.parse_args()
-@cli.command()
-def render_md():
- """Render dwc2_info to Markdown table"""
# Create an empty list to hold the dictionaries
- dwc2_info_list = []
+ md_table = []
# Iterate over the dwc2_info dictionary and extract fields
for device, reg_values in dwc2_info.items():
- entry_dict = {"Device": device}
+ md_item = {"Device": device}
for r_name, r_value in reg_values.items():
- entry_dict[r_name] = f"0x{r_value:08X}"
+ md_item[r_name] = f"0x{r_value:08X}"
- if r_name == 'gsnpsid':
+ if r_name == 'GSNPSID':
# Get dwc2 specs version
major = ((r_value >> 8) >> 4) & 0x0F
minor = (r_value >> 4) & 0xFF
patch = chr((r_value & 0x0F) + ord('a') - 0xA)
- entry_dict[f' - specs version'] = f"{major:X}.{minor:02X}{patch}"
- elif r_name.upper() in globals():
+ md_item[f' - specs version'] = f"{major:X}.{minor:02X}{patch}"
+ elif r_name in globals():
# Get bit-field values which exist as ctypes structures
- class_name = globals()[r_name.upper()]
- ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
- for field_name, field_type, _ in class_name._fields_:
- entry_dict[f' - {field_name}'] = getattr(ghwcfg, field_name)
+ class_hdl = globals()[r_name]
+ ghwcfg = class_hdl.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
+ for field_name, field_type, _ in class_hdl._fields_:
+ field_value = getattr(ghwcfg, field_name)
+ if class_hdl == GHWCFG2 and field_name in GHWCFG2_field:
+ field_value = GHWCFG2_field[field_name].get(field_value, f"Unknown ({field_value})")
+ if class_hdl == GHWCFG4 and field_name in GHWCFG4_field:
+ field_value = GHWCFG4_field[field_name].get(field_value, f"Unknown ({field_value})")
+
+ md_item[f' - {field_name}'] = field_value
- dwc2_info_list.append(entry_dict)
+ md_table.append(md_item)
# Create a Pandas DataFrame from the list of dictionaries
- df = pd.DataFrame(dwc2_info_list).set_index('Device')
+ df = pd.DataFrame(md_table).set_index('Device')
# Transpose the DataFrame to switch rows and columns
df = df.T
@@ -166,4 +193,4 @@ def render_md():
if __name__ == '__main__':
- cli()
+ main()
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 3237a50f63..395b6d8704 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -142,7 +142,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
// - dwc2 3.30a (H5) use USB_HS_PHYC
// - dwc2 4.11a (U5) use femtoPHY
static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
- if (hs_phy_type == HS_PHY_TYPE_NONE) {
+ if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
// Enable on-chip FS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
@@ -175,7 +175,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
#endif
// Enable on-chip HS PHY
- if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
+ if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
#ifdef USB_HS_PHYC
// Enable UTMI HS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
@@ -218,7 +218,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
// MCU specific PHY update, it is called AFTER init() and core reset
static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
// used to set turnaround time for fullspeed, nothing to do in highspeed mode
- if (hs_phy_type == HS_PHY_TYPE_NONE) {
+ if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
// Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
uint32_t turnaround;
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index c157712378..cf05bbfecf 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -1,17 +1,34 @@
-/**
- * @author MCD Application Team
- * Ha Thach (tinyusb.org)
- *
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+/** © Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- *
*/
#ifndef _TUSB_DWC2_TYPES_H_
@@ -29,6 +46,7 @@ typedef struct
uintptr_t reg_base;
uint32_t irqnum;
uint8_t ep_count;
+ uint8_t ep_in_count;
uint32_t ep_fifo_size;
}dwc2_controller_t;
@@ -69,86 +87,222 @@ typedef struct
#endif
enum {
- HS_PHY_TYPE_NONE = 0 , // not supported
- HS_PHY_TYPE_UTMI , // internal PHY (mostly)
- HS_PHY_TYPE_ULPI , // external PHY
- HS_PHY_TYPE_UTMI_ULPI ,
+ GHWCFG2_OPMODE_HNP_SRP = 0,
+ GHWCFG2_OPMODE_SRP = 1,
+ GHWCFG2_OPMODE_NON_HNP_NON_SRP = 2,
+ GHWCFG2_OPMODE_SRP_DEVICE = 3,
+ GHWCFFG2_OPMODE_NON_OTG_DEVICE = 4,
+ GHWCFG2_OPMODE_SRP_HOST = 5,
+ GHWCFG2_OPMODE_NON_OTG_HOST = 6,
+};
+enum {
+ GHWCFG2_ARCH_SLAVE_ONLY = 0,
+ GHWCFG2_ARCH_EXTERNAL_DMA = 1,
+ GHWCFG2_ARCH_INTERNAL_DMA = 2,
};
enum {
- FS_PHY_TYPE_NONE = 0, // not supported
- FS_PHY_TYPE_DEDICATED,
- FS_PHY_TYPE_UTMI,
- FS_PHY_TYPE_ULPI,
+ GHWCFG2_HSPHY_NOT_SUPPORTED = 0,
+ GHWCFG2_HSPHY_UTMI = 1, // internal PHY (mostly)
+ GHWCFG2_HSPHY_ULPI = 2, // external PHY (mostly)
+ GHWCFG2_HSPHY_UTMI_ULPI = 3, // both
+
};
-typedef struct TU_ATTR_PACKED
-{
- uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
- uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others
- uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split
- uint32_t hs_phy_type : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
- uint32_t fs_phy_type : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
- uint32_t num_dev_ep : 4; // Number of device endpoints (not including EP0)
- uint32_t num_host_ch : 4; // Number of host channel
- uint32_t period_channel_support : 1; // Support Periodic OUT Host Channel
- uint32_t enable_dynamic_fifo : 1; // Dynamic FIFO Sizing Enabled
- uint32_t mul_cpu_int : 1; // Multi-Processor Interrupt Enabled
- uint32_t reserved21 : 1;
- uint32_t nperiod_tx_q_depth : 2; // Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
- uint32_t host_period_tx_q_depth : 2; // Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
- uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30
- uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation
-} dwc2_ghwcfg2_t;
+enum {
+ GHWCFG2_FSPHY_NOT_SUPPORTED = 0,
+ GHWCFG2_FSPHY_DEDICATED = 1, // have dedicated FS PHY
+ GHWCFG2_FSPHY_UTMI = 2, // shared with UTMI+
+ GHWCFG2_FSPHY_ULPI = 3, // shared with ULPI
+};
+enum {
+ GHWCFFG4_PHY_DATA_WIDTH_8 = 0,
+ GHWCFFG4_PHY_DATA_WIDTH_16 = 1,
+ GHWCFFG4_PHY_DATA_WIDTH_8_16 = 2, // software selectable
+};
+
+//--------------------------------------------------------------------
+// Register bitfield definitions
+//--------------------------------------------------------------------
+typedef struct TU_ATTR_PACKED {
+ uint32_t ses_req_scs : 1; // 0 Session request success
+ uint32_t ses_req : 1; // 1 Session request
+ uint32_t vbval_ov_en : 1; // 2 VBUS valid override enable
+ uint32_t vbval_ov_val : 1; // 3 VBUS valid override value
+ uint32_t aval_ov_en : 1; // 4 A-peripheral session valid override enable
+ uint32_t aval_ov_al : 1; // 5 A-peripheral session valid override value
+ uint32_t bval_ov_en : 1; // 6 B-peripheral session valid override enable
+ uint32_t bval_ov_val : 1; // 7 B-peripheral session valid override value
+ uint32_t hng_scs : 1; // 8 Host negotiation success
+ uint32_t hnp_rq : 1; // 9 HNP (host negotiation protocol) request
+ uint32_t host_set_hnp_en : 1; // 10 Host set HNP enable
+ uint32_t dev_hnp_en : 1; // 11 Device HNP enabled
+ uint32_t embedded_host_en : 1; // 12 Embedded host enable
+ uint32_t rsv13_14 : 2; // 13.14 Reserved
+ uint32_t dbnc_filter_bypass : 1; // 15 Debounce filter bypass
+ uint32_t cid_status : 1; // 16 Connector ID status
+ uint32_t dbnc_done : 1; // 17 Debounce done
+ uint32_t ases_valid : 1; // 18 A-session valid
+ uint32_t bses_valid : 1; // 19 B-session valid
+ uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0
+ uint32_t current_mode : 1; // 21 Current mode of operation 0: device, 1: host
+ uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger
+ uint32_t chirp_en : 1; // 27 Chirp detection enable
+ uint32_t rsv28_30 : 3; // 28.30: Reserved
+ uint32_t test_mode_corr_eusb2 : 1; // 31 Test mode control for eUSB2 PHY
+} dwc2_gotgctl_t;
+TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+ uint32_t rsv0_1 : 2; // 0..1 Reserved
+ uint32_t ses_end_det : 1; // 2 Session end detected
+ uint32_t rsv3_7 : 5; // 3..7 Reserved
+ uint32_t srs_status_change : 1; // 8 Session request success status change
+ uint32_t hns_status_change : 1; // 9 Host negotiation success status change
+ uint32_t rsv10_16 : 7; // 10..16 Reserved
+ uint32_t hng_det : 1; // 17 Host negotiation detected
+ uint32_t adev_timeout_change : 1; // 18 A-device timeout change
+ uint32_t dbnc_done : 1; // 19 Debounce done
+ uint32_t mult_val_lp_change : 1; // 20 Multi-valued input pin change
+ uint32_t rsv21_31 :11; // 21..31 Reserved
+} dwc2_gotgint_t;
+TU_VERIFY_STATIC(sizeof(dwc2_gotgint_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+ uint32_t gintmask : 1; // 0 Global interrupt mask
+ uint32_t hbst_len : 4; // 1..4 Burst length/type
+ uint32_t dma_en : 1; // 5 DMA enable
+ uint32_t rsv6 : 1; // 6 Reserved
+ uint32_t nptxf_empty_lvl : 1; // 7 Non-periodic Tx FIFO empty level
+ uint32_t ptxf_empty_lvl : 1; // 8 Periodic Tx FIFO empty level
+ uint32_t rsv9_20 : 12; // 9.20: Reserved
+ uint32_t remote_mem_support : 1; // 21 Remote memory support
+ uint32_t notify_all_dma_write : 1; // 22 Notify all DMA writes
+ uint32_t ahb_single : 1; // 23 AHB single
+ uint32_t inv_desc_endian : 1; // 24 Inverse descriptor endian
+ uint32_t rsv25_31 : 7; // 25..31 Reserved
+} dwc2_gahbcfg_t;
+TU_VERIFY_STATIC(sizeof(dwc2_gahbcfg_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+ uint32_t timeout_cal : 3; /* 0..2 Timeout calibration.
+ The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard
+ timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field
+ based on the speed of enumeration. The number of bit times added per PHY clock are as follows:
+ - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times
+ - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */
+ uint32_t phy_if : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits
+ uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI
+ uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin
+ uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver
+ uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit
+ uint32_t srp_capable : 1; // 8 SRP-capable
+ uint32_t hnp_capable : 1; // 9 HNP-capable
+ uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+
+ uint32_t rsv14 : 1; // 14 Reserved
+ uint32_t phy_low_power_clk_sel : 1; /* 15 PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode.
+ In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs.
+ - 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit)
+ - 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */
+ uint32_t otg_i2c_sel : 1; // 16 OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals
+ uint32_t ulpi_fsls : 1; /* 17 ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS.
+ valid only when the FS serial transceiver is selected on the ULPI PHY. */
+ uint32_t ulpi_auto_resume : 1; // 18 ULPI Auto-resume
+ uint32_t ulpi_clk_sus_m : 1; // 19 ULPI Clock SuspendM
+ uint32_t ulpi_ext_vbus_drv : 1; // 20 ULPI External VBUS Drive
+ uint32_t ulpi_int_vbus_indicator : 1; // 21 ULPI Internal VBUS Indicator
+ uint32_t term_sel_dl_pulse : 1; // 22 TermSel DLine pulsing
+ uint32_t indicator_complement : 1; // 23 Indicator complement
+ uint32_t indicator_pass_through : 1; // 24 Indicator pass through
+ uint32_t ulpi_if_protect_disable : 1; // 25 ULPI interface protect disable
+ uint32_t ic_usb_capable : 1; // 26 IC_USB Capable
+ uint32_t ic_usb_traf_ctl : 1; // 27 IC_USB Traffic Control
+ uint32_t tx_end_delay : 1; // 28 TX end delay
+ uint32_t force_host_mode : 1; // 29 Force host mode
+ uint32_t force_dev_mode : 1; // 30 Force device mode
+ uint32_t corrupt_tx_pkt : 1; // 31 Corrupt Tx packet. 0: normal, 1: debug
+} dwc2_gusbcfg_t;
+TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+ uint32_t core_soft_rst : 1; // 0 Core Soft Reset
+ uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset
+ uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host)
+ uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush
+ uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush
+ uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush
+ uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number
+ uint32_t rsv11_28 :18; // 11..28 Reserved
+ uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a
+ uint32_t dma_req : 1; // 30 DMA Request
+ uint32_t ahb_idle : 1; // 31 AHB Idle
+} dwc2_grstctl_t;
+TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED {
+ uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode
+ uint32_t arch : 2; // 3..4 Slave/External/Internal DMA
+ uint32_t point2point : 1; // 5 0: support hub and split | 1: no hub, no split
+ uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
+ uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
+ uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0)
+ uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control)
+ uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel
+ uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled
+ uint32_t mul_proc_intrpt : 1; // 20 Multi-Processor Interrupt enabled (OTG_MULTI_PROC_INTRPT)
+ uint32_t reserved21 : 1; // 21 reserved
+ uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
+ uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
+ uint32_t token_q_depth : 5; // 26..30 Device IN token sequence learning queue depth: 0-30
+ uint32_t otg_enable_ic_usb : 1; // 31 IC_USB mode specified for mode of operation
+} dwc2_ghwcfg2_t;
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
-typedef struct TU_ATTR_PACKED
-{
- uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits)
- uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits)
- uint32_t otg_enable : 1; // 1 is OTG capable
- uint32_t i2c_enable : 1; // I2C interface is available
- uint32_t vendor_ctrl_itf : 1; // Vendor control interface is available
- uint32_t optional_feature_removed : 1; // remove User ID, GPIO, SOF toggle & counter
- uint32_t synch_reset : 1; // 0: async reset | 1: synch reset
- uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller
- uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
- uint32_t battery_charger_support : 1; // support battery charger
- uint32_t lpm_mode : 1; // LPC mode
- uint32_t total_fifo_size : 16; // DFIFO depth value in terms of 32-bit words
+typedef struct TU_ATTR_PACKED {
+ uint32_t xfer_size_width : 4; // 0..3 Transfer size counter in bits = 11 + n (max 19 bits)
+ uint32_t packet_size_width : 3; // 4..6 Packet size counter in bits = 4 + n (max 10 bits)
+ uint32_t otg_enable : 1; // 7 OTG capable
+ uint32_t i2c_enable : 1; // 8 I2C interface is available
+ uint32_t vendor_ctrl_itf : 1; // 9 Vendor control interface is available
+ uint32_t optional_feature_removed : 1; // 10 remove User ID, GPIO, SOF toggle & counter to save gate count
+ uint32_t synch_reset : 1; // 11 0: async reset | 1: synch reset
+ uint32_t otg_adp_support : 1; // 12 ADP logic is present along with HSOTG controller
+ uint32_t otg_enable_hsic : 1; // 13 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
+ uint32_t battery_charger_support : 1; // s14 upport battery charger
+ uint32_t lpm_mode : 1; // 15 LPM mode
+ uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words
}dwc2_ghwcfg3_t;
-
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
-typedef struct TU_ATTR_PACKED
-{
- uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints
- uint32_t power_optimized : 1; // Partial Power Down Enabled
- uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz
- uint32_t hibernation : 1; // Hibernation feature is enabled
- uint32_t reserved7 : 3;
- uint32_t service_interval_mode : 1; // Service Interval supported
- uint32_t ipg_isoc_en : 1; // IPG ISOC supported
- uint32_t acg_enable : 1; // ACG enabled
- uint32_t reserved13 : 1;
- uint32_t utmi_phy_data_width : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
- uint32_t dev_ctrl_ep_num : 4; // Number of Device control endpoints in addition to EP0
- uint32_t iddg_filter_enabled : 1;
- uint32_t vbus_valid_filter_enabled : 1;
- uint32_t a_valid_filter_enabled : 1;
- uint32_t b_valid_filter_enabled : 1;
- uint32_t dedicated_fifos : 1; // Dedicated tx fifo for device IN Endpoint is enabled
- uint32_t num_dev_in_eps : 4; // Number of Device IN Endpoints including EP0
- uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration
- uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA
+typedef struct TU_ATTR_PACKED {
+ uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints
+ uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled
+ uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz
+ uint32_t hibernation : 1; // 6 Hibernation feature is enabled
+ uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled
+ uint32_t reserved8 : 1; // 8 Reserved
+ uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1
+ uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported
+ uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported
+ uint32_t acg_support : 1; // 12 Active clock gating is supported
+ uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support
+ uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
+ uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0
+ uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled
+ uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled
+ uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled
+ uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled
+ uint32_t session_end_filter : 1; // 24 Session End Filter Enabled
+ uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint
+ uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0
+ uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled
+ uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA
}dwc2_ghwcfg4_t;
-
TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
// Host Channel
-typedef struct
-{
+typedef struct {
volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics
volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control
volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt
@@ -160,8 +314,7 @@ typedef struct
} dwc2_channel_t;
// Endpoint IN
-typedef struct
-{
+typedef struct {
volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control
uint32_t reserved04; // 904
volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt
@@ -173,8 +326,7 @@ typedef struct
} dwc2_epin_t;
// Endpoint OUT
-typedef struct
-{
+typedef struct {
volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control
uint32_t reserved04; // B04
volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt
@@ -184,105 +336,141 @@ typedef struct
uint32_t reserved18[2]; // B18..B1C
} dwc2_epout_t;
-typedef struct
-{
- //------------- Core Global -------------//
- volatile uint32_t gotgctl; // 000 OTG Control and Status
- volatile uint32_t gotgint; // 004 OTG Interrupt
- volatile uint32_t gahbcfg; // 008 AHB Configuration
- volatile uint32_t gusbcfg; // 00c USB Configuration
- volatile uint32_t grstctl; // 010 Reset
- volatile uint32_t gintsts; // 014 Interrupt
- volatile uint32_t gintmsk; // 018 Interrupt Mask
- volatile uint32_t grxstsr; // 01c Receive Status Debug Read
- volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
- volatile uint32_t grxfsiz; // 024 Receive FIFO Size
-union {
- volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
- volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
-};
- volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
- volatile uint32_t gi2cctl; // 030 I2C Address
- volatile uint32_t gpvndctl; // 034 PHY Vendor Control
-union {
- volatile uint32_t ggpio; // 038 General Purpose IO
- volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
-};
- volatile uint32_t guid; // 03C User (Application programmable) ID
- volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
- volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
-union {
- volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
- dwc2_ghwcfg2_t ghwcfg2_bm;
-};
-union {
- volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
- dwc2_ghwcfg3_t ghwcfg3_bm;
-};
-union {
- volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
- dwc2_ghwcfg4_t ghwcfg4_bm;
-};
- volatile uint32_t glpmcfg; // 054 Core LPM Configuration
- volatile uint32_t gpwrdn; // 058 Power Down
- volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
- volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status
- uint32_t reserved64[39]; // 064..0FF
- volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size
- volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
- uint32_t reserved140[176]; // 140..3FF
-
- //------------- Host -------------//
- volatile uint32_t hcfg; // 400 Host Configuration
- volatile uint32_t hfir; // 404 Host Frame Interval
- volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
- uint32_t reserved40c; // 40C
- volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status
- volatile uint32_t haint; // 414 Host All Channels Interrupt
- volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask
- volatile uint32_t hflbaddr; // 41C Host Frame List Base Address
- uint32_t reserved420[8]; // 420..43F
- volatile uint32_t hprt; // 440 Host Port Control and Status
- uint32_t reserved444[47]; // 444..4FF
-
- //------------- Host Channel -------------//
- dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15
- uint32_t reserved700[64]; // 700..7FF
-
- //------------- Device -------------//
- volatile uint32_t dcfg; // 800 Device Configuration
- volatile uint32_t dctl; // 804 Device Control
- volatile uint32_t dsts; // 808 Device Status (RO)
- uint32_t reserved80c; // 80C
- volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask
- volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask
- volatile uint32_t daint; // 818 Device All Endpoints Interrupt
- volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask
- volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1
- volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2
- volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time
- volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time
- volatile uint32_t dthrctl; // 830 Device threshold Control
- volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask
- volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt
- volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk
- volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
- volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask
- uint32_t reserved8c0[16]; // 8C0..8FF
-
- //------------- Device Endpoint -------------//
- dwc2_epin_t epin[16]; // 900..AFF IN Endpoints
- dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints
- uint32_t reservedd00[64]; // D00..DFF
-
- //------------- Power Clock -------------//
- volatile uint32_t pcgctl; // E00 Power and Clock Gating Control
- volatile uint32_t pcgctl1; // E04
- uint32_t reservede08[126]; // E08..FFF
-
- //------------- FIFOs -------------//
- // Word-accessed only using first pointer since it auto shift
- volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO
+typedef struct {
+ union {
+ volatile uint32_t diepctl;
+ volatile uint32_t doepctl;
+ volatile uint32_t ctl;
+ };
+ uint32_t rsv04;
+ union {
+ volatile uint32_t diepint;
+ volatile uint32_t doepint;
+ };
+ uint32_t rsv0c;
+ union {
+ volatile uint32_t dieptsiz;
+ volatile uint32_t doeptsiz;
+ };
+ union {
+ volatile uint32_t diepdma;
+ volatile uint32_t doepdma;
+ };
+ volatile uint32_t dtxfsts;
+ uint32_t rsv1c;
+}dwc2_dep_t;
+
+TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size");
+
+//--------------------------------------------------------------------
+// CSR Register Map
+//--------------------------------------------------------------------
+typedef struct {
+ //------------- Core Global -------------//
+ volatile uint32_t gotgctl; // 000 OTG Control and Status
+ volatile uint32_t gotgint; // 004 OTG Interrupt
+ volatile uint32_t gahbcfg; // 008 AHB Configuration
+ volatile uint32_t gusbcfg; // 00c USB Configuration
+ volatile uint32_t grstctl; // 010 Reset
+ volatile uint32_t gintsts; // 014 Interrupt
+ volatile uint32_t gintmsk; // 018 Interrupt Mask
+ volatile uint32_t grxstsr; // 01c Receive Status Debug Read
+ volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
+ volatile uint32_t grxfsiz; // 024 Receive FIFO Size
+ union {
+ volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
+ volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
+ };
+ volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
+ volatile uint32_t gi2cctl; // 030 I2C Address
+ volatile uint32_t gpvndctl; // 034 PHY Vendor Control
+ union {
+ volatile uint32_t ggpio; // 038 General Purpose IO
+ volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
+ };
+ volatile uint32_t guid; // 03C User (Application programmable) ID
+ volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
+ volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
+ union {
+ volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
+ volatile dwc2_ghwcfg2_t ghwcfg2_bm;
+ };
+ union {
+ volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
+ volatile dwc2_ghwcfg3_t ghwcfg3_bm;
+ };
+ union {
+ volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
+ volatile dwc2_ghwcfg4_t ghwcfg4_bm;
+ };
+ volatile uint32_t glpmcfg; // 054 Core LPM Configuration
+ volatile uint32_t gpwrdn; // 058 Power Down
+ volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
+ volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status
+ uint32_t reserved64[39]; // 064..0FF
+ volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size
+ volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
+ uint32_t reserved140[176]; // 140..3FF
+
+ //------------ Host -------------//
+ volatile uint32_t hcfg; // 400 Host Configuration
+ volatile uint32_t hfir; // 404 Host Frame Interval
+ volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
+ uint32_t reserved40c; // 40C
+ volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status
+ volatile uint32_t haint; // 414 Host All Channels Interrupt
+ volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask
+ volatile uint32_t hflbaddr; // 41C Host Frame List Base Address
+ uint32_t reserved420[8]; // 420..43F
+ volatile uint32_t hprt; // 440 Host Port Control and Status
+ uint32_t reserved444[47]; // 444..4FF
+
+ //------------- Host Channel -------------//
+ dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15
+ uint32_t reserved700[64]; // 700..7FF
+
+ //------------- Device -----------//
+ volatile uint32_t dcfg; // 800 Device Configuration
+ volatile uint32_t dctl; // 804 Device Control
+ volatile uint32_t dsts; // 808 Device Status (RO)
+ uint32_t reserved80c; // 80C
+ volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask
+ volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask
+ volatile uint32_t daint; // 818 Device All Endpoints Interrupt
+ volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask
+ volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1
+ volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2
+ volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time
+ volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time
+ volatile uint32_t dthrctl; // 830 Device threshold Control
+ volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask
+
+ // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line
+ // require OTG_MULTI_PROC_INTRPT=1
+ volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt
+ volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt mask
+ volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
+ volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask
+ uint32_t reserved8c0[16]; // 8C0..8FF
+
+ //------------- Device Endpoint -------------//
+ union {
+ dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT
+ struct {
+ dwc2_epin_t epin[16]; // 900..AFF IN Endpoints
+ dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints
+ };
+ };
+ uint32_t reservedd00[64]; // D00..DFF
+
+ //------------- Power Clock -------------//
+ volatile uint32_t pcgctl; // E00 Power and Clock Gating Control
+ volatile uint32_t pcgctl1; // E04
+ uint32_t reservede08[126]; // E08..FFF
+
+ //------------- FIFOs -------------//
+ // Word-accessed only using first pointer since it auto shift
+ volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO
} dwc2_regs_t;
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size");
@@ -940,6 +1128,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000
#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits
+#define DAINT_SHIFT(_dir) ((_dir == TUSB_DIR_IN) ? 0 : 16)
+
#if 0
/******************** Bit definition for OTG register ********************/
#define CHNUM_Pos (0U)
@@ -1222,6 +1412,12 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000
#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency
+// GDFIFOCFG
+#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
+#define GDFIFOCFG_EPINFOBASE_SHIFT 16
+#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
+#define GDFIFOCFG_GDFIFOCFG_SHIFT 0
+
/******************** Bit definition for DIEPEACHMSK1 register ********************/
#define DIEPEACHMSK1_XFRCM_Pos (0U)
#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001
@@ -1643,6 +1839,45 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000
#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth
+
+/******************** Bit definition for Common EPCTL register ********************/
+#define EPCTL_MPSIZ_Pos (0U)
+#define EPCTL_MPSIZ_Msk (0x7FFUL << EPCTL_MPSIZ_Pos) // 0x000007FF
+#define EPCTL_MPSIZ EPCTL_MPSIZ_Msk // Maximum packet size //Bit 1
+#define EPCTL_USBAEP_Pos (15U)
+#define EPCTL_USBAEP_Msk (0x1UL << EPCTL_USBAEP_Pos) // 0x00008000
+#define EPCTL_USBAEP EPCTL_USBAEP_Msk // USB active endpoint
+#define EPCTL_NAKSTS_Pos (17U)
+#define EPCTL_NAKSTS_Msk (0x1UL << EPCTL_NAKSTS_Pos) // 0x00020000
+#define EPCTL_NAKSTS EPCTL_NAKSTS_Msk // NAK status
+#define EPCTL_EPTYP_Pos (18U)
+#define EPCTL_EPTYP_Msk (0x3UL << EPCTL_EPTYP_Pos) // 0x000C0000
+#define EPCTL_EPTYP EPCTL_EPTYP_Msk // Endpoint type
+#define EPCTL_EPTYP_0 (0x1UL << EPCTL_EPTYP_Pos) // 0x00040000
+#define EPCTL_EPTYP_1 (0x2UL << EPCTL_EPTYP_Pos) // 0x00080000
+#define EPCTL_SNPM EPCTL_SNPM_Msk // Snoop mode
+#define EPCTL_STALL_Pos (21U)
+#define EPCTL_STALL_Msk (0x1UL << EPCTL_STALL_Pos) // 0x00200000
+#define EPCTL_STALL EPCTL_STALL_Msk // STALL handshake
+#define EPCTL_CNAK_Pos (26U)
+#define EPCTL_CNAK_Msk (0x1UL << EPCTL_CNAK_Pos) // 0x04000000
+#define EPCTL_CNAK EPCTL_CNAK_Msk // Clear NAK
+#define EPCTL_SNAK_Pos (27U)
+#define EPCTL_SNAK_Msk (0x1UL << EPCTL_SNAK_Pos) // 0x08000000
+#define EPCTL_SNAK EPCTL_SNAK_Msk // Set NAK
+#define EPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define EPCTL_SD0PID_SEVNFRM_Msk (0x1UL << EPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000
+#define EPCTL_SD0PID_SEVNFRM EPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID
+#define EPCTL_SODDFRM_Pos (29U)
+#define EPCTL_SODDFRM_Msk (0x1UL << EPCTL_SODDFRM_Pos) // 0x20000000
+#define EPCTL_SODDFRM EPCTL_SODDFRM_Msk // Set odd frame
+#define EPCTL_EPDIS_Pos (30U)
+#define EPCTL_EPDIS_Msk (0x1UL << EPCTL_EPDIS_Pos) // 0x40000000
+#define EPCTL_EPDIS EPCTL_EPDIS_Msk // Endpoint disable
+#define EPCTL_EPENA_Pos (31U)
+#define EPCTL_EPENA_Msk (0x1UL << EPCTL_EPENA_Pos) // 0x80000000
+#define EPCTL_EPENA EPCTL_EPENA_Msk // Endpoint enable
+
/******************** Bit definition for DOEPCTL register ********************/
#define DOEPCTL_MPSIZ_Pos (0U)
#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF
@@ -1693,15 +1928,19 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define DOEPINT_AHBERR_Pos (2U)
#define DOEPINT_AHBERR_Msk (0x1UL << DOEPINT_AHBERR_Pos) // 0x00000004
#define DOEPINT_AHBERR DOEPINT_AHBERR_Msk // AHB Error (AHBErr) during an OUT transaction
-#define DOEPINT_STUP_Pos (3U)
-#define DOEPINT_STUP_Msk (0x1UL << DOEPINT_STUP_Pos) // 0x00000008
-#define DOEPINT_STUP DOEPINT_STUP_Msk // SETUP phase done
+
+#define DOEPINT_SETUP_Pos (3U)
+#define DOEPINT_SETUP_Msk (0x1UL << DOEPINT_SETUP_Pos) // 0x00000008
+#define DOEPINT_SETUP DOEPINT_SETUP_Msk // SETUP phase done
+
#define DOEPINT_OTEPDIS_Pos (4U)
#define DOEPINT_OTEPDIS_Msk (0x1UL << DOEPINT_OTEPDIS_Pos) // 0x00000010
#define DOEPINT_OTEPDIS DOEPINT_OTEPDIS_Msk // OUT token received when endpoint disabled
-#define DOEPINT_OTEPSPR_Pos (5U)
-#define DOEPINT_OTEPSPR_Msk (0x1UL << DOEPINT_OTEPSPR_Pos) // 0x00000020
-#define DOEPINT_OTEPSPR DOEPINT_OTEPSPR_Msk // Status Phase Received For Control Write
+
+#define DOEPINT_STSPHSRX_Pos (5U)
+#define DOEPINT_STSPHSRX_Msk (0x1UL << DOEPINT_STSPHSRX_Pos) // 0x00000020
+#define DOEPINT_STSPHSRX DOEPINT_STSPHSRX_Msk // Status Phase Received For Control Write
+
#define DOEPINT_B2BSTUP_Pos (6U)
#define DOEPINT_B2BSTUP_Msk (0x1UL << DOEPINT_B2BSTUP_Pos) // 0x00000040
#define DOEPINT_B2BSTUP DOEPINT_B2BSTUP_Msk // Back-to-back SETUP packets received
@@ -1714,6 +1953,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define DOEPINT_NYET_Pos (14U)
#define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000
#define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt
+
#define DOEPINT_STPKTRX_Pos (15U)
#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000
#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
index 12d610bd65..3738ac0cb9 100644
--- a/src/portable/template/dcd_template.c
+++ b/src/portable/template/dcd_template.c
@@ -40,54 +40,45 @@
*------------------------------------------------------------------*/
// Initialize controller to device mode
-void dcd_init (uint8_t rhport)
-{
- (void) rhport;
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rhport; (void) rh_init;
+ return true;
}
// Enable device interrupt
-void dcd_int_enable (uint8_t rhport)
-{
+void dcd_int_enable (uint8_t rhport) {
(void) rhport;
}
// Disable device interrupt
-void dcd_int_disable (uint8_t rhport)
-{
+void dcd_int_disable (uint8_t rhport) {
(void) rhport;
}
// Receive Set Address request, mcu port must also include status IN response
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr) {
(void) rhport;
(void) dev_addr;
}
// Wake up host
-void dcd_remote_wakeup (uint8_t rhport)
-{
+void dcd_remote_wakeup (uint8_t rhport) {
(void) rhport;
}
// Connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport)
-{
+void dcd_connect(uint8_t rhport) {
(void) rhport;
}
// Disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport)
-{
+void dcd_disconnect(uint8_t rhport) {
(void) rhport;
}
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
(void) rhport;
(void) en;
-
- // TODO implement later
}
//--------------------------------------------------------------------+
@@ -95,21 +86,34 @@ void dcd_sof_enable(uint8_t rhport, bool en)
//--------------------------------------------------------------------+
// Configure endpoint's registers according to descriptor
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
-{
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) {
(void) rhport;
(void) ep_desc;
return false;
}
-void dcd_edpt_close_all (uint8_t rhport)
-{
+// Allocate packet buffer used by ISO endpoints
+// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
+ (void) rhport;
+ (void) ep_addr;
+ (void) largest_packet_size;
+ return false;
+}
+
+// Configure and enable an ISO endpoint according to descriptor
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) {
+ (void) rhport;
+ (void) desc_ep;
+ return false;
+}
+
+void dcd_edpt_close_all (uint8_t rhport) {
(void) rhport;
}
// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) {
(void) rhport;
(void) ep_addr;
(void) buffer;
@@ -118,8 +122,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
}
// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) {
(void) rhport;
(void) ep_addr;
(void) ff;
@@ -128,19 +131,15 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
}
// Stall endpoint
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) {
(void) rhport;
(void) ep_addr;
}
// clear stall, data toggle is also reset to DATA0
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) {
(void) rhport;
(void) ep_addr;
}
-
-
#endif
diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c
index b073d60570..d8bca196f5 100644
--- a/src/portable/template/hcd_template.c
+++ b/src/portable/template/hcd_template.c
@@ -44,9 +44,9 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
}
// Initialize controller to host mode
-bool hcd_init(uint8_t rhport) {
+bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
-
+ (void) rh_init;
return false;
}
diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index 8005f5f7be..3752ae2519 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -130,9 +130,8 @@ static void enable_functional_reset(const bool enable)
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
-void dcd_init (uint8_t rhport)
-{
- (void) rhport;
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rhport; (void) rh_init;
USBKEYPID = USBKEY;
@@ -164,6 +163,8 @@ void dcd_init (uint8_t rhport)
}
USBKEYPID = 0;
+
+ return true;
}
// There is no "USB peripheral interrupt disable" bit on MSP430, so we have
@@ -332,6 +333,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
return true;
}
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport; (void) ep_addr;
+ // TODO implement dcd_edpt_close()
+}
+
void dcd_edpt_close_all (uint8_t rhport)
{
(void) rhport;
@@ -694,7 +700,11 @@ static void handle_bus_power_event(void *param) {
// A successful lock is indicated by all PLL-related interrupt flags being cleared.
if(!USBPLLIR) {
- dcd_init(0); // Re-initialize the USB module.
+ const tusb_rhport_init_t rhport_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_FULL
+ };
+ dcd_init(0, &rhport_init); // Re-initialize the USB module.
}
} else { // Event caused by removal of bus power.
USBPWRCTL |= VBONIE; // Enable bus-power-applied interrupt.
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index 58628a8bb5..a03c945589 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -336,9 +336,9 @@ static void dcd_reset(void)
}
// Initializes the USB peripheral for device mode and enables it.
-void dcd_init(uint8_t rhport)
-{
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rhport;
+ (void) rh_init;
usb_pullup_out_write(0);
@@ -352,6 +352,8 @@ void dcd_init(uint8_t rhport)
// Turn on the external pullup
usb_pullup_out_write(1);
+
+ return true;
}
// Enables or disables the USB device interrupt(s). May be used to
@@ -436,6 +438,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
return true;
}
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport; (void) ep_addr;
+ // TODO implement dcd_edpt_close()
+}
+
void dcd_edpt_close_all (uint8_t rhport)
{
(void) rhport;
diff --git a/src/portable/wch/ch32_usbfs_reg.h b/src/portable/wch/ch32_usbfs_reg.h
new file mode 100644
index 0000000000..68be64f5e1
--- /dev/null
+++ b/src/portable/wch/ch32_usbfs_reg.h
@@ -0,0 +1,175 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Matthew Tran
+ * Copyright (c) 2024 hathach
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef USB_CH32_USBFS_REG_H
+#define USB_CH32_USBFS_REG_H
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_CH32F20X
+ #include
+#elif CFG_TUSB_MCU == OPT_MCU_CH32V103
+ #include
+ typedef struct
+ {
+ __IO uint8_t BASE_CTRL;
+ __IO uint8_t UDEV_CTRL;
+ __IO uint8_t INT_EN;
+ __IO uint8_t DEV_ADDR;
+ __IO uint8_t Reserve0;
+ __IO uint8_t MIS_ST;
+ __IO uint8_t INT_FG;
+ __IO uint8_t INT_ST;
+ __IO uint32_t RX_LEN;
+ __IO uint8_t UEP4_1_MOD;
+ __IO uint8_t UEP2_3_MOD;
+ __IO uint8_t UEP5_6_MOD;
+ __IO uint8_t UEP7_MOD;
+ __IO uint32_t UEP0_DMA;
+ __IO uint32_t UEP1_DMA;
+ __IO uint32_t UEP2_DMA;
+ __IO uint32_t UEP3_DMA;
+ __IO uint32_t UEP4_DMA;
+ __IO uint32_t UEP5_DMA;
+ __IO uint32_t UEP6_DMA;
+ __IO uint32_t UEP7_DMA;
+ __IO uint16_t UEP0_TX_LEN;
+ __IO uint8_t UEP0_TX_CTRL;
+ __IO uint8_t UEP0_RX_CTRL;
+ __IO uint16_t UEP1_TX_LEN;
+ __IO uint8_t UEP1_TX_CTRL;
+ __IO uint8_t UEP1_RX_CTRL;
+ __IO uint16_t UEP2_TX_LEN;
+ __IO uint8_t UEP2_TX_CTRL;
+ __IO uint8_t UEP2_RX_CTRL;
+ __IO uint16_t UEP3_TX_LEN;
+ __IO uint8_t UEP3_TX_CTRL;
+ __IO uint8_t UEP3_RX_CTRL;
+ __IO uint16_t UEP4_TX_LEN;
+ __IO uint8_t UEP4_TX_CTRL;
+ __IO uint8_t UEP4_RX_CTRL;
+ __IO uint16_t UEP5_TX_LEN;
+ __IO uint8_t UEP5_TX_CTRL;
+ __IO uint8_t UEP5_RX_CTRL;
+ __IO uint16_t UEP6_TX_LEN;
+ __IO uint8_t UEP6_TX_CTRL;
+ __IO uint8_t UEP6_RX_CTRL;
+ __IO uint16_t UEP7_TX_LEN;
+ __IO uint8_t UEP7_TX_CTRL;
+ __IO uint8_t UEP7_RX_CTRL;
+ __IO uint32_t Reserve1;
+ __IO uint32_t OTG_CR;
+ __IO uint32_t OTG_SR;
+ } USBOTG_FS_TypeDef;
+
+ #define USBOTG_FS ((USBOTG_FS_TypeDef *) 0x40023400)
+#elif CFG_TUSB_MCU == OPT_MCU_CH32V20X
+ #include
+#elif CFG_TUSB_MCU == OPT_MCU_CH32V307
+ #include
+ #define USBHD_IRQn OTG_FS_IRQn
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+// CTRL
+#define USBFS_CTRL_DMA_EN (1 << 0)
+#define USBFS_CTRL_CLR_ALL (1 << 1)
+#define USBFS_CTRL_RESET_SIE (1 << 2)
+#define USBFS_CTRL_INT_BUSY (1 << 3)
+#define USBFS_CTRL_SYS_CTRL (1 << 4)
+#define USBFS_CTRL_DEV_PUEN (1 << 5)
+#define USBFS_CTRL_LOW_SPEED (1 << 6)
+#define USBFS_CTRL_HOST_MODE (1 << 7)
+
+// INT_EN
+#define USBFS_INT_EN_BUS_RST (1 << 0)
+#define USBFS_INT_EN_DETECT (1 << 0)
+#define USBFS_INT_EN_TRANSFER (1 << 1)
+#define USBFS_INT_EN_SUSPEND (1 << 2)
+#define USBFS_INT_EN_HST_SOF (1 << 3)
+#define USBFS_INT_EN_FIFO_OV (1 << 4)
+#define USBFS_INT_EN_DEV_NAK (1 << 6)
+#define USBFS_INT_EN_DEV_SOF (1 << 7)
+
+// INT_FG
+#define USBFS_INT_FG_BUS_RST (1 << 0)
+#define USBFS_INT_FG_DETECT (1 << 0)
+#define USBFS_INT_FG_TRANSFER (1 << 1)
+#define USBFS_INT_FG_SUSPEND (1 << 2)
+#define USBFS_INT_FG_HST_SOF (1 << 3)
+#define USBFS_INT_FG_FIFO_OV (1 << 4)
+#define USBFS_INT_FG_SIE_FREE (1 << 5)
+#define USBFS_INT_FG_TOG_OK (1 << 6)
+#define USBFS_INT_FG_IS_NAK (1 << 7)
+
+// INT_ST
+#define USBFS_INT_ST_MASK_UIS_ENDP(x) (((x) >> 0) & 0x0F)
+#define USBFS_INT_ST_MASK_UIS_TOKEN(x) (((x) >> 4) & 0x03)
+
+// UDEV_CTRL
+#define USBFS_UDEV_CTRL_PORT_EN (1 << 0)
+#define USBFS_UDEV_CTRL_GP_BIT (1 << 1)
+#define USBFS_UDEV_CTRL_LOW_SPEED (1 << 2)
+#define USBFS_UDEV_CTRL_DM_PIN (1 << 4)
+#define USBFS_UDEV_CTRL_DP_PIN (1 << 5)
+#define USBFS_UDEV_CTRL_PD_DIS (1 << 7)
+
+// TX_CTRL
+#define USBFS_EP_T_RES_MASK (3 << 0)
+#define USBFS_EP_T_TOG (1 << 2)
+#define USBFS_EP_T_AUTO_TOG (1 << 3)
+
+#define USBFS_EP_T_RES_ACK (0 << 0)
+#define USBFS_EP_T_RES_NYET (1 << 0)
+#define USBFS_EP_T_RES_NAK (2 << 0)
+#define USBFS_EP_T_RES_STALL (3 << 0)
+
+// RX_CTRL
+#define USBFS_EP_R_RES_MASK (3 << 0)
+#define USBFS_EP_R_TOG (1 << 2)
+#define USBFS_EP_R_AUTO_TOG (1 << 3)
+
+#define USBFS_EP_R_RES_ACK (0 << 0)
+#define USBFS_EP_R_RES_NYET (1 << 0)
+#define USBFS_EP_R_RES_NAK (2 << 0)
+#define USBFS_EP_R_RES_STALL (3 << 0)
+
+// token PID
+#define PID_OUT 0
+#define PID_SOF 1
+#define PID_IN 2
+#define PID_SETUP 3
+
+#endif // USB_CH32_USBFS_REG_H
diff --git a/src/portable/wch/ch32_usbhs_reg.h b/src/portable/wch/ch32_usbhs_reg.h
index 9b956231fb..87300b4970 100644
--- a/src/portable/wch/ch32_usbhs_reg.h
+++ b/src/portable/wch/ch32_usbhs_reg.h
@@ -1,12 +1,51 @@
-#ifndef _USB_CH32_USBHS_REG_H
-#define _USB_CH32_USBHS_REG_H
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Matthew Tran
+ * Copyright (c) 2024 hathach
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef USB_CH32_USBHS_REG_H
+#define USB_CH32_USBHS_REG_H
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_CH32V307
+ #include
+#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X
+ #include
+#endif
-#if (CFG_TUSB_MCU == OPT_MCU_CH32V307)
-#include
-#elif (CFG_TUSB_MCU == OPT_MCU_CH32F20X)
-#include
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
#endif
+
/******************* GLOBAL ******************/
// USB CONTROL
@@ -36,8 +75,13 @@
// USB DEV AD
#define USBHS_DEV_AD_OFFSET 0x03
+
// USB FRAME_NO
#define USBHS_FRAME_NO_OFFSET 0x04
+#define USBHS_FRAME_NO_NUM_MASK (0x7FF)
+#define USBHS_FRAME_NO_MICROFRAME_SHIFT (11)
+#define USBHS_FRAME_NO_MICROFRAME_MASK (0x7 << USBHS_FRAME_NO_MICROFRAME_SHIFT)
+
// USB SUSPEND
#define USBHS_SUSPEND_OFFSET 0x06
#define USBHS_DEV_REMOTE_WAKEUP (1 << 2)
@@ -47,7 +91,10 @@
// USB SPEED TYPE
#define USBHS_SPEED_TYPE_OFFSET 0x08
-#define USBSPEED_MASK (0x03)
+#define USBHS_SPEED_TYPE_MASK 0x03
+#define USBHS_SPEED_TYPE_FULL 0
+#define USBHS_SPEED_TYPE_HIGH 1
+#define USBHS_SPEED_TYPE_LOW 2
// USB_MIS_ST
#define USBHS_MIS_ST_OFFSET 0x09
@@ -72,12 +119,16 @@
#define USBHS_ISO_ACT_FLAG (1 << 6)
// INT_ST
-#define USBHS_INT_ST_OFFSET 0x0B
-#define USBHS_DEV_UIS_IS_NAK (1 << 7)
-#define USBHS_DEV_UIS_TOG_OK (1 << 6)
-#define MASK_UIS_TOKEN (3 << 4)
-#define MASK_UIS_ENDP (0x0F)
-#define MASK_UIS_H_RES (0x0F)
+#define USBHS_INT_ST_OFFSET 0x0B
+#define USBHS_DEV_UIS_IS_NAK (1 << 7)
+#define USBHS_DEV_UIS_TOG_OK (1 << 6)
+#define MASK_UIS_TOKEN (3 << 4)
+#define USBHS_TOKEN_PID_OUT (0 << 4)
+#define USBHS_TOKEN_PID_SOF (1 << 4)
+#define USBHS_TOKEN_PID_IN (2 << 4)
+#define USBHS_TOKEN_PID_SETUP (3 << 4)
+#define MASK_UIS_ENDP (0x0F)
+#define MASK_UIS_H_RES (0x0F)
#define USBHS_TOGGLE_OK (0x40)
#define USBHS_HOST_RES (0x0f)
@@ -340,10 +391,5 @@
#define USBHS_UH_T_TOG_AUTO (1 << 5)
#define USBHS_UH_T_DATA_NO (1 << 6)
-// 00: OUT, 01:SOF, 10:IN, 11:SETUP
-#define PID_OUT 0
-#define PID_SOF 1
-#define PID_IN 2
-#define PID_SETUP 3
#endif
diff --git a/src/portable/wch/dcd_ch32_usbfs.c b/src/portable/wch/dcd_ch32_usbfs.c
new file mode 100644
index 0000000000..4e8e25a001
--- /dev/null
+++ b/src/portable/wch/dcd_ch32_usbfs.c
@@ -0,0 +1,347 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Matthew Tran
+ * Copyright (c) 2024 hathach
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_WCH_USBFS) && CFG_TUD_WCH_USBIP_USBFS
+
+#include "device/dcd.h"
+#include "ch32_usbfs_reg.h"
+
+/* private defines */
+#define EP_MAX (8)
+
+#define EP_DMA(ep) ((&USBOTG_FS->UEP0_DMA)[ep])
+#define EP_TX_LEN(ep) ((&USBOTG_FS->UEP0_TX_LEN)[2 * ep])
+#define EP_TX_CTRL(ep) ((&USBOTG_FS->UEP0_TX_CTRL)[4 * ep])
+#define EP_RX_CTRL(ep) ((&USBOTG_FS->UEP0_RX_CTRL)[4 * ep])
+
+/* private data */
+struct usb_xfer {
+ bool valid;
+ uint8_t* buffer;
+ size_t len;
+ size_t processed_len;
+ size_t max_size;
+};
+
+static struct {
+ bool ep0_tog;
+ bool isochronous[EP_MAX];
+ struct usb_xfer xfer[EP_MAX][2];
+ TU_ATTR_ALIGNED(4) uint8_t buffer[EP_MAX][2][64];
+ TU_ATTR_ALIGNED(4) struct {
+ // OUT transfers >64 bytes will overwrite queued IN data!
+ uint8_t out[64];
+ uint8_t in[1023];
+ uint8_t pad;
+ } ep3_buffer;
+} data;
+
+/* private helpers */
+static void update_in(uint8_t rhport, uint8_t ep, bool force) {
+ struct usb_xfer* xfer = &data.xfer[ep][TUSB_DIR_IN];
+ if (xfer->valid) {
+ if (force || xfer->len) {
+ size_t len = TU_MIN(xfer->max_size, xfer->len);
+ if (ep == 0) {
+ memcpy(data.buffer[ep][TUSB_DIR_OUT], xfer->buffer, len); // ep0 uses same chunk
+ } else if (ep == 3) {
+ memcpy(data.ep3_buffer.in, xfer->buffer, len);
+ } else {
+ memcpy(data.buffer[ep][TUSB_DIR_IN], xfer->buffer, len);
+ }
+ xfer->buffer += len;
+ xfer->len -= len;
+ xfer->processed_len += len;
+
+ EP_TX_LEN(ep) = len;
+ if (ep == 0) {
+ EP_TX_CTRL(0) = USBFS_EP_T_RES_ACK | (data.ep0_tog ? USBFS_EP_T_TOG : 0);
+ data.ep0_tog = !data.ep0_tog;
+ } else if (data.isochronous[ep]) {
+ EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~(USBFS_EP_T_RES_MASK)) | USBFS_EP_T_RES_NYET;
+ } else {
+ EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~(USBFS_EP_T_RES_MASK)) | USBFS_EP_T_RES_ACK;
+ }
+ } else {
+ xfer->valid = false;
+ EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~(USBFS_EP_T_RES_MASK)) | USBFS_EP_T_RES_NAK;
+ dcd_event_xfer_complete(
+ rhport, ep | TUSB_DIR_IN_MASK, xfer->processed_len,
+ XFER_RESULT_SUCCESS, true);
+ }
+ }
+}
+
+static void update_out(uint8_t rhport, uint8_t ep, size_t rx_len) {
+ struct usb_xfer* xfer = &data.xfer[ep][TUSB_DIR_OUT];
+ if (xfer->valid) {
+ size_t len = TU_MIN(xfer->max_size, TU_MIN(xfer->len, rx_len));
+ if (ep == 3) {
+ memcpy(xfer->buffer, data.ep3_buffer.out, len);
+ } else {
+ memcpy(xfer->buffer, data.buffer[ep][TUSB_DIR_OUT], len);
+ }
+ xfer->buffer += len;
+ xfer->len -= len;
+ xfer->processed_len += len;
+
+ if (xfer->len == 0 || len < xfer->max_size) {
+ xfer->valid = false;
+ dcd_event_xfer_complete(rhport, ep, xfer->processed_len, XFER_RESULT_SUCCESS, true);
+ }
+
+ if (ep == 0) {
+ EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+ }
+ }
+}
+
+/* public functions */
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rh_init;
+ // init registers
+ USBOTG_FS->BASE_CTRL = USBFS_CTRL_SYS_CTRL | USBFS_CTRL_INT_BUSY | USBFS_CTRL_DMA_EN;
+ USBOTG_FS->UDEV_CTRL = USBFS_UDEV_CTRL_PD_DIS | USBFS_UDEV_CTRL_PORT_EN;
+ USBOTG_FS->DEV_ADDR = 0x00;
+
+ USBOTG_FS->INT_FG = 0xFF;
+ USBOTG_FS->INT_EN = USBFS_INT_EN_BUS_RST | USBFS_INT_EN_TRANSFER | USBFS_INT_EN_SUSPEND;
+
+ // setup endpoint 0
+ EP_DMA(0) = (uint32_t) &data.buffer[0][0];
+ EP_TX_LEN(0) = 0;
+ EP_TX_CTRL(0) = USBFS_EP_T_RES_NAK;
+ EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+
+ // enable other endpoints but NAK everything
+ USBOTG_FS->UEP4_1_MOD = 0xCC;
+ USBOTG_FS->UEP2_3_MOD = 0xCC;
+ USBOTG_FS->UEP5_6_MOD = 0xCC;
+ USBOTG_FS->UEP7_MOD = 0x0C;
+
+ for (uint8_t ep = 1; ep < EP_MAX; ep++) {
+ EP_DMA(ep) = (uint32_t) &data.buffer[ep][0];
+ EP_TX_LEN(ep) = 0;
+ EP_TX_CTRL(ep) = USBFS_EP_T_AUTO_TOG | USBFS_EP_T_RES_NAK;
+ EP_RX_CTRL(ep) = USBFS_EP_R_AUTO_TOG | USBFS_EP_R_RES_NAK;
+ }
+ EP_DMA(3) = (uint32_t) &data.ep3_buffer.out[0];
+
+ dcd_connect(rhport);
+
+ return true;
+}
+
+void dcd_int_handler(uint8_t rhport) {
+ (void) rhport;
+ uint8_t status = USBOTG_FS->INT_FG;
+ if (status & USBFS_INT_FG_TRANSFER) {
+ uint8_t ep = USBFS_INT_ST_MASK_UIS_ENDP(USBOTG_FS->INT_ST);
+ uint8_t token = USBFS_INT_ST_MASK_UIS_TOKEN(USBOTG_FS->INT_ST);
+
+ switch (token) {
+ case PID_OUT: {
+ uint16_t rx_len = USBOTG_FS->RX_LEN;
+ update_out(rhport, ep, rx_len);
+ break;
+ }
+
+ case PID_IN:
+ update_in(rhport, ep, false);
+ break;
+
+ case PID_SETUP:
+ // setup clears stall
+ EP_TX_CTRL(0) = USBFS_EP_T_RES_NAK;
+ EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+
+ data.ep0_tog = true;
+ dcd_event_setup_received(rhport, &data.buffer[0][TUSB_DIR_OUT][0], true);
+ break;
+ }
+
+ USBOTG_FS->INT_FG = USBFS_INT_FG_TRANSFER;
+ } else if (status & USBFS_INT_FG_BUS_RST) {
+ data.ep0_tog = true;
+ data.xfer[0][TUSB_DIR_OUT].max_size = 64;
+ data.xfer[0][TUSB_DIR_IN].max_size = 64;
+
+ dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
+
+ USBOTG_FS->DEV_ADDR = 0x00;
+ EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+
+ USBOTG_FS->INT_FG = USBFS_INT_FG_BUS_RST;
+ } else if (status & USBFS_INT_FG_SUSPEND) {
+ dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_SUSPEND};
+ dcd_event_handler(&event, true);
+ USBOTG_FS->INT_FG = USBFS_INT_FG_SUSPEND;
+ }
+}
+
+void dcd_int_enable(uint8_t rhport) {
+ (void) rhport;
+ NVIC_EnableIRQ(USBHD_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+ (void) rhport;
+ NVIC_DisableIRQ(USBHD_IRQn);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+ (void) dev_addr;
+ dcd_edpt_xfer(rhport, 0x80, NULL, 0); // zlp status response
+}
+
+void dcd_remote_wakeup(uint8_t rhport) {
+ (void) rhport;
+ // TODO optional
+}
+
+void dcd_connect(uint8_t rhport) {
+ (void) rhport;
+ USBOTG_FS->BASE_CTRL |= USBFS_CTRL_DEV_PUEN;
+}
+
+void dcd_disconnect(uint8_t rhport) {
+ (void) rhport;
+ USBOTG_FS->BASE_CTRL &= ~USBFS_CTRL_DEV_PUEN;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en) {
+ (void) rhport;
+ (void) en;
+
+ // TODO implement later
+}
+
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
+ (void) rhport;
+ if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+ request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+ request->bRequest == TUSB_REQ_SET_ADDRESS) {
+ USBOTG_FS->DEV_ADDR = (uint8_t) request->wValue;
+ }
+ EP_TX_CTRL(0) = USBFS_EP_T_RES_NAK;
+ EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) {
+ (void) rhport;
+ uint8_t ep = tu_edpt_number(desc_ep->bEndpointAddress);
+ uint8_t dir = tu_edpt_dir(desc_ep->bEndpointAddress);
+ TU_ASSERT(ep < EP_MAX);
+
+ data.isochronous[ep] = desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS;
+ data.xfer[ep][dir].max_size = tu_edpt_packet_size(desc_ep);
+
+ if (ep != 0) {
+ if (dir == TUSB_DIR_OUT) {
+ if (data.isochronous[ep]) {
+ EP_RX_CTRL(ep) = USBFS_EP_R_AUTO_TOG | USBFS_EP_R_RES_NYET;
+ } else {
+ EP_RX_CTRL(ep) = USBFS_EP_R_AUTO_TOG | USBFS_EP_R_RES_ACK;
+ }
+ } else {
+ EP_TX_LEN(ep) = 0;
+ EP_TX_CTRL(ep) = USBFS_EP_T_AUTO_TOG | USBFS_EP_T_RES_NAK;
+ }
+ }
+ return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport) {
+ (void) rhport;
+ // TODO optional
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport;
+ (void) ep_addr;
+ // TODO optional
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+ (void) rhport;
+ uint8_t ep = tu_edpt_number(ep_addr);
+ uint8_t dir = tu_edpt_dir(ep_addr);
+
+ struct usb_xfer* xfer = &data.xfer[ep][dir];
+ dcd_int_disable(rhport);
+ xfer->valid = true;
+ xfer->buffer = buffer;
+ xfer->len = total_bytes;
+ xfer->processed_len = 0;
+ dcd_int_enable(rhport);
+
+ if (dir == TUSB_DIR_IN) {
+ update_in(rhport, ep, true);
+ }
+ return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport;
+ uint8_t ep = tu_edpt_number(ep_addr);
+ uint8_t dir = tu_edpt_dir(ep_addr);
+ if (ep == 0) {
+ if (dir == TUSB_DIR_OUT) {
+ EP_RX_CTRL(0) = USBFS_EP_R_RES_STALL;
+ } else {
+ EP_TX_LEN(0) = 0;
+ EP_TX_CTRL(0) = USBFS_EP_T_RES_STALL;
+ }
+ } else {
+ if (dir == TUSB_DIR_OUT) {
+ EP_RX_CTRL(ep) = (EP_RX_CTRL(ep) & ~USBFS_EP_R_RES_MASK) | USBFS_EP_R_RES_STALL;
+ } else {
+ EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~USBFS_EP_T_RES_MASK) | USBFS_EP_T_RES_STALL;
+ }
+ }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport;
+ uint8_t ep = tu_edpt_number(ep_addr);
+ uint8_t dir = tu_edpt_dir(ep_addr);
+ if (ep == 0) {
+ if (dir == TUSB_DIR_OUT) {
+ EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK;
+ }
+ } else {
+ if (dir == TUSB_DIR_OUT) {
+ EP_RX_CTRL(ep) = (EP_RX_CTRL(ep) & ~(USBFS_EP_R_RES_MASK | USBFS_EP_R_TOG)) | USBFS_EP_R_RES_ACK;
+ } else {
+ EP_TX_CTRL(ep) = (EP_TX_CTRL(ep) & ~(USBFS_EP_T_RES_MASK | USBFS_EP_T_TOG)) | USBFS_EP_T_RES_NAK;
+ }
+ }
+}
+
+#endif
diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c
index 1f1c0b8764..f8bf3c8896 100644
--- a/src/portable/wch/dcd_ch32_usbhs.c
+++ b/src/portable/wch/dcd_ch32_usbhs.c
@@ -2,6 +2,7 @@
* The MIT License (MIT)
*
* Copyright (c) 2022 Greg Davill
+ * Copyright (c) 2023 Denis Krasutski
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -26,366 +27,397 @@
#include "tusb_option.h"
-#if CFG_TUD_ENABLED && ((CFG_TUSB_MCU == OPT_MCU_CH32V307) || (CFG_TUSB_MCU == OPT_MCU_CH32F20X))
-#include "device/dcd.h"
-
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_WCH_USBHS) && CFG_TUD_WCH_USBIP_USBHS
#include "ch32_usbhs_reg.h"
+#include "device/dcd.h"
// Max number of bi-directional endpoints including EP0
-#define EP_MAX 16
+#define EP_MAX 16
typedef struct {
- uint8_t *buffer;
- // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API
- uint16_t total_len;
- uint16_t queued_len;
- uint16_t max_size;
- bool short_packet;
+ uint8_t* buffer;
+ uint16_t total_len;
+ uint16_t queued_len;
+ uint16_t max_size;
+ bool is_last_packet;
+ bool is_iso;
} xfer_ctl_t;
+typedef enum {
+ EP_RESPONSE_ACK,
+ EP_RESPONSE_NAK,
+} ep_response_list_t;
+
#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
static xfer_ctl_t xfer_status[EP_MAX][2];
-#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2)
-#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4)
-#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4)
-#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2)
+#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep) * 2)
+#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep) * 4)
+#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep) * 4)
+#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep) * 2)
#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1))
#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1))
/* Endpoint Buffer */
-TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64)
+TU_ATTR_ALIGNED(4) static uint8_t ep0_buffer[CFG_TUD_ENDPOINT0_SIZE];
+
+static void ep_set_response_and_toggle(uint8_t ep_num, tusb_dir_t ep_dir, ep_response_list_t response_type) {
+ if (ep_dir == TUSB_DIR_IN) {
+ uint8_t response = (response_type == EP_RESPONSE_ACK) ? USBHS_EP_T_RES_ACK : USBHS_EP_T_RES_NAK;
+ if (ep_num == 0) {
+ if (response_type == EP_RESPONSE_ACK) {
+ if (EP_TX_LEN(ep_num) == 0) {
+ EP_TX_CTRL(ep_num) |= USBHS_EP_T_TOG_1;
+ } else {
+ EP_TX_CTRL(ep_num) ^= USBHS_EP_T_TOG_1;
+ }
+ }
+ }
+ if (xfer_status[ep_num][TUSB_DIR_IN].is_iso == true) {
+ EP_TX_CTRL(ep_num) = USBHS_EP_T_AUTOTOG;
+ } else {
+ EP_TX_CTRL(ep_num) = (EP_TX_CTRL(ep_num) & ~(USBHS_EP_T_RES_MASK)) | response;
+ }
+ } else {
+ uint8_t response = (response_type == EP_RESPONSE_ACK) ? USBHS_EP_R_RES_ACK : USBHS_EP_R_RES_NAK;
+ if (ep_num == 0) {
+ if (response_type == EP_RESPONSE_ACK) {
+ if (xfer_status[ep_num][TUSB_DIR_OUT].queued_len == 0) {
+ EP_RX_CTRL(ep_num) |= USBHS_EP_R_TOG_1;
+ }
+ } else {
+ EP_RX_CTRL(ep_num) ^= USBHS_EP_R_TOG_1;
+ }
+ }
+ EP_RX_CTRL(ep_num) = (EP_RX_CTRL(ep_num) & ~(USBHS_EP_R_RES_MASK)) | response;
+ }
+}
-volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01;
+static void xfer_data_packet(uint8_t ep_num, tusb_dir_t ep_dir, xfer_ctl_t* xfer) {
+ if (ep_dir == TUSB_DIR_IN) {
+ uint16_t remaining = xfer->total_len - xfer->queued_len;
+ uint16_t next_tx_size = TU_MIN(remaining, xfer->max_size);
-void dcd_init(uint8_t rhport) {
- (void)rhport;
+ if (ep_num == 0) {
+ memcpy(ep0_buffer, &xfer->buffer[xfer->queued_len], next_tx_size);
+ } else {
+ EP_TX_DMA_ADDR(ep_num) = (uint32_t) &xfer->buffer[xfer->queued_len];
+ }
- memset(&xfer_status, 0, sizeof(xfer_status));
+ EP_TX_LEN(ep_num) = next_tx_size;
+ xfer->queued_len += next_tx_size;
+ if (xfer->queued_len == xfer->total_len) {
+ xfer->is_last_packet = true;
+ }
+ if (xfer->is_iso == true) {
+ /* Enable EP to generate ISA_ACT interrupt */
+ USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << ep_num);
+ }
+ } else { /* TUSB_DIR_OUT */
+ uint16_t left_to_receive = xfer->total_len - xfer->queued_len;
+ uint16_t max_possible_rx_size = TU_MIN(xfer->max_size, left_to_receive);
- USBHSD->HOST_CTRL = 0x00;
- USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
+ if (max_possible_rx_size == left_to_receive) {
+ xfer->is_last_packet = true;
+ }
- USBHSD->CONTROL = 0;
+ if (ep_num > 0) {
+ EP_RX_DMA_ADDR(ep_num) = (uint32_t) &xfer->buffer[xfer->queued_len];
+ EP_RX_MAX_LEN(ep_num) = max_possible_rx_size;
+ }
+ }
+ ep_set_response_and_toggle(ep_num, ep_dir, USBHS_EP_R_RES_ACK);
+}
+
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rhport;
+ (void) rh_init;
+
+ memset(&xfer_status, 0, sizeof(xfer_status));
+
+ USBHSD->HOST_CTRL = 0x00;
+ USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
+
+ USBHSD->CONTROL = 0;
#if TUD_OPT_HIGH_SPEED
- USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
+ USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
#else
- #error OPT_MODE_FULL_SPEED not currently supported on CH32
- USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
+ #error OPT_MODE_FULL_SPEED not currently supported on CH32
+ USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
#endif
- USBHSD->INT_EN = 0;
- USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN;
-
- /* ALL endpoint enable */
- USBHSD->ENDP_CONFIG = 0xffffffff;
-
- USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
- USBHSD->ENDP_TYPE = 0x00;
- USBHSD->BUF_MODE = 0x00;
+ USBHSD->INT_EN = 0;
+ USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_BUS_RST_EN | USBHS_SUSPEND_EN | USBHS_ISO_ACT_EN;
- USBHSD->UEP0_MAX_LEN = 64;
+ USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
+ USBHSD->ENDP_TYPE = 0x00;
+ USBHSD->BUF_MODE = 0x00;
- USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD;
+ for (int ep = 0; ep < EP_MAX; ep++) {
+ EP_TX_LEN(ep) = 0;
+ EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
+ EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
- USBHSD->UEP0_TX_LEN = 0;
- USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK;
- USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
+ EP_RX_MAX_LEN(ep) = 0;
+ }
- for (int ep = 1; ep < EP_MAX; ep++) {
- EP_TX_LEN(ep) = 0;
- EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
- EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+ USBHSD->UEP0_DMA = (uint32_t) ep0_buffer;
+ USBHSD->UEP0_MAX_LEN = CFG_TUD_ENDPOINT0_SIZE;
+ xfer_status[0][TUSB_DIR_OUT].max_size = CFG_TUD_ENDPOINT0_SIZE;
+ xfer_status[0][TUSB_DIR_IN].max_size = CFG_TUD_ENDPOINT0_SIZE;
- EP_RX_MAX_LEN(ep) = 512;
- }
+ USBHSD->DEV_AD = 0;
+ USBHSD->CONTROL |= USBHS_DEV_PU_EN;
- USBHSD->DEV_AD = 0;
- USBHSD->CONTROL |= USBHS_DEV_PU_EN;
+ return true;
}
void dcd_int_enable(uint8_t rhport) {
- (void)rhport;
-
- NVIC_EnableIRQ(USBHS_IRQn);
+ (void) rhport;
+ NVIC_EnableIRQ(USBHS_IRQn);
}
void dcd_int_disable(uint8_t rhport) {
- (void)rhport;
-
- NVIC_DisableIRQ(USBHS_IRQn);
+ (void) rhport;
+ NVIC_DisableIRQ(USBHS_IRQn);
}
void dcd_edpt_close_all(uint8_t rhport) {
- (void)rhport;
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
- (void)dev_addr;
-
- // Response with zlp status
- dcd_edpt_xfer(rhport, 0x80, NULL, 0);
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
(void) rhport;
-}
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
- (void)rhport;
+ for (size_t ep = 1; ep < EP_MAX; ep++) {
+ EP_TX_LEN(ep) = 0;
+ EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
+ EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
- if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
- request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
- request->bRequest == TUSB_REQ_SET_ADDRESS) {
- USBHSD->DEV_AD = (uint8_t)request->wValue;
- }
+ EP_RX_MAX_LEN(ep) = 0;
+ }
- EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK;
- EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK;
+ USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
}
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) {
- (void)rhport;
-
- uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
- uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
- TU_ASSERT(epnum < EP_MAX);
-
- xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
- xfer->max_size = tu_edpt_packet_size(desc_edpt);
-
- if (epnum != 0) {
- if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) {
- EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK;
- } else {
- EP_TX_LEN(epnum) = 0;
- EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
- }
- }
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+ (void) dev_addr;
- return true;
+ // Response with zlp status
+ dcd_edpt_xfer(rhport, 0x80, NULL, 0);
}
-int usbd_ep_close(const uint8_t ep) {
- (void)ep;
-
- return 0;
+void dcd_remote_wakeup(uint8_t rhport) {
+ (void) rhport;
}
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
- (void)rhport;
-
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
- if (epnum == 0) {
- if (dir == TUSB_DIR_OUT) {
- USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL;
- } else {
- USBHSD->UEP0_TX_LEN = 0;
- USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL;
- }
- } else {
- if (dir == TUSB_DIR_OUT) {
- EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL;
-
- } else {
- EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL;
- }
- }
+void dcd_sof_enable(uint8_t rhport, bool en) {
+ (void) rhport;
+ if (en) {
+ USBHSD->INT_EN |= USBHS_SOF_ACT_EN;
+ } else {
+ USBHSD->INT_EN &= ~(USBHS_SOF_ACT_EN);
+ }
}
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
- (void)rhport;
-
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
+ (void) rhport;
- if (epnum == 0) {
- if (dir == TUSB_DIR_OUT) {
- USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
- } else {
- }
- } else {
- if (dir == TUSB_DIR_OUT) {
- EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK;
+ if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+ request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+ request->bRequest == TUSB_REQ_SET_ADDRESS) {
+ USBHSD->DEV_AD = (uint8_t) request->wValue;
+ }
- } else {
- EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK;
- }
- }
+ EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+ EP_RX_CTRL(0) = USBHS_EP_R_RES_NAK | USBHS_EP_R_TOG_0;
}
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) {
- (void)rhport;
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
-
- xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
- xfer->buffer = buffer;
- // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API
- xfer->total_len = total_bytes;
- xfer->queued_len = 0;
- xfer->short_packet = false;
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
+ (void) rhport;
- // uint16_t num_packets = (total_bytes / xfer->max_size);
- uint16_t short_packet_size = total_bytes % (xfer->max_size + 1);
+ uint8_t const ep_num = tu_edpt_number(desc_edpt->bEndpointAddress);
+ tusb_dir_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
- // Zero-size packet is special case.
- if (short_packet_size == 0 || (total_bytes == 0)) {
- xfer->short_packet = true;
- }
+ TU_ASSERT(ep_num < EP_MAX);
- if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
- if (!total_bytes) {
- xfer->short_packet = true;
- if (epnum == 0) {
- USBHSD->UEP0_TX_LEN = 0;
- USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
- USBHS_Dev_Endp0_Tog ^= 1;
- } else {
- EP_TX_LEN(epnum) = 0;
- EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
- }
- } else {
- if (epnum == 0) {
- xfer->queued_len += short_packet_size;
- memcpy(&EP0_DatabufHD[0], buffer, short_packet_size);
-
- USBHSD->UEP0_TX_LEN = short_packet_size;
- USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
- USBHS_Dev_Endp0_Tog ^= 1;
- } else {
- xfer->queued_len += short_packet_size;
-
- EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer;
- USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum);
- EP_TX_LEN(epnum) = short_packet_size;
- EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
- }
- }
- } else { /* TUSB_DIR_OUT */
- if (epnum == 0) {
- uint32_t read_count = USBHSD->RX_LEN;
- read_count = TU_MIN(read_count, total_bytes);
-
- if ((total_bytes == 8)) {
- read_count = 8;
- memcpy(buffer, &EP0_DatabufHD[0], 8);
- } else {
- memcpy(buffer, &EP0_DatabufHD[0], read_count);
- }
- } else {
- EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer;
- USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum);
- }
-
- // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes);
- }
+ if (ep_num == 0) {
return true;
-}
+ }
+ xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, dir);
+ xfer->max_size = tu_edpt_packet_size(desc_edpt);
-static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) {
- // xfer->queued_len = xfer->total_len - remaining;
-
- uint16_t remaining = xfer->total_len - xfer->queued_len;
- uint16_t to_recv_size;
-
- if (remaining <= xfer->max_size) {
- // Avoid buffer overflow.
- to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
+ xfer->is_iso = (desc_edpt->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+ if (dir == TUSB_DIR_OUT) {
+ USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << ep_num);
+ EP_RX_CTRL(ep_num) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+ if (xfer->is_iso == true) {
+ USBHSD->ENDP_TYPE |= (USBHS_EP0_R_TYP << ep_num);
+ }
+ EP_RX_MAX_LEN(ep_num) = xfer->max_size;
+ } else {
+ if (xfer->is_iso == true) {
+ USBHSD->ENDP_TYPE |= (USBHS_EP0_T_TYP << ep_num);
} else {
- // Room for full packet, choose recv_size based on what the microcontroller
- // claims.
- to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
+ /* Enable all types except Isochronous to avoid ISO_ACT interrupt generation */
+ USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << ep_num);
}
+ EP_TX_LEN(ep_num) = 0;
+ EP_TX_CTRL(ep_num) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+ }
- if (to_recv_size) {
- }
+ return true;
+}
- xfer->queued_len += xfer_size;
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport;
- // Per USB spec, a short OUT packet (including length 0) is always
- // indicative of the end of a transfer (at least for ctl, bulk, int).
- xfer->short_packet = (xfer_size < xfer->max_size);
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+
+ if (dir == TUSB_DIR_OUT) {
+ EP_RX_CTRL(ep_num) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+ EP_RX_MAX_LEN(ep_num) = 0;
+ USBHSD->ENDP_TYPE &= ~(USBHS_EP0_R_TYP << ep_num);
+ USBHSD->ENDP_CONFIG &= ~(USBHS_EP0_R_EN << ep_num);
+ } else { // TUSB_DIR_IN
+ EP_TX_CTRL(ep_num) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+ EP_TX_LEN(ep_num) = 0;
+ USBHSD->ENDP_TYPE &= ~(USBHS_EP0_T_TYP << ep_num);
+ USBHSD->ENDP_CONFIG &= ~(USBHS_EP0_T_EN << ep_num);
+ }
}
-void dcd_int_handler(uint8_t rhport) {
- (void)rhport;
-
- uint32_t end_num, rx_token;
- uint8_t intflag = 0;
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport;
- intflag = USBHSD->INT_FG;
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
- if (intflag & USBHS_TRANSFER_FLAG) {
+ if (dir == TUSB_DIR_OUT) {
+ EP_RX_CTRL(ep_num) = USBHS_EP_R_RES_STALL;
+ } else {
+ EP_TX_LEN(0) = 0;
+ EP_TX_CTRL(ep_num) = USBHS_EP_T_RES_STALL;
+ }
+}
- end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP;
- rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03;
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+ (void) rhport;
- uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0);
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
- xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp));
+ if (dir == TUSB_DIR_OUT) {
+ EP_RX_CTRL(ep_num) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+ } else {
+ EP_TX_CTRL(ep_num) = USBHS_EP_T_AUTOTOG | USBHS_EP_R_RES_NAK;
+ }
+}
- if (rx_token == PID_OUT) {
- uint16_t rx_len = USBHSD->RX_LEN;
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+ (void) rhport;
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
- receive_packet(xfer, rx_len);
+ xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, dir);
+ xfer->buffer = buffer;
+ xfer->total_len = total_bytes;
+ xfer->queued_len = 0;
+ xfer->is_last_packet = false;
- if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
- xfer->short_packet = false;
+ xfer_data_packet(ep_num, dir, xfer);
- dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
- }
+ return true;
+}
- if (end_num == 0) {
- USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
- }
+void dcd_int_handler(uint8_t rhport) {
+ (void) rhport;
- } else if (rx_token == PID_IN) {
- if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
- xfer->short_packet = false;
- xfer->total_len = 0;
- dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+ uint8_t int_flag = USBHSD->INT_FG;
+ uint8_t int_status = USBHSD->INT_ST;
- EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK;
+ if (int_flag & (USBHS_ISO_ACT_FLAG | USBHS_TRANSFER_FLAG)) {
+ uint8_t const token = int_status & MASK_UIS_TOKEN;
- if (end_num == 0) {
- }
- } else {
- dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len);
- }
- }
+ if (token == USBHS_TOKEN_PID_SOF) {
+ uint32_t frame_count = USBHSD->FRAME_NO & USBHS_FRAME_NO_NUM_MASK;
+ dcd_event_sof(rhport, frame_count, true);
+ }else {
+ uint8_t const ep_num = int_status & MASK_UIS_ENDP;
+ tusb_dir_t const ep_dir = (token == USBHS_TOKEN_PID_IN) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+ uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir);
+ xfer_ctl_t* xfer = XFER_CTL_BASE(ep_num, ep_dir);
- USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */
- } else if (intflag & USBHS_SETUP_FLAG) {
- USBHS_Dev_Endp0_Tog = 1;
- dcd_event_setup_received(0, EP0_DatabufHD, true);
+ if (token == USBHS_TOKEN_PID_OUT) {
+ uint16_t rx_len = USBHSD->RX_LEN;
- USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
- } else if (intflag & USBHS_DETECT_FLAG) {
- USBHS_Dev_Endp0_Tog = 1;
+ if (ep_num == 0) {
+ memcpy(&xfer->buffer[xfer->queued_len], ep0_buffer, rx_len);
+ }
- xfer_status[0][TUSB_DIR_OUT].max_size = 64;
- xfer_status[0][TUSB_DIR_IN].max_size = 64;
+ xfer->queued_len += rx_len;
+ if (rx_len < xfer->max_size) {
+ xfer->is_last_packet = true;
+ }
+ } else if (token == USBHS_TOKEN_PID_IN) {
+ if (xfer->is_iso && xfer->is_last_packet) {
+ /* Disable EP to avoid ISO_ACT interrupt generation */
+ USBHSD->ENDP_CONFIG &= ~(USBHS_EP0_T_EN << ep_num);
+ } else {
+ // Do nothing, no need to update xfer->is_last_packet, it is already updated in xfer_data_packet
+ }
+ }
+
+ if (xfer->is_last_packet == true) {
+ ep_set_response_and_toggle(ep_num, ep_dir, EP_RESPONSE_NAK);
+ dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+ } else {
+ /* prepare next part of packet to xref */
+ xfer_data_packet(ep_num, ep_dir, xfer);
+ }
+ }
- dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
+ USBHSD->INT_FG = (int_flag & (USBHS_ISO_ACT_FLAG | USBHS_TRANSFER_FLAG)); /* Clear flag */
+ } else if (int_flag & USBHS_SETUP_FLAG) {
+ ep_set_response_and_toggle(0, TUSB_DIR_IN, EP_RESPONSE_NAK);
+ ep_set_response_and_toggle(0, TUSB_DIR_OUT, EP_RESPONSE_NAK);
+ dcd_event_setup_received(0, ep0_buffer, true);
+
+ USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
+ } else if (int_flag & USBHS_BUS_RST_FLAG) {
+ // TODO CH32 does not detect actual speed at this time (should be known at end of reset)
+ // This interrupt probably triggered at start of bus reset
+// tusb_speed_t actual_speed;
+// switch(USBHSD->SPEED_TYPE & USBHS_SPEED_TYPE_MASK){
+// case USBHS_SPEED_TYPE_HIGH:
+// actual_speed = TUSB_SPEED_HIGH;
+// break;
+// case USBHS_SPEED_TYPE_FULL:
+// actual_speed = TUSB_SPEED_FULL;
+// break;
+// case USBHS_SPEED_TYPE_LOW:
+// actual_speed = TUSB_SPEED_LOW;
+// break;
+// default:
+// TU_ASSERT(0,);
+// break;
+// }
+// dcd_event_bus_reset(0, actual_speed, true);
+
+ dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
- USBHSD->DEV_AD = 0;
- USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
+ USBHSD->DEV_AD = 0;
+ EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
+ EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
- USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */
- } else if (intflag & USBHS_SUSPEND_FLAG) {
- dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND };
- dcd_event_handler(&event, true);
+ USBHSD->INT_FG = USBHS_BUS_RST_FLAG; /* Clear flag */
+ } else if (int_flag & USBHS_SUSPEND_FLAG) {
+ dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_SUSPEND};
+ dcd_event_handler(&event, true);
- USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */
- }
+ USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */
+ }
}
#endif
diff --git a/src/tusb.c b/src/tusb.c
index 0092267a19..e6f8055b7b 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -39,21 +39,58 @@
#include "host/usbh_pvt.h"
#endif
+#define TUP_USBIP_CONTROLLER_NUM 2
+
+static tusb_role_t _rhport_role[TUP_USBIP_CONTROLLER_NUM] = { 0 };
+
//--------------------------------------------------------------------+
// Public API
//--------------------------------------------------------------------+
-bool tusb_init(void) {
- #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
- // init device stack CFG_TUSB_RHPORTx_MODE must be defined
- TU_ASSERT ( tud_init(TUD_OPT_RHPORT) );
+bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ // backward compatible called with tusb_init(void)
+ #if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT)
+ if (rh_init == NULL) {
+ #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
+ // init device stack CFG_TUSB_RHPORTx_MODE must be defined
+ const tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL
+ };
+ TU_ASSERT ( tud_rhport_init(rhport, &dev_init) );
+ _rhport_role[TUD_OPT_RHPORT] = TUSB_ROLE_DEVICE;
+ #endif
+
+ #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT)
+ // init host stack CFG_TUSB_RHPORTx_MODE must be defined
+ const tusb_rhport_init_t host_init = {
+ .role = TUSB_ROLE_HOST,
+ .speed = TUH_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL
+ };
+ TU_ASSERT( tuh_rhport_init(TUH_OPT_RHPORT, &host_init) );
+ _rhport_role[TUH_OPT_RHPORT] = TUSB_ROLE_HOST;
+ #endif
+
+ return true;
+ }
#endif
- #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT)
- // init host stack CFG_TUSB_RHPORTx_MODE must be defined
- TU_ASSERT( tuh_init(TUH_OPT_RHPORT) );
+ // new API with explicit rhport and role
+ TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM && rh_init->role != TUSB_ROLE_INVALID);
+
+ #if CFG_TUD_ENABLED
+ if (rh_init->role == TUSB_ROLE_DEVICE) {
+ TU_ASSERT(tud_rhport_init(rhport, rh_init));
+ }
#endif
+ #if CFG_TUH_ENABLED
+ if (rh_init->role == TUSB_ROLE_HOST) {
+ TU_ASSERT(tuh_rhport_init(rhport, rh_init));
+ }
+ #endif
+
+ _rhport_role[rhport] = rh_init->role;
return true;
}
@@ -71,6 +108,23 @@ bool tusb_inited(void) {
return ret;
}
+void tusb_int_handler(uint8_t rhport, bool in_isr) {
+ TU_VERIFY(rhport < TUP_USBIP_CONTROLLER_NUM,);
+
+ #if CFG_TUD_ENABLED
+ if (_rhport_role[rhport] == TUSB_ROLE_DEVICE) {
+ (void) in_isr;
+ dcd_int_handler(rhport);
+ }
+ #endif
+
+ #if CFG_TUH_ENABLED
+ if (_rhport_role[rhport] == TUSB_ROLE_HOST) {
+ hcd_int_handler(rhport, in_isr);
+ }
+ #endif
+}
+
//--------------------------------------------------------------------+
// Descriptor helper
//--------------------------------------------------------------------+
@@ -216,13 +270,17 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf,
bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) {
- osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutexdef);
- (void) new_mutex;
(void) is_tx;
s->is_host = is_host;
tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable);
- tu_fifo_config_mutex(&s->ff, is_tx ? new_mutex : NULL, is_tx ? NULL : new_mutex);
+
+ #if OSAL_MUTEX_REQUIRED
+ if (ff_buf && ff_bufsize) {
+ osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutexdef);
+ tu_fifo_config_mutex(&s->ff, is_tx ? new_mutex : NULL, is_tx ? NULL : new_mutex);
+ }
+ #endif
s->ep_buf = ep_buf;
s->ep_bufsize = ep_bufsize;
@@ -239,43 +297,40 @@ bool tu_edpt_stream_deinit(tu_edpt_stream_t* s) {
return true;
}
-TU_ATTR_ALWAYS_INLINE static inline
-bool stream_claim(tu_edpt_stream_t* s) {
+TU_ATTR_ALWAYS_INLINE static inline bool stream_claim(uint8_t hwid, tu_edpt_stream_t* s) {
if (s->is_host) {
#if CFG_TUH_ENABLED
- return usbh_edpt_claim(s->daddr, s->ep_addr);
+ return usbh_edpt_claim(hwid, s->ep_addr);
#endif
} else {
#if CFG_TUD_ENABLED
- return usbd_edpt_claim(s->rhport, s->ep_addr);
+ return usbd_edpt_claim(hwid, s->ep_addr);
#endif
}
return false;
}
-TU_ATTR_ALWAYS_INLINE static inline
-bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) {
+TU_ATTR_ALWAYS_INLINE static inline bool stream_xfer(uint8_t hwid, tu_edpt_stream_t* s, uint16_t count) {
if (s->is_host) {
#if CFG_TUH_ENABLED
- return usbh_edpt_xfer(s->daddr, s->ep_addr, count ? s->ep_buf : NULL, count);
+ return usbh_edpt_xfer(hwid, s->ep_addr, count ? s->ep_buf : NULL, count);
#endif
} else {
#if CFG_TUD_ENABLED
- return usbd_edpt_xfer(s->rhport, s->ep_addr, count ? s->ep_buf : NULL, count);
+ return usbd_edpt_xfer(hwid, s->ep_addr, count ? s->ep_buf : NULL, count);
#endif
}
return false;
}
-TU_ATTR_ALWAYS_INLINE static inline
-bool stream_release(tu_edpt_stream_t* s) {
+TU_ATTR_ALWAYS_INLINE static inline bool stream_release(uint8_t hwid, tu_edpt_stream_t* s) {
if (s->is_host) {
#if CFG_TUH_ENABLED
- return usbh_edpt_release(s->daddr, s->ep_addr);
+ return usbh_edpt_release(hwid, s->ep_addr);
#endif
} else {
#if CFG_TUD_ENABLED
- return usbd_edpt_release(s->rhport, s->ep_addr);
+ return usbd_edpt_release(hwid, s->ep_addr);
#endif
}
return false;
@@ -284,83 +339,117 @@ bool stream_release(tu_edpt_stream_t* s) {
//--------------------------------------------------------------------+
// Stream Write
//--------------------------------------------------------------------+
-bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) {
+bool tu_edpt_stream_write_zlp_if_needed(uint8_t hwid, tu_edpt_stream_t* s, uint32_t last_xferred_bytes) {
// ZLP condition: no pending data, last transferred bytes is multiple of packet size
- TU_VERIFY(!tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize - 1))));
- TU_VERIFY(stream_claim(s));
- TU_ASSERT(stream_xfer(s, 0));
+ const uint16_t mps = s->is_mps512 ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+ TU_VERIFY(!tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (mps - 1))));
+ TU_VERIFY(stream_claim(hwid, s));
+ TU_ASSERT(stream_xfer(hwid, s, 0));
return true;
}
-uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) {
+uint32_t tu_edpt_stream_write_xfer(uint8_t hwid, tu_edpt_stream_t* s) {
// skip if no data
TU_VERIFY(tu_fifo_count(&s->ff), 0);
- // Claim the endpoint
- TU_VERIFY(stream_claim(s), 0);
+ TU_VERIFY(stream_claim(hwid, s), 0);
// Pull data from FIFO -> EP buf
uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
if (count) {
- TU_ASSERT(stream_xfer(s, count), 0);
+ TU_ASSERT(stream_xfer(hwid, s, count), 0);
return count;
} else {
// Release endpoint since we don't make any transfer
// Note: data is dropped if terminal is not connected
- stream_release(s);
+ stream_release(hwid, s);
return 0;
}
}
-uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const* buffer, uint32_t bufsize) {
+uint32_t tu_edpt_stream_write(uint8_t hwid, tu_edpt_stream_t* s, void const* buffer, uint32_t bufsize) {
TU_VERIFY(bufsize); // TODO support ZLP
- uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
- // flush if fifo has more than packet size or
- // in rare case: fifo depth is configured too small (which never reach packet size)
- if ((tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize)) {
- tu_edpt_stream_write_xfer(s);
+ if (0 == tu_fifo_depth(&s->ff)) {
+ // no fifo for buffered
+ TU_VERIFY(stream_claim(hwid, s), 0);
+ const uint32_t xact_len = tu_min32(bufsize, s->ep_bufsize);
+ memcpy(s->ep_buf, buffer, xact_len);
+ TU_ASSERT(stream_xfer(hwid, s, (uint16_t) xact_len), 0);
+ return xact_len;
+ } else {
+ const uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
+
+ // flush if fifo has more than packet size or
+ // in rare case: fifo depth is configured too small (which never reach packet size)
+ const uint16_t mps = s->is_mps512 ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+ if ((tu_fifo_count(&s->ff) >= mps) || (tu_fifo_depth(&s->ff) < mps)) {
+ tu_edpt_stream_write_xfer(hwid, s);
+ }
+ return ret;
}
+}
- return ret;
+uint32_t tu_edpt_stream_write_available(uint8_t hwid, tu_edpt_stream_t* s) {
+ if (tu_fifo_depth(&s->ff)) {
+ return (uint32_t) tu_fifo_remaining(&s->ff);
+ } else {
+ bool is_busy = true;
+ if (s->is_host) {
+ #if CFG_TUH_ENABLED
+ is_busy = usbh_edpt_busy(hwid, s->ep_addr);
+ #endif
+ } else {
+ #if CFG_TUD_ENABLED
+ is_busy = usbd_edpt_busy(hwid, s->ep_addr);
+ #endif
+ }
+ return is_busy ? 0 : s->ep_bufsize;
+ }
}
//--------------------------------------------------------------------+
// Stream Read
//--------------------------------------------------------------------+
-uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) {
- uint16_t available = tu_fifo_remaining(&s->ff);
-
- // Prepare for incoming data but only allow what we can store in the ring buffer.
- // TODO Actually we can still carry out the transfer, keeping count of received bytes
- // and slowly move it to the FIFO when read().
- // This pre-check reduces endpoint claiming
- TU_VERIFY(available >= s->ep_packetsize);
-
- // claim endpoint
- TU_VERIFY(stream_claim(s), 0);
-
- // get available again since fifo can be changed before endpoint is claimed
- available = tu_fifo_remaining(&s->ff);
-
- if (available >= s->ep_packetsize) {
- // multiple of packet size limit by ep bufsize
- uint16_t count = (uint16_t) (available & ~(s->ep_packetsize - 1));
- count = tu_min16(count, s->ep_bufsize);
-
- TU_ASSERT(stream_xfer(s, count), 0);
- return count;
+uint32_t tu_edpt_stream_read_xfer(uint8_t hwid, tu_edpt_stream_t* s) {
+ if (0 == tu_fifo_depth(&s->ff)) {
+ // no fifo for buffered
+ TU_VERIFY(stream_claim(hwid, s), 0);
+ TU_ASSERT(stream_xfer(hwid, s, s->ep_bufsize), 0);
+ return s->ep_bufsize;
} else {
- // Release endpoint since we don't make any transfer
- stream_release(s);
- return 0;
+ const uint16_t mps = s->is_mps512 ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+ uint16_t available = tu_fifo_remaining(&s->ff);
+
+ // Prepare for incoming data but only allow what we can store in the ring buffer.
+ // TODO Actually we can still carry out the transfer, keeping count of received bytes
+ // and slowly move it to the FIFO when read().
+ // This pre-check reduces endpoint claiming
+ TU_VERIFY(available >= mps);
+
+ TU_VERIFY(stream_claim(hwid, s), 0);
+
+ // get available again since fifo can be changed before endpoint is claimed
+ available = tu_fifo_remaining(&s->ff);
+
+ if (available >= mps) {
+ // multiple of packet size limit by ep bufsize
+ uint16_t count = (uint16_t) (available & ~(mps - 1));
+ count = tu_min16(count, s->ep_bufsize);
+ TU_ASSERT(stream_xfer(hwid, s, count), 0);
+ return count;
+ } else {
+ // Release endpoint since we don't make any transfer
+ stream_release(hwid, s);
+ return 0;
+ }
}
}
-uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) {
+uint32_t tu_edpt_stream_read(uint8_t hwid, tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) {
uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize);
- tu_edpt_stream_read_xfer(s);
+ tu_edpt_stream_read_xfer(hwid, s);
return num_read;
}
@@ -398,7 +487,7 @@ static void dump_str_line(uint8_t const* buf, uint16_t count) {
tu_printf(" |");
// each line is 16 bytes
for (uint16_t i = 0; i < count; i++) {
- const char ch = buf[i];
+ int ch = buf[i];
tu_printf("%c", isprint(ch) ? ch : '.');
}
tu_printf("|\r\n");
diff --git a/src/tusb.h b/src/tusb.h
index c9d56d3c30..2f30a57394 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -38,8 +38,6 @@
#include "osal/osal.h"
#include "common/tusb_fifo.h"
-#include "class/hid/hid.h"
-
//------------- TypeC -------------//
#if CFG_TUC_ENABLED
#include "typec/usbc.h"
@@ -132,17 +130,44 @@
// APPLICATION API
//--------------------------------------------------------------------+
-// Initialize device/host stack
+
+#if CFG_TUH_ENABLED || CFG_TUD_ENABLED
+
+// Internal helper for backward compatible with tusb_init(void)
+bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
+
+// Initialize roothub port with device/host role
// Note: when using with RTOS, this should be called after scheduler/kernel is started.
-// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
-bool tusb_init(void);
+// Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+// Note2: defined as macro for backward compatible with tusb_init(void), can be changed to function in the future.
+#if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT)
+ #define _tusb_init_arg0() tusb_rhport_init(0, NULL)
+#else
+ #define _tusb_init_arg0() TU_VERIFY_STATIC(false, "CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE must be defined")
+#endif
+
+#define _tusb_init_arg1(_rhport) _tusb_init_arg0()
+#define _tusb_init_arg2(_rhport, _rh_init) tusb_rhport_init(_rhport, _rh_init)
+#define tusb_init(...) TU_FUNC_OPTIONAL_ARG(_tusb_init, __VA_ARGS__)
// Check if stack is initialized
bool tusb_inited(void);
+// Called to handle usb interrupt/event. tusb_init(rhport, role) must be called before
+void tusb_int_handler(uint8_t rhport, bool in_isr);
+
// TODO
// bool tusb_teardown(void);
+#else
+
+#define tusb_init(...) (false)
+#define tusb_int_handler(...) do {}while(0)
+#define tusb_inited() (false)
+
+#endif
+
+
#ifdef __cplusplus
}
#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index cbcb69edd1..fdc9497476 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -29,14 +29,12 @@
#include "common/tusb_compiler.h"
-// Version is release as major.minor.revision eg 1.0.0. though there could be notable APIs before a new release.
-// For notable API changes within a release, we increase the build number.
+// Version is release as major.minor.revision eg 1.0.0
#define TUSB_VERSION_MAJOR 0
-#define TUSB_VERSION_MINOR 16
+#define TUSB_VERSION_MINOR 17
#define TUSB_VERSION_REVISION 0
-#define TUSB_VERSION_BUILD 3
-#define TUSB_VERSION_NUMBER (TUSB_VERSION_MAJOR << 24 | TUSB_VERSION_MINOR << 16 | TUSB_VERSION_REVISION << 8 | TUSB_VERSION_BUILD)
+#define TUSB_VERSION_NUMBER (TUSB_VERSION_MAJOR * 10000 + TUSB_VERSION_MINOR * 100 + TUSB_VERSION_REVISION)
#define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
//--------------------------------------------------------------------+
@@ -55,7 +53,8 @@
#define OPT_MCU_LPC18XX 6 ///< NXP LPC18xx
#define OPT_MCU_LPC40XX 7 ///< NXP LPC40xx
#define OPT_MCU_LPC43XX 8 ///< NXP LPC43xx
-#define OPT_MCU_LPC51UXX 9 ///< NXP LPC51U6x
+#define OPT_MCU_LPC51 9 ///< NXP LPC51
+#define OPT_MCU_LPC51UXX OPT_MCU_LPC51 ///< NXP LPC51
#define OPT_MCU_LPC54 10 ///< NXP LPC54
#define OPT_MCU_LPC55 11 ///< NXP LPC55
// legacy naming
@@ -92,6 +91,7 @@
#define OPT_MCU_STM32U5 313 ///< ST U5
#define OPT_MCU_STM32L5 314 ///< ST L5
#define OPT_MCU_STM32H5 315 ///< ST H5
+#define OPT_MCU_STM32U0 316 ///< ST U0
// Sony
#define OPT_MCU_CXD56 400 ///< SONY CXD56
@@ -119,6 +119,13 @@
// Espressif
#define OPT_MCU_ESP32S2 900 ///< Espressif ESP32-S2
#define OPT_MCU_ESP32S3 901 ///< Espressif ESP32-S3
+#define OPT_MCU_ESP32 902 ///< Espressif ESP32 (for host max3421e)
+#define OPT_MCU_ESP32C3 903 ///< Espressif ESP32-C3
+#define OPT_MCU_ESP32C6 904 ///< Espressif ESP32-C6
+#define OPT_MCU_ESP32C2 905 ///< Espressif ESP32-C2
+#define OPT_MCU_ESP32H2 906 ///< Espressif ESP32-H2
+#define OPT_MCU_ESP32P4 907 ///< Espressif ESP32-P4
+#define TUP_MCU_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU
// Dialog
#define OPT_MCU_DA1469X 1000 ///< Dialog Semiconductor DA1469x
@@ -176,12 +183,19 @@
// WCH
#define OPT_MCU_CH32V307 2200 ///< WCH CH32V307
#define OPT_MCU_CH32F20X 2210 ///< WCH CH32F20x
-
+#define OPT_MCU_CH32V20X 2220 ///< WCH CH32V20X
+#define OPT_MCU_CH32V103 2230 ///< WCH CH32V103
// NXP LPC MCX
#define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series
#define OPT_MCU_MCXA15 2301 ///< NXP MCX A15 Series
+// Analog Devices
+#define OPT_MCU_MAX32690 2400 ///< ADI MAX32690
+#define OPT_MCU_MAX32666 2401 ///< ADI MAX32666/5
+#define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2
+#define OPT_MCU_MAX78002 2403 ///< ADI MAX78002
+
// Check if configured MCU is one of listed
// Apply _TU_CHECK_MCU with || as separator to list of input
#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m)
@@ -199,19 +213,9 @@
#define OPT_OS_RTTHREAD 6 ///< RT-Thread
#define OPT_OS_RTX4 7 ///< Keil RTX 4
-// Allow to use command line to change the config name/location
-#ifdef CFG_TUSB_CONFIG_FILE
- #include CFG_TUSB_CONFIG_FILE
-#else
- #include "tusb_config.h"
-#endif
-
-#include "common/tusb_mcu.h"
-
-//--------------------------------------------------------------------
-// RootHub Mode Configuration
-// CFG_TUSB_RHPORTx_MODE contains operation mode and speed for that port
-//--------------------------------------------------------------------
+//--------------------------------------------------------------------+
+// Mode and Speed
+//--------------------------------------------------------------------+
// Low byte is operational mode
#define OPT_MODE_NONE 0x0000 ///< Disabled
@@ -225,7 +229,51 @@
#define OPT_MODE_HIGH_SPEED 0x0400 ///< High Speed
#define OPT_MODE_SPEED_MASK 0xff00
-//------------- Roothub as Device -------------//
+//--------------------------------------------------------------------+
+// Include tusb_config.h
+//--------------------------------------------------------------------+
+
+// Allow to use command line to change the config name/location
+#ifdef CFG_TUSB_CONFIG_FILE
+ #include CFG_TUSB_CONFIG_FILE
+#else
+ #include "tusb_config.h"
+#endif
+
+//--------------------------------------------------------------------+
+// USBIP
+//--------------------------------------------------------------------+
+
+// DWC2 controller: use DMA for data transfer
+// For processors with data cache enabled, USB endpoint buffer region
+// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
+// For example, on Cortex-M7 the MPU region can be configured as normal
+// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
+#ifndef CFG_TUD_DWC2_DMA
+ #define CFG_TUD_DWC2_DMA 0
+#endif
+
+// Enable PIO-USB software host controller
+#ifndef CFG_TUH_RPI_PIO_USB
+ #define CFG_TUH_RPI_PIO_USB 0
+#endif
+
+#ifndef CFG_TUD_RPI_PIO_USB
+ #define CFG_TUD_RPI_PIO_USB 0
+#endif
+
+// MAX3421 Host controller option
+#ifndef CFG_TUH_MAX3421
+ #define CFG_TUH_MAX3421 0
+#endif
+
+#include "common/tusb_mcu.h"
+
+//--------------------------------------------------------------------
+// RootHub Mode detection
+//--------------------------------------------------------------------
+
+//------------- Root hub as Device -------------//
#if defined(CFG_TUSB_RHPORT0_MODE) && ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE)
#define TUD_RHPORT_MODE (CFG_TUSB_RHPORT0_MODE)
@@ -253,7 +301,7 @@
// highspeed support indicator
#define TUD_OPT_HIGH_SPEED (CFG_TUD_MAX_SPEED ? (CFG_TUD_MAX_SPEED & OPT_MODE_HIGH_SPEED) : TUP_RHPORT_HIGHSPEED)
-//------------- Roothub as Host -------------//
+//------------- Root hub as Host -------------//
#if defined(CFG_TUSB_RHPORT0_MODE) && ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST)
#define TUH_RHPORT_MODE (CFG_TUSB_RHPORT0_MODE)
@@ -359,6 +407,20 @@
#define CFG_TUD_INTERFACE_MAX 16
#endif
+// default to max hardware endpoint, but can be smaller to save RAM
+#ifndef CFG_TUD_ENDPPOINT_MAX
+ #define CFG_TUD_ENDPPOINT_MAX TUP_DCD_ENDPOINT_MAX
+#endif
+
+#if CFG_TUD_ENDPPOINT_MAX > TUP_DCD_ENDPOINT_MAX
+ #error "CFG_TUD_ENDPPOINT_MAX must be less than or equal to TUP_DCD_ENDPOINT_MAX"
+#endif
+
+// USB 2.0 7.1.20: compliance test mode support
+#ifndef CFG_TUD_TEST_MODE
+ #define CFG_TUD_TEST_MODE 0
+#endif
+
//------------- Device Class Driver -------------//
#ifndef CFG_TUD_BTH
#define CFG_TUD_BTH 0
@@ -454,26 +516,26 @@
#define CFG_TUH_CDC 0
#endif
+// FTDI is not part of CDC class, only to re-use CDC driver API
#ifndef CFG_TUH_CDC_FTDI
- // FTDI is not part of CDC class, only to re-use CDC driver API
#define CFG_TUH_CDC_FTDI 0
#endif
+// List of product IDs that can use the FTDI CDC driver. 0x0403 is FTDI's VID
#ifndef CFG_TUH_CDC_FTDI_VID_PID_LIST
- // List of product IDs that can use the FTDI CDC driver. 0x0403 is FTDI's VID
#define CFG_TUH_CDC_FTDI_VID_PID_LIST \
{0x0403, 0x6001}, {0x0403, 0x6006}, {0x0403, 0x6010}, {0x0403, 0x6011}, \
{0x0403, 0x6014}, {0x0403, 0x6015}, {0x0403, 0x8372}, {0x0403, 0xFBFA}, \
{0x0403, 0xCD18}
#endif
+// CP210X is not part of CDC class, only to re-use CDC driver API
#ifndef CFG_TUH_CDC_CP210X
- // CP210X is not part of CDC class, only to re-use CDC driver API
#define CFG_TUH_CDC_CP210X 0
#endif
+// List of product IDs that can use the CP210X CDC driver. 0x10C4 is Silicon Labs' VID
#ifndef CFG_TUH_CDC_CP210X_VID_PID_LIST
- // List of product IDs that can use the CP210X CDC driver. 0x10C4 is Silicon Labs' VID
#define CFG_TUH_CDC_CP210X_VID_PID_LIST \
{0x10C4, 0xEA60}, {0x10C4, 0xEA70}
#endif
@@ -483,8 +545,8 @@
#define CFG_TUH_CDC_CH34X 0
#endif
+// List of product IDs that can use the CH34X CDC driver
#ifndef CFG_TUH_CDC_CH34X_VID_PID_LIST
- // List of product IDs that can use the CH34X CDC driver
#define CFG_TUH_CDC_CH34X_VID_PID_LIST \
{ 0x1a86, 0x5523 }, /* ch341 chip */ \
{ 0x1a86, 0x7522 }, /* ch340k chip */ \
@@ -515,20 +577,6 @@
#define CFG_TUH_API_EDPT_XFER 0
#endif
-// Enable PIO-USB software host controller
-#ifndef CFG_TUH_RPI_PIO_USB
- #define CFG_TUH_RPI_PIO_USB 0
-#endif
-
-#ifndef CFG_TUD_RPI_PIO_USB
- #define CFG_TUD_RPI_PIO_USB 0
-#endif
-
-// MAX3421 Host controller option
-#ifndef CFG_TUH_MAX3421
- #define CFG_TUH_MAX3421 0
-#endif
-
//--------------------------------------------------------------------+
// TypeC Options (Default)
//--------------------------------------------------------------------+
diff --git a/src/typec/tcd.h b/src/typec/tcd.h
index 86499c9516..bcbdab8ed2 100644
--- a/src/typec/tcd.h
+++ b/src/typec/tcd.h
@@ -63,7 +63,7 @@ typedef struct TU_ATTR_PACKED {
} xfer_complete;
};
-} tcd_event_t;;
+} tcd_event_t;
//--------------------------------------------------------------------+
//
diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc
index 06ddddc4a2..046a90555b 100644
--- a/test/fuzz/dcd_fuzz.cc
+++ b/test/fuzz/dcd_fuzz.cc
@@ -46,9 +46,10 @@ tu_static State state = {false, 0, 0};
// All no-ops as we are fuzzing.
//--------------------------------------------------------------------+
extern "C" {
-void dcd_init(uint8_t rhport) {
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
UNUSED(rhport);
- return;
+ UNUSED(rh_init);
+ return true;
}
void dcd_int_handler(uint8_t rhport) {
diff --git a/test/fuzz/net_fuzz.cc b/test/fuzz/net_fuzz.cc
index 63cd1ac98a..468437b0c8 100644
--- a/test/fuzz/net_fuzz.cc
+++ b/test/fuzz/net_fuzz.cc
@@ -69,14 +69,6 @@ void tud_network_init_cb(void) {
// TODO removed later since it is not part of tinyusb stack
uint8_t tud_network_mac_address[6] = {0};
-//------------- NCM -------------//
-
-// callback to client providing optional indication of internal state of network
-// driver
-void tud_network_link_state_cb(bool state) {
- (void)state;
- // NoOp.
-}
-}
+} // extern "C"
#endif
diff --git a/test/hil/hil_hfp.json b/test/hil/hfp.json
similarity index 100%
rename from test/hil/hil_hfp.json
rename to test/hil/hfp.json
diff --git a/test/hil/hil_ci_set_matrix.py b/test/hil/hil_ci_set_matrix.py
new file mode 100644
index 0000000000..192174e166
--- /dev/null
+++ b/test/hil/hil_ci_set_matrix.py
@@ -0,0 +1,43 @@
+import argparse
+import json
+import os
+
+
+def main():
+ parser = argparse.ArgumentParser()
+ parser.add_argument('config_file', help='Configuration JSON file')
+ args = parser.parse_args()
+
+ config_file = args.config_file
+
+ # if config file is not found, try to find it in the same directory as this script
+ if not os.path.exists(config_file):
+ config_file = os.path.join(os.path.dirname(__file__), config_file)
+ with open(config_file) as f:
+ config = json.load(f)
+
+ matrix = {
+ 'arm-gcc': [],
+ 'esp-idf': []
+ }
+ for board in config['boards']:
+ name = board['name']
+ if board['flasher'] == 'esptool':
+ toolchain = 'esp-idf'
+ else:
+ toolchain = 'arm-gcc'
+
+ if 'build' in board and 'flags_on' in board['build']:
+ for f in board['build']['flags_on']:
+ if f == '':
+ matrix[toolchain].append(f'-b {name}')
+ else:
+ matrix[toolchain].append(f'-b {name} -f1 {f.replace(" ", " -f1 ")}')
+ else:
+ matrix[toolchain].append(f'-b {name}')
+
+ print(json.dumps(matrix))
+
+
+if __name__ == '__main__':
+ main()
diff --git a/test/hil/hil_pi4.json b/test/hil/hil_pi4.json
deleted file mode 100644
index 8aff81910b..0000000000
--- a/test/hil/hil_pi4.json
+++ /dev/null
@@ -1,37 +0,0 @@
-{
- "boards": [
- {
- "name": "raspberry_pi_pico",
- "uid": "E6614C311B764A37",
- "flasher": "openocd",
- "flasher_sn": "E6614103E72C1D2F",
- "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\""
- },
- {
- "name": "espressif_s3_devkitm",
- "uid": "84F703C084E4",
- "tests": [
- "cdc_msc_freertos", "hid_composite_freertos"
- ],
- "flasher": "esptool",
- "flasher_sn": "3ea619acd1cdeb11a0a0b806e93fd3f1",
- "flasher_args": "-b 1500000"
- },
- {
- "name": "feather_nrf52840_express",
- "uid": "1F0479CD0F764471",
- "flasher": "jlink",
- "flasher_sn": "000682804350",
- "flasher_args": "-device nrf52840_xxaa"
- },
- {
- "name": "itsybitsy_m4",
- "uid": "D784B28C5338533335202020FF044726",
- "flasher": "bossac",
- "flashser_vendor": "Adafruit Industries",
- "flasher_product": "ItsyBitsy M4 Express",
- "flasher_reset_pin": "2",
- "flasher_args": "--offset 0x4000"
- }
- ]
-}
diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py
old mode 100644
new mode 100755
index 7f03ce43f1..0d7cae77e9
--- a/test/hil/hil_test.py
+++ b/test/hil/hil_test.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
#
# The MIT License (MIT)
#
@@ -25,24 +26,30 @@
# ACTION=="add", SUBSYSTEM=="tty", SUBSYSTEMS=="usb", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", SYMLINK+="ttyUSB_%c.%s{bInterfaceNumber}"
# ACTION=="add", SUBSYSTEM=="block", SUBSYSTEMS=="usb", ENV{ID_FS_USAGE}=="filesystem", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", RUN{program}+="/usr/bin/systemd-mount --no-block --automount=yes --collect $devnode /media/blkUSB_%c.%s{bInterfaceNumber}"
+import argparse
import os
+import re
import sys
import time
-import click
import serial
import subprocess
import json
import glob
+from multiprocessing import Pool
+import fs
-# for RPI double reset
-try:
- import gpiozero
-except ImportError:
- pass
+ENUM_TIMEOUT = 30
+STATUS_OK = "\033[32mOK\033[0m"
+STATUS_FAILED = "\033[31mFailed\033[0m"
+STATUS_SKIPPED = "\033[33mSkipped\033[0m"
-ENUM_TIMEOUT = 10
+verbose = False
+# -------------------------------------------------------------
+# Path
+# -------------------------------------------------------------
+OPENCOD_ADI_PATH = f'{os.getenv("HOME")}/app/openocd_adi'
# get usb serial by id
def get_serial_dev(id, vendor_str, product_str, ifnum):
@@ -58,9 +65,8 @@ def get_serial_dev(id, vendor_str, product_str, ifnum):
return port_list[0]
-# Currently not used, left as reference
+# get usb disk by id
def get_disk_dev(id, vendor_str, lun):
- # get usb disk by id
return f'/dev/disk/by-id/usb-{vendor_str}_Mass_Storage_{id}-0:{lun}'
@@ -77,113 +83,186 @@ def open_serial_dev(port):
# slight delay since kernel may occupy the port briefly
time.sleep(0.5)
timeout = timeout - 0.5
- ser = serial.Serial(port, timeout=1)
+ ser = serial.Serial(port, timeout=5)
break
except serial.SerialException:
pass
time.sleep(0.5)
timeout = timeout - 0.5
- assert timeout, 'Device not available or Cannot open port'
+
+ assert timeout, f'Cannot open port f{port}' if os.path.exists(port) else f'Port {port} not existed'
return ser
-def read_disk_file(id, fname):
- # on different self-hosted, the mount point is different
- file_list = [
- f'/media/blkUSB_{id[-8:]}.02/{fname}',
- f'/media/{os.getenv("USER")}/TinyUSB MSC/{fname}'
- ]
+def read_disk_file(uid, lun, fname):
+ # open_fs("fat://{dev}) require 'pip install pyfatfs'
+ dev = get_disk_dev(uid, 'TinyUSB', lun)
timeout = ENUM_TIMEOUT
while timeout:
- for file in file_list:
- if os.path.isfile(file):
- with open(file, 'rb') as f:
+ if os.path.exists(dev):
+ fat = fs.open_fs(f'fat://{dev}?read_only=true')
+ try:
+ with fat.open(fname, 'rb') as f:
data = f.read()
- return data
-
+ finally:
+ fat.close()
+ assert data, f'Cannot read file {fname} from {dev}'
+ return data
time.sleep(1)
- timeout = timeout - 1
+ timeout -= 1
- assert timeout, 'Device not available'
+ assert timeout, f'Storage {dev} not existed'
return None
# -------------------------------------------------------------
# Flashing firmware
# -------------------------------------------------------------
+def run_cmd(cmd, cwd=None):
+ r = subprocess.run(cmd, cwd=cwd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ if r.returncode != 0:
+ title = f'COMMAND FAILED: {cmd}'
+ print()
+ if os.getenv('CI'):
+ print(f"::group::{title}")
+ print(r.stdout.decode("utf-8"))
+ print(f"::endgroup::")
+ else:
+ print(title)
+ print(r.stdout.decode("utf-8"))
+ elif verbose:
+ print(cmd)
+ print(r.stdout.decode("utf-8"))
+ return r
+
+
def flash_jlink(board, firmware):
- script = ['halt', 'r', f'loadfile {firmware}', 'r', 'go', 'exit']
- with open('flash.jlink', 'w') as f:
+ script = ['halt', 'r', f'loadfile {firmware}.elf', 'r', 'go', 'exit']
+ f_jlink = f'{board["name"]}_{os.path.basename(firmware)}.jlink'
+ with open(f_jlink, 'w') as f:
f.writelines(f'{s}\n' for s in script)
- ret = subprocess.run(
- f'JLinkExe -USB {board["flasher_sn"]} {board["flasher_args"]} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink',
- shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
- os.remove('flash.jlink')
+ ret = run_cmd(f'JLinkExe -USB {board["flasher_sn"]} {board["flasher_args"]} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile {f_jlink}')
+ os.remove(f_jlink)
+ return ret
+
+
+def flash_stlink(board, firmware):
+ ret = run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={board["flasher_sn"]} --write {firmware}.elf --go')
+ return ret
+
+
+def flash_stflash(board, firmware):
+ ret = run_cmd(f'st-flash --serial {board["flasher_sn"]} write {firmware}.bin 0x8000000')
return ret
def flash_openocd(board, firmware):
- ret = subprocess.run(
- f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "program {firmware} reset exit"',
- shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ ret = run_cmd(f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "program {firmware}.elf reset exit"')
+ return ret
+
+
+def flash_openocd_wch(board, firmware):
+ # Content of the wch-riscv.cfg file
+ cfg_content = """
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
+"""
+ f_wch = f"wch-riscv_{board['uid']}.cfg"
+ if not os.path.exists(f_wch):
+ with open(f_wch, 'w') as file:
+ file.write(cfg_content)
+
+ ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} '
+ f'-c "program {firmware}.elf reset exit"')
+ return ret
+
+
+def flash_openocd_adi(board, firmware):
+ ret = run_cmd(f'{OPENCOD_ADI_PATH}/src/openocd -c "adapter serial {board["flasher_sn"]}" -s {OPENCOD_ADI_PATH}/tcl '
+ f'{board["flasher_args"]} -c "program {firmware}.elf reset exit"')
+ return ret
+
+def flash_wlink_rs(board, firmware):
+ # wlink use index for probe selection and lacking usb serial support
+ ret = run_cmd(f'wlink flash {firmware}.elf')
return ret
def flash_esptool(board, firmware):
port = get_serial_dev(board["flasher_sn"], None, None, 0)
- dir = os.path.dirname(firmware)
- with open(f'{dir}/config.env') as f:
- IDF_TARGET = json.load(f)['IDF_TARGET']
- with open(f'{dir}/flash_args') as f:
+ fw_dir = os.path.dirname(f'{firmware}.bin')
+ with open(f'{fw_dir}/config.env') as f:
+ idf_target = json.load(f)['IDF_TARGET']
+ with open(f'{fw_dir}/flash_args') as f:
flash_args = f.read().strip().replace('\n', ' ')
- command = (f'esptool.py --chip {IDF_TARGET} -p {port} {board["flasher_args"]} '
+ command = (f'esptool.py --chip {idf_target} -p {port} {board["flasher_args"]} '
f'--before=default_reset --after=hard_reset write_flash {flash_args}')
- ret = subprocess.run(command, shell=True, cwd=dir, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ ret = run_cmd(command, cwd=fw_dir)
return ret
-def doublereset_with_rpi_gpio(board):
- # Off = 0 = Reset
- led = gpiozero.LED(board["flasher_reset_pin"])
+def flash_uniflash(board, firmware):
+ ret = run_cmd(f'dslite.sh {board["flasher_args"]} -f {firmware}.hex')
+ return ret
- led.off()
- time.sleep(0.1)
- led.on()
- time.sleep(0.1)
- led.off()
- time.sleep(0.1)
- led.on()
-def flash_bossac(board, firmware):
- # double reset to enter bootloader
- doublereset_with_rpi_gpio(board)
+# -------------------------------------------------------------
+# Tests: dual
+# -------------------------------------------------------------
- port = get_serial_dev(board["uid"], board["flashser_vendor"], board["flasher_product"], 0)
- timeout = ENUM_TIMEOUT
- while timeout:
- if os.path.exists(port):
- break
+def test_dual_host_info_to_device_cdc(board):
+ uid = board['uid']
+ declared_devs = [f'{d["vid_pid"]}_{d["serial"]}' for d in board['tests']['dual_attached']]
+
+ port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0)
+ ser = open_serial_dev(port)
+ # read from cdc, first line should contain vid/pid and serial
+ data = ser.read(1000)
+ lines = data.decode('utf-8').splitlines()
+ enum_dev_sn = []
+ for l in lines:
+ vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l)
+ if vid_pid_sn:
+ print(f'\r\n {l} ', end='')
+ enum_dev_sn.append(f'{vid_pid_sn.group(1)}_{vid_pid_sn.group(2)}_{vid_pid_sn.group(3)}')
+
+ if set(declared_devs) != set(enum_dev_sn):
+ # for pico/pico2 make this test optional
+ failed_msg = f'Enumerated devices {enum_dev_sn} not match with declared {declared_devs}'
+ if 'raspberry_pi_pico' in board['name']:
+ print(f'\r\n {failed_msg} {STATUS_FAILED} ', end='')
else:
- time.sleep(0.5)
- timeout = timeout - 0.5
- assert timeout, 'bossac bootloader is not available'
- # sleep a bit more for bootloader to be ready
- time.sleep(0.5)
- ret = subprocess.run(f'bossac --port {port} {board["flasher_args"]} -U -i -R -e -w {firmware}', shell=True, stdout=subprocess.PIPE,
- stderr=subprocess.STDOUT)
- return ret
+ assert False, failed_msg
+ return 0
+
# -------------------------------------------------------------
-# Tests
+# Tests: device
# -------------------------------------------------------------
-def test_board_test(id):
+def test_device_board_test(board):
# Dummy test
pass
-def test_cdc_dual_ports(id):
- port1 = get_serial_dev(id, 'TinyUSB', "TinyUSB_Device", 0)
- port2 = get_serial_dev(id, 'TinyUSB', "TinyUSB_Device", 2)
+def test_device_cdc_dual_ports(board):
+ uid = board['uid']
+ port1 = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0)
+ port2 = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 2)
ser1 = open_serial_dev(port1)
ser2 = open_serial_dev(port2)
@@ -192,28 +271,29 @@ def test_cdc_dual_ports(id):
str1 = b"test_no1"
ser1.write(str1)
ser1.flush()
- assert ser1.read(100) == str1.lower(), 'Port1 wrong data'
- assert ser2.read(100) == str1.upper(), 'Port2 wrong data'
+ assert ser1.read(len(str1)) == str1.lower(), 'Port1 wrong data'
+ assert ser2.read(len(str1)) == str1.upper(), 'Port2 wrong data'
str2 = b"test_no2"
ser2.write(str2)
ser2.flush()
- assert ser1.read(100) == str2.lower(), 'Port1 wrong data'
- assert ser2.read(100) == str2.upper(), 'Port2 wrong data'
+ assert ser1.read(len(str2)) == str2.lower(), 'Port1 wrong data'
+ assert ser2.read(len(str2)) == str2.upper(), 'Port2 wrong data'
-def test_cdc_msc(id):
+def test_device_cdc_msc(board):
+ uid = board['uid']
# Echo test
- port = get_serial_dev(id, 'TinyUSB', "TinyUSB_Device", 0)
+ port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0)
ser = open_serial_dev(port)
str = b"test_str"
ser.write(str)
ser.flush()
- assert ser.read(100) == str, 'CDC wrong data'
+ assert ser.read(len(str)) == str, 'CDC wrong data'
# Block test
- data = read_disk_file(id, 'README.TXT')
+ data = read_disk_file(uid,0,'README.TXT')
readme = \
b"This is tinyusb's MassStorage Class demo.\r\n\r\n\
If you find any bugs or get any questions, feel free to file an\r\n\
@@ -222,57 +302,60 @@ def test_cdc_msc(id):
assert data == readme, 'MSC wrong data'
-def test_cdc_msc_freertos(id):
- test_cdc_msc(id)
+def test_device_cdc_msc_freertos(board):
+ test_device_cdc_msc(board)
+
+def test_device_dfu(board):
+ uid = board['uid']
-def test_dfu(id):
# Wait device enum
timeout = ENUM_TIMEOUT
while timeout:
- ret = subprocess.run(f'dfu-util -l',
- shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ ret = run_cmd(f'dfu-util -l')
stdout = ret.stdout.decode()
- if f'serial="{id}"' in stdout and 'Found DFU: [cafe:4000]' in stdout:
+ if f'serial="{uid}"' in stdout and 'Found DFU: [cafe:4000]' in stdout:
break
time.sleep(1)
timeout = timeout - 1
assert timeout, 'Device not available'
+ f_dfu0 = f'dfu0_{uid}'
+ f_dfu1 = f'dfu1_{uid}'
+
# Test upload
try:
- os.remove('dfu0')
- os.remove('dfu1')
+ os.remove(f_dfu0)
+ os.remove(f_dfu1)
except OSError:
pass
- ret = subprocess.run(f'dfu-util -S {id} -a 0 -U dfu0',
- shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ ret = run_cmd(f'dfu-util -S {uid} -a 0 -U {f_dfu0}')
assert ret.returncode == 0, 'Upload failed'
- ret = subprocess.run(f'dfu-util -S {id} -a 1 -U dfu1',
- shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ ret = run_cmd(f'dfu-util -S {uid} -a 1 -U {f_dfu1}')
assert ret.returncode == 0, 'Upload failed'
- with open('dfu0') as f:
+ with open(f_dfu0) as f:
assert 'Hello world from TinyUSB DFU! - Partition 0' in f.read(), 'Wrong uploaded data'
- with open('dfu1') as f:
+ with open(f_dfu1) as f:
assert 'Hello world from TinyUSB DFU! - Partition 1' in f.read(), 'Wrong uploaded data'
- os.remove('dfu0')
- os.remove('dfu1')
+ os.remove(f_dfu0)
+ os.remove(f_dfu1)
+
+def test_device_dfu_runtime(board):
+ uid = board['uid']
-def test_dfu_runtime(id):
# Wait device enum
timeout = ENUM_TIMEOUT
while timeout:
- ret = subprocess.run(f'dfu-util -l',
- shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ ret = run_cmd(f'dfu-util -l')
stdout = ret.stdout.decode()
- if f'serial="{id}"' in stdout and 'Found Runtime: [cafe:4000]' in stdout:
+ if f'serial="{uid}"' in stdout and 'Found Runtime: [cafe:4000]' in stdout:
break
time.sleep(1)
timeout = timeout - 1
@@ -280,10 +363,11 @@ def test_dfu_runtime(id):
assert timeout, 'Device not available'
-def test_hid_boot_interface(id):
- kbd = get_hid_dev(id, 'TinyUSB', 'TinyUSB_Device', 'event-kbd')
- mouse1 = get_hid_dev(id, 'TinyUSB', 'TinyUSB_Device', 'if01-event-mouse')
- mouse2 = get_hid_dev(id, 'TinyUSB', 'TinyUSB_Device', 'if01-mouse')
+def test_device_hid_boot_interface(board):
+ uid = board['uid']
+ kbd = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'event-kbd')
+ mouse1 = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'if01-event-mouse')
+ mouse2 = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'if01-mouse')
# Wait device enum
timeout = ENUM_TIMEOUT
while timeout:
@@ -292,10 +376,10 @@ def test_hid_boot_interface(id):
time.sleep(1)
timeout = timeout - 1
- assert timeout, 'Device not available'
+ assert timeout, 'HID device not available'
-def test_hid_composite_freertos(id):
+def test_device_hid_composite_freertos(id):
# TODO implement later
pass
@@ -303,82 +387,124 @@ def test_hid_composite_freertos(id):
# -------------------------------------------------------------
# Main
# -------------------------------------------------------------
-@click.command()
-@click.argument('config_file')
-@click.option('-b', '--board', multiple=True, default=None, help='Boards to test, all if not specified')
-def main(config_file, board):
- """
- Hardware test on specified boards
- """
- config_file = os.path.join(os.path.dirname(__file__), config_file)
- with open(config_file) as f:
- config = json.load(f)
-
- # all possible tests
- all_tests = [
- 'cdc_dual_ports', 'cdc_msc', 'dfu', 'dfu_runtime', 'hid_boot_interface',
- ]
-
- if len(board) == 0:
- config_boards = config['boards']
- else:
- config_boards = [e for e in config['boards'] if e['name'] in board]
-
- for item in config_boards:
- print(f'Testing board:{item["name"]}')
- flasher = item['flasher'].lower()
-
- # default to all tests
- if 'tests' in item:
- test_list = item['tests']
- else:
- test_list = all_tests
-
- # board_test is added last to disable board's usb
- test_list.append('board_test')
-
- # remove skip_tests
- if 'tests_skip' in item:
- for skip in item['tests_skip']:
+# device tests
+device_tests = [
+ 'device/cdc_dual_ports',
+ 'device/cdc_msc',
+ 'device/dfu',
+ 'device/cdc_msc_freertos', # don't test 2 cdc_msc next to each other
+ 'device/dfu_runtime',
+ 'device/hid_boot_interface',
+]
+
+dual_tests = [
+ 'dual/host_info_to_device_cdc',
+]
+
+
+def test_board(board):
+ name = board['name']
+ flasher = board['flasher'].lower()
+
+ # default to all tests
+ test_list = list(device_tests)
+
+ if 'tests' in board:
+ board_tests = board['tests']
+ if 'dual_attached' in board_tests:
+ test_list += dual_tests
+ if 'only' in board_tests:
+ test_list = board_tests['only']
+ if 'skip' in board_tests:
+ for skip in board_tests['skip']:
if skip in test_list:
test_list.remove(skip)
+ print(f'{name:25} {skip:30} ... Skip')
- for test in test_list:
- fw_list = [
- # cmake: esp32 & samd51 use .bin file
- f'cmake-build/cmake-build-{item["name"]}/device/{test}/{test}.elf',
- f'cmake-build/cmake-build-{item["name"]}/device/{test}/{test}.bin',
- # make
- f'examples/device/{test}/_build/{item["name"]}/{test}.elf'
- ]
-
- fw = None
- for f in fw_list:
- if os.path.isfile(f):
- fw = f
- break
+ # board_test is added last to disable board's usb
+ test_list.append('device/board_test')
- if fw is None:
- print(f'Cannot find binary file for {test}')
- sys.exit(-1)
+ err_count = 0
+ flags_on_list = [""]
+ if 'build' in board and 'flags_on' in board['build']:
+ flags_on_list = board['build']['flags_on']
- print(f' {test} ...', end='')
+ for f1 in flags_on_list:
+ f1_str = ""
+ if f1 != "":
+ f1_str = '-' + f1.replace(' ', '-')
+ for test in test_list:
+ fw_dir = f'cmake-build/cmake-build-{name}{f1_str}/{test}'
+ if not os.path.exists(fw_dir):
+ fw_dir = f'examples/cmake-build-{name}{f1_str}/{test}'
+ fw_name = f'{fw_dir}/{os.path.basename(test)}'
+ print(f'{name+f1_str:40} {test:30} ... ', end='')
+
+ if not os.path.exists(fw_dir):
+ print('Skip (no binary)')
+ continue
# flash firmware. It may fail randomly, retry a few times
for i in range(3):
- ret = globals()[f'flash_{flasher}'](item, fw)
+ ret = globals()[f'flash_{flasher}'](board, fw_name)
if ret.returncode == 0:
break
else:
print(f'Flashing failed, retry {i+1}')
time.sleep(1)
- assert ret.returncode == 0, 'Flash failed\n' + ret.stdout.decode()
+ if ret.returncode == 0:
+ try:
+ ret = globals()[f'test_{test.replace("/", "_")}'](board)
+ print('OK')
+ except Exception as e:
+ err_count += 1
+ print(STATUS_FAILED)
+ print(f' {e}')
+ else:
+ err_count += 1
+ print(f'Flash {STATUS_FAILED}')
+ return err_count
+
+
+def main():
+ """
+ Hardware test on specified boards
+ """
+ global verbose
+
+ duration = time.time()
+
+ parser = argparse.ArgumentParser()
+ parser.add_argument('config_file', help='Configuration JSON file')
+ parser.add_argument('-b', '--board', action='append', default=[], help='Boards to test, all if not specified')
+ parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output')
+ args = parser.parse_args()
+
+ config_file = args.config_file
+ boards = args.board
+ verbose = args.verbose
+
+ # if config file is not found, try to find it in the same directory as this script
+ if not os.path.exists(config_file):
+ config_file = os.path.join(os.path.dirname(__file__), config_file)
+ with open(config_file) as f:
+ config = json.load(f)
+
+ if len(boards) == 0:
+ config_boards = config['boards']
+ else:
+ config_boards = [e for e in config['boards'] if e['name'] in boards]
- # run test
- globals()[f'test_{test}'](item['uid'])
+ with Pool(processes=os.cpu_count()) as pool:
+ err_count = sum(pool.map(test_board, config_boards))
- print('OK')
+ duration = time.time() - duration
+ print()
+ print("-" * 30)
+ print(f'Total failed: {err_count} in {duration:.1f}s')
+ print("-" * 30)
+ sys.exit(err_count)
if __name__ == '__main__':
diff --git a/test/hil/requirements.txt b/test/hil/requirements.txt
new file mode 100644
index 0000000000..c33980c9da
--- /dev/null
+++ b/test/hil/requirements.txt
@@ -0,0 +1,2 @@
+fs
+pyfatfs
diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json
new file mode 100644
index 0000000000..2313f5d13c
--- /dev/null
+++ b/test/hil/tinyusb.json
@@ -0,0 +1,129 @@
+{
+ "boards": [
+ {
+ "name": "espressif_s3_devkitm",
+ "uid": "84F703C084E4",
+ "build" : {
+ "flags_on": ["", "CFG_TUD_DWC2_DMA"]
+ },
+ "tests": {
+ "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"]
+ },
+ "flasher": "esptool",
+ "flasher_sn": "3ea619acd1cdeb11a0a0b806e93fd3f1",
+ "flasher_args": "-b 1500000"
+ },
+ {
+ "name": "feather_nrf52840_express",
+ "uid": "1F0479CD0F764471",
+ "flasher": "jlink",
+ "flasher_sn": "000682804350",
+ "flasher_args": "-device nrf52840_xxaa"
+ },
+ {
+ "name": "max32666fthr",
+ "uid": "0C81464124010B20FF0A08CC2C",
+ "flasher": "openocd_adi",
+ "flasher_sn": "E6614C311B597D32",
+ "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg"
+ },
+ {
+ "name": "metro_m4_express",
+ "uid": "9995AD485337433231202020FF100A34",
+ "flasher": "jlink",
+ "flasher_sn": "123456",
+ "flasher_args": "-device ATSAMD51J19",
+ "tests": {
+ "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}]
+ }
+ },
+ {
+ "name": "lpcxpresso11u37",
+ "uid": "17121919",
+ "flasher": "jlink",
+ "flasher_sn": "000724441579",
+ "flasher_args": "-device LPC11U37/401"
+ },
+ {
+ "name": "ra4m1_ek",
+ "uid": "152E163038303131393346E46F26574B",
+ "tests": {
+ "skip": ["device/cdc_msc", "device/cdc_msc_freertos"]
+ },
+ "comment": "MSC is slow to enumerated #2602",
+ "flasher": "jlink",
+ "flasher_sn": "000831174392",
+ "flasher_args": "-device R7FA4M1AB"
+ },
+ {
+ "name": "raspberry_pi_pico",
+ "uid": "E6614C311B764A37",
+ "flasher": "openocd",
+ "flasher_sn": "E6614103E72C1D2F",
+ "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"",
+ "tests": {
+ "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002470"}]
+ }
+ },
+ {
+ "name": "raspberry_pi_pico2",
+ "uid": "560AE75E1C7152C9",
+ "flasher": "openocd",
+ "flasher_sn": "E6633861A3978538",
+ "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2350.cfg -c \"adapter speed 5000\"",
+ "tests": {
+ "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "533D004242"}]
+ }
+ },
+ {
+ "name": "stm32f072disco",
+ "uid": "3A001A001357364230353532",
+ "flasher": "jlink",
+ "flasher_sn": "779541626",
+ "flasher_args": "-device stm32f072rb"
+ },
+ {
+ "name": "stm32f407disco",
+ "uid": "30001A000647313332353735",
+ "build" : {
+ "flags_on": ["", "CFG_TUD_DWC2_DMA"]
+ },
+ "flasher": "jlink",
+ "flasher_sn": "000773661813",
+ "flasher_args": "-device stm32f407vg"
+ },
+ {
+ "name": "stm32g0b1nucleo",
+ "uid": "4D0038000450434E37343120",
+ "flasher": "openocd",
+ "flasher_sn": "066FFF495087534867063844",
+ "flasher_args": "-f interface/stlink.cfg -f target/stm32g0x.cfg"
+ }
+ ],
+ "boards-skip": [
+ {
+ "name": "stm32f769disco",
+ "uid": "21002F000F51363531383437",
+ "build" : {
+ "flags_on": ["", "CFG_TUD_DWC2_DMA"]
+ },
+ "flasher": "jlink",
+ "flasher_sn": "000778170924",
+ "flasher_args": "-device stm32f769ni"
+ },
+ {
+ "name": "mimxrt1015_evk",
+ "uid": "DC28F865D2111D228D00B0543A70463C",
+ "flasher": "jlink",
+ "flasher_sn": "000726284213",
+ "flasher_args": "-device MIMXRT1015DAF5A"
+ },
+ {
+ "name": "nanoch32v203",
+ "uid": "CDAB277B0FBC03E339E339E3",
+ "flasher": "openocd_wch",
+ "flasher_sn": "EBCA8F0670AF",
+ "flasher_args": ""
+ }
+ ]
+}
diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c
index a624185247..f2a4fa2958 100644
--- a/test/unit-test/test/device/msc/test_msc_device.c
+++ b/test/unit-test/test/device/msc/test_msc_device.c
@@ -197,10 +197,14 @@ void setUp(void)
dcd_int_disable_Ignore();
dcd_int_enable_Ignore();
- if ( !tud_inited() )
- {
- dcd_init_Expect(rhport);
- tusb_init();
+ if ( !tud_inited() ) {
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+
+ dcd_init_ExpectAndReturn(0, &dev_init, true);
+ tusb_init(0, &dev_init);
}
dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, false);
diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c
index 00950c5a99..9879cd4ba8 100644
--- a/test/unit-test/test/device/usbd/test_usbd.c
+++ b/test/unit-test/test/device/usbd/test_usbd.c
@@ -102,38 +102,38 @@ uint8_t const* desc_configuration;
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
-uint8_t const * tud_descriptor_device_cb(void)
-{
+uint8_t const * tud_descriptor_device_cb(void) {
return desc_device;
}
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index) {
return desc_configuration;
}
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
return NULL;
}
-void setUp(void)
-{
+void setUp(void) {
dcd_int_disable_Ignore();
dcd_int_enable_Ignore();
- if ( !tud_inited() )
- {
+ if ( !tud_inited() ) {
+ tusb_rhport_init_t dev_init = {
+ .role = TUSB_ROLE_DEVICE,
+ .speed = TUSB_SPEED_AUTO
+ };
+
mscd_init_Expect();
- dcd_init_Expect(rhport);
- tusb_init();
+ dcd_init_ExpectAndReturn(0, &dev_init, true);
+
+ tusb_init(0, &dev_init);
}
}
-void tearDown(void)
-{
+void tearDown(void) {
}
//--------------------------------------------------------------------+
diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py
old mode 100644
new mode 100755
index 00c0da8cc3..a8e5b27265
--- a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py
+++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py
@@ -1,4 +1,4 @@
-#! python3
+#!/usr/bin/env python3
# ==========================================
# Unity Project - A Test Framework for C
# Copyright (c) 2015 Alexander Mueller / XelaRellum@web.de
diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py
old mode 100644
new mode 100755
index 71dd568883..2379ad49a7
--- a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py
+++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
import sys
import os
from glob import glob
diff --git a/test/unit-test/vendor/ceedling/vendor/unity/src/unity_internals.h b/test/unit-test/vendor/ceedling/vendor/unity/src/unity_internals.h
index 2c91b6db1f..d66309f96d 100644
--- a/test/unit-test/vendor/ceedling/vendor/unity/src/unity_internals.h
+++ b/test/unit-test/vendor/ceedling/vendor/unity/src/unity_internals.h
@@ -632,14 +632,14 @@ void UnityAssertNumbersArrayWithin(const UNITY_UINT delta,
const UNITY_FLAGS_T flags);
#ifndef UNITY_EXCLUDE_SETJMP_H
-UNITY_NORETURN void UnityFail(const char* message, const UNITY_LINE_TYPE line);
-UNITY_NORETURN void UnityIgnore(const char* message, const UNITY_LINE_TYPE line);
+UNITY_NORETURN void UnityFail(const char* msg, const UNITY_LINE_TYPE line);
+UNITY_NORETURN void UnityIgnore(const char* msg, const UNITY_LINE_TYPE line);
#else
-void UnityFail(const char* message, const UNITY_LINE_TYPE line);
-void UnityIgnore(const char* message, const UNITY_LINE_TYPE line);
+void UnityFail(const char* msg, const UNITY_LINE_TYPE line);
+void UnityIgnore(const char* msg, const UNITY_LINE_TYPE line);
#endif
-void UnityMessage(const char* message, const UNITY_LINE_TYPE line);
+void UnityMessage(const char* msg, const UNITY_LINE_TYPE line);
#ifndef UNITY_EXCLUDE_FLOAT
void UnityAssertFloatsWithin(const UNITY_FLOAT delta,
diff --git a/tools/build.py b/tools/build.py
new file mode 100755
index 0000000000..91d4ebd303
--- /dev/null
+++ b/tools/build.py
@@ -0,0 +1,259 @@
+#!/usr/bin/env python3
+import argparse
+import random
+import os
+import sys
+import time
+import subprocess
+from pathlib import Path
+from multiprocessing import Pool
+
+import build_utils
+
+STATUS_OK = "\033[32mOK\033[0m"
+STATUS_FAILED = "\033[31mFailed\033[0m"
+STATUS_SKIPPED = "\033[33mSkipped\033[0m"
+
+RET_OK = 0
+RET_FAILED = 1
+RET_SKIPPED = 2
+
+build_format = '| {:30} | {:40} | {:16} | {:5} |'
+build_separator = '-' * 95
+build_status = [STATUS_OK, STATUS_FAILED, STATUS_SKIPPED]
+
+verbose = False
+
+# -----------------------------
+# Helper
+# -----------------------------
+def run_cmd(cmd):
+ #print(cmd)
+ r = subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+ title = f'Command Error: {cmd}'
+ if r.returncode != 0:
+ # print build output if failed
+ if os.getenv('GITHUB_ACTIONS'):
+ print(f"::group::{title}")
+ print(r.stdout.decode("utf-8"))
+ print(f"::endgroup::")
+ else:
+ print(title)
+ print(r.stdout.decode("utf-8"))
+ elif verbose:
+ print(cmd)
+ print(r.stdout.decode("utf-8"))
+ return r
+
+
+def find_family(board):
+ bsp_dir = Path("hw/bsp")
+ for family_dir in bsp_dir.iterdir():
+ if family_dir.is_dir():
+ board_dir = family_dir / 'boards' / board
+ if board_dir.exists():
+ return family_dir.name
+ return None
+
+
+def get_examples(family):
+ all_examples = []
+ for d in os.scandir("examples"):
+ if d.is_dir() and 'cmake' not in d.name and 'build_system' not in d.name:
+ for entry in os.scandir(d.path):
+ if entry.is_dir() and 'cmake' not in entry.name:
+ if family != 'espressif' or 'freertos' in entry.name:
+ all_examples.append(d.name + '/' + entry.name)
+
+ if family == 'espressif':
+ all_examples.append('device/board_test')
+ all_examples.append('device/video_capture')
+ all_examples.sort()
+ return all_examples
+
+
+def print_build_result(board, example, status, duration):
+ if isinstance(duration, (int, float)):
+ duration = "{:.2f}s".format(duration)
+ print(build_format.format(board, example, build_status[status], duration))
+
+# -----------------------------
+# CMake
+# -----------------------------
+def cmake_board(board, toolchain, build_flags_on):
+ ret = [0, 0, 0]
+ start_time = time.monotonic()
+
+ build_dir = f'cmake-build/cmake-build-{board}'
+ build_flags = ''
+ if len(build_flags_on) > 0:
+ build_flags = ' '.join(f'-D{flag}=1' for flag in build_flags_on)
+ build_flags = f'-DCFLAGS_CLI="{build_flags}"'
+ build_dir += '-' + '-'.join(build_flags_on)
+
+ family = find_family(board)
+ if family == 'espressif':
+ # for espressif, we have to build example individually
+ all_examples = get_examples(family)
+ for example in all_examples:
+ if build_utils.skip_example(example, board):
+ ret[2] += 1
+ else:
+ rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" '
+ f'-DBOARD={board} {build_flags}')
+ if rcmd.returncode == 0:
+ rcmd = run_cmd(f'cmake --build {build_dir}/{example}')
+ ret[0 if rcmd.returncode == 0 else 1] += 1
+ else:
+ rcmd = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel '
+ f'-DTOOLCHAIN={toolchain} {build_flags}')
+ if rcmd.returncode == 0:
+ rcmd = run_cmd(f"cmake --build {build_dir}")
+ ret[0 if rcmd.returncode == 0 else 1] += 1
+
+ example = 'all'
+ print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
+ return ret
+
+
+# -----------------------------
+# Make
+# -----------------------------
+def make_one_example(example, board, make_option):
+ # Check if board is skipped
+ if build_utils.skip_example(example, board):
+ print_build_result(board, example, 2, '-')
+ r = 2
+ else:
+ start_time = time.monotonic()
+ # skip -j for circleci
+ if not os.getenv('CIRCLECI'):
+ make_option += ' -j'
+ make_cmd = f"make -C examples/{example} BOARD={board} {make_option}"
+ # run_cmd(f"{make_cmd} clean")
+ build_result = run_cmd(f"{make_cmd} all")
+ r = 0 if build_result.returncode == 0 else 1
+ print_build_result(board, example, r, time.monotonic() - start_time)
+
+ ret = [0, 0, 0]
+ ret[r] = 1
+ return ret
+
+
+def make_board(board, toolchain):
+ print(build_separator)
+ all_examples = get_examples(find_family(board))
+ start_time = time.monotonic()
+ ret = [0, 0, 0]
+ with Pool(processes=os.cpu_count()) as pool:
+ pool_args = list((map(lambda e, b=board, o=f"TOOLCHAIN={toolchain}": [e, b, o], all_examples)))
+ r = pool.starmap(make_one_example, pool_args)
+ # sum all element of same index (column sum)
+ ret = list(map(sum, list(zip(*r))))
+ example = 'all'
+ print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
+ return ret
+
+
+# -----------------------------
+# Build Family
+# -----------------------------
+def build_boards_list(boards, toolchain, build_system, build_flags_on):
+ ret = [0, 0, 0]
+ for b in boards:
+ r = [0, 0, 0]
+ if build_system == 'cmake':
+ r = cmake_board(b, toolchain, build_flags_on)
+ elif build_system == 'make':
+ r = make_board(b, toolchain)
+ ret[0] += r[0]
+ ret[1] += r[1]
+ ret[2] += r[2]
+ return ret
+
+
+def build_family(family, toolchain, build_system, build_flags_on, one_per_family, boards):
+ all_boards = []
+ for entry in os.scandir(f"hw/bsp/{family}/boards"):
+ if entry.is_dir() and entry.name != 'pico_sdk':
+ all_boards.append(entry.name)
+ all_boards.sort()
+
+ ret = [0, 0, 0]
+ # If only-one flag is set, select one random board
+ if one_per_family:
+ for b in boards:
+ # skip if -b already specify one in this family
+ if find_family(b) == family:
+ return ret
+ all_boards = [random.choice(all_boards)]
+
+ ret = build_boards_list(all_boards, toolchain, build_system, build_flags_on)
+ return ret
+
+
+# -----------------------------
+# Main
+# -----------------------------
+def main():
+ global verbose
+
+ parser = argparse.ArgumentParser()
+ parser.add_argument('families', nargs='*', default=[], help='Families to build')
+ parser.add_argument('-b', '--board', action='append', default=[], help='Boards to build')
+ parser.add_argument('-t', '--toolchain', default='gcc', help='Toolchain to use, default is gcc')
+ parser.add_argument('-s', '--build-system', default='cmake', help='Build system to use, default is cmake')
+ parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Build flag to pass to build system')
+ parser.add_argument('-1', '--one-per-family', action='store_true', default=False, help='Build only one random board inside a family')
+ parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output')
+ args = parser.parse_args()
+
+ families = args.families
+ boards = args.board
+ toolchain = args.toolchain
+ build_system = args.build_system
+ build_flags_on = args.build_flags_on
+ one_per_family = args.one_per_family
+ verbose = args.verbose
+
+ if len(families) == 0 and len(boards) == 0:
+ print("Please specify families or board to build")
+ return 1
+
+ print(build_separator)
+ print(build_format.format('Board', 'Example', '\033[39mResult\033[0m', 'Time'))
+ total_time = time.monotonic()
+ result = [0, 0, 0]
+
+ # build families
+ all_families = []
+ if 'all' in families:
+ for entry in os.scandir("hw/bsp"):
+ if entry.is_dir() and entry.name != 'espressif' and os.path.isfile(entry.path + "/family.cmake"):
+ all_families.append(entry.name)
+ else:
+ all_families = list(families)
+ all_families.sort()
+
+ # succeeded, failed, skipped
+ for f in all_families:
+ r = build_family(f, toolchain, build_system, build_flags_on, one_per_family, boards)
+ result[0] += r[0]
+ result[1] += r[1]
+ result[2] += r[2]
+
+ # build boards
+ r = build_boards_list(boards, toolchain, build_system, build_flags_on)
+ result[0] += r[0]
+ result[1] += r[1]
+ result[2] += r[2]
+
+ total_time = time.monotonic() - total_time
+ print(build_separator)
+ print(f"Build Summary: {result[0]} {STATUS_OK}, {result[1]} {STATUS_FAILED} and took {total_time:.2f}s")
+ print(build_separator)
+ return result[1]
+
+
+if __name__ == '__main__':
+ sys.exit(main())
diff --git a/tools/build_board.py b/tools/build_board.py
deleted file mode 100644
index 13376d1267..0000000000
--- a/tools/build_board.py
+++ /dev/null
@@ -1,69 +0,0 @@
-import os
-import sys
-import time
-import subprocess
-from multiprocessing import Pool
-
-import build_utils
-
-SUCCEEDED = "\033[32msucceeded\033[0m"
-FAILED = "\033[31mfailed\033[0m"
-SKIPPED = "\033[33mskipped\033[0m"
-
-build_separator = '-' * 106
-
-
-def filter_with_input(mylist):
- if len(sys.argv) > 1:
- input_args = list(set(mylist).intersection(sys.argv))
- if len(input_args) > 0:
- mylist[:] = input_args
-
-
-if __name__ == '__main__':
- # If examples are not specified in arguments, build all
- all_examples = []
- for dir1 in os.scandir("examples"):
- if dir1.is_dir():
- for entry in os.scandir(dir1.path):
- if entry.is_dir():
- all_examples.append(dir1.name + '/' + entry.name)
- filter_with_input(all_examples)
- all_examples.sort()
-
- # If boards are not specified in arguments, build all
- all_boards = []
- for entry in os.scandir("hw/bsp"):
- if entry.is_dir() and os.path.exists(entry.path + "/board.mk"):
- all_boards.append(entry.name)
- filter_with_input(all_boards)
- all_boards.sort()
-
- # Get dependencies
- for b in all_boards:
- subprocess.run("make -C examples/device/board_test BOARD={} get-deps".format(b), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
- print(build_separator)
- print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
- total_time = time.monotonic()
-
- # succeeded, failed, skipped
- total_result = [0, 0, 0]
- for example in all_examples:
- print(build_separator)
- with Pool(processes=os.cpu_count()) as pool:
- pool_args = list((map(lambda b, e=example, o='': [e, b, o], all_boards)))
- result = pool.starmap(build_utils.build_example, pool_args)
- # sum all element of same index (column sum)
- result = list(map(sum, list(zip(*result))))
-
- # add to total result
- total_result = list(map(lambda x, y: x + y, total_result, result))
-
- total_time = time.monotonic() - total_time
- print(build_separator)
- print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1],
- FAILED, total_result[2], SKIPPED, total_time))
- print(build_separator)
-
- sys.exit(total_result[1])
diff --git a/tools/build_cmake.py b/tools/build_cmake.py
deleted file mode 100644
index e539b9f940..0000000000
--- a/tools/build_cmake.py
+++ /dev/null
@@ -1,105 +0,0 @@
-import os
-import sys
-import time
-import subprocess
-import pathlib
-from multiprocessing import Pool
-
-import build_utils
-
-SUCCEEDED = "\033[32msucceeded\033[0m"
-FAILED = "\033[31mfailed\033[0m"
-SKIPPED = "\033[33mskipped\033[0m"
-
-build_separator = '-' * 106
-
-def filter_with_input(mylist):
- if len(sys.argv) > 1:
- input_args = list(set(mylist).intersection(sys.argv))
- if len(input_args) > 0:
- mylist[:] = input_args
-
-
-def build_family(family, cmake_option):
- all_boards = []
- for entry in os.scandir("hw/bsp/{}/boards".format(family)):
- if entry.is_dir() and entry.name != 'pico_sdk':
- all_boards.append(entry.name)
- all_boards.sort()
-
- # success, failed, skipped
- ret = [0, 0, 0]
- for board in all_boards:
- start_time = time.monotonic()
-
- build_dir = f"cmake-build/cmake-build-{board}"
-
- # Generate build
- r = subprocess.run(f"cmake examples -B {build_dir} -G \"Ninja\" -DFAMILY={family} -DBOARD"
- f"={board} {cmake_option}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
- # Build
- if r.returncode == 0:
- r = subprocess.run(f"cmake --build {build_dir}", shell=True, stdout=subprocess.PIPE,
- stderr=subprocess.STDOUT)
-
- duration = time.monotonic() - start_time
-
- if r.returncode == 0:
- status = SUCCEEDED
- ret[0] += 1
- else:
- status = FAILED
- ret[1] += 1
-
- flash_size = "-"
- sram_size = "-"
- example = 'all'
- title = build_utils.build_format.format(example, board, status, "{:.2f}s".format(duration), flash_size, sram_size)
-
- if os.getenv('CI'):
- # always print build output if in CI
- print(f"::group::{title}")
- print(r.stdout.decode("utf-8"))
- print(f"::endgroup::")
- else:
- # print build output if failed
- print(title)
- if r.returncode != 0:
- print(r.stdout.decode("utf-8"))
-
- return ret
-
-
-if __name__ == '__main__':
- cmake_options = ''
- for a in sys.argv[1:]:
- if a.startswith('-'):
- cmake_options += ' ' + a
-
- # If family are not specified in arguments, build all supported
- all_families = []
- for entry in os.scandir("hw/bsp"):
- if entry.is_dir() and entry.name != 'espressif' and os.path.isfile(entry.path + "/family.cmake"):
- all_families.append(entry.name)
- filter_with_input(all_families)
- all_families.sort()
-
- print(build_separator)
- print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
- total_time = time.monotonic()
-
- # succeeded, failed, skipped
- total_result = [0, 0, 0]
- for family in all_families:
- fret = build_family(family, cmake_options)
- if len(fret) == len(total_result):
- total_result = [total_result[i] + fret[i] for i in range(len(fret))]
-
- total_time = time.monotonic() - total_time
- print(build_separator)
- print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1],
- FAILED, total_result[2], SKIPPED, total_time))
- print(build_separator)
-
- sys.exit(total_result[1])
diff --git a/tools/build_esp32.py b/tools/build_esp32.py
deleted file mode 100644
index 951467c23c..0000000000
--- a/tools/build_esp32.py
+++ /dev/null
@@ -1,106 +0,0 @@
-import os
-import glob
-import sys
-import subprocess
-import time
-
-import build_utils
-
-SUCCEEDED = "\033[32msucceeded\033[0m"
-FAILED = "\033[31mfailed\033[0m"
-SKIPPED = "\033[33mskipped\033[0m"
-
-success_count = 0
-fail_count = 0
-skip_count = 0
-exit_status = 0
-
-total_time = time.monotonic()
-
-build_format = '| {:30} | {:30} | {:18} | {:7} | {:6} | {:6} |'
-build_separator = '-' * 107
-
-def filter_with_input(mylist):
- if len(sys.argv) > 1:
- input_args = list(set(mylist).intersection(sys.argv))
- if len(input_args) > 0:
- mylist[:] = input_args
-
-
-# Build all examples if not specified
-all_examples = [entry.replace('examples/', '') for entry in glob.glob("examples/*/*_freertos")]
-filter_with_input(all_examples)
-all_examples.append('device/board_test')
-all_examples.sort()
-
-# Build all boards if not specified
-all_boards = []
-for entry in os.scandir("hw/bsp/espressif/boards"):
- if entry.is_dir():
- all_boards.append(entry.name)
-filter_with_input(all_boards)
-all_boards.sort()
-
-def build_board(example, board):
- global success_count, fail_count, skip_count, exit_status
- start_time = time.monotonic()
-
- # Check if board is skipped
- build_dir = f"cmake-build/cmake-build-{board}/{example}"
-
- # Generate and build
- r = subprocess.run(f"cmake examples/{example} -B {build_dir} -G \"Ninja\" -DBOARD={board} -DMAX3421_HOST=1",
- shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
- if r.returncode == 0:
- r = subprocess.run(f"cmake --build {build_dir}", shell=True, stdout=subprocess.PIPE,
- stderr=subprocess.STDOUT)
- build_duration = time.monotonic() - start_time
- flash_size = "-"
- sram_size = "-"
-
- if r.returncode == 0:
- success = SUCCEEDED
- success_count += 1
- #(flash_size, sram_size) = build_size(example, board)
- else:
- exit_status = r.returncode
- success = FAILED
- fail_count += 1
-
- title = build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size)
- if os.getenv('CI'):
- # always print build output if in CI
- print(f"::group::{title}")
- print(r.stdout.decode("utf-8"))
- print(f"::endgroup::")
- else:
- # print build output if failed
- print(title)
- if r.returncode != 0:
- print(r.stdout.decode("utf-8"))
-
-
-def build_size(example, board):
- #elf_file = 'examples/device/{}/_build/{}/{}-firmware.elf'.format(example, board, board)
- elf_file = 'examples/device/{}/_build/{}/*.elf'.format(example, board)
- size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
- size_list = size_output.split('\n')[1].split('\t')
- flash_size = int(size_list[0])
- sram_size = int(size_list[1]) + int(size_list[2])
- return (flash_size, sram_size)
-
-
-print(build_separator)
-print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
-print(build_separator)
-
-for example in all_examples:
- for board in all_boards:
- build_board(example, board)
-
-total_time = time.monotonic() - total_time
-print(build_separator)
-print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(success_count, SUCCEEDED, fail_count, FAILED, skip_count, SKIPPED, total_time))
-print(build_separator)
-
-sys.exit(exit_status)
diff --git a/tools/build_make.py b/tools/build_make.py
deleted file mode 100644
index 240fc8d640..0000000000
--- a/tools/build_make.py
+++ /dev/null
@@ -1,80 +0,0 @@
-import os
-import sys
-import time
-from multiprocessing import Pool
-
-import build_utils
-
-SUCCEEDED = "\033[32msucceeded\033[0m"
-FAILED = "\033[31mfailed\033[0m"
-SKIPPED = "\033[33mskipped\033[0m"
-
-build_separator = '-' * 106
-
-
-def filter_with_input(mylist):
- if len(sys.argv) > 1:
- input_args = list(set(mylist).intersection(sys.argv))
- if len(input_args) > 0:
- mylist[:] = input_args
-
-
-def build_family(example, family, make_option):
- all_boards = []
- for entry in os.scandir("hw/bsp/{}/boards".format(family)):
- if entry.is_dir() and entry.name != 'pico_sdk':
- all_boards.append(entry.name)
- filter_with_input(all_boards)
- all_boards.sort()
-
- with Pool(processes=os.cpu_count()) as pool:
- pool_args = list((map(lambda b, e=example, o=make_option: [e, b, o], all_boards)))
- result = pool.starmap(build_utils.build_example, pool_args)
- # sum all element of same index (column sum)
- return list(map(sum, list(zip(*result))))
-
-
-if __name__ == '__main__':
- make_option = ''
- for a in sys.argv:
- if 'TOOLCHAIN=' in sys.argv:
- make_option += ' ' + a
-
- # If examples are not specified in arguments, build all
- all_examples = []
- for d in os.scandir("examples"):
- if d.is_dir() and 'cmake' not in d.name and 'build_system' not in d.name:
- for entry in os.scandir(d.path):
- if entry.is_dir() and 'cmake' not in entry.name:
- all_examples.append(d.name + '/' + entry.name)
- filter_with_input(all_examples)
- all_examples.sort()
-
- # If family are not specified in arguments, build all
- all_families = []
- for entry in os.scandir("hw/bsp"):
- if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name != 'espressif':
- all_families.append(entry.name)
- filter_with_input(all_families)
- all_families.sort()
-
- print(build_separator)
- print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
- total_time = time.monotonic()
-
- # succeeded, failed, skipped
- total_result = [0, 0, 0]
- for example in all_examples:
- print(build_separator)
- for family in all_families:
- fret = build_family(example, family, make_option)
- if len(fret) == len(total_result):
- total_result = [total_result[i] + fret[i] for i in range(len(fret))]
-
- total_time = time.monotonic() - total_time
- print(build_separator)
- print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1],
- FAILED, total_result[2], SKIPPED, total_time))
- print(build_separator)
-
- sys.exit(total_result[1])
diff --git a/tools/build_utils.py b/tools/build_utils.py
old mode 100644
new mode 100755
index b66b64b975..5462829e2b
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
import subprocess
import pathlib
import time
@@ -13,33 +14,25 @@ def skip_example(example, board):
ex_dir = pathlib.Path('examples/') / example
bsp = pathlib.Path("hw/bsp")
- if (bsp / board / "board.mk").exists():
- # board without family
- board_dir = bsp / board
- family = ""
- mk_contents = ""
- else:
- # board within family
- board_dir = list(bsp.glob("*/boards/" + board))
- if not board_dir:
- # Skip unknown boards
- return True
-
- board_dir = list(board_dir)[0]
+ # board within family
+ board_dir = list(bsp.glob("*/boards/" + board))
+ if not board_dir:
+ # Skip unknown boards
+ return True
- family_dir = board_dir.parent.parent
- family = family_dir.name
+ board_dir = list(board_dir)[0]
+ family_dir = board_dir.parent.parent
+ family = family_dir.name
- # family.mk
- family_mk = family_dir / "family.mk"
- mk_contents = family_mk.read_text()
+ # family.mk
+ family_mk = family_dir / "family.mk"
+ mk_contents = family_mk.read_text()
# Find the mcu, first in family mk then board mk
if "CFG_TUSB_MCU=OPT_MCU_" not in mk_contents:
- board_mk = board_dir / "board.cmake"
+ board_mk = board_dir / "board.mk"
if not board_mk.exists():
- board_mk = board_dir / "board.mk"
-
+ board_mk = board_dir / "board.cmake"
mk_contents = board_mk.read_text()
mcu = "NONE"
@@ -49,18 +42,23 @@ def skip_example(example, board):
token = token.strip("\"")
_, opt_mcu = token.split("=")
mcu = opt_mcu[len("OPT_MCU_"):]
- break
if "esp32s2" in token:
mcu = "ESP32S2"
- break
if "esp32s3" in token:
mcu = "ESP32S3"
+ if mcu != "NONE":
break
# Skip all OPT_MCU_NONE these are WIP port
if mcu == "NONE":
return True
+ max3421_enabled = False
+ for line in mk_contents.splitlines():
+ if "MAX3421_HOST=1" in line or 'MAX3421_HOST 1' in line:
+ max3421_enabled = True
+ break
+
skip_file = ex_dir / "skip.txt"
only_file = ex_dir / "only.txt"
@@ -74,6 +72,7 @@ def skip_example(example, board):
if only_file.exists():
onlys = only_file.read_text().split()
if not ("mcu:" + mcu in onlys or
+ ("mcu:MAX3421" in onlys and max3421_enabled) or
"board:" + board in onlys or
"family:" + family in onlys):
return True
@@ -81,43 +80,6 @@ def skip_example(example, board):
return False
-def build_example(example, board, make_option):
- start_time = time.monotonic()
- flash_size = "-"
- sram_size = "-"
-
- # succeeded, failed, skipped
- ret = [0, 0, 0]
-
- make_cmd = "make -j -C examples/{} BOARD={} {}".format(example, board, make_option)
-
- # Check if board is skipped
- if skip_example(example, board):
- status = SKIPPED
- ret[2] = 1
- print(build_format.format(example, board, status, '-', flash_size, sram_size))
- else:
- #subprocess.run(make_cmd + " clean", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
- build_result = subprocess.run(make_cmd + " all", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
- if build_result.returncode == 0:
- status = SUCCEEDED
- ret[0] = 1
- (flash_size, sram_size) = build_size(make_cmd)
- #subprocess.run(make_cmd + " copy-artifact", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
- else:
- status = FAILED
- ret[1] = 1
-
- build_duration = time.monotonic() - start_time
- print(build_format.format(example, board, status, "{:.2f}s".format(build_duration), flash_size, sram_size))
-
- if build_result.returncode != 0:
- print(build_result.stdout.decode("utf-8"))
-
- return ret
-
-
def build_size(make_cmd):
size_output = subprocess.run(make_cmd + ' size', shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8").splitlines()
for i, l in enumerate(size_output):
diff --git a/tools/gen_doc.py b/tools/gen_doc.py
old mode 100644
new mode 100755
index c632945884..c69f3ff293
--- a/tools/gen_doc.py
+++ b/tools/gen_doc.py
@@ -1,3 +1,4 @@
+#!/usr/bin/env python3
import pandas as pd
from tabulate import tabulate
from pathlib import Path
@@ -7,9 +8,9 @@
TOP = Path(__file__).parent.parent.resolve()
-###########################################
+# -----------------------------------------
# Dependencies
-###########################################
+# -----------------------------------------
def gen_deps_doc():
deps_rst = Path(TOP) / "docs/reference/dependencies.rst"
diff --git a/tools/get_deps.py b/tools/get_deps.py
old mode 100644
new mode 100755
index bf6ef8c00d..519cb1d534
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -1,3 +1,5 @@
+#!/usr/bin/env python3
+import argparse
import sys
import subprocess
from pathlib import Path
@@ -13,7 +15,7 @@
'159e31b689577dbf69cf0683bbaffbd71fa5ee10',
'all'],
'tools/uf2': ['https://github.com/microsoft/uf2.git',
- '19615407727073e36d81bf239c52108ba92e7660',
+ 'c594542b2faa01cc33a2b97c9fbebc38549df80a',
'all'],
}
@@ -23,6 +25,9 @@
'hw/mcu/allwinner': ['https://github.com/hathach/allwinner_driver.git',
'8e5e89e8e132c0fd90e72d5422e5d3d68232b756',
'fc100s'],
+ 'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git',
+ 'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75',
+ 'max32650 max32666 max32690 max78002'],
'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git',
'91060164afe239fcb394122e8bf9eb24d3194eb1',
'brtmm90x'],
@@ -37,9 +42,9 @@
'xmc4000'],
'hw/mcu/microchip': ['https://github.com/hathach/microchip_driver.git',
'9e8b37e307d8404033bb881623a113931e1edf27',
- 'sam3x samd11 samd21 samd51 same5x same7x saml2x samg'],
+ 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg'],
'hw/mcu/mindmotion/mm32sdk': ['https://github.com/hathach/mm32sdk.git',
- '0b79559eb411149d36e073c1635c620e576308d4',
+ 'b93e856211060ae825216c6a1d6aa347ec758843',
'mm32'],
'hw/mcu/nordic/nrfx': ['https://github.com/NordicSemiconductor/nrfx.git',
'7c47cc0a56ce44658e6da2458e86cd8783ccc4a2',
@@ -48,13 +53,13 @@
'2204191ec76283371419fbcec207da02e1bc22fa',
'nuc'],
'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git',
- '04bfe7a5f6ee74a89a28ad618d3367dcfcfb7d83',
+ 'b41cf930e65c734d8ec6de04f1d57d46787c76ae',
'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
'144f1eb7ea8c06512e12f12b27383601c0272410',
'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
- '0f747aaa0c16f750bdfa2ba37ec25d6c8e1bc117',
+ 'fe9133fc513b82cc3dc62c67cb51f2339cf29ef7',
'rp2040'],
'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
'd52e5a6a59b7c638da860c2bb309b6e78e752ff8',
@@ -166,9 +171,15 @@
'stm32wb'],
'hw/mcu/ti': ['https://github.com/hathach/ti_driver.git',
'143ed6cc20a7615d042b03b21e070197d473e6e5',
- 'msp430 msp432e4 tm4c123'],
+ 'msp430 msp432e4 tm4c'],
+ 'hw/mcu/wch/ch32v103': ['https://github.com/openwch/ch32v103.git',
+ '7578cae0b21f86dd053a1f781b2fc6ab99d0ec17',
+ 'ch32v10x'],
+ 'hw/mcu/wch/ch32v20x': ['https://github.com/openwch/ch32v20x.git',
+ 'c4c38f507e258a4e69b059ccc2dc27dde33cea1b',
+ 'ch32v20x'],
'hw/mcu/wch/ch32v307': ['https://github.com/openwch/ch32v307.git',
- '17761f5cf9dbbf2dcf665b7c04934188add20082',
+ '184f21b852cb95eed58e86e901837bc9fff68775',
'ch32v307'],
'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git',
'77c4095087e5ed2c548ec9058e655d0b8757663b',
@@ -179,7 +190,8 @@
'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'
'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5'
'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'
- 'sam3x samd11 samd21 samd51 same5x same7x saml2x samg'],
+ 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg'
+ 'tm4c'],
'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
'e73e04ca63495672d955f9268e003cffe168fcd8',
'lpc55'],
@@ -226,27 +238,60 @@ def get_a_dep(d):
return 0
-# Arguments can be
-# - family name
-# - specific deps path
-# - all
-if __name__ == "__main__":
+def find_family(board):
+ bsp_dir = Path(TOP / "hw/bsp")
+ for family_dir in bsp_dir.iterdir():
+ if family_dir.is_dir():
+ board_dir = family_dir / 'boards' / board
+ if board_dir.exists():
+ return family_dir.name
+ return None
+
+
+def main():
+ parser = argparse.ArgumentParser()
+ parser.add_argument('families', nargs='*', default=[], help='Families to fetch')
+ parser.add_argument('-b', '--board', action='append', default=[], help='Boards to fetch')
+ parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Have no effect')
+ parser.add_argument('--print', action='store_true', help='Print commit hash only')
+ args = parser.parse_args()
+
+ families = args.families
+ boards = args.board
+ print_only = args.print
+
status = 0
deps = list(deps_mandatory.keys())
- # get all if 'all' is argument
- if len(sys.argv) == 2 and sys.argv[1] == 'all':
+
+ if 'all' in families:
deps += deps_optional.keys()
else:
- for arg in sys.argv[1:]:
- if arg in deps_all.keys():
- # if arg is a dep, add it
- deps.append(arg)
- else:
- # arg is a family name, add all deps of that family
- for d in deps_optional:
- if arg in deps_optional[d][2]:
- deps.append(d)
-
- with Pool() as pool:
- status = sum(pool.map(get_a_dep, deps))
- sys.exit(status)
+ families = list(families)
+ if boards is not None:
+ for b in boards:
+ f = find_family(b)
+ if f is not None:
+ families.append(f)
+
+ for f in families:
+ for d in deps_optional:
+ if d not in deps and f in deps_optional[d][2]:
+ deps.append(d)
+
+ if print_only:
+ pvalue = {}
+ # print only without arguments, always add CMSIS_5
+ if len(families) == 0 and len(boards) == 0:
+ deps.append('lib/CMSIS_5')
+ for d in deps:
+ commit = deps_all[d][1]
+ pvalue[d] = commit
+ print(pvalue)
+ else:
+ with Pool() as pool:
+ status = sum(pool.map(get_a_dep, deps))
+ return status
+
+
+if __name__ == "__main__":
+ sys.exit(main())
diff --git a/tools/iar_gen.py b/tools/iar_gen.py
old mode 100644
new mode 100755
index 264dd9a586..8d45659db4
--- a/tools/iar_gen.py
+++ b/tools/iar_gen.py
@@ -1,4 +1,4 @@
-#!/usr/bin/python3
+#!/usr/bin/env python3
import os
import sys
@@ -56,6 +56,7 @@ def Main():
def ListPath(path, blacklist=[]):
# Get all .c files
files = glob.glob(f'../{path}/**/*.c', recursive=True)
+ files.extend(glob.glob(f'../{path}/**/*.h', recursive=True))
# Filter
files = [x for x in files if all(y not in x for y in blacklist)]
# Get common dir list
@@ -77,6 +78,8 @@ def List():
ListPath('lib/SEGGER_RTT')
if __name__ == "__main__":
+ if os.path.dirname(os.getcwd()) != 'tools':
+ os.chdir('tools')
if (len(sys.argv) > 1):
if (sys.argv[1] == 'l'):
List()
diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index c3683c3d7c..33a6ef045b 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -10,57 +10,101 @@
$TUSB_DIR$/src/tusb.c
+ $TUSB_DIR$/src/tusb.h
+ $TUSB_DIR$/src/tusb_option.h
$TUSB_DIR$/src/class/audio/audio_device.c
+ $TUSB_DIR$/src/class/audio/audio.h
+ $TUSB_DIR$/src/class/audio/audio_device.h
$TUSB_DIR$/src/class/bth/bth_device.c
+ $TUSB_DIR$/src/class/bth/bth_device.h
$TUSB_DIR$/src/class/cdc/cdc_device.c
$TUSB_DIR$/src/class/cdc/cdc_host.c
$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c
+ $TUSB_DIR$/src/class/cdc/cdc.h
+ $TUSB_DIR$/src/class/cdc/cdc_device.h
+ $TUSB_DIR$/src/class/cdc/cdc_host.h
+ $TUSB_DIR$/src/class/cdc/cdc_rndis.h
+ $TUSB_DIR$/src/class/cdc/cdc_rndis_host.h
$TUSB_DIR$/src/class/dfu/dfu_device.c
$TUSB_DIR$/src/class/dfu/dfu_rt_device.c
+ $TUSB_DIR$/src/class/dfu/dfu.h
+ $TUSB_DIR$/src/class/dfu/dfu_device.h
+ $TUSB_DIR$/src/class/dfu/dfu_rt_device.h
$TUSB_DIR$/src/class/hid/hid_device.c
$TUSB_DIR$/src/class/hid/hid_host.c
+ $TUSB_DIR$/src/class/hid/hid.h
+ $TUSB_DIR$/src/class/hid/hid_device.h
+ $TUSB_DIR$/src/class/hid/hid_host.h
$TUSB_DIR$/src/class/midi/midi_device.c
+ $TUSB_DIR$/src/class/midi/midi.h
+ $TUSB_DIR$/src/class/midi/midi_device.h
$TUSB_DIR$/src/class/msc/msc_device.c
$TUSB_DIR$/src/class/msc/msc_host.c
+ $TUSB_DIR$/src/class/msc/msc.h
+ $TUSB_DIR$/src/class/msc/msc_device.h
+ $TUSB_DIR$/src/class/msc/msc_host.h
$TUSB_DIR$/src/class/net/ecm_rndis_device.c
$TUSB_DIR$/src/class/net/ncm_device.c
+ $TUSB_DIR$/src/class/net/ncm.h
+ $TUSB_DIR$/src/class/net/net_device.h
$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c
+ $TUSB_DIR$/src/class/usbtmc/usbtmc.h
+ $TUSB_DIR$/src/class/usbtmc/usbtmc_device.h
$TUSB_DIR$/src/class/vendor/vendor_device.c
$TUSB_DIR$/src/class/vendor/vendor_host.c
+ $TUSB_DIR$/src/class/vendor/vendor_device.h
+ $TUSB_DIR$/src/class/vendor/vendor_host.h
$TUSB_DIR$/src/class/video/video_device.c
+ $TUSB_DIR$/src/class/video/video.h
+ $TUSB_DIR$/src/class/video/video_device.h
$TUSB_DIR$/src/common/tusb_fifo.c
+ $TUSB_DIR$/src/common/tusb_common.h
+ $TUSB_DIR$/src/common/tusb_compiler.h
+ $TUSB_DIR$/src/common/tusb_debug.h
+ $TUSB_DIR$/src/common/tusb_fifo.h
+ $TUSB_DIR$/src/common/tusb_mcu.h
+ $TUSB_DIR$/src/common/tusb_private.h
+ $TUSB_DIR$/src/common/tusb_types.h
+ $TUSB_DIR$/src/common/tusb_verify.h
$TUSB_DIR$/src/device/usbd.c
$TUSB_DIR$/src/device/usbd_control.c
+ $TUSB_DIR$/src/device/dcd.h
+ $TUSB_DIR$/src/device/usbd.h
+ $TUSB_DIR$/src/device/usbd_pvt.h
$TUSB_DIR$/src/host/hub.c
$TUSB_DIR$/src/host/usbh.c
+ $TUSB_DIR$/src/host/hcd.h
+ $TUSB_DIR$/src/host/hub.h
+ $TUSB_DIR$/src/host/usbh.h
+ $TUSB_DIR$/src/host/usbh_pvt.h
$TUSB_DIR$/src/portable/analog/max3421/hcd_max3421.c
@@ -70,26 +114,39 @@
$TUSB_DIR$/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+ $TUSB_DIR$/src/portable/chipidea/ci_fs/ci_fs_kinetis.h
+ $TUSB_DIR$/src/portable/chipidea/ci_fs/ci_fs_mcx.h
+ $TUSB_DIR$/src/portable/chipidea/ci_fs/ci_fs_type.h
$TUSB_DIR$/src/portable/chipidea/ci_hs/dcd_ci_hs.c
$TUSB_DIR$/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+ $TUSB_DIR$/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+ $TUSB_DIR$/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+ $TUSB_DIR$/src/portable/chipidea/ci_hs/ci_hs_mcx.h
+ $TUSB_DIR$/src/portable/chipidea/ci_hs/ci_hs_type.h
$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c
$TUSB_DIR$/src/portable/ehci/ehci.c
+ $TUSB_DIR$/src/portable/ehci/ehci.h
+ $TUSB_DIR$/src/portable/ehci/ehci_api.h
$TUSB_DIR$/src/portable/mentor/musb/dcd_musb.c
$TUSB_DIR$/src/portable/mentor/musb/hcd_musb.c
+ $TUSB_DIR$/src/portable/mentor/musb/musb_msp432e.h
+ $TUSB_DIR$/src/portable/mentor/musb/musb_tm4c.h
+ $TUSB_DIR$/src/portable/mentor/musb/musb_type.h
$TUSB_DIR$/src/portable/microchip/pic/dcd_pic.c
$TUSB_DIR$/src/portable/microchip/pic32mz/dcd_pic32mz.c
+ $TUSB_DIR$/src/portable/microchip/pic32mz/usbhs_registers.h
$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c
@@ -99,6 +156,7 @@
$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c
+ $TUSB_DIR$/src/portable/microchip/samx7x/common_usb_regs.h
$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -122,12 +180,14 @@
$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+ $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
$TUSB_DIR$/src/portable/ohci/ohci.c
+ $TUSB_DIR$/src/portable/ohci/ohci.h
$TUSB_DIR$/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -137,42 +197,79 @@
$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c
$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c
$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c
+ $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.h
$TUSB_DIR$/src/portable/renesas/rusb2/dcd_rusb2.c
$TUSB_DIR$/src/portable/renesas/rusb2/hcd_rusb2.c
$TUSB_DIR$/src/portable/renesas/rusb2/rusb2_common.c
+ $TUSB_DIR$/src/portable/renesas/rusb2/rusb2_ra.h
+ $TUSB_DIR$/src/portable/renesas/rusb2/rusb2_rx.h
+ $TUSB_DIR$/src/portable/renesas/rusb2/rusb2_type.h
$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c
$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+ $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
$TUSB_DIR$/src/portable/st/typec/typec_stm32.c
$TUSB_DIR$/src/portable/sunxi/dcd_sunxi_musb.c
+ $TUSB_DIR$/src/portable/sunxi/musb_def.h
$TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c
+ $TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_bcm.h
+ $TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_efm32.h
+ $TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_esp32.h
+ $TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_gd32.h
+ $TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_stm32.h
+ $TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_type.h
+ $TUSB_DIR$/src/portable/synopsys/dwc2/dwc2_xmc.h
$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c
+ $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.h
+ $TUSB_DIR$/src/portable/wch/dcd_ch32_usbfs.c
$TUSB_DIR$/src/portable/wch/dcd_ch32_usbhs.c
+ $TUSB_DIR$/src/portable/wch/ch32_usbhs_reg.h
$TUSB_DIR$/src/typec/usbc.c
+ $TUSB_DIR$/src/typec/pd_types.h
+ $TUSB_DIR$/src/typec/tcd.h
+ $TUSB_DIR$/src/typec/usbc.h
+
+
+ $TUSB_DIR$/src/class/cdc/serial/ch34x.h
+ $TUSB_DIR$/src/class/cdc/serial/cp210x.h
+ $TUSB_DIR$/src/class/cdc/serial/ftdi_sio.h
+
+
+ $TUSB_DIR$/src/osal/osal.h
+ $TUSB_DIR$/src/osal/osal_freertos.h
+ $TUSB_DIR$/src/osal/osal_mynewt.h
+ $TUSB_DIR$/src/osal/osal_none.h
+ $TUSB_DIR$/src/osal/osal_pico.h
+ $TUSB_DIR$/src/osal/osal_rtthread.h
+ $TUSB_DIR$/src/osal/osal_rtx4.h
$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c
+ $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
+
+
+ $TUSB_DIR$/lib/SEGGER_RTT/Config/SEGGER_RTT_Conf.h
diff --git a/tools/make_release.py b/tools/make_release.py
old mode 100644
new mode 100755
index 256ca8f21d..92c75baf93
--- a/tools/make_release.py
+++ b/tools/make_release.py
@@ -1,6 +1,8 @@
+#!/usr/bin/env python3
import re
+import gen_doc
-version = '0.16.0'
+version = '0.17.0'
print('version {}'.format(version))
ver_id = version.split('.')
@@ -46,4 +48,6 @@
# docs/info/changelog.rst
###################
+gen_doc.gen_deps_doc()
+
print("Update docs/info/changelog.rst")
diff --git a/tools/mksunxi.py b/tools/mksunxi.py
old mode 100644
new mode 100755
diff --git a/tools/pcapng_to_corpus.py b/tools/pcapng_to_corpus.py
index 9c31365ebf..3089f0bb65 100755
--- a/tools/pcapng_to_corpus.py
+++ b/tools/pcapng_to_corpus.py
@@ -1,4 +1,4 @@
-#!/bin/python3
+#!/usr/bin/env python3
import argparse
import pcapng
import zipfile