From f5e2e6c89c4a5b95b4751a22882d90126cb05f26 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 9 Oct 2023 11:48:50 -0700 Subject: [PATCH 01/10] Adding documentation. Signed-off-by: Tim 'mithro' Ansell --- pdk/README.md | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 pdk/README.md diff --git a/pdk/README.md b/pdk/README.md new file mode 100644 index 00000000..4c847f81 --- /dev/null +++ b/pdk/README.md @@ -0,0 +1,56 @@ +# PDKs (Process Design Kits) + +The current PDKs supported by `bazel_rules_hdl` are; + * [SkyWater 130nm](../dependency_support/com_google_skywater_pdk/) + * [ASAP7](../dependency_support/org_theopenroadproject_asap7/) + +## Adding new PDK + +Adding a new PDK involves 3 things; + + 1) Adding PDK repository to the `../dependency_support` directory which + exports the required files via `filegroup` build rules. + + 2) Adding `open_road_pdk_configuration` `BUILD` rule(s). + + 3) Adding basic tests that confirm the PDK is usable. + (a) Add synthesis test under `//synthesis/tests` + (b) Add flow test under `//flows/tests` + +### File groups + +File groups should be grouped by file usage. + +Some groups which might be created are; + * Simulation + * `v_XXX` - Verilog models for digital simulation (& logical equivalence). + * `spice_XXX` - Analog models for spice simulation. + + * Digital place and route + * `lef_XXX` - Components in LEF format. + * `lef_tech` - Additional misc LEF cells which are needed for place and route. + * `lib_XXXX` (or `libgz_XXXX`) - Timing information in (compressed) Liberty + format (used for synthesis and static timing analysis STA). + + * `gds_XXX` - Actual layouts used for GDS generation and potentially + parasitics extraction. + + * `lvs_XXX` - Logic verse Schematic (LVS) checking. + +`XXX` can be; + * `cells` - Standard cells + * `sram` - SRAM blocks + + +### Cell Library Naming + +Cell library naming should be; + * `--` - examples include; + * `asap7-rvt-tt` + * `asap7`: ASAP 7nm predictive PDK. + * `sc7p5t` : 7.5 track standard cells + * `tt`: Typical corner. + * `sky130-hdll-ff_025C_1v50` + * `sky130`: SkyWater 130nm process technology. + * `hdll`: High density, low leakage standard cells. + * `ff_025C_1v50` : Fast corner at 25 degrees C and 1.5 volts. From 427c7b04156c3df543a0d52b2326143d3572e984 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Fri, 6 Oct 2023 16:34:23 -0700 Subject: [PATCH 02/10] Adding all ASAP7 standard cell libraries. Signed-off-by: Tim 'mithro' Ansell --- .../org_theopenroadproject_asap7/BUILD | 3 +- .../asap7-sc6t_rev26-common.bzl | 34 + .../asap7-sc6t_rev26_lvt-cells.bzl | 69 ++ .../asap7-sc6t_rev26_rvt-cells.bzl | 69 ++ .../asap7-sc6t_rev26_slvt-cells.bzl | 69 ++ .../asap7-sc7p5t_rev27-common.bzl | 34 + .../asap7-sc7p5t_rev27_lvt-cells.bzl | 70 ++ .../asap7-sc7p5t_rev27_rvt-cells.bzl | 70 ++ .../asap7-sc7p5t_rev27_rvt_4x-cells.bzl | 129 ++++ .../asap7-sc7p5t_rev27_slvt-cells.bzl | 70 ++ .../asap7-sc7p5t_rev28-common.bzl | 33 + .../asap7-sc7p5t_rev28_lvt-cells.bzl | 69 ++ .../asap7-sc7p5t_rev28_rvt-cells.bzl | 69 ++ .../asap7-sc7p5t_rev28_slvt-cells.bzl | 69 ++ .../org_theopenroadproject_asap7/asap7.bzl | 141 +++- .../build-BUILD.py | 81 +++ .../bundled.BUILD.bazel | 687 +++++++++++++++++- .../{pdn_config.pdn => pdn_config_1x.pdn} | 0 .../pdn_config_4x.pdn | 44 ++ synthesis/tests/BUILD | 344 ++++++++- 20 files changed, 2120 insertions(+), 34 deletions(-) create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26-common.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_lvt-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_rvt-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_slvt-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27-common.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_lvt-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_slvt-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28-common.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_lvt-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_rvt-cells.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_slvt-cells.bzl create mode 100755 dependency_support/org_theopenroadproject_asap7/build-BUILD.py rename dependency_support/org_theopenroadproject_asap7/{pdn_config.pdn => pdn_config_1x.pdn} (100%) create mode 100644 dependency_support/org_theopenroadproject_asap7/pdn_config_4x.pdn diff --git a/dependency_support/org_theopenroadproject_asap7/BUILD b/dependency_support/org_theopenroadproject_asap7/BUILD index ac93c942..d664b872 100644 --- a/dependency_support/org_theopenroadproject_asap7/BUILD +++ b/dependency_support/org_theopenroadproject_asap7/BUILD @@ -15,6 +15,7 @@ exports_files([ "tracks.tcl", "rc_script.tcl", - "pdn_config.pdn", + "pdn_config_1x.pdn", # FIXME: Where did this come from? + "pdn_config_4x.pdn", # FIXME: Where did this come from? "asap7.lyt", # Imported from OpenROAD-flow-scripts on 24.07.2023 at 6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8 from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8/flow/platforms/asap7/KLayout/asap7.lyt ]) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26-common.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26-common.bzl new file mode 100644 index 00000000..57c55414 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26-common.bzl @@ -0,0 +1,34 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +########################################################################## +# ASAP7 "rev 26" 6 track standard cell library with SRAM blocks. +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc6t_rev26", + rev = "26", + tracks = "6t", +) + +filegroup( + name = "asap7-misc-sc6t_rev26-lef", + # FIXME: Where is the 1x techlef? + srcs = ["asap7sc6t_26/techlef_misc/asap7sc6t_tech_4x_210831.lef"], +) + +filegroup( + name = "asap7-misc-sc6t_rev26_4x-lef", + srcs = ["asap7sc6t_26/techlef_misc/asap7sc6t_tech_4x_210831.lef"], +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_lvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_lvt-cells.bzl new file mode 100644 index 00000000..e599b13d --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_lvt-cells.bzl @@ -0,0 +1,69 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 26" 6 track standard cell library using low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_lvt", + rev = "26", + tracks = "6t", + vt = "lvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_lvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_rvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_rvt-cells.bzl new file mode 100644 index 00000000..554e4c2d --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_rvt-cells.bzl @@ -0,0 +1,69 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 26" 6 track standard cell library using regular VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_rvt", + rev = "26", + tracks = "6t", + vt = "rvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_rvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_slvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_slvt-cells.bzl new file mode 100644 index 00000000..86e6efc5 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc6t_rev26_slvt-cells.bzl @@ -0,0 +1,69 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 26" 6 track standard cell library using super-low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_slvt", + rev = "26", + tracks = "6t", + vt = "slvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_slvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27-common.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27-common.bzl new file mode 100644 index 00000000..06c7dbb5 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27-common.bzl @@ -0,0 +1,34 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +########################################################################## +# ASAP7 "rev 27" 7.5 track standard cell library with SRAM blocks. +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc7p5t_rev27", + rev = "27", + tracks = "7p5t", +) + +filegroup( + name = "asap7-misc-sc7p5t_rev27-lef", + # FIXME: Where is the 1x techlef? + srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], +) + +filegroup( + name = "asap7-misc-sc7p5t_rev27_4x-lef", + srcs = ["asap7sc7p5t_27/techlef_misc/asap7_tech_4x_201209.lef"], +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_lvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_lvt-cells.bzl new file mode 100644 index 00000000..617f9a77 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_lvt-cells.bzl @@ -0,0 +1,70 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 27" 7.5 track standard cell library using Low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_lvt", + rev = "27", + tracks = "7p5t", + vt = "lvt", + has_gds = False, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_lvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt-cells.bzl new file mode 100644 index 00000000..84746f02 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt-cells.bzl @@ -0,0 +1,70 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_rvt", + rev = "27", + tracks = "7p5t", + vt = "rvt", + has_gds = True, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl new file mode 100644 index 00000000..25d7bbc7 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl @@ -0,0 +1,129 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +########################################################################## +# Special 4x scaled version of the ASAP7 "rev 27" 7.5 track standard cell +# library using regular VT transistors. +########################################################################## + +# Layouts for GDS generation +# ------------------------------------------------------------------------ +# No GDS layouts for 4x cells + +# Timing information (in compressed Liberty format) for synthesis and static +# timing analysis (STA). +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-libgz", + actual = ":asap7-cells-sc7p5t_rev27_rvt-libgz", +) + +# Verilog models for digital simulation and logical equivalence +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-v", + actual = ":asap7-cells-sc7p5t_rev27_rvt-v", +) + +# CDL models for LVS checking +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-lvs", + actual = ":asap7-cells-sc7p5t_rev27_rvt-lvs", +) + +# CDL models for Spice simulation +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-spice", + actual = ":asap7-cells-sc7p5t_rev27_rvt-spice", +) + +# Place and route +# ------------------------------------------------------------------------ +filegroup( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-lef", + srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef"], +) + +# Library configuration +# ------------------------------------------------------------------------ +asap7_cell_library( + name = "asap7-sc7p5t_rev27_rvt_4x", + srcs = [ + ":asap7-cells-sc7p5t_rev27_rvt_4x-libgz", +# ":asap7-srams-sc7p5t_rev27_4x-libgz", + ], + cell_lef = ":asap7-cells-sc7p5t_rev27_rvt_4x-lef", +# platform_gds = ":asap7-cells-sc7p5t_rev27_rvt_4x-gds", + default_corner_delay_model = "ccs", + default_corner_swing = "SS", + openroad_configuration = ":open_road-asap7-sc7p5t_rev27_rvt_4x", + tech_lef = ":asap7-misc-sc7p5t_rev27_4x-lef", + visibility = [ + "//visibility:public", + ] +) + +# OpenROAD configuration +# ------------------------------------------------------------------------ +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt_4x", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_4x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +########################################################################## +########################################################################## diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_slvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_slvt-cells.bzl new file mode 100644 index 00000000..af07dd66 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev27_slvt-cells.bzl @@ -0,0 +1,70 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 27" 7.5 track standard cell library using Super-Low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_slvt", + rev = "27", + tracks = "7p5t", + vt = "slvt", + has_gds = False, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_slvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28-common.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28-common.bzl new file mode 100644 index 00000000..280902b4 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28-common.bzl @@ -0,0 +1,33 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +########################################################################## +# ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc7p5t_rev28", + rev = "28", + tracks = "7p5t", +) + +filegroup( + name = "asap7-misc-sc7p5t_rev28-lef", + srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], +) + +filegroup( + name = "asap7-misc-sc7p5t_rev28_4x-lef", + srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_4x_201209.lef"], +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_lvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_lvt-cells.bzl new file mode 100644 index 00000000..0f134303 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_lvt-cells.bzl @@ -0,0 +1,69 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 28" 7.5 track standard cell library using Low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev28_lvt", + rev = "28", + tracks = "7p5t", + vt = "lvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_lvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_rvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_rvt-cells.bzl new file mode 100644 index 00000000..5e6de519 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_rvt-cells.bzl @@ -0,0 +1,69 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 28" 7.5 track standard cell library using regular VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev28_rvt", + rev = "28", + tracks = "7p5t", + vt = "rvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_rvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_slvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_slvt-cells.bzl new file mode 100644 index 00000000..2a4f12b8 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_slvt-cells.bzl @@ -0,0 +1,69 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ASAP7 "rev 28" 7.5 track standard cell library using Super-Low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev28_slvt", + rev = "28", + tracks = "7p5t", + vt = "slvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_slvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7.bzl b/dependency_support/org_theopenroadproject_asap7/asap7.bzl index 0298d072..5d63c8f2 100644 --- a/dependency_support/org_theopenroadproject_asap7/asap7.bzl +++ b/dependency_support/org_theopenroadproject_asap7/asap7.bzl @@ -3,11 +3,147 @@ load("@rules_hdl//pdk:build_defs.bzl", "CornerInfo", "StandardCellInfo") load("@rules_hdl//pdk:open_road_configuration.bzl", "OpenRoadPdkInfo") + +def asap7_srams_files(name=None, rev=None, tracks=None, has_gds=True): + if rev not in ["26", "27", "28"]: + fail("Invalid rev {}".format(repr(rev))) + if tracks not in ["7p5t", "6t"]: + fail("Invalid rev {}".format(repr(tracks))) + + args = { + 'rev': str(rev), + 'tracks': str(tracks), + } + + # Layouts for GDS generation + # ------------------------------------------------------------------------ + if has_gds: + native.filegroup( + name = "asap7-srams-sc{tracks}_rev{rev}-gds".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}*_SRAM_*.gds".format(**args)]), + ) + + # Timing information (in compressed Liberty format) for synthesis and static + # timing analysis (STA). + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-srams-sc{tracks}_rev{rev}-libgz".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*SRAM*.lib.gz".format(**args)]), + ) + + # Verilog models for digital simulation and logical equivalence + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-srams-sc{tracks}_rev{rev}-v".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_SRAM_*.v".format(**args)]), + ) + + # CDL models for LVS checking + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-srams-sc{tracks}_rev{rev}-lvs".format(**args), + srcs = ["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)], + ) + + # CDL models for Spice simulation + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-srams-sc{tracks}_rev{rev}-spice".format(**args), + srcs = ["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)], + ) + + # Place and route + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-srams-sc{tracks}_rev{rev}-lef".format(**args), + srcs = ["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)], + ) + + +def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True): + if rev not in ["26", "27", "28"]: + fail("Invalid rev {}".format(repr(rev))) + if tracks not in ["7p5t", "6t"]: + fail("Invalid tracks {}".format(repr(tracks))) + if vt not in ["lvt", "rvt", "slvt"]: + fail("Invalid vt {}".format(repr(vt))) + + args = { + 'rev': rev, + 'tracks': tracks, + 'vt_long': vt, + 'vt_upper': vt.upper(), + 'vt_short': {'rvt': 'R', 'lvt': 'L', 'slvt': 'SL'}[vt], + } + + # Layouts for GDS generation + # ------------------------------------------------------------------------ + if has_gds: + native.filegroup( + name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}_{vt_short}*.gds".format(**args)]), + ) + + # Timing information (in compressed Liberty format) for synthesis and static + # timing analysis (STA). + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-libgz".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*_{vt_upper}_*.lib.gz".format(**args)]), + ) + + # Verilog models for digital simulation and logical equivalence + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-v".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_{vt_upper}_*.v".format(**args)]), + ) + + # CDL models for LVS checking + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lvs".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_{vt_short}.cdl".format(**args)]), + ) + + # CDL models for Spice simulation + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-spice".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_{vt_short}.sp".format(**args)]), + ) + + # Place and route + # ------------------------------------------------------------------------ + native.filegroup( + name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), + srcs = native.glob(["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}_{vt_short}_1x*.lef".format(**args)]), + ) + + # Library configuration + # ------------------------------------------------------------------------ + asap7_cell_library( + name = "asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), + srcs = [ + ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-libgz".format(**args), + #":asap7-srams-sc{tracks}_rev{rev}-libgz".format(**args), + ], + cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), + platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), + default_corner_delay_model = "ccs", + default_corner_swing = "SS", + openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), + tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args), + visibility = [ + "//visibility:public", + ] + ) + + def _asap7_cell_library_impl(ctx): liberty_files = [file for file in ctx.files.srcs if file.extension == "gz"] liberty_files = [file for file in liberty_files if "_{}_".format(ctx.attr.default_corner_delay_model) in file.basename] liberty_files = [file for file in liberty_files if "SRAM" not in file.basename] - liberty_files = [file for file in liberty_files if ctx.attr.cell_type in file.basename] uncompressed_files = [] for file in liberty_files: @@ -68,11 +204,10 @@ asap7_cell_library = rule( "tech_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The tech lef file for these standard cells"), "default_corner_swing": attr.string(mandatory = True, values = ["SS", "FF", "TT"]), "default_corner_delay_model": attr.string(mandatory = True, values = ["ccs", "ccsn", "ccsa"]), - "cell_type": attr.string(mandatory = True, values = ["RVT", "LVT", "SLVT"]), #TODO(b/212480812): Support multiple VTs in a single design. "openroad_configuration": attr.label(providers = [OpenRoadPdkInfo]), "cell_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The lef file for the standard cells"), - "platform_gds": attr.label(allow_single_file = True, mandatory = True, doc = "Platform GDS files"), + "platform_gds": attr.label(allow_single_file = True, mandatory = False, doc = "Platform GDS files"), "_combine_liberty": attr.label( default = Label("@rules_hdl//pdk/liberty:combine_liberty"), executable = True, diff --git a/dependency_support/org_theopenroadproject_asap7/build-BUILD.py b/dependency_support/org_theopenroadproject_asap7/build-BUILD.py new file mode 100755 index 00000000..44d69b0d --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/build-BUILD.py @@ -0,0 +1,81 @@ +#!/usr/bin/env python3 +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import pathlib + +__path__ = pathlib.Path(__file__).resolve() +__dir__ = __path__.parent + +license_header = [] +for l in open(__path__).readlines()[1:]: + if not l.startswith('#'): + break + license_header.append(l) + +output = [] +output.extend(license_header) +output.append('\n') +output.append('# DO NOT EDIT - This file is generated by `build-BUILD.py` script!\n') +output.append('\n') +output.append('''\ +""" +ASAP7 -- Arizona State University 7nm "predictive" PDK + +The PDK has RVT, LVT and SLVT based transistors. + +The ASAP7 PDK currently provides 3 standard cell libraries; + * Two revisions (rev 27 and rev 28) of a 7.5 track library + * One revision (rev 26) of a 6 track library + +These libraries are mapped to each of the transistor types; + * RVT -> R + * LVT -> L + * SLVT -> SL + +It also provides "4x scaled" versions of these libraries. These versions reuse +the same timing information but have their sizes scaled up. + +The libraries provide 3 corners, + * FF - fast + * TT - typical + * SS - slow + +By default if not otherwise explicitly specified the default selection will be +the 7.5 track library using RVT transistors and slow corner. +""" + +load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cell_library") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cells_files") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_srams_files") + +''') + +input_files = list(__dir__.glob('asap7-sc*-common.bzl')) + list(__dir__.glob('asap7-sc*-cells.bzl')) +input_files.sort() +for input_file in input_files: + output.append(f""" +# From {input_file.name} +""") + with open(input_file) as f: + lines = f.readlines() + while lines.pop(0) in license_header: + continue + output.extend(lines) + +bundle_file = __dir__ / 'bundled.BUILD.bazel' +with open(bundle_file, 'w') as f: + for l in output: + f.write(l) diff --git a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel index fd08494e..a7000df7 100644 --- a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel @@ -1,4 +1,4 @@ -# Copyright 2022 Google LLC +# Copyright 2023 Google LLC # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -12,28 +12,636 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""Arizona State University 7nm PDK""" +# DO NOT EDIT - This file is generated by `build-BUILD.py` script! + +""" +ASAP7 -- Arizona State University 7nm "predictive" PDK + +The PDK has RVT, LVT and SLVT based transistors. + +The ASAP7 PDK currently provides 3 standard cell libraries; + * Two revisions (rev 27 and rev 28) of a 7.5 track library + * One revision (rev 26) of a 6 track library + +These libraries are mapped to each of the transistor types; + * RVT -> R + * LVT -> L + * SLVT -> SL + +It also provides "4x scaled" versions of these libraries. These versions reuse +the same timing information but have their sizes scaled up. + +The libraries provide 3 corners, + * FF - fast + * TT - typical + * SS - slow + +By default if not otherwise explicitly specified the default selection will be +the 7.5 track library using RVT transistors and slow corner. +""" load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cell_library") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cells_files") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_srams_files") + + +# From asap7-sc6t_rev26-common.bzl +########################################################################## +# ASAP7 "rev 26" 6 track standard cell library with SRAM blocks. +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc6t_rev26", + rev = "26", + tracks = "6t", +) + +filegroup( + name = "asap7-misc-sc6t_rev26-lef", + # FIXME: Where is the 1x techlef? + srcs = ["asap7sc6t_26/techlef_misc/asap7sc6t_tech_4x_210831.lef"], +) + +filegroup( + name = "asap7-misc-sc6t_rev26_4x-lef", + srcs = ["asap7sc6t_26/techlef_misc/asap7sc6t_tech_4x_210831.lef"], +) + +# From asap7-sc6t_rev26_lvt-cells.bzl +# ASAP7 "rev 26" 6 track standard cell library using low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_lvt", + rev = "26", + tracks = "6t", + vt = "lvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_lvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) +# From asap7-sc6t_rev26_rvt-cells.bzl +# ASAP7 "rev 26" 6 track standard cell library using regular VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_rvt", + rev = "26", + tracks = "6t", + vt = "rvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_rvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From asap7-sc6t_rev26_slvt-cells.bzl +# ASAP7 "rev 26" 6 track standard cell library using super-low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_slvt", + rev = "26", + tracks = "6t", + vt = "slvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_slvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From asap7-sc7p5t_rev27-common.bzl +########################################################################## +# ASAP7 "rev 27" 7.5 track standard cell library with SRAM blocks. +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc7p5t_rev27", + rev = "27", + tracks = "7p5t", +) + +filegroup( + name = "asap7-misc-sc7p5t_rev27-lef", + # FIXME: Where is the 1x techlef? + srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], +) + +filegroup( + name = "asap7-misc-sc7p5t_rev27_4x-lef", + srcs = ["asap7sc7p5t_27/techlef_misc/asap7_tech_4x_201209.lef"], +) + +# From asap7-sc7p5t_rev27_lvt-cells.bzl +# ASAP7 "rev 27" 7.5 track standard cell library using Low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_lvt", + rev = "27", + tracks = "7p5t", + vt = "lvt", + has_gds = False, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_lvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From asap7-sc7p5t_rev27_rvt-cells.bzl +# ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_rvt", + rev = "27", + tracks = "7p5t", + vt = "rvt", + has_gds = True, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From asap7-sc7p5t_rev27_rvt_4x-cells.bzl +########################################################################## +# Special 4x scaled version of the ASAP7 "rev 27" 7.5 track standard cell +# library using regular VT transistors. +########################################################################## + +# Layouts for GDS generation +# ------------------------------------------------------------------------ +# No GDS layouts for 4x cells + +# Timing information (in compressed Liberty format) for synthesis and static +# timing analysis (STA). +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-libgz", + actual = ":asap7-cells-sc7p5t_rev27_rvt-libgz", +) + +# Verilog models for digital simulation and logical equivalence +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-v", + actual = ":asap7-cells-sc7p5t_rev27_rvt-v", +) + +# CDL models for LVS checking +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-lvs", + actual = ":asap7-cells-sc7p5t_rev27_rvt-lvs", +) + +# CDL models for Spice simulation +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-spice", + actual = ":asap7-cells-sc7p5t_rev27_rvt-spice", +) + +# Place and route +# ------------------------------------------------------------------------ +filegroup( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-lef", + srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef"], +) + +# Library configuration +# ------------------------------------------------------------------------ asap7_cell_library( - name = "asap7_rvt_1x", - srcs = glob(["asap7sc7p5t_28/LIB/CCS/*.lib.gz"]), - cell_lef = "asap7sc7p5t_28/LEF/asap7sc7p5t_28_R_1x_220121a.lef", - cell_type = "RVT", - platform_gds = "asap7sc7p5t_28/GDS/asap7sc7p5t_28_R_220121a.gds", + name = "asap7-sc7p5t_rev27_rvt_4x", + srcs = [ + ":asap7-cells-sc7p5t_rev27_rvt_4x-libgz", +# ":asap7-srams-sc7p5t_rev27_4x-libgz", + ], + cell_lef = ":asap7-cells-sc7p5t_rev27_rvt_4x-lef", +# platform_gds = ":asap7-cells-sc7p5t_rev27_rvt_4x-gds", default_corner_delay_model = "ccs", default_corner_swing = "SS", - openroad_configuration = ":open_road_asap7_1x", - tech_lef = "asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef", + openroad_configuration = ":open_road-asap7-sc7p5t_rev27_rvt_4x", + tech_lef = ":asap7-misc-sc7p5t_rev27_4x-lef", visibility = [ "//visibility:public", ] ) +# OpenROAD configuration +# ------------------------------------------------------------------------ +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt_4x", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_4x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +########################################################################## +########################################################################## + +# From asap7-sc7p5t_rev27_slvt-cells.bzl +# ASAP7 "rev 27" 7.5 track standard cell library using Super-Low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_slvt", + rev = "27", + tracks = "7p5t", + vt = "slvt", + has_gds = False, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_slvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From asap7-sc7p5t_rev28-common.bzl +########################################################################## +# ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc7p5t_rev28", + rev = "28", + tracks = "7p5t", +) + +filegroup( + name = "asap7-misc-sc7p5t_rev28-lef", + srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], +) + +filegroup( + name = "asap7-misc-sc7p5t_rev28_4x-lef", + srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_4x_201209.lef"], +) + +# From asap7-sc7p5t_rev28_lvt-cells.bzl +# ASAP7 "rev 28" 7.5 track standard cell library using Low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev28_lvt", + rev = "28", + tracks = "7p5t", + vt = "lvt", +) + open_road_pdk_configuration( - name = "open_road_asap7_1x", + name = "open_road-asap7-sc7p5t_rev28_lvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From asap7-sc7p5t_rev28_rvt-cells.bzl +# ASAP7 "rev 28" 7.5 track standard cell library using regular VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev28_rvt", + rev = "28", + tracks = "7p5t", + vt = "rvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_rvt", cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_R", do_not_use_cell_list = [ @@ -65,7 +673,7 @@ open_road_pdk_configuration( }, global_routing_signal_layers = "M2-M7", klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config.pdn", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", @@ -78,3 +686,60 @@ open_road_pdk_configuration( wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) + +# From asap7-sc7p5t_rev28_slvt-cells.bzl +# ASAP7 "rev 28" 7.5 track standard cell library using Super-Low VT transistors +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev28_slvt", + rev = "28", + tracks = "7p5t", + vt = "slvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_slvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7/pdn_config.pdn b/dependency_support/org_theopenroadproject_asap7/pdn_config_1x.pdn similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/pdn_config.pdn rename to dependency_support/org_theopenroadproject_asap7/pdn_config_1x.pdn diff --git a/dependency_support/org_theopenroadproject_asap7/pdn_config_4x.pdn b/dependency_support/org_theopenroadproject_asap7/pdn_config_4x.pdn new file mode 100644 index 00000000..94034dbf --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/pdn_config_4x.pdn @@ -0,0 +1,44 @@ +# Floorplan information - core boundary coordinates, std. cell row height, + +set ::halo 2 + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ; + +# Power nets +set ::power_nets "VDD" +set ::ground_nets "VSS" + +#################################### +# global connections +#################################### +add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$} +add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$} +add_global_connection -defer_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground +add_global_connection -defer_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$} +global_connect +#################################### +# voltage domains +#################################### +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} +#################################### +# standard cell grid +#################################### +# ASAP7 in its default configuration is multipled by +# 4x looking to fix this upstream. +set multipler 4.0 + +define_pdn_grid -name {top} -voltage_domains {CORE} +add_pdn_stripe -grid {top} -layer {M1} -width {0.072} -pitch {2.16} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M2} -width {0.072} -pitch {2.16} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M5} -width {0.48} -spacing {0.288} -pitch {47.52} -offset {1.188} +add_pdn_stripe -grid {top} -layer {M6} -width {1.1520} -spacing {0.384} -pitch {48} -offset {2.556} +add_pdn_connect -grid {top} -layers {M1 M2} +add_pdn_connect -grid {top} -layers {M2 M5} +add_pdn_connect -grid {top} -layers {M5 M6} + +pdn::allow_repair_channels true diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD index 686f89c7..c72341c3 100644 --- a/synthesis/tests/BUILD +++ b/synthesis/tests/BUILD @@ -33,28 +33,122 @@ verilog_library( ], ) +########################################################################## +# Verilog counter +########################################################################## + +verilog_library( + name = "verilog_counter", + srcs = [ + "counter.v", + ], +) + +# generic + +synthesize_rtl( + name = "verilog_counter-synth", + top_module = "counter", + deps = [ + ":verilog_counter", + ], +) + +run_opensta( + name = "verilog_counter-synth_sta", + synth_target = ":verilog_counter-synth", +) + place_and_route( - name = "counter_place_and_route", + name = "verilog_counter-place_and_route", clock_period = "10", core_padding_microns = 20, die_height_microns = 200, die_width_microns = 200, placement_density = "0.7", - synthesized_rtl = ":verilog_counter_synth", + synthesized_rtl = ":verilog_counter-synth", +) + +gds_write( + name = "verilog_counter-gds", + implemented_rtl = ":verilog_counter-place_and_route", +) + +########################################################################## +# ASAP7 7.5 track rev 28 +########################################################################## + +# asap7-sc7p5t_rev28_rvt +# ------------------------------------------------------------------------ + +synthesize_rtl( + name = "verilog_counter-asap7-sc7p5t_rev28_rvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev28_rvt", + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":verilog_counter", + ], +) + +run_opensta( + name = "verilog_counter-asap7-sc7p5t_rev28_rvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc7p5t_rev28_rvt-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc7p5t_rev28_rvt-place_and_route", + core_padding_microns = 1, + die_height_microns = 20, + die_width_microns = 20, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev28_rvt-synth", ) gds_write( - name = "counter_asic", - implemented_rtl = ":counter_place_and_route", + name = "verilog_counter-asap7-sc7p5t_rev28_rvt-gds", + implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev28_rvt-place_and_route", +) + +# asap7-sc7p5t_rev28_lvt + +synthesize_rtl( + name = "verilog_counter-asap7-sc7p5t_rev28_lvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev28_lvt", + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":verilog_counter", + ], ) run_opensta( - name = "verilog_counter_synth_sta", - synth_target = ":verilog_counter_synth", + name = "verilog_counter-asap7-sc7p5t_rev28_lvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc7p5t_rev28_lvt-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc7p5t_rev28_lvt-place_and_route", + core_padding_microns = 1, + die_height_microns = 20, + die_width_microns = 20, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev28_lvt-synth", +) + +gds_write( + name = "verilog_counter-asap7-sc7p5t_rev28_lvt-gds", + implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev28_lvt-place_and_route", ) +# asap7-sc7p5t_rev28_slvt + synthesize_rtl( - name = "verilog_counter_synth", + name = "verilog_counter-asap7-sc7p5t_rev28_slvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev28_slvt", + target_clock_period_pico_seconds = 10000, top_module = "counter", deps = [ ":verilog_counter", @@ -62,28 +156,67 @@ synthesize_rtl( ) run_opensta( - name = "verilog_counter_asap7_synth_sta", - synth_target = ":verilog_counter_asap7_synth", + name = "verilog_counter-asap7-sc7p5t_rev28_slvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc7p5t_rev28_slvt-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc7p5t_rev28_slvt-place_and_route", + core_padding_microns = 1, + die_height_microns = 20, + die_width_microns = 20, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev28_slvt-synth", ) gds_write( - name = "counter_asap7_asic", - implemented_rtl = ":counter_asap7_place_and_route", + name = "verilog_counter-asap7-sc7p5t_rev28_slvt-gds", + implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev28_slvt-place_and_route", +) + +########################################################################## +# ASAP7 7.5 track rev 27 +########################################################################## + +# asap7-sc7p5t_rev27_rvt +# ------------------------------------------------------------------------ + +synthesize_rtl( + name = "verilog_counter-asap7-sc7p5t_rev27_rvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev27_rvt", + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":verilog_counter", + ], +) + +run_opensta( + name = "verilog_counter-asap7-sc7p5t_rev27_rvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc7p5t_rev27_rvt-synth", ) place_and_route( - name = "counter_asap7_place_and_route", + name = "verilog_counter-asap7-sc7p5t_rev27_rvt-place_and_route", core_padding_microns = 1, die_height_microns = 20, die_width_microns = 20, placement_density = "0.65", sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter_asap7_synth", + synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev27_rvt-synth", +) + +gds_write( + name = "verilog_counter-asap7-sc7p5t_rev27_rvt-gds", + implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev27_rvt-place_and_route", ) +# asap7-sc7p5t_rev27_lvt + synthesize_rtl( - name = "verilog_counter_asap7_synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7_rvt_1x", + name = "verilog_counter-asap7-sc7p5t_rev27_lvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev27_lvt", target_clock_period_pico_seconds = 10000, top_module = "counter", deps = [ @@ -91,9 +224,182 @@ synthesize_rtl( ], ) -verilog_library( - name = "verilog_counter", - srcs = [ - "counter.v", +run_opensta( + name = "verilog_counter-asap7-sc7p5t_rev27_lvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc7p5t_rev27_lvt-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc7p5t_rev27_lvt-place_and_route", + core_padding_microns = 1, + die_height_microns = 20, + die_width_microns = 20, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev27_lvt-synth", +) + +gds_write( + name = "verilog_counter-asap7-sc7p5t_rev27_lvt-gds", + implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev27_lvt-place_and_route", +) + +# asap7-sc7p5t_rev27_slvt + +synthesize_rtl( + name = "verilog_counter-asap7-sc7p5t_rev27_slvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev27_slvt", + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":verilog_counter", + ], +) + +run_opensta( + name = "verilog_counter-asap7-sc7p5t_rev27_slvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc7p5t_rev27_slvt-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc7p5t_rev27_slvt-place_and_route", + core_padding_microns = 1, + die_height_microns = 20, + die_width_microns = 20, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev27_slvt-synth", +) + +gds_write( + name = "verilog_counter-asap7-sc7p5t_rev27_slvt-gds", + implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev27_slvt-place_and_route", +) + +########################################################################## +# ASAP7 7.5 track rev 27 4x scaled version +########################################################################## + +# asap7-sc7p5t_rev27_rvt_4x +# ------------------------------------------------------------------------ + +synthesize_rtl( + name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev27_rvt_4x", + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":verilog_counter", + ], +) + +run_opensta( + name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth_sta", + synth_target = ":verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x-place_and_route", + core_padding_microns = 1, + die_height_microns = 200, + die_width_microns = 200, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth", +) + +########################################################################## +# ASAP7 6 track rev 26 +########################################################################## + +# asap7-sc6t_rev26_rvt +# ------------------------------------------------------------------------ + +synthesize_rtl( + name = "verilog_counter-asap7-sc6t_rev26_rvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc6t_rev26_rvt", + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":verilog_counter", + ], +) + +run_opensta( + name = "verilog_counter-asap7-sc6t_rev26_rvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc6t_rev26_rvt-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc6t_rev26_rvt-place_and_route", + core_padding_microns = 1, + die_height_microns = 20, + die_width_microns = 20, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc6t_rev26_rvt-synth", +) + +gds_write( + name = "verilog_counter-asap7-sc6t_rev26_rvt-gds", + implemented_rtl = ":verilog_counter-asap7-sc6t_rev26_rvt-place_and_route", +) + +# asap7-sc6t_rev26_lvt + +synthesize_rtl( + name = "verilog_counter-asap7-sc6t_rev26_lvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc6t_rev26_lvt", + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":verilog_counter", + ], +) + +run_opensta( + name = "verilog_counter-asap7-sc6t_rev26_lvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc6t_rev26_lvt-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc6t_rev26_lvt-place_and_route", + core_padding_microns = 1, + die_height_microns = 20, + die_width_microns = 20, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc6t_rev26_lvt-synth", +) + +gds_write( + name = "verilog_counter-asap7-sc6t_rev26_lvt-gds", + implemented_rtl = ":verilog_counter-asap7-sc6t_rev26_lvt-place_and_route", +) + +# asap7-sc6t_rev26_slvt + +synthesize_rtl( + name = "verilog_counter-asap7-sc6t_rev26_slvt-synth", + standard_cells = "@org_theopenroadproject_asap7//:asap7-sc6t_rev26_slvt", + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":verilog_counter", ], ) + +run_opensta( + name = "verilog_counter-asap7-sc6t_rev26_slvt-synth_sta", + synth_target = ":verilog_counter-asap7-sc6t_rev26_slvt-synth", +) + +place_and_route( + name = "verilog_counter-asap7-sc6t_rev26_slvt-place_and_route", + core_padding_microns = 1, + die_height_microns = 20, + die_width_microns = 20, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":verilog_counter-asap7-sc6t_rev26_slvt-synth", +) From 9508260115710ffdc6005630a7f837e85c6a8809 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 7 Nov 2023 12:19:54 -0800 Subject: [PATCH 03/10] Commit before merge. Signed-off-by: Tim 'mithro' Ansell --- .../BUILD | 0 .../asap7-sc6t_rev26-common.bzl | 0 .../asap7-sc6t_rev26_lvt-cells.bzl | 0 .../asap7-sc6t_rev26_rvt-cells.bzl | 0 .../asap7-sc6t_rev26_slvt-cells.bzl | 0 .../asap7-sc7p5t_rev27-common.bzl | 0 .../asap7-sc7p5t_rev27_lvt-cells.bzl | 0 .../asap7-sc7p5t_rev27_rvt-cells.bzl | 0 .../asap7-sc7p5t_rev27_rvt_4x-cells.bzl | 0 .../asap7-sc7p5t_rev27_slvt-cells.bzl | 0 .../asap7-sc7p5t_rev28-common.bzl | 0 .../asap7-sc7p5t_rev28_lvt-cells.bzl | 0 .../asap7-sc7p5t_rev28_rvt-cells.bzl | 0 .../asap7-sc7p5t_rev28_slvt-cells.bzl | 0 .../asap7.bzl | 0 .../asap7.lyt | 0 .../build-BUILD.py | 0 .../bundled.BUILD.bazel | 0 .../org_theopenroadproject_asap7.bzl | 0 .../pdn_config_1x.pdn | 0 .../pdn_config_4x.pdn | 0 .../rc_script.tcl | 0 .../tracks.tcl | 0 23 files changed, 0 insertions(+), 0 deletions(-) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/BUILD (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/asap7-sc6t_rev26-common.bzl (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/asap7-sc6t_rev26_lvt-cells.bzl (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/asap7-sc6t_rev26_rvt-cells.bzl (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/asap7-sc6t_rev26_slvt-cells.bzl (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/asap7-sc7p5t_rev27-common.bzl (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/asap7-sc7p5t_rev27_lvt-cells.bzl (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/asap7-sc7p5t_rev27_rvt-cells.bzl (100%) rename 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org_theopenroadproject_asap7_pdk_r1p7}/asap7.lyt (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/build-BUILD.py (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/bundled.BUILD.bazel (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/org_theopenroadproject_asap7.bzl (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/pdn_config_1x.pdn (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/pdn_config_4x.pdn (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/rc_script.tcl (100%) rename dependency_support/{org_theopenroadproject_asap7 => org_theopenroadproject_asap7_pdk_r1p7}/tracks.tcl (100%) diff --git a/dependency_support/org_theopenroadproject_asap7/BUILD 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diff --git a/dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_slvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_slvt-cells.bzl similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/asap7-sc7p5t_rev28_slvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_slvt-cells.bzl diff --git a/dependency_support/org_theopenroadproject_asap7/asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/asap7.bzl rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl diff --git a/dependency_support/org_theopenroadproject_asap7/asap7.lyt b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.lyt similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/asap7.lyt rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.lyt diff --git a/dependency_support/org_theopenroadproject_asap7/build-BUILD.py b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/build-BUILD.py rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py diff --git a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/bundled.BUILD.bazel similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/bundled.BUILD.bazel diff --git a/dependency_support/org_theopenroadproject_asap7/org_theopenroadproject_asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/org_theopenroadproject_asap7.bzl rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl diff --git a/dependency_support/org_theopenroadproject_asap7/pdn_config_1x.pdn b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config_1x.pdn similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/pdn_config_1x.pdn rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config_1x.pdn diff --git a/dependency_support/org_theopenroadproject_asap7/pdn_config_4x.pdn b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config_4x.pdn similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/pdn_config_4x.pdn rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config_4x.pdn diff --git a/dependency_support/org_theopenroadproject_asap7/rc_script.tcl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/rc_script.tcl similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/rc_script.tcl rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/rc_script.tcl diff --git a/dependency_support/org_theopenroadproject_asap7/tracks.tcl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/tracks.tcl similarity index 100% rename from dependency_support/org_theopenroadproject_asap7/tracks.tcl rename to dependency_support/org_theopenroadproject_asap7_pdk_r1p7/tracks.tcl From 0987fbd036af8e39f0cd7c891a6b395c836c3cca Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 7 Nov 2023 13:01:54 -0800 Subject: [PATCH 04/10] Rework for the ASAP7 repo reorganization. Signed-off-by: Tim 'mithro' Ansell --- WORKSPACE | 3 +- .../com_icarus_iverilog.bzl | 2 +- dependency_support/dependency_support.bzl | 4 + .../asap7-sc7p5t_rev27_rvt-cells.bzl | 96 --- .../asap7.bzl | 100 +-- .../build-BUILD.py | 58 +- .../bundled.BUILD.bazel | 736 ------------------ .../org_theopenroadproject_asap7.bzl | 2 +- .../org_theopenroadproject_asap7_pdk_r1p7.bzl | 2 +- .../pdn_config.pdn | 40 - .../org_theopenroadproject_asap7sc6t_26/BUILD | 13 + .../bundled.BUILD.bazel | 243 ++++++ .../cells-lvt.bzl} | 11 +- .../cells-rvt.bzl} | 11 +- .../cells-slvt.bzl} | 11 +- .../common.bzl} | 6 +- .../org_theopenroadproject_asap7sc6t_26.bzl | 30 + .../BUILD | 13 + .../bundled.BUILD.bazel | 370 +++++++++ .../cells-lvt.bzl} | 11 +- .../cells-rvt.bzl | 71 ++ .../cells-rvt_4x.bzl} | 29 +- .../cells-slvt.bzl} | 11 +- .../common.bzl} | 14 +- .../org_theopenroadproject_asap7sc7p5t_27.bzl | 30 + .../bundled.BUILD.bazel | 209 ++++- .../cells-lvt.bzl} | 11 +- .../cells-rvt.bzl} | 11 +- .../cells-slvt.bzl} | 11 +- .../common.bzl} | 7 +- flows/analysis/BUILD.bazel | 8 +- flows/asap7.bzl | 100 +++ pdk/open_road_configuration.bzl | 3 + .../private/clock_tree_synthesis.bzl | 3 +- synthesis/tests/BUILD | 388 ++------- 35 files changed, 1304 insertions(+), 1364 deletions(-) delete mode 100644 dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl delete mode 100644 dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config.pdn create mode 100644 dependency_support/org_theopenroadproject_asap7sc6t_26/BUILD create mode 100644 dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_lvt-cells.bzl => org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl} (89%) rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_rvt-cells.bzl => org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl} (89%) rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_slvt-cells.bzl => org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl} (89%) rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26-common.bzl => org_theopenroadproject_asap7sc6t_26/common.bzl} (82%) create mode 100644 dependency_support/org_theopenroadproject_asap7sc6t_26/org_theopenroadproject_asap7sc6t_26.bzl create mode 100644 dependency_support/org_theopenroadproject_asap7sc7p5t_27/BUILD create mode 100644 dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_lvt-cells.bzl => org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl} (89%) create mode 100644 dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl => org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl} (86%) rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_slvt-cells.bzl => org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl} (89%) rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27-common.bzl => org_theopenroadproject_asap7sc7p5t_27/common.bzl} (71%) create mode 100644 dependency_support/org_theopenroadproject_asap7sc7p5t_27/org_theopenroadproject_asap7sc7p5t_27.bzl rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_lvt-cells.bzl => org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl} (89%) rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_rvt-cells.bzl => org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl} (89%) rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_slvt-cells.bzl => org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl} (89%) rename dependency_support/{org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28-common.bzl => org_theopenroadproject_asap7sc7p5t_28/common.bzl} (80%) create mode 100644 flows/asap7.bzl diff --git a/WORKSPACE b/WORKSPACE index b50a152d..33979887 100644 --- a/WORKSPACE +++ b/WORKSPACE @@ -93,12 +93,13 @@ llvm_toolchain( maybe( http_archive, name = "rules_7zip", + sha256 = "fd9e99f6ccb9e946755f9bc444abefbdd1eedb32c372c56dcacc7eb486aed178", strip_prefix = "rules_7zip-e00b15d3cb76b78ddc1c15e7426eb1d1b7ddaa3e", urls = ["https://github.com/zaucy/rules_7zip/archive/e00b15d3cb76b78ddc1c15e7426eb1d1b7ddaa3e.zip"], - sha256 = "fd9e99f6ccb9e946755f9bc444abefbdd1eedb32c372c56dcacc7eb486aed178", ) load("@rules_7zip//:setup.bzl", "setup_7zip") + setup_7zip() maybe( diff --git a/dependency_support/com_icarus_iverilog/com_icarus_iverilog.bzl b/dependency_support/com_icarus_iverilog/com_icarus_iverilog.bzl index 0b414ef8..989c11d0 100644 --- a/dependency_support/com_icarus_iverilog/com_icarus_iverilog.bzl +++ b/dependency_support/com_icarus_iverilog/com_icarus_iverilog.bzl @@ -22,7 +22,7 @@ def com_icarus_iverilog(): http_archive, name = "com_icarus_iverilog", urls = [ - "https://github.com/steveicarus/iverilog/archive/v12_0.tar.gz", + "https://github.com/steveicarus/iverilog/archive/v12_0.tar.gz", ], strip_prefix = "iverilog-12_0", sha256 = "a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d", diff --git a/dependency_support/dependency_support.bzl b/dependency_support/dependency_support.bzl index 68aa92a7..cbc66ddd 100644 --- a/dependency_support/dependency_support.bzl +++ b/dependency_support/dependency_support.bzl @@ -58,6 +58,8 @@ load("@rules_hdl//dependency_support/org_sourceware_libffi:org_sourceware_libffi load("@rules_hdl//dependency_support/org_swig:org_swig.bzl", "org_swig") load("@rules_hdl//dependency_support/org_theopenroadproject:org_theopenroadproject.bzl", "org_theopenroadproject") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:org_theopenroadproject_asap7_pdk_r1p7.bzl", "org_theopenroadproject_asap7_pdk_r1p7") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc6t_26:org_theopenroadproject_asap7sc6t_26.bzl", "org_theopenroadproject_asap7sc6t_26") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc7p5t_27:org_theopenroadproject_asap7sc7p5t_27.bzl", "org_theopenroadproject_asap7sc7p5t_27") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc7p5t_28:org_theopenroadproject_asap7sc7p5t_28.bzl", "org_theopenroadproject_asap7sc7p5t_28") load("@rules_hdl//dependency_support/pybind11:pybind11.bzl", "pybind11") load("@rules_hdl//dependency_support/tk_tcl:tk_tcl.bzl", "tk_tcl") @@ -105,6 +107,8 @@ def dependency_support(): org_swig() org_theopenroadproject() org_theopenroadproject_asap7_pdk_r1p7() + org_theopenroadproject_asap7sc6t_26() + org_theopenroadproject_asap7sc7p5t_27() org_theopenroadproject_asap7sc7p5t_28() pybind11() tk_tcl() diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl deleted file mode 100644 index 69e7c725..00000000 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl +++ /dev/null @@ -1,96 +0,0 @@ -# Copyright 2023 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -<<<<<<<< HEAD:dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl -# ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc7p5t_rev27_rvt", - rev = "27", - tracks = "7p5t", - vt = "rvt", - has_gds = True, -======== -"""Arizona State University 7nm PDK""" - -load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") -load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") - -asap7_cell_library( - name = "asap7_rvt_1x", - srcs = glob(["LIB/CCS/*.lib.7z"]), - cell_lef = "LEF/asap7sc7p5t_28_R_1x_220121a.lef", - cell_type = "RVT", - platform_gds = "GDS/asap7sc7p5t_28_R_220121a.gds", - default_corner_delay_model = "ccs", - default_corner_swing = "SS", - openroad_configuration = ":open_road_asap7_1x", - tech_lef = "techlef_misc/asap7_tech_1x_201209.lef", - visibility = [ - "//visibility:public", - ] ->>>>>>>> temp-fix-asap7:dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_rvt", - cell_site = "asap7sc7p5t", - cts_buffer_cell = "BUFx4_ASAP7_75t_R", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_R", - fill_cells = [ - "FILLERxp5_ASAP7_75t_R", - "DECAPx1_ASAP7_75t_R", - "DECAPx2_ASAP7_75t_R", - "DECAPx4_ASAP7_75t_R", - "DECAPx6_ASAP7_75t_R", - "DECAPx10_ASAP7_75t_R", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", -<<<<<<<< HEAD:dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", -======== - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config.pdn", ->>>>>>>> temp-fix-asap7:dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_R", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_R/H", - tie_low_port = "TIELOx1_ASAP7_75t_R/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl index 109dae25..ab619ed7 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl @@ -3,17 +3,24 @@ load("@rules_hdl//pdk:build_defs.bzl", "CornerInfo", "StandardCellInfo") load("@rules_hdl//pdk:open_road_configuration.bzl", "OpenRoadPdkInfo") -<<<<<<< HEAD +def asap7_srams_files(name = None, rev = None, tracks = None, has_gds = True): + """Generate ASAP7 sram's filegroup targets (asap7-cells-XXX). + + Args: + name: Macro instance name. + rev: ASAP7 revision ("26" / "27" / "28"). + tracks: Number of tracks ("7p5t", "6t"). + has_gds: SRAM have GDS layouts. + """ -def asap7_srams_files(name=None, rev=None, tracks=None, has_gds=True): if rev not in ["26", "27", "28"]: fail("Invalid rev {}".format(repr(rev))) if tracks not in ["7p5t", "6t"]: fail("Invalid rev {}".format(repr(tracks))) args = { - 'rev': str(rev), - 'tracks': str(tracks), + "rev": str(rev), + "tracks": str(tracks), } # Layouts for GDS generation @@ -21,47 +28,56 @@ def asap7_srams_files(name=None, rev=None, tracks=None, has_gds=True): if has_gds: native.filegroup( name = "asap7-srams-sc{tracks}_rev{rev}-gds".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}*_SRAM_*.gds".format(**args)]), + srcs = native.glob(["GDS/asap7sc{tracks}_{rev}*_SRAM_*.gds".format(**args)]), ) # Timing information (in compressed Liberty format) for synthesis and static # timing analysis (STA). # ------------------------------------------------------------------------ native.filegroup( - name = "asap7-srams-sc{tracks}_rev{rev}-libgz".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*SRAM*.lib.gz".format(**args)]), + name = "asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args), + srcs = native.glob(["LIB/CCS/*SRAM*.lib.7z".format(**args)]), ) # Verilog models for digital simulation and logical equivalence # ------------------------------------------------------------------------ native.filegroup( name = "asap7-srams-sc{tracks}_rev{rev}-v".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_SRAM_*.v".format(**args)]), + srcs = native.glob(["Verilog/asap7sc{tracks}_*_SRAM_*.v".format(**args)]), ) # CDL models for LVS checking # ------------------------------------------------------------------------ native.filegroup( name = "asap7-srams-sc{tracks}_rev{rev}-lvs".format(**args), - srcs = ["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)], + srcs = ["CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)], ) # CDL models for Spice simulation # ------------------------------------------------------------------------ native.filegroup( name = "asap7-srams-sc{tracks}_rev{rev}-spice".format(**args), - srcs = ["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)], + srcs = ["CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)], ) # Place and route # ------------------------------------------------------------------------ native.filegroup( name = "asap7-srams-sc{tracks}_rev{rev}-lef".format(**args), - srcs = ["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)], + srcs = ["LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)], ) +def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds = True): + """Generate ASAP7 cell's filegroup targets (asap7-cells-XXX). + + Args: + name: Macro instance name. + rev: ASAP7 revision ("26" / "27" / "28"). + tracks: Number of tracks ("7p5t", "6t"). + vt: VT type ("rvt", "lvt", "slvt"). + has_gds: Cells have GDS layouts. + """ -def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True): if rev not in ["26", "27", "28"]: fail("Invalid rev {}".format(repr(rev))) if tracks not in ["7p5t", "6t"]: @@ -70,11 +86,11 @@ def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True): fail("Invalid vt {}".format(repr(vt))) args = { - 'rev': rev, - 'tracks': tracks, - 'vt_long': vt, - 'vt_upper': vt.upper(), - 'vt_short': {'rvt': 'R', 'lvt': 'L', 'slvt': 'SL'}[vt], + "rev": rev, + "tracks": tracks, + "vt_long": vt, + "vt_upper": vt.upper(), + "vt_short": {"rvt": "R", "lvt": "L", "slvt": "SL"}[vt], } # Layouts for GDS generation @@ -82,43 +98,43 @@ def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True): if has_gds: native.filegroup( name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/GDS/asap7sc{tracks}_{rev}_{vt_short}*.gds".format(**args)]), + srcs = native.glob(["GDS/asap7sc{tracks}_{rev}_{vt_short}*.gds".format(**args)]), ) # Timing information (in compressed Liberty format) for synthesis and static # timing analysis (STA). # ------------------------------------------------------------------------ native.filegroup( - name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-libgz".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/LIB/CCS/*_{vt_upper}_*.lib.gz".format(**args)]), + name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args), + srcs = native.glob(["LIB/CCS/*_{vt_upper}_*.lib.7z".format(**args)]), ) # Verilog models for digital simulation and logical equivalence # ------------------------------------------------------------------------ native.filegroup( name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-v".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/Verilog/asap7sc{tracks}_*_{vt_upper}_*.v".format(**args)]), + srcs = native.glob(["Verilog/asap7sc{tracks}_*_{vt_upper}_*.v".format(**args)]), ) # CDL models for LVS checking # ------------------------------------------------------------------------ native.filegroup( name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lvs".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/CDL/LVS/asap7sc{tracks}_{rev}_{vt_short}.cdl".format(**args)]), + srcs = native.glob(["CDL/LVS/asap7sc{tracks}_{rev}_{vt_short}.cdl".format(**args)]), ) # CDL models for Spice simulation # ------------------------------------------------------------------------ native.filegroup( name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-spice".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_{vt_short}.sp".format(**args)]), + srcs = native.glob(["CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_{vt_short}.sp".format(**args)]), ) # Place and route # ------------------------------------------------------------------------ native.filegroup( name = "asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), - srcs = native.glob(["asap7sc{tracks}_{rev}/LEF/asap7sc{tracks}_{rev}_{vt_short}_1x*.lef".format(**args)]), + srcs = native.glob(["LEF/asap7sc{tracks}_{rev}_{vt_short}_1x*.lef".format(**args)]), ) # Library configuration @@ -126,8 +142,8 @@ def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True): asap7_cell_library( name = "asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), srcs = [ - ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-libgz".format(**args), - #":asap7-srams-sc{tracks}_rev{rev}-libgz".format(**args), + ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args), + #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args), ], cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), @@ -137,29 +153,17 @@ def asap7_cells_files(name=None, rev=None, tracks=None, vt=None, has_gds=True): tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args), visibility = [ "//visibility:public", - ] + ], ) - -def _asap7_cell_library_impl(ctx): - liberty_files = [file for file in ctx.files.srcs if file.extension == "gz"] - liberty_files = [file for file in liberty_files if "_{}_".format(ctx.attr.default_corner_delay_model) in file.basename] - liberty_files = [file for file in liberty_files if "SRAM" not in file.basename] - - uncompressed_files = [] - for file in liberty_files: - uncompressed_file = ctx.actions.declare_file(file.basename[:-len(".gz")]) -======= def _asap7_cell_library_impl(ctx): liberty_files = [file for file in ctx.files.srcs if file.extension == "7z"] liberty_files = [file for file in liberty_files if "_{}_".format(ctx.attr.default_corner_delay_model) in file.basename] liberty_files = [file for file in liberty_files if "SRAM" not in file.basename] - liberty_files = [file for file in liberty_files if ctx.attr.cell_type in file.basename] uncompressed_files = [] for file in liberty_files: uncompressed_file = ctx.actions.declare_file(file.basename[:-len(".7z")]) ->>>>>>> temp-fix-asap7 ctx.actions.run_shell( outputs = [ uncompressed_file, @@ -167,12 +171,6 @@ def _asap7_cell_library_impl(ctx): inputs = [ file, ], -<<<<<<< HEAD - command = "gunzip --to-stdout {compressed_file} > {uncompressed_file}".format( - compressed_file = file.path, - uncompressed_file = uncompressed_file.path, - ), -======= command = "{tool} x -so -- {compressed_file} > {uncompressed_file}".format( tool = ctx.executable._uncompress.path, compressed_file = file.path, @@ -181,7 +179,6 @@ def _asap7_cell_library_impl(ctx): tools = [ ctx.executable._uncompress, ], ->>>>>>> temp-fix-asap7 ) uncompressed_files.append(uncompressed_file) @@ -227,30 +224,19 @@ asap7_cell_library = rule( "tech_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The tech lef file for these standard cells"), "default_corner_swing": attr.string(mandatory = True, values = ["SS", "FF", "TT"]), "default_corner_delay_model": attr.string(mandatory = True, values = ["ccs", "ccsn", "ccsa"]), -<<<<<<< HEAD #TODO(b/212480812): Support multiple VTs in a single design. "openroad_configuration": attr.label(providers = [OpenRoadPdkInfo]), "cell_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The lef file for the standard cells"), "platform_gds": attr.label(allow_single_file = True, mandatory = False, doc = "Platform GDS files"), -======= - "cell_type": attr.string(mandatory = True, values = ["RVT", "LVT", "SLVT"]), - #TODO(b/212480812): Support multiple VTs in a single design. - "openroad_configuration": attr.label(providers = [OpenRoadPdkInfo]), - "cell_lef": attr.label(allow_single_file = True, mandatory = True, doc = "The lef file for the standard cells"), - "platform_gds": attr.label(allow_single_file = True, mandatory = True, doc = "Platform GDS files"), ->>>>>>> temp-fix-asap7 "_combine_liberty": attr.label( default = Label("@rules_hdl//pdk/liberty:combine_liberty"), executable = True, cfg = "exec", ), -<<<<<<< HEAD -======= "_uncompress": attr.label( default = Label("@7zip//:7za"), executable = True, cfg = "exec", ), ->>>>>>> temp-fix-asap7 }, ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py index 44d69b0d..fef44181 100755 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py @@ -24,12 +24,12 @@ break license_header.append(l) -output = [] -output.extend(license_header) -output.append('\n') -output.append('# DO NOT EDIT - This file is generated by `build-BUILD.py` script!\n') -output.append('\n') -output.append('''\ +header = [] +header.extend(license_header) +header.append('\n') +header.append('# DO NOT EDIT - This file is generated by `build-BUILD.py` script!\n') +header.append('\n') +header.append('''\ """ ASAP7 -- Arizona State University 7nm "predictive" PDK @@ -57,25 +57,35 @@ """ load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") -load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cell_library") -load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cells_files") -load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_srams_files") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files") ''') -input_files = list(__dir__.glob('asap7-sc*-common.bzl')) + list(__dir__.glob('asap7-sc*-cells.bzl')) -input_files.sort() -for input_file in input_files: - output.append(f""" -# From {input_file.name} +for scdir in list(sorted(__dir__.parent.glob('org_theopenroadproject_asap7sc*'))): + print('Processing ', scdir) + output = [] + output.extend(header) + + common_file = scdir / 'common.bzl' + assert common_file.exists(), common_file + + input_files = [common_file] + list(scdir.glob('cells-*.bzl')) + input_files.sort() + for input_file in input_files: + output.append(f""" +# From {scdir.name}/{input_file.name} """) - with open(input_file) as f: - lines = f.readlines() - while lines.pop(0) in license_header: - continue - output.extend(lines) - -bundle_file = __dir__ / 'bundled.BUILD.bazel' -with open(bundle_file, 'w') as f: - for l in output: - f.write(l) + print('Reading', input_file) + with open(input_file) as f: + lines = f.readlines() + while lines.pop(0) in license_header: + continue + output.extend(lines) + + output_file = scdir / 'bundled.BUILD.bazel' + print('Writing', output_file) + with open(output_file, 'w') as f: + for l in output: + f.write(l) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/bundled.BUILD.bazel index f0472f64..ae4883d1 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/bundled.BUILD.bazel @@ -12,739 +12,3 @@ # See the License for the specific language governing permissions and # limitations under the License. -<<<<<<< HEAD -# DO NOT EDIT - This file is generated by `build-BUILD.py` script! - -""" -ASAP7 -- Arizona State University 7nm "predictive" PDK - -The PDK has RVT, LVT and SLVT based transistors. - -The ASAP7 PDK currently provides 3 standard cell libraries; - * Two revisions (rev 27 and rev 28) of a 7.5 track library - * One revision (rev 26) of a 6 track library - -These libraries are mapped to each of the transistor types; - * RVT -> R - * LVT -> L - * SLVT -> SL - -It also provides "4x scaled" versions of these libraries. These versions reuse -the same timing information but have their sizes scaled up. - -The libraries provide 3 corners, - * FF - fast - * TT - typical - * SS - slow - -By default if not otherwise explicitly specified the default selection will be -the 7.5 track library using RVT transistors and slow corner. -""" - -load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") -load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cell_library") -load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cells_files") -load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_srams_files") - - -# From asap7-sc6t_rev26-common.bzl -########################################################################## -# ASAP7 "rev 26" 6 track standard cell library with SRAM blocks. -########################################################################## - -asap7_srams_files( - name = "asap7-srams-sc6t_rev26", - rev = "26", - tracks = "6t", -) - -filegroup( - name = "asap7-misc-sc6t_rev26-lef", - # FIXME: Where is the 1x techlef? - srcs = ["asap7sc6t_26/techlef_misc/asap7sc6t_tech_4x_210831.lef"], -) - -filegroup( - name = "asap7-misc-sc6t_rev26_4x-lef", - srcs = ["asap7sc6t_26/techlef_misc/asap7sc6t_tech_4x_210831.lef"], -) - -# From asap7-sc6t_rev26_lvt-cells.bzl -# ASAP7 "rev 26" 6 track standard cell library using low VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc6t_rev26_lvt", - rev = "26", - tracks = "6t", - vt = "lvt", -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc6t_rev26_lvt", - cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_L", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_L", - fill_cells = [ - "FILLERxp5_ASAP7_75t_L", - "DECAPx1_ASAP7_75t_L", - "DECAPx2_ASAP7_75t_L", - "DECAPx4_ASAP7_75t_L", - "DECAPx6_ASAP7_75t_L", - "DECAPx10_ASAP7_75t_L", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_L", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_L/H", - tie_low_port = "TIELOx1_ASAP7_75t_L/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -# From asap7-sc6t_rev26_rvt-cells.bzl -# ASAP7 "rev 26" 6 track standard cell library using regular VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc6t_rev26_rvt", - rev = "26", - tracks = "6t", - vt = "rvt", -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc6t_rev26_rvt", - cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_R", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_R", - fill_cells = [ - "FILLERxp5_ASAP7_75t_R", - "DECAPx1_ASAP7_75t_R", - "DECAPx2_ASAP7_75t_R", - "DECAPx4_ASAP7_75t_R", - "DECAPx6_ASAP7_75t_R", - "DECAPx10_ASAP7_75t_R", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_R", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_R/H", - tie_low_port = "TIELOx1_ASAP7_75t_R/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -# From asap7-sc6t_rev26_slvt-cells.bzl -# ASAP7 "rev 26" 6 track standard cell library using super-low VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc6t_rev26_slvt", - rev = "26", - tracks = "6t", - vt = "slvt", -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc6t_rev26_slvt", - cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_SL", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_SL", - fill_cells = [ - "FILLERxp5_ASAP7_75t_SL", - "DECAPx1_ASAP7_75t_SL", - "DECAPx2_ASAP7_75t_SL", - "DECAPx4_ASAP7_75t_SL", - "DECAPx6_ASAP7_75t_SL", - "DECAPx10_ASAP7_75t_SL", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_SL", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", - tie_low_port = "TIELOx1_ASAP7_75t_SL/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -# From asap7-sc7p5t_rev27-common.bzl -########################################################################## -# ASAP7 "rev 27" 7.5 track standard cell library with SRAM blocks. -########################################################################## - -asap7_srams_files( - name = "asap7-srams-sc7p5t_rev27", - rev = "27", - tracks = "7p5t", -) - -filegroup( - name = "asap7-misc-sc7p5t_rev27-lef", - # FIXME: Where is the 1x techlef? - srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], -) - -filegroup( - name = "asap7-misc-sc7p5t_rev27_4x-lef", - srcs = ["asap7sc7p5t_27/techlef_misc/asap7_tech_4x_201209.lef"], -) - -# From asap7-sc7p5t_rev27_lvt-cells.bzl -# ASAP7 "rev 27" 7.5 track standard cell library using Low VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc7p5t_rev27_lvt", - rev = "27", - tracks = "7p5t", - vt = "lvt", - has_gds = False, -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_lvt", - cell_site = "asap7sc7p5t", - cts_buffer_cell = "BUFx4_ASAP7_75t_L", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_L", - fill_cells = [ - "FILLERxp5_ASAP7_75t_L", - "DECAPx1_ASAP7_75t_L", - "DECAPx2_ASAP7_75t_L", - "DECAPx4_ASAP7_75t_L", - "DECAPx6_ASAP7_75t_L", - "DECAPx10_ASAP7_75t_L", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_L", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_L/H", - tie_low_port = "TIELOx1_ASAP7_75t_L/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -# From asap7-sc7p5t_rev27_rvt-cells.bzl -# ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc7p5t_rev27_rvt", - rev = "27", - tracks = "7p5t", - vt = "rvt", - has_gds = True, -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_rvt", - cell_site = "asap7sc7p5t", - cts_buffer_cell = "BUFx4_ASAP7_75t_R", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_R", - fill_cells = [ - "FILLERxp5_ASAP7_75t_R", - "DECAPx1_ASAP7_75t_R", - "DECAPx2_ASAP7_75t_R", - "DECAPx4_ASAP7_75t_R", - "DECAPx6_ASAP7_75t_R", - "DECAPx10_ASAP7_75t_R", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_R", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_R/H", - tie_low_port = "TIELOx1_ASAP7_75t_R/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -# From asap7-sc7p5t_rev27_rvt_4x-cells.bzl -########################################################################## -# Special 4x scaled version of the ASAP7 "rev 27" 7.5 track standard cell -# library using regular VT transistors. -########################################################################## - -# Layouts for GDS generation -# ------------------------------------------------------------------------ -# No GDS layouts for 4x cells - -# Timing information (in compressed Liberty format) for synthesis and static -# timing analysis (STA). -# ------------------------------------------------------------------------ -alias( - name = "asap7-cells-sc7p5t_rev27_rvt_4x-libgz", - actual = ":asap7-cells-sc7p5t_rev27_rvt-libgz", -) - -# Verilog models for digital simulation and logical equivalence -# ------------------------------------------------------------------------ -alias( - name = "asap7-cells-sc7p5t_rev27_rvt_4x-v", - actual = ":asap7-cells-sc7p5t_rev27_rvt-v", -) - -# CDL models for LVS checking -# ------------------------------------------------------------------------ -alias( - name = "asap7-cells-sc7p5t_rev27_rvt_4x-lvs", - actual = ":asap7-cells-sc7p5t_rev27_rvt-lvs", -) - -# CDL models for Spice simulation -# ------------------------------------------------------------------------ -alias( - name = "asap7-cells-sc7p5t_rev27_rvt_4x-spice", - actual = ":asap7-cells-sc7p5t_rev27_rvt-spice", -) - -# Place and route -# ------------------------------------------------------------------------ -filegroup( - name = "asap7-cells-sc7p5t_rev27_rvt_4x-lef", - srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef"], -) - -# Library configuration -# ------------------------------------------------------------------------ -asap7_cell_library( - name = "asap7-sc7p5t_rev27_rvt_4x", - srcs = [ - ":asap7-cells-sc7p5t_rev27_rvt_4x-libgz", -# ":asap7-srams-sc7p5t_rev27_4x-libgz", - ], - cell_lef = ":asap7-cells-sc7p5t_rev27_rvt_4x-lef", -# platform_gds = ":asap7-cells-sc7p5t_rev27_rvt_4x-gds", - default_corner_delay_model = "ccs", - default_corner_swing = "SS", - openroad_configuration = ":open_road-asap7-sc7p5t_rev27_rvt_4x", - tech_lef = ":asap7-misc-sc7p5t_rev27_4x-lef", - visibility = [ - "//visibility:public", - ] -) - -# OpenROAD configuration -# ------------------------------------------------------------------------ -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_rvt_4x", - cell_site = "asap7sc7p5t", - cts_buffer_cell = "BUFx4_ASAP7_75t_R", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_R", - fill_cells = [ - "FILLERxp5_ASAP7_75t_R", - "DECAPx1_ASAP7_75t_R", - "DECAPx2_ASAP7_75t_R", - "DECAPx4_ASAP7_75t_R", - "DECAPx6_ASAP7_75t_R", - "DECAPx10_ASAP7_75t_R", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_4x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_R", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_R/H", - tie_low_port = "TIELOx1_ASAP7_75t_R/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -########################################################################## -########################################################################## - -# From asap7-sc7p5t_rev27_slvt-cells.bzl -# ASAP7 "rev 27" 7.5 track standard cell library using Super-Low VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc7p5t_rev27_slvt", - rev = "27", - tracks = "7p5t", - vt = "slvt", - has_gds = False, -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_slvt", - cell_site = "asap7sc7p5t", - cts_buffer_cell = "BUFx4_ASAP7_75t_SL", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_SL", - fill_cells = [ - "FILLERxp5_ASAP7_75t_SL", - "DECAPx1_ASAP7_75t_SL", - "DECAPx2_ASAP7_75t_SL", - "DECAPx4_ASAP7_75t_SL", - "DECAPx6_ASAP7_75t_SL", - "DECAPx10_ASAP7_75t_SL", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_SL", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", - tie_low_port = "TIELOx1_ASAP7_75t_SL/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -# From asap7-sc7p5t_rev28-common.bzl -########################################################################## -# ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. -########################################################################## - -asap7_srams_files( - name = "asap7-srams-sc7p5t_rev28", - rev = "28", - tracks = "7p5t", -) - -filegroup( - name = "asap7-misc-sc7p5t_rev28-lef", - srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], -) - -filegroup( - name = "asap7-misc-sc7p5t_rev28_4x-lef", - srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_4x_201209.lef"], -) - -# From asap7-sc7p5t_rev28_lvt-cells.bzl -# ASAP7 "rev 28" 7.5 track standard cell library using Low VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc7p5t_rev28_lvt", - rev = "28", - tracks = "7p5t", - vt = "lvt", -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_lvt", - cell_site = "asap7sc7p5t", - cts_buffer_cell = "BUFx4_ASAP7_75t_L", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_L", - fill_cells = [ - "FILLERxp5_ASAP7_75t_L", - "DECAPx1_ASAP7_75t_L", - "DECAPx2_ASAP7_75t_L", - "DECAPx4_ASAP7_75t_L", - "DECAPx6_ASAP7_75t_L", - "DECAPx10_ASAP7_75t_L", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_L", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_L/H", - tie_low_port = "TIELOx1_ASAP7_75t_L/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -# From asap7-sc7p5t_rev28_rvt-cells.bzl -# ASAP7 "rev 28" 7.5 track standard cell library using regular VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc7p5t_rev28_rvt", - rev = "28", - tracks = "7p5t", - vt = "rvt", -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_rvt", - cell_site = "asap7sc7p5t", - cts_buffer_cell = "BUFx4_ASAP7_75t_R", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_R", - fill_cells = [ - "FILLERxp5_ASAP7_75t_R", - "DECAPx1_ASAP7_75t_R", - "DECAPx2_ASAP7_75t_R", - "DECAPx4_ASAP7_75t_R", - "DECAPx6_ASAP7_75t_R", - "DECAPx10_ASAP7_75t_R", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_R", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_R/H", - tie_low_port = "TIELOx1_ASAP7_75t_R/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) - -# From asap7-sc7p5t_rev28_slvt-cells.bzl -# ASAP7 "rev 28" 7.5 track standard cell library using Super-Low VT transistors -# ------------------------------------------------------------------------ -asap7_cells_files( - name = "asap7-cells-sc7p5t_rev28_slvt", - rev = "28", - tracks = "7p5t", - vt = "slvt", -) - -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_slvt", - cell_site = "asap7sc7p5t", - cts_buffer_cell = "BUFx4_ASAP7_75t_SL", - do_not_use_cell_list = [ - "*x1_ASAP7*", - "*x1p*_ASAP7*", - "*xp*_ASAP7*", - "SDF*", - "ICG*", - "DFFH*", - ], - endcap_cell = "TAPCELL_ASAP7_75t_SL", - fill_cells = [ - "FILLERxp5_ASAP7_75t_SL", - "DECAPx1_ASAP7_75t_SL", - "DECAPx2_ASAP7_75t_SL", - "DECAPx4_ASAP7_75t_SL", - "DECAPx6_ASAP7_75t_SL", - "DECAPx10_ASAP7_75t_SL", - ], - global_placement_cell_pad = 2, - global_routing_clock_layers = "M2-M7", - global_routing_layer_adjustments = { - "M2": "0.5", - "M3": "0.5", - "M4": "0.5", - "M5": "0.5", - "M6": "0.5", - "M7": "0.5", - }, - global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", - pin_horizontal_metal_layer = "M4", - pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_SL", - tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", - tie_low_port = "TIELOx1_ASAP7_75t_SL/L", - tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", - wire_rc_clock_metal_layer = "M5", - wire_rc_signal_metal_layer = "M2", -) -======= -"""Arizona State University 7nm PDK""" - ->>>>>>> temp-fix-asap7 diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl index aa699e5d..50d93c40 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl @@ -22,7 +22,7 @@ def org_theopenroadproject_asap7_pdk_r1p7(): http_archive, name = "org_theopenroadproject_asap7_pdk_r1p7", urls = [ - "https://github.com/The-OpenROAD-Project/asap7_pdk_r1p7/archive/1ff7649bbf423207f6f70293dc1cf630cd477365.tar.gz" + "https://github.com/The-OpenROAD-Project/asap7_pdk_r1p7/archive/1ff7649bbf423207f6f70293dc1cf630cd477365.tar.gz", ], strip_prefix = "asap7_pdk_r1p7-1ff7649bbf423207f6f70293dc1cf630cd477365", sha256 = "b5847f93e55debb49d03ec581e22eb301109ff90c9ad19d35ae1223c70250391", diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7_pdk_r1p7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7_pdk_r1p7.bzl index aa699e5d..50d93c40 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7_pdk_r1p7.bzl +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7_pdk_r1p7.bzl @@ -22,7 +22,7 @@ def org_theopenroadproject_asap7_pdk_r1p7(): http_archive, name = "org_theopenroadproject_asap7_pdk_r1p7", urls = [ - "https://github.com/The-OpenROAD-Project/asap7_pdk_r1p7/archive/1ff7649bbf423207f6f70293dc1cf630cd477365.tar.gz" + "https://github.com/The-OpenROAD-Project/asap7_pdk_r1p7/archive/1ff7649bbf423207f6f70293dc1cf630cd477365.tar.gz", ], strip_prefix = "asap7_pdk_r1p7-1ff7649bbf423207f6f70293dc1cf630cd477365", sha256 = "b5847f93e55debb49d03ec581e22eb301109ff90c9ad19d35ae1223c70250391", diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config.pdn b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config.pdn deleted file mode 100644 index a612880d..00000000 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/pdn_config.pdn +++ /dev/null @@ -1,40 +0,0 @@ -# Floorplan information - core boundary coordinates, std. cell row height, - -set ::halo 2 - -# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area -set ::rails_start_with "POWER" ; - -# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area -set ::stripes_start_with "POWER" ; - -# Power nets -set ::power_nets "VDD" -set ::ground_nets "VSS" - -#################################### -# global connections -#################################### -add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power -add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$} -add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$} -add_global_connection -defer_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground -add_global_connection -defer_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$} -global_connect -#################################### -# voltage domains -#################################### -set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} -#################################### -# standard cell grid -#################################### -define_pdn_grid -name {top} -voltage_domains {CORE} -add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {11.88} -offset {0.300} -add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {12} -offset {0.513} -add_pdn_connect -grid {top} -layers {M1 M2} -add_pdn_connect -grid {top} -layers {M2 M5} -add_pdn_connect -grid {top} -layers {M5 M6} - -pdn::allow_repair_channels true diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/BUILD b/dependency_support/org_theopenroadproject_asap7sc6t_26/BUILD new file mode 100644 index 00000000..6d6d1266 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/BUILD @@ -0,0 +1,13 @@ +# Copyright 2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel new file mode 100644 index 00000000..95d78515 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel @@ -0,0 +1,243 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# DO NOT EDIT - This file is generated by `build-BUILD.py` script! + +""" +ASAP7 -- Arizona State University 7nm "predictive" PDK + +The PDK has RVT, LVT and SLVT based transistors. + +The ASAP7 PDK currently provides 3 standard cell libraries; + * Two revisions (rev 27 and rev 28) of a 7.5 track library + * One revision (rev 26) of a 6 track library + +These libraries are mapped to each of the transistor types; + * RVT -> R + * LVT -> L + * SLVT -> SL + +It also provides "4x scaled" versions of these libraries. These versions reuse +the same timing information but have their sizes scaled up. + +The libraries provide 3 corners, + * FF - fast + * TT - typical + * SS - slow + +By default if not otherwise explicitly specified the default selection will be +the 7.5 track library using RVT transistors and slow corner. +""" + +load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files") + + +# From org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl +""" ASAP7 "rev 26" 6 track standard cell library using low VT transistors """ + +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_lvt", + rev = "26", + tracks = "6t", + vt = "lvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_lvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl +""" ASAP7 "rev 26" 6 track standard cell library using regular VT transistors """ + +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_rvt", + rev = "26", + tracks = "6t", + vt = "rvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_rvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl +""" ASAP7 "rev 26" 6 track standard cell library using super-low VT transistors """ + +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc6t_rev26_slvt", + rev = "26", + tracks = "6t", + vt = "slvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_slvt", + cell_site = "asap7sc6t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From org_theopenroadproject_asap7sc6t_26/common.bzl +########################################################################## +""" ASAP7 "rev 26" 6 track standard cell library with SRAM blocks. """ +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc6t_rev26", + rev = "26", + tracks = "6t", +) + +filegroup( + name = "asap7-misc-sc6t_rev26-lef", + # FIXME: Where is the 1x techlef? + srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"], +) + +filegroup( + name = "asap7-misc-sc6t_rev26_4x-lef", + srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"], +) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_lvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl similarity index 89% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_lvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl index e599b13d..cd519caa 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_lvt-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl @@ -12,7 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -# ASAP7 "rev 26" 6 track standard cell library using low VT transistors +""" ASAP7 "rev 26" 6 track standard cell library using low VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc6t_rev26_lvt", @@ -53,17 +54,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_L", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_L/H", tie_low_port = "TIELOx1_ASAP7_75t_L/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_rvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl similarity index 89% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_rvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl index 554e4c2d..ca3e58ce 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_rvt-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl @@ -12,7 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -# ASAP7 "rev 26" 6 track standard cell library using regular VT transistors +""" ASAP7 "rev 26" 6 track standard cell library using regular VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc6t_rev26_rvt", @@ -53,17 +54,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_R", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_R/H", tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_slvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl similarity index 89% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_slvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl index 86e6efc5..a46c4839 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26_slvt-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl @@ -12,7 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -# ASAP7 "rev 26" 6 track standard cell library using super-low VT transistors +""" ASAP7 "rev 26" 6 track standard cell library using super-low VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc6t_rev26_slvt", @@ -53,17 +54,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_SL", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", tie_low_port = "TIELOx1_ASAP7_75t_SL/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26-common.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/common.bzl similarity index 82% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26-common.bzl rename to dependency_support/org_theopenroadproject_asap7sc6t_26/common.bzl index 57c55414..0ce244f7 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc6t_rev26-common.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/common.bzl @@ -13,7 +13,7 @@ # limitations under the License. ########################################################################## -# ASAP7 "rev 26" 6 track standard cell library with SRAM blocks. +""" ASAP7 "rev 26" 6 track standard cell library with SRAM blocks. """ ########################################################################## asap7_srams_files( @@ -25,10 +25,10 @@ asap7_srams_files( filegroup( name = "asap7-misc-sc6t_rev26-lef", # FIXME: Where is the 1x techlef? - srcs = ["asap7sc6t_26/techlef_misc/asap7sc6t_tech_4x_210831.lef"], + srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"], ) filegroup( name = "asap7-misc-sc6t_rev26_4x-lef", - srcs = ["asap7sc6t_26/techlef_misc/asap7sc6t_tech_4x_210831.lef"], + srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"], ) diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/org_theopenroadproject_asap7sc6t_26.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/org_theopenroadproject_asap7sc6t_26.bzl new file mode 100644 index 00000000..b8fbb8ac --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/org_theopenroadproject_asap7sc6t_26.bzl @@ -0,0 +1,30 @@ +# Copyright 2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Registers Bazel workspaces for the Boost C++ libraries.""" + +load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive") +load("@bazel_tools//tools/build_defs/repo:utils.bzl", "maybe") + +def org_theopenroadproject_asap7sc6t_26(): + maybe( + http_archive, + name = "org_theopenroadproject_asap7sc6t_26", + urls = [ + "https://github.com/The-OpenROAD-Project/asap7sc6t_26/archive/f572bf760c8bdc853cbafd0742790aba0780089c.tar.gz", + ], + strip_prefix = "asap7sc6t_26-f572bf760c8bdc853cbafd0742790aba0780089c", + sha256 = "4bfe15775eaab3a5cc443d444ef82bf7b9c818ba2ed948ce3d9cc6a4cfa1c36c", + build_file = Label("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc6t_26:bundled.BUILD.bazel"), + ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/BUILD b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/BUILD new file mode 100644 index 00000000..6d6d1266 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/BUILD @@ -0,0 +1,13 @@ +# Copyright 2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel new file mode 100644 index 00000000..ca2682ab --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel @@ -0,0 +1,370 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# DO NOT EDIT - This file is generated by `build-BUILD.py` script! + +""" +ASAP7 -- Arizona State University 7nm "predictive" PDK + +The PDK has RVT, LVT and SLVT based transistors. + +The ASAP7 PDK currently provides 3 standard cell libraries; + * Two revisions (rev 27 and rev 28) of a 7.5 track library + * One revision (rev 26) of a 6 track library + +These libraries are mapped to each of the transistor types; + * RVT -> R + * LVT -> L + * SLVT -> SL + +It also provides "4x scaled" versions of these libraries. These versions reuse +the same timing information but have their sizes scaled up. + +The libraries provide 3 corners, + * FF - fast + * TT - typical + * SS - slow + +By default if not otherwise explicitly specified the default selection will be +the 7.5 track library using RVT transistors and slow corner. +""" + +load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files") + + +# From org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl +""" ASAP7 "rev 27" 7.5 track standard cell library using Low VT transistors """ + +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_lvt", + rev = "27", + tracks = "7p5t", + vt = "lvt", + has_gds = False, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_lvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl +""" ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors """ + +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_rvt", + rev = "27", + tracks = "7p5t", + vt = "rvt", + has_gds = True, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl +########################################################################## +""" +Special 4x scaled version of the ASAP7 "rev 27" 7.5 track standard cell +library using regular VT transistors. +""" +########################################################################## + +# Layouts for GDS generation +# ------------------------------------------------------------------------ +# No GDS layouts for 4x cells + +# Timing information (in compressed Liberty format) for synthesis and static +# timing analysis (STA). +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-lib7z", + actual = ":asap7-cells-sc7p5t_rev27_rvt-lib7z", +) + +# Verilog models for digital simulation and logical equivalence +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-v", + actual = ":asap7-cells-sc7p5t_rev27_rvt-v", +) + +# CDL models for LVS checking +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-lvs", + actual = ":asap7-cells-sc7p5t_rev27_rvt-lvs", +) + +# CDL models for Spice simulation +# ------------------------------------------------------------------------ +alias( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-spice", + actual = ":asap7-cells-sc7p5t_rev27_rvt-spice", +) + +# Place and route +# ------------------------------------------------------------------------ +filegroup( + name = "asap7-cells-sc7p5t_rev27_rvt_4x-lef", + srcs = ["LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef"], +) + +# Library configuration +# ------------------------------------------------------------------------ +asap7_cell_library( + name = "asap7-sc7p5t_rev27_rvt_4x", + srcs = [ + ":asap7-cells-sc7p5t_rev27_rvt_4x-lib7z", + # ":asap7-srams-sc7p5t_rev27_4x-lib7z", + ], + cell_lef = ":asap7-cells-sc7p5t_rev27_rvt_4x-lef", + # platform_gds = ":asap7-cells-sc7p5t_rev27_rvt_4x-gds", + default_corner_delay_model = "ccs", + default_corner_swing = "SS", + openroad_configuration = ":open_road-asap7-sc7p5t_rev27_rvt_4x", + tech_lef = ":asap7-misc-sc7p5t_rev27_4x-lef", + visibility = [ + "//visibility:public", + ], +) + +# OpenROAD configuration +# ------------------------------------------------------------------------ +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt_4x", + cell_site = "asap7sc7p5t", + check_placement = False, + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_4x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +########################################################################## +########################################################################## + +# From org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl +""" ASAP7 "rev 27" 7.5 track standard cell library using Super-Low VT transistors """ + +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_slvt", + rev = "27", + tracks = "7p5t", + vt = "slvt", + has_gds = False, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_slvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From org_theopenroadproject_asap7sc7p5t_27/common.bzl +########################################################################## +""" ASAP7 "rev 27" 7.5 track standard cell library with SRAM blocks. """ +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc7p5t_rev27", + rev = "27", + tracks = "7p5t", +) + +# FIXME: Where is the 1x techlef? +#filegroup( +# name = "asap7-misc-sc7p5t_rev27-lef", +# srcs = ["techlef_misc/asap7_tech_4x_201209.lef"], +#) +alias( + name = "asap7-misc-sc7p5t_rev27-lef", + actual = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-misc-sc7p5t_rev28-lef", +) + +filegroup( + name = "asap7-misc-sc7p5t_rev27_4x-lef", + srcs = ["techlef_misc/asap7_tech_4x_201209.lef"], +) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_lvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl similarity index 89% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_lvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl index 617f9a77..a417c714 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_lvt-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl @@ -12,7 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -# ASAP7 "rev 27" 7.5 track standard cell library using Low VT transistors +""" ASAP7 "rev 27" 7.5 track standard cell library using Low VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev27_lvt", @@ -54,17 +55,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_L", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_L/H", tie_low_port = "TIELOx1_ASAP7_75t_L/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl new file mode 100644 index 00000000..bbf20558 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl @@ -0,0 +1,71 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors """ + +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev27_rvt", + rev = "27", + tracks = "7p5t", + vt = "rvt", + has_gds = True, +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_R", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_R", + fill_cells = [ + "FILLERxp5_ASAP7_75t_R", + "DECAPx1_ASAP7_75t_R", + "DECAPx2_ASAP7_75t_R", + "DECAPx4_ASAP7_75t_R", + "DECAPx6_ASAP7_75t_R", + "DECAPx10_ASAP7_75t_R", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_R", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_R/H", + tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl similarity index 86% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl index 25d7bbc7..ee4b7234 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt_4x-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl @@ -13,8 +13,10 @@ # limitations under the License. ########################################################################## -# Special 4x scaled version of the ASAP7 "rev 27" 7.5 track standard cell -# library using regular VT transistors. +""" +Special 4x scaled version of the ASAP7 "rev 27" 7.5 track standard cell +library using regular VT transistors. +""" ########################################################################## # Layouts for GDS generation @@ -25,8 +27,8 @@ # timing analysis (STA). # ------------------------------------------------------------------------ alias( - name = "asap7-cells-sc7p5t_rev27_rvt_4x-libgz", - actual = ":asap7-cells-sc7p5t_rev27_rvt-libgz", + name = "asap7-cells-sc7p5t_rev27_rvt_4x-lib7z", + actual = ":asap7-cells-sc7p5t_rev27_rvt-lib7z", ) # Verilog models for digital simulation and logical equivalence @@ -54,7 +56,7 @@ alias( # ------------------------------------------------------------------------ filegroup( name = "asap7-cells-sc7p5t_rev27_rvt_4x-lef", - srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef"], + srcs = ["LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef"], ) # Library configuration @@ -62,18 +64,18 @@ filegroup( asap7_cell_library( name = "asap7-sc7p5t_rev27_rvt_4x", srcs = [ - ":asap7-cells-sc7p5t_rev27_rvt_4x-libgz", -# ":asap7-srams-sc7p5t_rev27_4x-libgz", + ":asap7-cells-sc7p5t_rev27_rvt_4x-lib7z", + # ":asap7-srams-sc7p5t_rev27_4x-lib7z", ], cell_lef = ":asap7-cells-sc7p5t_rev27_rvt_4x-lef", -# platform_gds = ":asap7-cells-sc7p5t_rev27_rvt_4x-gds", + # platform_gds = ":asap7-cells-sc7p5t_rev27_rvt_4x-gds", default_corner_delay_model = "ccs", default_corner_swing = "SS", openroad_configuration = ":open_road-asap7-sc7p5t_rev27_rvt_4x", tech_lef = ":asap7-misc-sc7p5t_rev27_4x-lef", visibility = [ "//visibility:public", - ] + ], ) # OpenROAD configuration @@ -81,6 +83,7 @@ asap7_cell_library( open_road_pdk_configuration( name = "open_road-asap7-sc7p5t_rev27_rvt_4x", cell_site = "asap7sc7p5t", + check_placement = False, cts_buffer_cell = "BUFx4_ASAP7_75t_R", do_not_use_cell_list = [ "*x1_ASAP7*", @@ -110,17 +113,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_4x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_4x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_R", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_R/H", tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_slvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl similarity index 89% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_slvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl index af07dd66..8d324a5b 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_slvt-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl @@ -12,7 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -# ASAP7 "rev 27" 7.5 track standard cell library using Super-Low VT transistors +""" ASAP7 "rev 27" 7.5 track standard cell library using Super-Low VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev27_slvt", @@ -54,17 +55,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_SL", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", tie_low_port = "TIELOx1_ASAP7_75t_SL/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27-common.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/common.bzl similarity index 71% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27-common.bzl rename to dependency_support/org_theopenroadproject_asap7sc7p5t_27/common.bzl index 06c7dbb5..7bddbcf6 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27-common.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/common.bzl @@ -13,7 +13,7 @@ # limitations under the License. ########################################################################## -# ASAP7 "rev 27" 7.5 track standard cell library with SRAM blocks. +""" ASAP7 "rev 27" 7.5 track standard cell library with SRAM blocks. """ ########################################################################## asap7_srams_files( @@ -22,13 +22,17 @@ asap7_srams_files( tracks = "7p5t", ) -filegroup( +# FIXME: Where is the 1x techlef? +#filegroup( +# name = "asap7-misc-sc7p5t_rev27-lef", +# srcs = ["techlef_misc/asap7_tech_4x_201209.lef"], +#) +alias( name = "asap7-misc-sc7p5t_rev27-lef", - # FIXME: Where is the 1x techlef? - srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], + actual = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-misc-sc7p5t_rev28-lef", ) filegroup( name = "asap7-misc-sc7p5t_rev27_4x-lef", - srcs = ["asap7sc7p5t_27/techlef_misc/asap7_tech_4x_201209.lef"], + srcs = ["techlef_misc/asap7_tech_4x_201209.lef"], ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/org_theopenroadproject_asap7sc7p5t_27.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/org_theopenroadproject_asap7sc7p5t_27.bzl new file mode 100644 index 00000000..865a5614 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/org_theopenroadproject_asap7sc7p5t_27.bzl @@ -0,0 +1,30 @@ +# Copyright 2023 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""Registers Bazel workspaces for the Boost C++ libraries.""" + +load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive") +load("@bazel_tools//tools/build_defs/repo:utils.bzl", "maybe") + +def org_theopenroadproject_asap7sc7p5t_27(): + maybe( + http_archive, + name = "org_theopenroadproject_asap7sc7p5t_27", + urls = [ + "https://github.com/The-OpenROAD-Project/asap7sc7p5t_27/archive/900f55ed8bef025f39edcc8b8be5e04a2c55c15a.tar.gz", + ], + strip_prefix = "asap7sc7p5t_27-900f55ed8bef025f39edcc8b8be5e04a2c55c15a", + sha256 = "db5531736a34f34e919488468e8ee09ae87495ff8a6188fad375d68c19e10e20", + build_file = Label("@rules_hdl//dependency_support/org_theopenroadproject_asap7sc7p5t_27:bundled.BUILD.bazel"), + ) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel index 69e7c725..f3acd6ba 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel @@ -12,39 +12,111 @@ # See the License for the specific language governing permissions and # limitations under the License. -<<<<<<<< HEAD:dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl -# ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors +# DO NOT EDIT - This file is generated by `build-BUILD.py` script! + +""" +ASAP7 -- Arizona State University 7nm "predictive" PDK + +The PDK has RVT, LVT and SLVT based transistors. + +The ASAP7 PDK currently provides 3 standard cell libraries; + * Two revisions (rev 27 and rev 28) of a 7.5 track library + * One revision (rev 26) of a 6 track library + +These libraries are mapped to each of the transistor types; + * RVT -> R + * LVT -> L + * SLVT -> SL + +It also provides "4x scaled" versions of these libraries. These versions reuse +the same timing information but have their sizes scaled up. + +The libraries provide 3 corners, + * FF - fast + * TT - typical + * SS - slow + +By default if not otherwise explicitly specified the default selection will be +the 7.5 track library using RVT transistors and slow corner. +""" + +load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files") + + +# From org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl +""" ASAP7 "rev 28" 7.5 track standard cell library using Low VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( - name = "asap7-cells-sc7p5t_rev27_rvt", - rev = "27", + name = "asap7-cells-sc7p5t_rev28_lvt", + rev = "28", tracks = "7p5t", - vt = "rvt", - has_gds = True, -======== -"""Arizona State University 7nm PDK""" + vt = "lvt", +) -load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") -load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_lvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_L", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_L", + fill_cells = [ + "FILLERxp5_ASAP7_75t_L", + "DECAPx1_ASAP7_75t_L", + "DECAPx2_ASAP7_75t_L", + "DECAPx4_ASAP7_75t_L", + "DECAPx6_ASAP7_75t_L", + "DECAPx10_ASAP7_75t_L", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_L", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_L/H", + tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl +""" ASAP7 "rev 28" 7.5 track standard cell library using regular VT transistors """ -asap7_cell_library( - name = "asap7_rvt_1x", - srcs = glob(["LIB/CCS/*.lib.7z"]), - cell_lef = "LEF/asap7sc7p5t_28_R_1x_220121a.lef", - cell_type = "RVT", - platform_gds = "GDS/asap7sc7p5t_28_R_220121a.gds", - default_corner_delay_model = "ccs", - default_corner_swing = "SS", - openroad_configuration = ":open_road_asap7_1x", - tech_lef = "techlef_misc/asap7_tech_1x_201209.lef", - visibility = [ - "//visibility:public", - ] ->>>>>>>> temp-fix-asap7:dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev28_rvt", + rev = "28", + tracks = "7p5t", + vt = "rvt", ) open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_rvt", + name = "open_road-asap7-sc7p5t_rev28_rvt", cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_R", do_not_use_cell_list = [ @@ -75,13 +147,8 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", -<<<<<<<< HEAD:dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev27_rvt-cells.bzl - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", -======== klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config.pdn", ->>>>>>>> temp-fix-asap7:dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", @@ -94,3 +161,83 @@ open_road_pdk_configuration( wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) + +# From org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl +""" ASAP7 "rev 28" 7.5 track standard cell library using Super-Low VT transistors """ + +# ------------------------------------------------------------------------ +asap7_cells_files( + name = "asap7-cells-sc7p5t_rev28_slvt", + rev = "28", + tracks = "7p5t", + vt = "slvt", +) + +open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_slvt", + cell_site = "asap7sc7p5t", + cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + do_not_use_cell_list = [ + "*x1_ASAP7*", + "*x1p*_ASAP7*", + "*xp*_ASAP7*", + "SDF*", + "ICG*", + "DFFH*", + ], + endcap_cell = "TAPCELL_ASAP7_75t_SL", + fill_cells = [ + "FILLERxp5_ASAP7_75t_SL", + "DECAPx1_ASAP7_75t_SL", + "DECAPx2_ASAP7_75t_SL", + "DECAPx4_ASAP7_75t_SL", + "DECAPx6_ASAP7_75t_SL", + "DECAPx10_ASAP7_75t_SL", + ], + global_placement_cell_pad = 2, + global_routing_clock_layers = "M2-M7", + global_routing_layer_adjustments = { + "M2": "0.5", + "M3": "0.5", + "M4": "0.5", + "M5": "0.5", + "M6": "0.5", + "M7": "0.5", + }, + global_routing_signal_layers = "M2-M7", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", + pin_horizontal_metal_layer = "M4", + pin_vertical_metal_layer = "M5", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", + tap_cell = "TAPCELL_ASAP7_75t_SL", + tapcell_distance = 25, + tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", + tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_separation = 0, + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", + wire_rc_clock_metal_layer = "M5", + wire_rc_signal_metal_layer = "M2", +) + +# From org_theopenroadproject_asap7sc7p5t_28/common.bzl +########################################################################## +""" ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. """ +########################################################################## + +asap7_srams_files( + name = "asap7-srams-sc7p5t_rev28", + rev = "28", + tracks = "7p5t", +) + +filegroup( + name = "asap7-misc-sc7p5t_rev28-lef", + srcs = ["techlef_misc/asap7_tech_1x_201209.lef"], + visibility = ["//visibility:public"], +) + +filegroup( + name = "asap7-misc-sc7p5t_rev28_4x-lef", + srcs = ["techlef_misc/asap7_tech_4x_201209.lef"], +) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_lvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl similarity index 89% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_lvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl index 0f134303..a6908754 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_lvt-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl @@ -12,7 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -# ASAP7 "rev 28" 7.5 track standard cell library using Low VT transistors +""" ASAP7 "rev 28" 7.5 track standard cell library using Low VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev28_lvt", @@ -53,17 +54,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_L", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_L/H", tie_low_port = "TIELOx1_ASAP7_75t_L/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_rvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl similarity index 89% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_rvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl index 5e6de519..e15ac9a6 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_rvt-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl @@ -12,7 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -# ASAP7 "rev 28" 7.5 track standard cell library using regular VT transistors +""" ASAP7 "rev 28" 7.5 track standard cell library using regular VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev28_rvt", @@ -53,17 +54,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_R", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_R/H", tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_slvt-cells.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl similarity index 89% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_slvt-cells.bzl rename to dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl index 2a4f12b8..682ef7e8 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28_slvt-cells.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl @@ -12,7 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. -# ASAP7 "rev 28" 7.5 track standard cell library using Super-Low VT transistors +""" ASAP7 "rev 28" 7.5 track standard cell library using Super-Low VT transistors """ + # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev28_slvt", @@ -53,17 +54,17 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", - klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.lyt", - pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:pdn_config_1x.pdn", + klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", + pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_1x.pdn", pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", - rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:rc_script.tcl", + rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_SL", tapcell_distance = 25, tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", tie_low_port = "TIELOx1_ASAP7_75t_SL/L", tie_separation = 0, - tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7:tracks.tcl", + tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28-common.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl similarity index 80% rename from dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28-common.bzl rename to dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl index 280902b4..5cb41ea0 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7-sc7p5t_rev28-common.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl @@ -13,7 +13,7 @@ # limitations under the License. ########################################################################## -# ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. +""" ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. """ ########################################################################## asap7_srams_files( @@ -24,10 +24,11 @@ asap7_srams_files( filegroup( name = "asap7-misc-sc7p5t_rev28-lef", - srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], + srcs = ["techlef_misc/asap7_tech_1x_201209.lef"], + visibility = ["//visibility:public"], ) filegroup( name = "asap7-misc-sc7p5t_rev28_4x-lef", - srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_4x_201209.lef"], + srcs = ["techlef_misc/asap7_tech_4x_201209.lef"], ) diff --git a/flows/analysis/BUILD.bazel b/flows/analysis/BUILD.bazel index f0f573b9..43f5f0d4 100644 --- a/flows/analysis/BUILD.bazel +++ b/flows/analysis/BUILD.bazel @@ -43,7 +43,7 @@ analyze_rtl_binary( name = "critical_path_asap7", analysis_script = "critical_path.tcl", constants = ["clock_port"], - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7_rvt_1x", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", ) analyze_rtl_binary( @@ -54,14 +54,14 @@ analyze_rtl_binary( "reg_start", "reg_end", ], - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7_rvt_1x", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", ) analyze_rtl_binary( name = "pipeline_balance_asap7", analysis_script = "pipeline_balance.tcl", constants = ["clock_port"], - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7_rvt_1x", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", ) analyze_rtl_binary( @@ -83,5 +83,5 @@ analyze_rtl_binary( "clock_period_ps", ], outputs = ["metrics"], - standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7_rvt_1x", + standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt", ) diff --git a/flows/asap7.bzl b/flows/asap7.bzl new file mode 100644 index 00000000..bfedcb67 --- /dev/null +++ b/flows/asap7.bzl @@ -0,0 +1,100 @@ +# Copyright 2021-2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Macro for quick ASAP7 basic flow. """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("//gds_write:build_defs.bzl", "gds_write") +load("//place_and_route:build_defs.bzl", "place_and_route") +load("//static_timing:build_defs.bzl", "run_opensta") +load("//synthesis:build_defs.bzl", "synthesize_rtl") + +def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20): + """Generate targets for a quick basic ASAP7 flow. + + Args: + name: Name for the macro instance. + target: Verilog library name. + rev: ASAP7 revision (26 / 27 / 28). + tracks: Number of tracks ("7p5t", "6t"). + vt: VT type ("rvt", "lvt", "slvt"). + has_gds: Cells have GDS layouts. + size: Size of the die in microns. + """ + if rev not in [26, 27, 28]: + fail("Invalid rev {}".format(repr(rev))) + if tracks not in ["7p5t", "6t"]: + fail("Invalid rev {}".format(repr(tracks))) + + a = { + "name": target, + "tracks": tracks, + "rev": rev, + "vt": vt, + } + + synthesize_rtl( + name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), + standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}".format(**a), + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":{name}".format(**a), + ], + ) + build_test( + name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), + targets = [ + ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), + ], + ) + + run_opensta( + name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth_sta".format(**a), + synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), + ) + build_test( + name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth_sta".format(**a), + targets = [ + ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), + ], + ) + + place_and_route( + name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a), + core_padding_microns = 1, + die_height_microns = size, + die_width_microns = size, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), + ) + build_test( + name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a), + targets = [ + ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a), + ], + ) + + if has_gds: + gds_write( + name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a), + implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a), + ) + build_test( + name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a), + targets = [ + ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a), + ], + ) diff --git a/pdk/open_road_configuration.bzl b/pdk/open_road_configuration.bzl index d272257c..88b6450f 100644 --- a/pdk/open_road_configuration.bzl +++ b/pdk/open_road_configuration.bzl @@ -40,6 +40,7 @@ OpenRoadPdkInfo = provider( "rc_script_configuration": "RC script for the various metal layers", "tapcell_tcl": "TCL file that sets tapcell options. This overrides other tapcell attributes in this rule.", "placement_padding_tcl": "TCL Script for handling the placement padding of cells", + "check_placement": "Check the placement in the placement script", "detailed_routing_configuration": "optional detailed routing configuration", "density_fill_config": "optional path to file with metal fill configuration", "klayout_tech_file": "KLayout technology file for GDS write", @@ -77,6 +78,7 @@ def _open_road_pdk_configuration_impl(ctx): rc_script_configuration = ctx.file.rc_script_configuration, tapcell_tcl = ctx.file.tapcell_tcl, placement_padding_tcl = ctx.file.placement_padding_tcl, + check_placement = ctx.attr.check_placement, detailed_routing_configuration = ctx.attr.detailed_routing_configuration, density_fill_config = ctx.attr.density_fill_config, klayout_tech_file = ctx.attr.klayout_tech_file, @@ -109,6 +111,7 @@ open_road_pdk_configuration = rule( "rc_script_configuration": attr.label(allow_single_file = True), "tapcell_tcl": attr.label(allow_single_file = True, doc = "TCL file that sets tapcell options. This overrides other tapcell attributes in this rule."), "placement_padding_tcl": attr.label(allow_single_file = True, doc = "TCL Script for handling the placement padding of cells"), + "check_placement": attr.bool(mandatory = False, default = True), "detailed_routing_configuration": attr.label(providers = [DetailedRoutingInfo]), "density_fill_config": attr.label(allow_single_file = True), "klayout_tech_file": attr.label(mandatory = True, allow_single_file = True), diff --git a/place_and_route/private/clock_tree_synthesis.bzl b/place_and_route/private/clock_tree_synthesis.bzl index 3e6e4fdf..9972fb25 100644 --- a/place_and_route/private/clock_tree_synthesis.bzl +++ b/place_and_route/private/clock_tree_synthesis.bzl @@ -57,8 +57,9 @@ def clock_tree_synthesis(ctx, open_road_info): "filler_placement \"{filler_cells}\"".format( filler_cells = " ".join(open_road_configuration.fill_cells), ), - "check_placement", ] + if open_road_configuration.check_placement: + open_road_commands.append("check_placement") command_output = openroad_command( ctx, diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD index afee4275..75bb5502 100644 --- a/synthesis/tests/BUILD +++ b/synthesis/tests/BUILD @@ -12,6 +12,8 @@ # See the License for the specific language governing permissions and # limitations under the License. +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("//flows:asap7.bzl", "asap7_targets") load("//gds_write:build_defs.bzl", "gds_write") load("//place_and_route:build_defs.bzl", "place_and_route") load("//static_timing:build_defs.bzl", "run_opensta") @@ -73,332 +75,104 @@ gds_write( implemented_rtl = ":verilog_counter-place_and_route", ) -########################################################################## -# ASAP7 7.5 track rev 28 -########################################################################## - -# asap7-sc7p5t_rev28_rvt -# ------------------------------------------------------------------------ - -synthesize_rtl( - name = "verilog_counter-asap7-sc7p5t_rev28_rvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev28_rvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc7p5t_rev28_rvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc7p5t_rev28_rvt-synth", -) - -place_and_route( - name = "verilog_counter-asap7-sc7p5t_rev28_rvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev28_rvt-synth", -) - -gds_write( - name = "verilog_counter-asap7-sc7p5t_rev28_rvt-gds", - implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev28_rvt-place_and_route", -) - -# asap7-sc7p5t_rev28_lvt - -synthesize_rtl( - name = "verilog_counter-asap7-sc7p5t_rev28_lvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev28_lvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc7p5t_rev28_lvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc7p5t_rev28_lvt-synth", -) - -place_and_route( - name = "verilog_counter-asap7-sc7p5t_rev28_lvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev28_lvt-synth", -) - -gds_write( - name = "verilog_counter-asap7-sc7p5t_rev28_lvt-gds", - implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev28_lvt-place_and_route", -) - -# asap7-sc7p5t_rev28_slvt - -synthesize_rtl( - name = "verilog_counter-asap7-sc7p5t_rev28_slvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev28_slvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ +build_test( + name = "build-verilog_counter", + targets = [ ":verilog_counter", + ":verilog_counter-synth", + ":verilog_counter-synth_sta", + ":verilog_counter-place_and_route", + ":verilog_counter-gds", ], ) -run_opensta( - name = "verilog_counter-asap7-sc7p5t_rev28_slvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc7p5t_rev28_slvt-synth", +# ASAP7 7.5 track rev 28 +asap7_targets( + name = "verilog_counter-asap7-sc7p5t_rev28_rvt", + rev = 28, + target = "verilog_counter", + tracks = "7p5t", + vt = "rvt", ) -place_and_route( - name = "verilog_counter-asap7-sc7p5t_rev28_slvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev28_slvt-synth", +asap7_targets( + name = "verilog_counter-asap7-sc7p5t_rev28_lvt", + rev = 28, + target = "verilog_counter", + tracks = "7p5t", + vt = "lvt", ) -gds_write( - name = "verilog_counter-asap7-sc7p5t_rev28_slvt-gds", - implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev28_slvt-place_and_route", +asap7_targets( + name = "verilog_counter-asap7-sc7p5t_rev28_slvt", + rev = 28, + target = "verilog_counter", + tracks = "7p5t", + vt = "slvt", ) -########################################################################## # ASAP7 7.5 track rev 27 -########################################################################## - -# asap7-sc7p5t_rev27_rvt -# ------------------------------------------------------------------------ - -synthesize_rtl( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev27_rvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc7p5t_rev27_rvt-synth", -) - -place_and_route( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev27_rvt-synth", -) - -gds_write( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt-gds", - implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev27_rvt-place_and_route", -) - -# asap7-sc7p5t_rev27_lvt - -synthesize_rtl( - name = "verilog_counter-asap7-sc7p5t_rev27_lvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev27_lvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc7p5t_rev27_lvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc7p5t_rev27_lvt-synth", -) - -place_and_route( - name = "verilog_counter-asap7-sc7p5t_rev27_lvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev27_lvt-synth", -) - -gds_write( - name = "verilog_counter-asap7-sc7p5t_rev27_lvt-gds", - implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev27_lvt-place_and_route", -) - -# asap7-sc7p5t_rev27_slvt - -synthesize_rtl( - name = "verilog_counter-asap7-sc7p5t_rev27_slvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev27_slvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc7p5t_rev27_slvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc7p5t_rev27_slvt-synth", +asap7_targets( + name = "verilog_counter-asap7-sc7p5t_rev27_rvt", + rev = 27, + target = "verilog_counter", + tracks = "7p5t", + vt = "rvt", ) -place_and_route( - name = "verilog_counter-asap7-sc7p5t_rev27_slvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev27_slvt-synth", +asap7_targets( + name = "verilog_counter-asap7-sc7p5t_rev27_lvt", + has_gds = False, # No GDS for rev27 LVT + rev = 27, + target = "verilog_counter", + tracks = "7p5t", + vt = "lvt", ) -gds_write( - name = "verilog_counter-asap7-sc7p5t_rev27_slvt-gds", - implemented_rtl = ":verilog_counter-asap7-sc7p5t_rev27_slvt-place_and_route", +asap7_targets( + name = "verilog_counter-asap7-sc7p5t_rev27_slvt", + has_gds = False, # No GDS for rev27 LVT + rev = 27, + target = "verilog_counter", + tracks = "7p5t", + vt = "slvt", ) -########################################################################## # ASAP7 7.5 track rev 27 4x scaled version -########################################################################## - -# asap7-sc7p5t_rev27_rvt_4x -# ------------------------------------------------------------------------ - -synthesize_rtl( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc7p5t_rev27_rvt_4x", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth_sta", - synth_target = ":verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth", -) - -place_and_route( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x-place_and_route", - core_padding_microns = 1, - die_height_microns = 200, - die_width_microns = 200, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc7p5t_rev27_rvt_4x-synth", +asap7_targets( + name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x", + size = 2000, + has_gds = False, # No GDS for the 4x cells + rev = 27, + target = "verilog_counter", + tracks = "7p5t", + vt = "rvt_4x", ) -########################################################################## # ASAP7 6 track rev 26 -########################################################################## - -# asap7-sc6t_rev26_rvt -# ------------------------------------------------------------------------ - -synthesize_rtl( - name = "verilog_counter-asap7-sc6t_rev26_rvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc6t_rev26_rvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc6t_rev26_rvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc6t_rev26_rvt-synth", -) - -place_and_route( - name = "verilog_counter-asap7-sc6t_rev26_rvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc6t_rev26_rvt-synth", -) - -gds_write( - name = "verilog_counter-asap7-sc6t_rev26_rvt-gds", - implemented_rtl = ":verilog_counter-asap7-sc6t_rev26_rvt-place_and_route", -) - -# asap7-sc6t_rev26_lvt - -synthesize_rtl( - name = "verilog_counter-asap7-sc6t_rev26_lvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc6t_rev26_lvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc6t_rev26_lvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc6t_rev26_lvt-synth", -) - -place_and_route( - name = "verilog_counter-asap7-sc6t_rev26_lvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc6t_rev26_lvt-synth", -) - -gds_write( - name = "verilog_counter-asap7-sc6t_rev26_lvt-gds", - implemented_rtl = ":verilog_counter-asap7-sc6t_rev26_lvt-place_and_route", -) - -# asap7-sc6t_rev26_slvt - -synthesize_rtl( - name = "verilog_counter-asap7-sc6t_rev26_slvt-synth", - standard_cells = "@org_theopenroadproject_asap7//:asap7-sc6t_rev26_slvt", - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":verilog_counter", - ], -) - -run_opensta( - name = "verilog_counter-asap7-sc6t_rev26_slvt-synth_sta", - synth_target = ":verilog_counter-asap7-sc6t_rev26_slvt-synth", -) - -place_and_route( - name = "verilog_counter-asap7-sc6t_rev26_slvt-place_and_route", - core_padding_microns = 1, - die_height_microns = 20, - die_width_microns = 20, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":verilog_counter-asap7-sc6t_rev26_slvt-synth", +asap7_targets( + name = "verilog_counter-asap7-6t_rev26_rvt", + has_gds = False, # FIXME: These cells do actually have GDS + rev = 26, + target = "verilog_counter", + tracks = "6t", + vt = "rvt", +) + +asap7_targets( + name = "verilog_counter-asap7-6t_rev26_lvt", + has_gds = False, # FIXME: These cells do actually have GDS + rev = 26, + target = "verilog_counter", + tracks = "6t", + vt = "lvt", +) + +asap7_targets( + name = "verilog_counter-asap7-6t_rev26_slvt", + has_gds = False, # FIXME: These cells do actually have GDS + rev = 26, + target = "verilog_counter", + tracks = "6t", + vt = "slvt", ) From 14c7e3c24e3427d027e75c08ccc58244e44674af Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 8 Nov 2023 11:32:35 -0800 Subject: [PATCH 05/10] Fix 6t target config. Signed-off-by: Tim 'mithro' Ansell --- .../bundled.BUILD.bazel | 76 ++++++++++--------- .../cells-lvt.bzl | 22 +++--- .../cells-rvt.bzl | 22 +++--- .../cells-slvt.bzl | 22 +++--- .../common.bzl | 10 ++- 5 files changed, 80 insertions(+), 72 deletions(-) diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel index 95d78515..2c52b334 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel @@ -60,7 +60,7 @@ asap7_cells_files( open_road_pdk_configuration( name = "open_road-asap7-sc6t_rev26_lvt", cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_L", + cts_buffer_cell = "BUFx4_ASAP7_6t_L", do_not_use_cell_list = [ "*x1_ASAP7*", "*x1p*_ASAP7*", @@ -69,14 +69,14 @@ open_road_pdk_configuration( "ICG*", "DFFH*", ], - endcap_cell = "TAPCELL_ASAP7_75t_L", + endcap_cell = "TAPCELL_ASAP7_6t_L", fill_cells = [ - "FILLERxp5_ASAP7_75t_L", - "DECAPx1_ASAP7_75t_L", - "DECAPx2_ASAP7_75t_L", - "DECAPx4_ASAP7_75t_L", - "DECAPx6_ASAP7_75t_L", - "DECAPx10_ASAP7_75t_L", + "FILLERxp5_ASAP7_6t_L", + "DECAPx1_ASAP7_6t_L", + "DECAPx2_ASAP7_6t_L", + "DECAPx4_ASAP7_6t_L", + "DECAPx6_ASAP7_6t_L", + "DECAPx10_ASAP7_6t_L", ], global_placement_cell_pad = 2, global_routing_clock_layers = "M2-M7", @@ -94,10 +94,10 @@ open_road_pdk_configuration( pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_L", + tap_cell = "TAPCELL_ASAP7_6t_L", tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_L/H", - tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_high_port = "TIEHIxp5_ASAP7_6t_L/H", + tie_low_port = "TIELOxp5_ASAP7_6t_L/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", @@ -118,7 +118,7 @@ asap7_cells_files( open_road_pdk_configuration( name = "open_road-asap7-sc6t_rev26_rvt", cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_R", + cts_buffer_cell = "BUFx4_ASAP7_6t_R", do_not_use_cell_list = [ "*x1_ASAP7*", "*x1p*_ASAP7*", @@ -127,14 +127,14 @@ open_road_pdk_configuration( "ICG*", "DFFH*", ], - endcap_cell = "TAPCELL_ASAP7_75t_R", + endcap_cell = "TAPCELL_ASAP7_6t_R", fill_cells = [ - "FILLERxp5_ASAP7_75t_R", - "DECAPx1_ASAP7_75t_R", - "DECAPx2_ASAP7_75t_R", - "DECAPx4_ASAP7_75t_R", - "DECAPx6_ASAP7_75t_R", - "DECAPx10_ASAP7_75t_R", + "FILLERxp5_ASAP7_6t_R", + "DECAPx1_ASAP7_6t_R", + "DECAPx2_ASAP7_6t_R", + "DECAPx4_ASAP7_6t_R", + "DECAPx6_ASAP7_6t_R", + "DECAPx10_ASAP7_6t_R", ], global_placement_cell_pad = 2, global_routing_clock_layers = "M2-M7", @@ -152,10 +152,10 @@ open_road_pdk_configuration( pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_R", + tap_cell = "TAPCELL_ASAP7_6t_R", tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_R/H", - tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_high_port = "TIEHIxp5_ASAP7_6t_R/H", + tie_low_port = "TIELOxp5_ASAP7_6t_R/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", @@ -176,7 +176,7 @@ asap7_cells_files( open_road_pdk_configuration( name = "open_road-asap7-sc6t_rev26_slvt", cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + cts_buffer_cell = "BUFx4_ASAP7_6t_SL", do_not_use_cell_list = [ "*x1_ASAP7*", "*x1p*_ASAP7*", @@ -185,14 +185,14 @@ open_road_pdk_configuration( "ICG*", "DFFH*", ], - endcap_cell = "TAPCELL_ASAP7_75t_SL", + endcap_cell = "TAPCELL_ASAP7_6t_SL", fill_cells = [ - "FILLERxp5_ASAP7_75t_SL", - "DECAPx1_ASAP7_75t_SL", - "DECAPx2_ASAP7_75t_SL", - "DECAPx4_ASAP7_75t_SL", - "DECAPx6_ASAP7_75t_SL", - "DECAPx10_ASAP7_75t_SL", + "FILLERxp5_ASAP7_6t_SL", + "DECAPx1_ASAP7_6t_SL", + "DECAPx2_ASAP7_6t_SL", + "DECAPx4_ASAP7_6t_SL", + "DECAPx6_ASAP7_6t_SL", + "DECAPx10_ASAP7_6t_SL", ], global_placement_cell_pad = 2, global_routing_clock_layers = "M2-M7", @@ -210,10 +210,10 @@ open_road_pdk_configuration( pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_SL", + tap_cell = "TAPCELL_ASAP7_6t_SL", tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", - tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_high_port = "TIEHIxp5_ASAP7_6t_SL/H", + tie_low_port = "TIELOxp5_ASAP7_6t_SL/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", @@ -231,10 +231,14 @@ asap7_srams_files( tracks = "6t", ) -filegroup( +# FIXME: Where is the 1x techlef? +#filegroup( +# name = "asap7-misc-sc6t_rev26-lef", +# srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"], +#) +alias( name = "asap7-misc-sc6t_rev26-lef", - # FIXME: Where is the 1x techlef? - srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"], + actual = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-misc-sc7p5t_rev28-lef", ) filegroup( diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl index cd519caa..52b4163b 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl @@ -25,7 +25,7 @@ asap7_cells_files( open_road_pdk_configuration( name = "open_road-asap7-sc6t_rev26_lvt", cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_L", + cts_buffer_cell = "BUFx4_ASAP7_6t_L", do_not_use_cell_list = [ "*x1_ASAP7*", "*x1p*_ASAP7*", @@ -34,14 +34,14 @@ open_road_pdk_configuration( "ICG*", "DFFH*", ], - endcap_cell = "TAPCELL_ASAP7_75t_L", + endcap_cell = "TAPCELL_ASAP7_6t_L", fill_cells = [ - "FILLERxp5_ASAP7_75t_L", - "DECAPx1_ASAP7_75t_L", - "DECAPx2_ASAP7_75t_L", - "DECAPx4_ASAP7_75t_L", - "DECAPx6_ASAP7_75t_L", - "DECAPx10_ASAP7_75t_L", + "FILLERxp5_ASAP7_6t_L", + "DECAPx1_ASAP7_6t_L", + "DECAPx2_ASAP7_6t_L", + "DECAPx4_ASAP7_6t_L", + "DECAPx6_ASAP7_6t_L", + "DECAPx10_ASAP7_6t_L", ], global_placement_cell_pad = 2, global_routing_clock_layers = "M2-M7", @@ -59,10 +59,10 @@ open_road_pdk_configuration( pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_L", + tap_cell = "TAPCELL_ASAP7_6t_L", tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_L/H", - tie_low_port = "TIELOx1_ASAP7_75t_L/L", + tie_high_port = "TIEHIxp5_ASAP7_6t_L/H", + tie_low_port = "TIELOxp5_ASAP7_6t_L/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl index ca3e58ce..1129c6c8 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl @@ -25,7 +25,7 @@ asap7_cells_files( open_road_pdk_configuration( name = "open_road-asap7-sc6t_rev26_rvt", cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_R", + cts_buffer_cell = "BUFx4_ASAP7_6t_R", do_not_use_cell_list = [ "*x1_ASAP7*", "*x1p*_ASAP7*", @@ -34,14 +34,14 @@ open_road_pdk_configuration( "ICG*", "DFFH*", ], - endcap_cell = "TAPCELL_ASAP7_75t_R", + endcap_cell = "TAPCELL_ASAP7_6t_R", fill_cells = [ - "FILLERxp5_ASAP7_75t_R", - "DECAPx1_ASAP7_75t_R", - "DECAPx2_ASAP7_75t_R", - "DECAPx4_ASAP7_75t_R", - "DECAPx6_ASAP7_75t_R", - "DECAPx10_ASAP7_75t_R", + "FILLERxp5_ASAP7_6t_R", + "DECAPx1_ASAP7_6t_R", + "DECAPx2_ASAP7_6t_R", + "DECAPx4_ASAP7_6t_R", + "DECAPx6_ASAP7_6t_R", + "DECAPx10_ASAP7_6t_R", ], global_placement_cell_pad = 2, global_routing_clock_layers = "M2-M7", @@ -59,10 +59,10 @@ open_road_pdk_configuration( pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_R", + tap_cell = "TAPCELL_ASAP7_6t_R", tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_R/H", - tie_low_port = "TIELOx1_ASAP7_75t_R/L", + tie_high_port = "TIEHIxp5_ASAP7_6t_R/H", + tie_low_port = "TIELOxp5_ASAP7_6t_R/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl index a46c4839..a426bb3f 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl @@ -25,7 +25,7 @@ asap7_cells_files( open_road_pdk_configuration( name = "open_road-asap7-sc6t_rev26_slvt", cell_site = "asap7sc6t", - cts_buffer_cell = "BUFx4_ASAP7_75t_SL", + cts_buffer_cell = "BUFx4_ASAP7_6t_SL", do_not_use_cell_list = [ "*x1_ASAP7*", "*x1p*_ASAP7*", @@ -34,14 +34,14 @@ open_road_pdk_configuration( "ICG*", "DFFH*", ], - endcap_cell = "TAPCELL_ASAP7_75t_SL", + endcap_cell = "TAPCELL_ASAP7_6t_SL", fill_cells = [ - "FILLERxp5_ASAP7_75t_SL", - "DECAPx1_ASAP7_75t_SL", - "DECAPx2_ASAP7_75t_SL", - "DECAPx4_ASAP7_75t_SL", - "DECAPx6_ASAP7_75t_SL", - "DECAPx10_ASAP7_75t_SL", + "FILLERxp5_ASAP7_6t_SL", + "DECAPx1_ASAP7_6t_SL", + "DECAPx2_ASAP7_6t_SL", + "DECAPx4_ASAP7_6t_SL", + "DECAPx6_ASAP7_6t_SL", + "DECAPx10_ASAP7_6t_SL", ], global_placement_cell_pad = 2, global_routing_clock_layers = "M2-M7", @@ -59,10 +59,10 @@ open_road_pdk_configuration( pin_horizontal_metal_layer = "M4", pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", - tap_cell = "TAPCELL_ASAP7_75t_SL", + tap_cell = "TAPCELL_ASAP7_6t_SL", tapcell_distance = 25, - tie_high_port = "TIEHIx1_ASAP7_75t_SL/H", - tie_low_port = "TIELOx1_ASAP7_75t_SL/L", + tie_high_port = "TIEHIxp5_ASAP7_6t_SL/H", + tie_low_port = "TIELOxp5_ASAP7_6t_SL/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks.tcl", wire_rc_clock_metal_layer = "M5", diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/common.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/common.bzl index 0ce244f7..16eb4dc5 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/common.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/common.bzl @@ -22,10 +22,14 @@ asap7_srams_files( tracks = "6t", ) -filegroup( +# FIXME: Where is the 1x techlef? +#filegroup( +# name = "asap7-misc-sc6t_rev26-lef", +# srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"], +#) +alias( name = "asap7-misc-sc6t_rev26-lef", - # FIXME: Where is the 1x techlef? - srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"], + actual = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-misc-sc7p5t_rev28-lef", ) filegroup( From 9fac313d966a53d8248a48bc792e43e0d1a7233e Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 8 Nov 2023 11:32:35 -0800 Subject: [PATCH 06/10] Disable 6t targets for now. Signed-off-by: Tim 'mithro' Ansell --- synthesis/tests/BUILD | 50 +++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD index 75bb5502..a81a085a 100644 --- a/synthesis/tests/BUILD +++ b/synthesis/tests/BUILD @@ -150,29 +150,27 @@ asap7_targets( ) # ASAP7 6 track rev 26 -asap7_targets( - name = "verilog_counter-asap7-6t_rev26_rvt", - has_gds = False, # FIXME: These cells do actually have GDS - rev = 26, - target = "verilog_counter", - tracks = "6t", - vt = "rvt", -) - -asap7_targets( - name = "verilog_counter-asap7-6t_rev26_lvt", - has_gds = False, # FIXME: These cells do actually have GDS - rev = 26, - target = "verilog_counter", - tracks = "6t", - vt = "lvt", -) - -asap7_targets( - name = "verilog_counter-asap7-6t_rev26_slvt", - has_gds = False, # FIXME: These cells do actually have GDS - rev = 26, - target = "verilog_counter", - tracks = "6t", - vt = "slvt", -) +# FIXME: Enable the 6 track config. +#asap7_targets( +# name = "verilog_counter-asap7-6t_rev26_rvt", +# rev = 26, +# target = "verilog_counter", +# tracks = "6t", +# vt = "rvt", +#) +# +#asap7_targets( +# name = "verilog_counter-asap7-6t_rev26_lvt", +# rev = 26, +# target = "verilog_counter", +# tracks = "6t", +# vt = "lvt", +#) +# +#asap7_targets( +# name = "verilog_counter-asap7-6t_rev26_slvt", +# rev = 26, +# target = "verilog_counter", +# tracks = "6t", +# vt = "slvt", +#) From 4b0ada6cc4360a967dd27692676489cf24f9d14c Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 8 Nov 2023 12:01:50 -0800 Subject: [PATCH 07/10] Working on 4x config. Signed-off-by: Tim 'mithro' Ansell --- .../org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel | 2 +- .../org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel index ca2682ab..e2d126e4 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel @@ -272,7 +272,7 @@ open_road_pdk_configuration( pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_R", - tapcell_distance = 25, + tapcell_distance = 25 * 4, # We are using the by 4 variants of these cells. tie_high_port = "TIEHIx1_ASAP7_75t_R/H", tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl index ee4b7234..a8fc7eba 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl @@ -119,7 +119,7 @@ open_road_pdk_configuration( pin_vertical_metal_layer = "M5", rc_script_configuration = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:rc_script.tcl", tap_cell = "TAPCELL_ASAP7_75t_R", - tapcell_distance = 25, + tapcell_distance = 25 * 4, # We are using the by 4 variants of these cells. tie_high_port = "TIEHIx1_ASAP7_75t_R/H", tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, From c4e22741572fc9f44ba6f0e5591c8284b7004789 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 8 Nov 2023 12:00:39 -0800 Subject: [PATCH 08/10] Disable 4x scaled 7.5 track config. Signed-off-by: Tim 'mithro' Ansell --- synthesis/tests/BUILD | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD index a81a085a..f931eee2 100644 --- a/synthesis/tests/BUILD +++ b/synthesis/tests/BUILD @@ -139,15 +139,16 @@ asap7_targets( ) # ASAP7 7.5 track rev 27 4x scaled version -asap7_targets( - name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x", - size = 2000, - has_gds = False, # No GDS for the 4x cells - rev = 27, - target = "verilog_counter", - tracks = "7p5t", - vt = "rvt_4x", -) +# FIXME: Enable the 4x scaled 7.5 track config. +#asap7_targets( +# name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x", +# size = 2000, +# has_gds = False, # No GDS for the 4x cells +# rev = 27, +# target = "verilog_counter", +# tracks = "7p5t", +# vt = "rvt_4x", +#) # ASAP7 6 track rev 26 # FIXME: Enable the 6 track config. From 9521b50717fee75477a70f526f959866ec3d3e86 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 8 Nov 2023 12:37:57 -0800 Subject: [PATCH 09/10] Fix the SRAM macro. Signed-off-by: Tim 'mithro' Ansell --- .../org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl index ab619ed7..e9480145 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl @@ -50,21 +50,21 @@ def asap7_srams_files(name = None, rev = None, tracks = None, has_gds = True): # ------------------------------------------------------------------------ native.filegroup( name = "asap7-srams-sc{tracks}_rev{rev}-lvs".format(**args), - srcs = ["CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)], + srcs = native.glob(["CDL/LVS/asap7sc{tracks}_{rev}_*SRAM*.cdl".format(**args)]), ) # CDL models for Spice simulation # ------------------------------------------------------------------------ native.filegroup( name = "asap7-srams-sc{tracks}_rev{rev}-spice".format(**args), - srcs = ["CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)], + srcs = native.glob(["CDL/xAct3D_extracted/asap7sc{tracks}_{rev}_*SRAM*.sp".format(**args)]), ) # Place and route # ------------------------------------------------------------------------ native.filegroup( name = "asap7-srams-sc{tracks}_rev{rev}-lef".format(**args), - srcs = ["LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)], + srcs = native.glob(["LEF/asap7sc{tracks}_{rev}*_SRAM_*.lef".format(**args)]), ) def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds = True): From 7ef2b943210604b9955c1be73421793afe4743f3 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 8 Nov 2023 17:31:35 -0800 Subject: [PATCH 10/10] Remove unused file. Signed-off-by: Tim 'mithro' Ansell --- .../org_theopenroadproject_asap7.bzl | 30 ------------------- 1 file changed, 30 deletions(-) delete mode 100644 dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl deleted file mode 100644 index 50d93c40..00000000 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/org_theopenroadproject_asap7.bzl +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2022 Google LLC -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -"""Registers Bazel workspaces for the Boost C++ libraries.""" - -load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive") -load("@bazel_tools//tools/build_defs/repo:utils.bzl", "maybe") - -def org_theopenroadproject_asap7_pdk_r1p7(): - maybe( - http_archive, - name = "org_theopenroadproject_asap7_pdk_r1p7", - urls = [ - "https://github.com/The-OpenROAD-Project/asap7_pdk_r1p7/archive/1ff7649bbf423207f6f70293dc1cf630cd477365.tar.gz", - ], - strip_prefix = "asap7_pdk_r1p7-1ff7649bbf423207f6f70293dc1cf630cd477365", - sha256 = "b5847f93e55debb49d03ec581e22eb301109ff90c9ad19d35ae1223c70250391", - build_file = Label("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:bundled.BUILD.bazel"), - )