debug_opcode_transition.sav

[*]
[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
[*] Mon Aug 15 01:41:54 2022
[*]
[dumpfile] "/home/horacio/src/riscv_i32_minimum/test_case_rv32.vcd"
[dumpfile_mtime] "Mon Aug 15 01:38:31 2022"
[dumpfile_size] 46760
[savefile] "/home/horacio/src/riscv_i32_minimum/debug_opcode_transition.sav"
[timestart] 24930
[size] 1920 1015
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[treeopen] test_bench_rv32.
[treeopen] test_bench_rv32.execute_0.
[treeopen] test_bench_rv32.execute_0.alu_rv_0.
[treeopen] test_bench_rv32.execute_0.alu_rv_0.alu_register_register_0.
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[sst_vpaned_height] 295
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test_bench_rv32.clock
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test_bench_rv32.opcode[6:0]
test_bench_rv32.rs1_value[31:0]
test_bench_rv32.rs2_value[31:0]
test_bench_rv32.immediate12_itype[31:0]
test_bench_rv32.rd_value[31:0]
test_bench_rv32.rd[4:0]
@28
test_bench_rv32.alu_register_register_enable
test_bench_rv32.execute_0.alu_rv_0.alu_register_register_0.alu_base_0.alu_base_enable
@22
test_bench_rv32.execute_0.alu_rv_0.alu_register_register_0.alu_base_0.rd_value[31:0]
test_bench_rv32.execute_0.alu_rv_0.alu_register_register_0.alu_base_0.rs1_value[31:0]
test_bench_rv32.execute_0.alu_rv_0.alu_register_register_0.alu_base_0.rs2_value[31:0]
@28
test_bench_rv32.alu_register_immediate_enable
@23
test_bench_rv32.fetch_0.instruction[31:0]
[pattern_trace] 1
[pattern_trace] 0