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Upstream INT3472 GPIO type 0x12 / Lattice MIPI aggregator support #281
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Hmm, doing a duckduckgo search for "Lattice MIPI aggregator" ends up at: https://www.latticesemi.com/Products/FPGAandCPLD/CrossLink If the "Lattice MIPI aggregator" is a MIPI CSI-2 mux/demux then it really needs to be modelled as part of the media-controller graph similar to how upstream handles the IVSC chip. |
Hi @jwrdegoede ,
SoC controls Lattice by USB command. The virtual I2C & GPIO are actually on USB connection between SoC and Lattice. There are also MIPI CSI-2 connections between SoC & Lattice.
Yes, SoC can transfer firmware updates to Lattice chip. But I don't know the detail steps.
We need at least a USB virtual GPIO & I2C driver for Lattice device. Once the drivers are ready, we can drive the virtual handshake GPIO to high to powe-up the sensor.
I2C, MIPI CSI-2 and some power & clock pins.
Yes.
For my point of view, the I2C is virtual so actually driver send I2C request to USBIO driver, then USBIO driver construct the USB command from SoC to Lattice, then Lattice hardware/firmware send the actual I2C command to camera sensor.
I can draw what I know here:
@lwang47-amr Please help correct me if anything wrong, thanks! |
@hao-yao thank you for your answers and for the ASCII art schematic that is very helpful. So it looks like the MIPI-CSI2 parts needs to become a media-controller entity on the media-controller graph just like how this is done for the iVSC chip. I also see that the drivers for this from https://github.com/intel/usbio-drivers/ are still using the old MFD framework similar to how the iVSC drivers where changed from MFD to use the new auxbus interface, this will also need to use the auxbus with separate auxbus children devices for the I2C-controller, GPIO-controller and MIPI/vision parts. @lwang47-amr, what are the plans / timeline for upstreaming the drivers for this ? |
hi its been a month. any new updates on the issue? |
This is what I'm currently getting on Fedora 41, qcam shows no available sensors to use. I forced the usage of the ov08x40 kernel module and blacklisted ov2740 since it seemed to get automatically loaded for some reason, but didn't make any difference. This is on a Lenovo X1C G12 v4l2-ctl --list-devices
dmesg
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Is this the Lattice MIPI aggregator USB device? This is from a thinkpad X1 2-in-1 Gen 9
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I looked into this a bit more. To answer my own question, the USB device with ID I compiled a 6.12.1 kernel with the handshake pin patch that @jwrdegoede linked above applied. In addition, I compiled the usbio-drivers kernel module and loaded it before the With those changes, both the I assume it may work if the handshake pin is asserted. In the discussion of the patch, @hao-yao commented "It starts outputing MIPI packages when we pull handshake pins high". Unfortunately is is not clear which pin the handshake pin is. The @hao-yao can you help with this? |
Also, when also loading the
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Hi, nice to meet you. I saw your reply about this to my blogpost https://hansdegoede.dreamwidth.org/28841.html but lets continue discussing this here. I should receive a X1 Carbon with the Lattice MIPI aggregator chip soon. Once I have it I'll try to get things to work with the out of tree drivers for this and then once I have things working we can see from there. Note I'm taking 2 weeks of with Christmas so I likely won't get around to this until after January 1st. Thank you for your offer to help with this, once we have things working I believe that the code from https://github.com/intel/usbio-drivers will need a bunch of work before it will be submitted upstream. Like moving it from being a MFD driver to the new auxiliary bus kernel framework similar to what was done for the LJCA driver before it was mainlined. @hao-yao do you know what Intel's plans are for upstreaming the usb-io drivers ? I want to avoid us doing double work where e.g. Intel is already working on moving the code to the auxiliary bus infrastructure and we end up doing the same work a second time. |
Hans @jwrdegoede ,
As far as I know, the owner team of usbio-drivers is working on the upstreaming in progress, however I don't know the detail plan or schedule. I think you can check with the usbio-drivers maintainer for the detail. |
@jwrdegoede Nice to meet you too. Sounds good, I will be happy to help early next year. |
Some Meteor Lake laptops return a GPIO/pin type of 0x12 from the INT3472 79234640-9e10-4fea-a5c1-b5aa8b19756f _DSM.
A while ago 2 patches have been posted upstream for this indicating that this is related to a new "Lattice MIPI aggregator" chip:
https://lore.kernel.org/platform-driver-x86/[email protected]/
https://lore.kernel.org/platform-driver-x86/[email protected]/
With mainline kernel + libcamera softISP support landing in Fedora 41:
https://hansdegoede.dreamwidth.org/28841.html
Users are now reporting issues with things not working on e.g. a HP Spectre x360 14-eu0xxx with an OVTI08F4/ov08x40 sensor.
dmesg shows the following line indicating that this laptop has the "Lattice MIPI aggregator" chip:
I would like to start working on supporting this setup in the mainline kernel, but first I need to better understand what the "Lattice MIPI aggregator" chip exactly is.
The ACPI tables show that the sensor is directly connected to one of the designware I2C controllers of the main SoC, so there seems to be no USB attached IO-expander (LJCA) ?
I guess that the "Lattice MIPI aggregator" takes the place of the IO-expander and that it takes care of providing extclk/xvclk, voltages and control of reset/powerdown GPIOs? And that all of that then gets controlled by this one single handshake GPIO and the chip takes care of doing the necessary power up/down sequencing with all necessary delays itself ?
Can you please answer the following questions:
My goal with these questions is to better understand what the exact function / purpose of the "Lattice MIPI aggregator" is.
Once I have a clearer picture of what the exact function / purpose of the "Lattice MIPI aggregator" is I'll send a proposal for how to get this supported in the upstream kernel to the linux-media mailinglist.
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