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multiplier.qsf
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# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# multiplier_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C20F400C7
set_global_assignment -name TOP_LEVEL_ENTITY multiplier
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "8.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:13:37 DECEMBER 19, 2011"
set_global_assignment -name LAST_QUARTUS_VERSION 8.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AHDL_FILE logic.tdf
set_global_assignment -name BDF_FILE multiplier.bdf
set_global_assignment -name BDF_FILE state_machine.bdf
set_global_assignment -name BDF_FILE p_register.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE multiplier.vwf
set_global_assignment -name BDF_FILE block_name.bdf
set_global_assignment -name BDF_FILE input_select.bdf
set_global_assignment -name BDF_FILE bit_flips.bdf
set_global_assignment -name BDF_FILE add_subt_decision.bdf
set_global_assignment -name BDF_FILE adder.bdf
set_global_assignment -name BDF_FILE add_subt_select.bdf
set_global_assignment -name BDF_FILE bus_combine.bdf
set_global_assignment -name QIP_FILE lpm_add_sub0.qip
set_global_assignment -name BDF_FILE temp_register.bdf
set_global_assignment -name BDF_FILE np_register.bdf
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE multiplier.vwf
set_global_assignment -name BDF_FILE adder_subtractor.bdf
set_global_assignment -name BDF_FILE simple_adder.bdf
set_global_assignment -name BDF_FILE CLA_logic.bdf
set_global_assignment -name VHDL_FILE overflow_generate.vhd