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base repository: ucb-bar/esp-llvm
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base: riscv-trunk
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head repository: jeffy1009/riscv-llvm
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  • 14 commits
  • 8 files changed
  • 2 contributors

Commits on Jul 28, 2016

  1. expand bswap intrinsic 

    bswap operation should be expanded. RISC-V instruction selection cannot
handle this operation.
    @jeffy1009
    jeffy1009 committed Jul 28, 2016
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  2. fix isBranch 

    JAL, JALR is not branch, but call. This bug caused infinite loops in
RISC-V branch selector. Since JAL, JALR was considered as a branch, the
branch selector tried to handle those instructions, but the changes were
made at the terminator instruction which is the end of the basic
block. This led to adding branch instruction again and again at the end
of the basic block
    @jeffy1009
    jeffy1009 committed Jul 28, 2016
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  3. add register mask to call instruction 

    There were no register mask operand in call instruction, which made
register allocator use caller-saved register without properly saving and
restoring it. So sometimes the procedure call has overridden the
register, which caused program crashes.
    @jeffy1009
    jeffy1009 committed Jul 28, 2016
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    771d505 View commit details

  4. ExternalSymbol lowering 

    Calls to ExternalSymbol like memset, memcpy was converted to JAL
instruction, and it caused linking to fail in some big programs, since
the address offset could not fit in the immediate fields.
    @jeffy1009
    jeffy1009 committed Jul 28, 2016
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    5c98580 View commit details

  5. update pointer to clang repo

    @jeffy1009
    jeffy1009 committed Jul 28, 2016
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Commits on Apr 3, 2017

  1. Always use frame pointer 

    see the commited comments for the explanation

Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed Apr 3, 2017
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  2. Fixed VAArg lowering in RV64 

    In RISC-V, 32-bit and 64-bit types are allowed in the instruction
selection stage. Var args are passed to the callee either
in register or in memory. Those passed in registers are also pushed onto
the stack in the callee. va_start() will set the pointer to the first
argument and each call of va_arg() will advance the pointer.
In RISCV64, both 32-bit and 64-bit types are pushed on the stack 8-byte
aligned. So the pointer must be advanced by 8 every time.

Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed Apr 3, 2017
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  3. Fixed and refactored emitSelectCC 

    emitSelectCC assigned true and false value oppositely in one of its
if-else cases. Fixed the issue and also refactored the code.

(cherry picked from commit 026b87dec7a53c98a1539b1b46f038a0a1819cb6)
Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed Apr 3, 2017
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  4. Generate explicit sign and zero extension 

    RISCV-64 needs explicit sign extension for instructions without "W" at
the end, and explicit zero extension for MUL instruction. Before this
fix, "truncate" and "zext" IR instructions are selected to
EXTRACT_SUBREG and SUBREG_TO_REG, respectively, which were optimized
away during the following passes. This fix is not pretty, but I couldn't
think of a better way that's also simple to apply.

Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed Apr 3, 2017
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  5. RISCV_ZEXT expansion: Added kill flags 

    Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed Apr 3, 2017
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  6. Override isFPCloseToIncomingSP() 

    In current RISCV-LLVM, FP is actually set to the post-prolog SP,
pointing the bottom of the function frame. Emergency spill slot needs to
be close to the bottom of the stack, so that it can be reachble from FP
without using another register (that is, the offset is fit into the imm
field of LD/ST). If the offset does not fit, then we need a register to
load the offset into, so we need to find another emergency spill slot..
creating the infinite loop.
isFPCloseToIncomingSP() provides easy way to make the emergency spill
slot close to the top/bottom of the stack frame.

Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed Apr 3, 2017
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  7. Assert on byval flags 

    I put Byval flags handling in clang TargetInfo.cpp. So there shouldn't
be any byval flags in IR.

Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed Apr 3, 2017
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Commits on May 31, 2017

  1. fixed minor uninitialized read bug ... 

    that caused undeterministic stack offset

Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed May 31, 2017
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  2. fixed isLoad/StoreFromStackSlot ... 

    which caused register to be spilled repeatedly and sometimes generated a
long sequence of the same ld/st instructions

Signed-off-by: Jangseop Shin <[email protected]>
    @jeffy1009
    jeffy1009 committed May 31, 2017
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23 changes: 19 additions & 4 deletions lib/Target/RISCV/RISCVFrameLowering.cpp
View file
Original file line number Diff line number Diff line change
@@ -63,9 +63,23 @@ RISCVFrameLowering::RISCVFrameLowering()
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return MF.getTarget().Options.DisableFramePointerElim(MF) ||
MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
// FIXME
// s0 - fp alias caused some bugs when compiler tries to use fp register for
// other purpose than frame pointer (e.g. when -fomit-frame-pointer is
// applied). The reason is that s0 is not in GR32 in RISCVRegisterInfo.td, so
// the compiler couldn't find the register class for s0. But adding it to
// GR32 might cause other problems: GR32 is used for the allocation order
// during regalloc and thus fp and s0 will both be in the alloc order, which can
// be a problem. Also, during prolog-epilog insertion, if fp is used in the
// function, both fp and s0 will be in the SavedRegs computed by
// TFI->determineCalleeSaves(), and then compiler might allocate stack slots for
// both fp and s0. The same applies to s0_64 & fp_64.
// Until this problem is solved, we just force compiler to use fp as the frame
// pointer only.
return true;
// const MachineFrameInfo *MFI = MF.getFrameInfo();
// return MF.getTarget().Options.DisableFramePointerElim(MF) ||
// MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
}


@@ -312,7 +326,8 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &Sa
if (isInt<12>(MaxSPOffset))
return;

const TargetRegisterClass *RC = &RISCV::GR32BitRegClass;
const TargetRegisterClass *RC = STI.isRV64()?
&RISCV::GR64BitRegClass : &RISCV::GR32BitRegClass;
int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
RC->getAlignment(), false);
RS->addScavengingFrameIndex(FI);
5 changes: 5 additions & 0 deletions lib/Target/RISCV/RISCVFrameLowering.h
View file
Original file line number Diff line number Diff line change
@@ -20,6 +20,11 @@ class RISCVFrameLowering : public TargetFrameLowering {
public:
RISCVFrameLowering();

// In RISCV, FP is set to the post-prolog SP (Don't know why..)
// Need to override this to false, so that emergency spill slot is always
// reachable from FP (so that the offset fits in the imm field of LD)
bool isFPCloseToIncomingSP() const { return false; }

bool hasFP(const MachineFunction &MF) const;

/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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