Using a dual ADC raspberry pHAT for 20Msps+ acquisition
- High speed ADC pHAT
- version: V2.0
- date: 05/03/2018
- cost:99$
- sourcing:OSHPark, MacroFab, Tindie
- technology: SMD, AD9200
- language: C. Kernel module
- author: Kelu124
ITF-1_GND
ITF-2_VDD_5V
ITF-19_3.3V
ITF-12_RPIn
Signal Digitalized
AD9200
The aim of this module is to achieve 20Msps, at 9bits or more.
Raw Signal
->ITF-12_RPIn
->Selector
->ADC
->Buffer
->Pi
->Signal Digitalized
Raw Signal
->Onboard header
->Selector
+Vref/2 jumper
->ADC
GND
->Selector
External
->Selector
ITF-4_RawSig
->Doj Jumper
->ITF-12_RPIn
ITF-11_OffSig
->Doj Jumper
ITF-3_ENV
->Doj Jumper
- High speed, 9 bit ADCs!
- Full Altium source, Gerbers, BOM, schematics.
- Driver for the board.
- SMDs is tough to assemble
- Linux is not real time: there will be inaccuracies in the measurements!
- Need a custom kernel module
- See above ;)
You can refer to the 20180415r experiment. It is made of a unipolar pulser, double ADC board, and analog processing board. The experiment documentations is based on :
- Raspberry Pi drivers which create the /dev/ device on the raspberry pi from which a
cat /dev/hsdk/ > Datafile.DAT
extracts signals. The driver includes control for the pulser. - An example of Raw data that is created out of the driver
- the Jupyter notebook which processes capture files from the ADC into signals
- the resulting Processed data
Even without the board, you can use an example of such a file to play with.
Testing the module with the signal emulator module, which yields a signal at 1.9MHz, it well seen at 1.9MHz, with a sampling speed equal to two times this freq, ie 24Msps ! See the details below:
Experiment is detailed here.
With the details
Problem was that the Pi0 or PiW, with the current kernel module, can't run faster than around 10 to 12 Msps. Clock can be faster, but the memcpy limits the transfer to memory. Soooo.. what can we do? As a reminder, I wanted at least a 10Msps 10bit ADC.
Solution Why not interleaving two ADCs, with clocks in opposite phase? Hum that means 2 times 10 bits, and I had only 18 pins left once the Ultrasound SDK board connected. That means.. quite obviously, 2 times 9 bits.
So now I can run at twice the speed of the transfer, so a bit over 20Msps, over this time 9 bits. Or by oversampling, that could be 10Msps at 10 bits. With more flexibility !
Win.
At least for the moment, now I need to order the PCBs and some components.
-> BOM is around 30$ components, 5$ OSHPark PCB.. that's quite neat.
With the enveloppe
With the raw signal
See the jupyter notebook:
Issues: bugs in connected ADC pins + no offset really
and the corresponding schematics (PDF).
Beware the motherboard is designed to have the phat assembled as shown below
or as below:
- Lots
- Write the Quickstart
- Getting a board an soldering some ADCs
- Understand GPIO mem mapping
- Get raw data with offset vref/2
- Tests with a single ADC at 11Msps
- Produce a batch of rev2 elmo
- @ivan for his help on altium
The echOmods project and its prototypes (amongst which we find the ADC pHAT module) are open hardware, and working with open-hardware components.
Licensed under TAPR Open Hardware License (www.tapr.org/OHL)
Copyright Kelu124 ([email protected]) 2015-2018
The following work is base on a previous TAPR project, Murgen - and respects its TAPR license.
Copyright Kelu124 ([email protected]) 2015-2018