Referring to the Comportable guideline for peripheral device functionality , the module uart
Primary Clock: clk_i
Other Clocks: none
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO
Pin name
Direction
Description
rx
input
Serial receive bit
tx
output
Serial transmit bit
Port Name
Package::Struct
Type
Act
Width
Description
lsio_trigger
logic
uni
req
1
Self-clearing status trigger for the DMA. Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour.
tl
tlul_pkg::tl
req_rsp
rsp
1
Interrupt Name
Type
Description
tx_watermark
Status
raised if the transmit FIFO is past the high-water mark.
rx_watermark
Status
raised if the receive FIFO is past the high-water mark.
tx_done
Event
raised if the transmit FIFO has emptied and no transmit is ongoing.
rx_overflow
Event
raised if the receive FIFO has overflowed.
rx_frame_err
Event
raised if a framing error has been detected on receive.
rx_break_err
Event
raised if break condition has been detected on receive.
rx_timeout
Event
raised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.
rx_parity_err
Event
raised if the receiver has detected a parity error.
tx_empty
Status
raised if the transmit FIFO is empty.
Alert Name
Description
fatal_fault
This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
Countermeasure ID
Description
UART.BUS.INTEGRITY
End-to-end bus integrity scheme.