From c3ed16defef06f51ecd2d6f0ebc935611f757584 Mon Sep 17 00:00:00 2001 From: Pascal Nasahl Date: Thu, 14 Nov 2024 17:30:20 +0100 Subject: [PATCH] [sival,otbn] Add CW340 exec. env for otbn_mem_scramble_test Closes lowRISC/opentitan#20119. Signed-off-by: Pascal Nasahl --- sw/device/tests/BUILD | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 9216394294302..de8e2d25a001c 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -2510,14 +2510,14 @@ opentitan_test( name = "otbn_mem_scramble_test", srcs = ["otbn_mem_scramble_test.c"], exec_env = dicts.add( - EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, { + "//hw/top_earlgrey:fpga_cw340_sival": None, "//hw/top_earlgrey:silicon_creator": None, + "//hw/top_earlgrey:sim_dv": None, + "//hw/top_earlgrey:sim_verilator": None, }, ), - # TODO(#12486) [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel - fpga = fpga_params(tags = ["broken"]), verilator = verilator_params(timeout = "long"), deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey",