diff --git a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson index 6e61d34f93098..dbf00edeea48c 100644 --- a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson +++ b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson @@ -256,7 +256,29 @@ local: "false" expose: "true" }, - + { name: "PMPRstCfg" + type: "ibex_pkg::pmp_cfg_t" + default: "ibex_pkg::PmpCfgRst" + desc: "Reset value of PMP config CSRs" + local: "false" + expose: "true" + unpacked_dimensions: "[16]" + }, + { name: "PMPRstAddr" + type: "logic [33:0]" + default: "ibex_pkg::PmpAddrRst" + desc: "Reset value of PMP address CSRs" + local: "false" + expose: "true" + unpacked_dimensions: "[16]" + }, + { name: "PMPRstMsecCfg" + type: "ibex_pkg::pmp_mseccfg_t" + default: "ibex_pkg::PmpMseccfgRst" + desc: "Reset value of MSECCFG CSR" + local: "false" + expose: "true" + }, { name: "RV32E" type: "bit" default: "0" diff --git a/hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh b/hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh deleted file mode 100644 index 26f468f877300..0000000000000 --- a/hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh +++ /dev/null @@ -1,56 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Default reset values for PMP CSRs. Where the number of regions -// (PMPNumRegions) is less than 16 the reset values for the higher numbered -// regions are ignored. -// -// See the Ibex Reference Guide (Custom Reset Values under Physical Memory -// Protection) for more information. - -localparam pmp_cfg_t pmp_cfg_rst[16] = '{ - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 0 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 1 - '{lock: 1'b1, mode: PMP_MODE_NAPOT, exec: 1'b1, write: 1'b0, read: 1'b1}, // rgn 2 [ROM: LRX] - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 3 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 4 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 5 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 6 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 7 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 8 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 9 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 10 - '{lock: 1'b1, mode: PMP_MODE_TOR, exec: 1'b0, write: 1'b1, read: 1'b1}, // rgn 11 [MMIO: LRW] - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 12 - '{lock: 1'b1, mode: PMP_MODE_NAPOT, exec: 1'b1, write: 1'b1, read: 1'b1}, // rgn 13 [DV_ROM: LRWX] - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // rgn 14 - '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0} // rgn 15 -}; - -// Addresses are given in byte granularity for readibility. A minimum of two -// bits will be stripped off the bottom (PMPGranularity == 0) with more stripped -// off at coarser granularities. -// -// Note: The size of region 2 below must match `_epmp_reset_rx_size` in -// `sw/device/silicon_creator/rom/rom.ld` -localparam [33:0] pmp_addr_rst[16] = '{ - 34'h00000000, // rgn 0 - 34'h00000000, // rgn 1 - 34'h000083fc, // rgn 2 [ROM: base=0x0000_8000 size=0x800 (2KiB)] - 34'h00000000, // rgn 3 - 34'h00000000, // rgn 4 - 34'h00000000, // rgn 5 - 34'h00000000, // rgn 6 - 34'h00000000, // rgn 7 - 34'h00000000, // rgn 8 - 34'h00000000, // rgn 9 - 34'h40000000, // rgn 10 [MMIO: lo=0x4000_0000] - 34'h42010000, // rgn 11 [MMIO: hi=0x4201_0000] - 34'h00000000, // rgn 12 - 34'h000107fc, // rgn 13 [DV_ROM: base=0x0001_0000 size=0x1000 (4KiB)] - 34'h00000000, // rgn 14 - 34'h00000000 // rgn 15 -}; - -localparam pmp_mseccfg_t pmp_mseccfg_rst = '{rlb : 1'b1, mmwp: 1'b1, mml: 1'b0}; diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv index ebea08e1f9472..0faf981765012 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv @@ -12,30 +12,33 @@ module rv_core_ibex import rv_core_ibex_pkg::*; import rv_core_ibex_reg_pkg::*; #( - parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, - parameter bit PMPEnable = 1'b1, - parameter int unsigned PMPGranularity = 0, - parameter int unsigned PMPNumRegions = 16, - parameter int unsigned MHPMCounterNum = 10, - parameter int unsigned MHPMCounterWidth = 32, - parameter bit RV32E = 0, - parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MSingleCycle, - parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BOTEarlGrey, - parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF, - parameter bit BranchTargetALU = 1'b1, - parameter bit WritebackStage = 1'b1, - parameter bit ICache = 1'b1, - parameter bit ICacheECC = 1'b1, - parameter bit ICacheScramble = 1'b1, - parameter bit BranchPredictor = 1'b0, - parameter bit DbgTriggerEn = 1'b1, - parameter int unsigned DbgHwBreakNum = 4, - parameter bit SecureIbex = 1'b1, - parameter ibex_pkg::lfsr_seed_t RndCnstLfsrSeed = ibex_pkg::RndCnstLfsrSeedDefault, - parameter ibex_pkg::lfsr_perm_t RndCnstLfsrPerm = ibex_pkg::RndCnstLfsrPermDefault, - parameter int unsigned DmHaltAddr = 32'h1A110800, - parameter int unsigned DmExceptionAddr = 32'h1A110808, - parameter bit PipeLine = 1'b0, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit PMPEnable = 1'b1, + parameter int unsigned PMPGranularity = 0, + parameter int unsigned PMPNumRegions = 16, + parameter int unsigned MHPMCounterNum = 10, + parameter int unsigned MHPMCounterWidth = 32, + parameter ibex_pkg::pmp_cfg_t PMPRstCfg[16] = ibex_pkg::PmpCfgRst, + parameter logic [33:0] PMPRstAddr[16] = ibex_pkg::PmpAddrRst, + parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg = ibex_pkg::PmpMseccfgRst, + parameter bit RV32E = 0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MSingleCycle, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BOTEarlGrey, + parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF, + parameter bit BranchTargetALU = 1'b1, + parameter bit WritebackStage = 1'b1, + parameter bit ICache = 1'b1, + parameter bit ICacheECC = 1'b1, + parameter bit ICacheScramble = 1'b1, + parameter bit BranchPredictor = 1'b0, + parameter bit DbgTriggerEn = 1'b1, + parameter int unsigned DbgHwBreakNum = 4, + parameter bit SecureIbex = 1'b1, + parameter ibex_pkg::lfsr_seed_t RndCnstLfsrSeed = ibex_pkg::RndCnstLfsrSeedDefault, + parameter ibex_pkg::lfsr_perm_t RndCnstLfsrPerm = ibex_pkg::RndCnstLfsrPermDefault, + parameter int unsigned DmHaltAddr = 32'h1A110800, + parameter int unsigned DmExceptionAddr = 32'h1A110808, + parameter bit PipeLine = 1'b0, parameter logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] RndCnstIbexKeyDefault = ibex_pkg::RndCnstIbexKeyDefault, parameter logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonceDefault = @@ -371,6 +374,9 @@ module rv_core_ibex .PMPNumRegions ( PMPNumRegions ), .MHPMCounterNum ( MHPMCounterNum ), .MHPMCounterWidth ( MHPMCounterWidth ), + .PMPRstCfg ( PMPRstCfg ), + .PMPRstAddr ( PMPRstAddr ), + .PMPRstMsecCfg ( PMPRstMsecCfg ), .RV32E ( RV32E ), .RV32M ( RV32M ), .RV32B ( RV32B ), diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core index e95dedb2bcb2e..411f32b76570b 100644 --- a/hw/ip/rv_core_ibex/rv_core_ibex.core +++ b/hw/ip/rv_core_ibex/rv_core_ibex.core @@ -28,7 +28,6 @@ filesets: - rtl/rv_core_ibex_cfg_reg_top.sv - rtl/rv_core_ibex.sv - rtl/rv_core_addr_trans.sv - - rtl/ibex_pmp_reset.svh: {is_include_file: true} file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index ab6543f08f581..9465df162333e 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -8172,6 +8172,9 @@ PMPNumRegions: "16" MHPMCounterNum: "2" MHPMCounterWidth: "32" + PMPRstCfg: ibex_pmp_reset_pkg::PmpCfgRst + PMPRstAddr: ibex_pmp_reset_pkg::PmpAddrRst + PMPRstMsecCfg: ibex_pmp_reset_pkg::PmpMseccfgRst RV32E: "0" RV32M: ibex_pkg::RV32MSingleCycle RV32B: ibex_pkg::RV32BOTEarlGrey @@ -8322,6 +8325,32 @@ expose: "true" name_top: RvCoreIbexMHPMCounterWidth } + { + name: PMPRstCfg + desc: Reset value of PMP config CSRs + type: ibex_pkg::pmp_cfg_t + unpacked_dimensions: "[16]" + default: ibex_pmp_reset_pkg::PmpCfgRst + expose: "true" + name_top: RvCoreIbexPMPRstCfg + } + { + name: PMPRstAddr + desc: Reset value of PMP address CSRs + type: logic [33:0] + unpacked_dimensions: "[16]" + default: ibex_pmp_reset_pkg::PmpAddrRst + expose: "true" + name_top: RvCoreIbexPMPRstAddr + } + { + name: PMPRstMsecCfg + desc: Reset value of MSECCFG CSR + type: ibex_pkg::pmp_mseccfg_t + default: ibex_pmp_reset_pkg::PmpMseccfgRst + expose: "true" + name_top: RvCoreIbexPMPRstMsecCfg + } { name: RV32E desc: RV32E diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 976784a19c5db..e8b18d7d7d96d 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -930,6 +930,9 @@ PMPNumRegions: "16", MHPMCounterNum: "2", MHPMCounterWidth: "32", + PMPRstCfg: "ibex_pmp_reset_pkg::PmpCfgRst", + PMPRstAddr: "ibex_pmp_reset_pkg::PmpAddrRst", + PMPRstMsecCfg: "ibex_pmp_reset_pkg::PmpMseccfgRst", RV32E: "0", RV32M: "ibex_pkg::RV32MSingleCycle", RV32B: "ibex_pkg::RV32BOTEarlGrey", diff --git a/hw/top_earlgrey/ibex_pmp_reset_pkg.core b/hw/top_earlgrey/ibex_pmp_reset_pkg.core new file mode 100644 index 0000000000000..b6c7ed22bb800 --- /dev/null +++ b/hw/top_earlgrey/ibex_pmp_reset_pkg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# XXX: This name is currently required as global identifier until we have +# support for "interfaces" or a similar concept. +# Tracked in https://github.com/olofk/fusesoc/issues/235 +name: "lowrisc:constants:ibex_pmp_reset_pkg" +description: "Top-level specific PMP reset settings" +filesets: + files_rtl: + depend: + - lowrisc:ip:rv_core_ibex_pkg + files: + - rtl/ibex_pmp_reset_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 8405c618911e7..32ba8fbfb475b 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -111,6 +111,9 @@ module top_earlgrey #( parameter int unsigned RvCoreIbexPMPNumRegions = 16, parameter int unsigned RvCoreIbexMHPMCounterNum = 2, parameter int unsigned RvCoreIbexMHPMCounterWidth = 32, + parameter ibex_pkg::pmp_cfg_t RvCoreIbexPMPRstCfg[16] = ibex_pmp_reset_pkg::PmpCfgRst, + parameter logic [33:0] RvCoreIbexPMPRstAddr[16] = ibex_pmp_reset_pkg::PmpAddrRst, + parameter ibex_pkg::pmp_mseccfg_t RvCoreIbexPMPRstMsecCfg = ibex_pmp_reset_pkg::PmpMseccfgRst, parameter bit RvCoreIbexRV32E = 0, parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle, parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BOTEarlGrey, @@ -2627,6 +2630,9 @@ module top_earlgrey #( .PMPNumRegions(RvCoreIbexPMPNumRegions), .MHPMCounterNum(RvCoreIbexMHPMCounterNum), .MHPMCounterWidth(RvCoreIbexMHPMCounterWidth), + .PMPRstCfg(RvCoreIbexPMPRstCfg), + .PMPRstAddr(RvCoreIbexPMPRstAddr), + .PMPRstMsecCfg(RvCoreIbexPMPRstMsecCfg), .RV32E(RvCoreIbexRV32E), .RV32M(RvCoreIbexRV32M), .RV32B(RvCoreIbexRV32B), diff --git a/hw/top_earlgrey/rtl/ibex_pmp_reset_pkg.sv b/hw/top_earlgrey/rtl/ibex_pmp_reset_pkg.sv new file mode 100644 index 0000000000000..450e25d320ec4 --- /dev/null +++ b/hw/top_earlgrey/rtl/ibex_pmp_reset_pkg.sv @@ -0,0 +1,58 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ibex_pmp_reset_pkg; + import ibex_pkg::*; + + // Default reset values for PMP CSRs. Where the number of regions + // (PMPNumRegions) is less than 16 the reset values for the higher numbered + // regions are ignored. + + localparam pmp_cfg_t PmpCfgRst[16] = '{ + // Region info + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 0 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 1 + '{lock: 1'b1, mode: PMP_MODE_NAPOT, exec: 1'b1, write: 1'b0, read: 1'b1}, // 2 [ROM: LRX] + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 3 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 4 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 5 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 6 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 7 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 8 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 9 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 10 + '{lock: 1'b1, mode: PMP_MODE_TOR, exec: 1'b0, write: 1'b1, read: 1'b1}, // 11 [MMIO: LRW] + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 12 + '{lock: 1'b1, mode: PMP_MODE_NAPOT, exec: 1'b1, write: 1'b1, read: 1'b1}, // 13 [DV_ROM: LRWX] + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 14 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0} // 15 + }; + + // Addresses are given in byte granularity for readibility. A minimum of two + // bits will be stripped off the bottom (PMPGranularity == 0) with more stripped + // off at coarser granularities. + // + // Note: The size of region 2 below must match `_epmp_reset_rx_size` in + // `sw/device/silicon_creator/rom/rom.ld` + localparam logic [33:0] PmpAddrRst[16] = '{ + 34'h00000000, // rgn 0 + 34'h00000000, // rgn 1 + 34'h000083fc, // rgn 2 [ROM: base=0x0000_8000 size=0x800 (2KiB)] + 34'h00000000, // rgn 3 + 34'h00000000, // rgn 4 + 34'h00000000, // rgn 5 + 34'h00000000, // rgn 6 + 34'h00000000, // rgn 7 + 34'h00000000, // rgn 8 + 34'h00000000, // rgn 9 + 34'h40000000, // rgn 10 [MMIO: lo=0x4000_0000] + 34'h42010000, // rgn 11 [MMIO: hi=0x4201_0000] + 34'h00000000, // rgn 12 + 34'h000107fc, // rgn 13 [DV_ROM: base=0x0001_0000 size=0x1000 (4KiB)] + 34'h00000000, // rgn 14 + 34'h00000000 // rgn 15 + }; + + localparam pmp_mseccfg_t PmpMseccfgRst = '{rlb : 1'b1, mmwp: 1'b1, mml: 1'b0}; +endpackage diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index f6b24ec6c687f..49a1a40993ccf 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -34,6 +34,7 @@ filesets: - lowrisc:ip:keymgr - lowrisc:constants:top_pkg - lowrisc:constants:jtag_id_pkg + - lowrisc:constants:ibex_pmp_reset_pkg - lowrisc:ip:otp_ctrl - lowrisc:ip:lc_ctrl - lowrisc:ip:usbdev