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xrun(64): 18.09-s011: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
TOOL: xrun(64) 18.09-s011: Started on Dec 08, 2022 at 03:28:49 CST
xrun
-64bit
-gui
-access r
cpu.v
sort_corrected_branch_test.v
Recompiling... reason: file './cpu.v' is newer than expected.
expected: Thu Dec 8 03:21:46 2022
actual: Thu Dec 8 03:28:39 2022
file: cpu.v
module worklib.mux:v
errors: 0, warnings: 0
module worklib.and_gate:v
errors: 0, warnings: 0
module worklib.nor_gate:v
errors: 0, warnings: 0
module worklib.xor_gate:v
errors: 0, warnings: 0
module worklib.or_gate:v
errors: 0, warnings: 0
module worklib.mux_32:v
errors: 0, warnings: 0
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: Registers.v line 3, file: cpu.v line 2)
module worklib.and_gate:v
errors: 0, warnings: 1
module worklib.dff:v
errors: 0, warnings: 0
module worklib.registers:v
errors: 0, warnings: 0
module worklib.dff_32:v
errors: 0, warnings: 0
module worklib.large_mux:v
errors: 0, warnings: 0
module worklib.dec_32:v
errors: 0, warnings: 0
module worklib.and_gate_32:v
errors: 0, warnings: 0
module or_gate (x, y, z);
|
xmvlog: *W,RECOME (./or_gate.v,1|13): recompiling design unit worklib.or_gate:v.
First compiled from line 1 of or_gate.v.
(`include file: ./or_gate.v line 1, `include file: Full_adder.v line 2, `include file: adder_32.v line 2, `include file: pc.v line 2, `include file: inst_memory.v line 1, file: cpu.v line 3)
module worklib.or_gate:v
errors: 0, warnings: 1
module xor_gate (x, y, z);
|
xmvlog: *W,RECOME (./xor_gate.v,2|14): recompiling design unit worklib.xor_gate:v.
First compiled from line 2 of xor_gate.v.
(`include file: ./xor_gate.v line 2, `include file: Full_adder.v line 3, `include file: adder_32.v line 2, `include file: pc.v line 2, `include file: inst_memory.v line 1, file: cpu.v line 3)
module worklib.xor_gate:v
errors: 0, warnings: 1
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: Full_adder.v line 4, `include file: adder_32.v line 2, `include file: pc.v line 2, `include file: inst_memory.v line 1, file: cpu.v line 3)
module worklib.and_gate:v
errors: 0, warnings: 1
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: shiftextender.v line 2, `include file: pc.v line 3, `include file: inst_memory.v line 1, file: cpu.v line 3)
module worklib.and_gate:v
errors: 0, warnings: 1
module worklib.and_gate_n:v
errors: 0, warnings: 0
module and_gate_32 (x, y, z);
|
xmvlog: *W,RECOME (./and_gate_32.v,1|17): recompiling design unit worklib.and_gate_32:v.
First compiled from line 1 of and_gate_32.v.
(`include file: ./and_gate_32.v line 1, `include file: shiftextender.v line 4, `include file: pc.v line 3, `include file: inst_memory.v line 1, file: cpu.v line 3)
module worklib.and_gate_32:v
errors: 0, warnings: 1
module mux_32 (sel, src0, src1, z);
|
xmvlog: *W,RECOME (./mux_32.v,1|12): recompiling design unit worklib.mux_32:v.
First compiled from line 1 of mux_32.v.
(`include file: ./mux_32.v line 1, `include file: pc.v line 4, `include file: inst_memory.v line 1, file: cpu.v line 3)
module worklib.mux_32:v
errors: 0, warnings: 1
1'h2 : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,44|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 44, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'h3 : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,45|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 45, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'h4 : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,46|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 46, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'h5 : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,47|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 47, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'h6 : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,48|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 48, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'h7 : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,49|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 49, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'h8 : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,50|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 50, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'h9 : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,51|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 51, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'ha : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,52|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 52, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hb : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,53|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 53, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hc : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,54|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 54, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hd : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,55|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 55, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'he : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,56|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 56, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hf : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,57|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 57, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hA : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,58|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 58, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hB : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,59|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 59, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hC : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,60|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 60, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hD : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,61|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 61, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hE : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,62|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 62, `include file: inst_memory.v line 2, file: cpu.v line 3)
1'hF : hex = 1;
|
xmvlog: *W,INTOVF (sram.v,63|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: sram.v line 63, `include file: inst_memory.v line 2, file: cpu.v line 3)
initiate();
|
xmvlog: *W,TMTPAR (sram.v,171|17): A task enable with no arguments must not include an empty set of parentheses [10.2.2 (IEEE Std 1364-2005)]. The compiler has ignored the parentheses. Use 'xmhelp xmvlog TMTPAR' for further information.
(`include file: sram.v line 171, `include file: inst_memory.v line 2, file: cpu.v line 3)
checkRAM();
|
xmvlog: *W,TMTPAR (sram.v,176|17): A task enable with no arguments must not include an empty set of parentheses [10.2.2 (IEEE Std 1364-2005)]. The compiler has ignored the parentheses. Use 'xmhelp xmvlog TMTPAR' for further information.
(`include file: sram.v line 176, `include file: inst_memory.v line 2, file: cpu.v line 3)
module or_gate (x, y, z);
|
xmvlog: *W,RECOME (./or_gate.v,1|13): recompiling design unit worklib.or_gate:v.
First compiled from line 1 of or_gate.v.
(`include file: ./or_gate.v line 1, `include file: alu_control.v line 2, file: cpu.v line 4)
module worklib.or_gate:v
errors: 0, warnings: 1
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: alu_control.v line 3, file: cpu.v line 4)
module worklib.and_gate:v
errors: 0, warnings: 1
module mux (sel, src0, src1, z);
|
xmvlog: *W,RECOME (./mux.v,1|9): recompiling design unit worklib.mux:v.
First compiled from line 1 of mux.v.
(`include file: ./mux.v line 1, `include file: np_selb.v line 2, file: cpu.v line 5)
module worklib.mux:v
errors: 0, warnings: 1
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: np_selb.v line 3, file: cpu.v line 5)
module worklib.and_gate:v
errors: 0, warnings: 1
module nor_gate (x, y, z);
|
xmvlog: *W,RECOME (./nor_gate.v,1|14): recompiling design unit worklib.nor_gate:v.
First compiled from line 1 of nor_gate.v.
(`include file: ./nor_gate.v line 1, `include file: np_selb.v line 5, file: cpu.v line 5)
module worklib.nor_gate:v
errors: 0, warnings: 1
module xor_gate (x, y, z);
|
xmvlog: *W,RECOME (./xor_gate.v,2|14): recompiling design unit worklib.xor_gate:v.
First compiled from line 2 of xor_gate.v.
(`include file: ./xor_gate.v line 2, `include file: np_selb.v line 6, file: cpu.v line 5)
module worklib.xor_gate:v
errors: 0, warnings: 1
module or_gate (x, y, z);
|
xmvlog: *W,RECOME (./or_gate.v,1|13): recompiling design unit worklib.or_gate:v.
First compiled from line 1 of or_gate.v.
(`include file: ./or_gate.v line 1, `include file: np_selb.v line 7, file: cpu.v line 5)
module worklib.or_gate:v
errors: 0, warnings: 1
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: data_path.v line 1, file: cpu.v line 6)
module worklib.and_gate:v
errors: 0, warnings: 1
module and_gate_n (x, y, z);
|
xmvlog: *W,RECOME (./and_gate_n.v,1|16): recompiling design unit worklib.and_gate_n:v.
First compiled from line 1 of and_gate_n.v.
(`include file: ./and_gate_n.v line 1, `include file: data_path.v line 2, file: cpu.v line 6)
module worklib.and_gate_n:v
errors: 0, warnings: 1
module and_gate_32 (x, y, z);
|
xmvlog: *W,RECOME (./and_gate_32.v,1|17): recompiling design unit worklib.and_gate_32:v.
First compiled from line 1 of and_gate_32.v.
(`include file: ./and_gate_32.v line 1, `include file: data_path.v line 3, file: cpu.v line 6)
module worklib.and_gate_32:v
errors: 0, warnings: 1
module mux_32 (sel, src0, src1, z);
|
xmvlog: *W,RECOME (./mux_32.v,1|12): recompiling design unit worklib.mux_32:v.
First compiled from line 1 of mux_32.v.
(`include file: ./mux_32.v line 1, `include file: data_path.v line 4, file: cpu.v line 6)
module worklib.mux_32:v
errors: 0, warnings: 1
module xor_gate (x, y, z);
|
xmvlog: *W,RECOME (./xor_gate.v,2|14): recompiling design unit worklib.xor_gate:v.
First compiled from line 2 of xor_gate.v.
(`include file: ./xor_gate.v line 2, `include file: full_adder_1bit.v line 1, `include file: full_adder_32bit.v line 2, `include file: ALU.v line 2, `include file: data_path.v line 6, file: cpu.v line 6)
module worklib.xor_gate:v
errors: 0, warnings: 1
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: full_adder_1bit.v line 2, `include file: full_adder_32bit.v line 2, `include file: ALU.v line 2, `include file: data_path.v line 6, file: cpu.v line 6)
module worklib.and_gate:v
errors: 0, warnings: 1
module or_gate (x, y, z);
|
xmvlog: *W,RECOME (./or_gate.v,1|13): recompiling design unit worklib.or_gate:v.
First compiled from line 1 of or_gate.v.
(`include file: ./or_gate.v line 1, `include file: full_adder_1bit.v line 3, `include file: full_adder_32bit.v line 2, `include file: ALU.v line 2, `include file: data_path.v line 6, file: cpu.v line 6)
module worklib.or_gate:v
errors: 0, warnings: 1
module xor_gate (x, y, z);
|
xmvlog: *W,RECOME (./xor_gate.v,2|14): recompiling design unit worklib.xor_gate:v.
First compiled from line 2 of xor_gate.v.
(`include file: ./xor_gate.v line 2, `include file: full_adder_32bit.v line 3, `include file: ALU.v line 2, `include file: data_path.v line 6, file: cpu.v line 6)
module worklib.xor_gate:v
errors: 0, warnings: 1
module and_gate_32 (x, y, z);
|
xmvlog: *W,RECOME (./and_gate_32.v,1|17): recompiling design unit worklib.and_gate_32:v.
First compiled from line 1 of and_gate_32.v.
(`include file: ./and_gate_32.v line 1, `include file: ALU.v line 5, `include file: data_path.v line 6, file: cpu.v line 6)
module worklib.and_gate_32:v
errors: 0, warnings: 1
module mux_32 (sel, src0, src1, z);
|
xmvlog: *W,RECOME (./mux_32.v,1|12): recompiling design unit worklib.mux_32:v.
First compiled from line 1 of mux_32.v.
(`include file: ./mux_32.v line 1, `include file: mux8_1_32bit.v line 2, `include file: ALU.v line 9, `include file: data_path.v line 6, file: cpu.v line 6)
module worklib.mux_32:v
errors: 0, warnings: 1
module mux (sel, src0, src1, z);
|
xmvlog: *W,RECOME (./mux.v,1|9): recompiling design unit worklib.mux:v.
First compiled from line 1 of mux.v.
(`include file: ./mux.v line 1, `include file: mux8_1_1bit.v line 3, `include file: ALU.v line 10, `include file: data_path.v line 6, file: cpu.v line 6)
module worklib.mux:v
errors: 0, warnings: 1
1'h2 : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,45|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 45, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'h3 : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,46|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 46, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'h4 : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,47|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 47, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'h5 : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,48|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 48, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'h6 : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,49|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 49, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'h7 : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,50|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 50, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'h8 : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,51|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 51, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'h9 : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,52|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 52, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'ha : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,53|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 53, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hb : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,54|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 54, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hc : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,55|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 55, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hd : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,56|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 56, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'he : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,57|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 57, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hf : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,58|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 58, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hA : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,59|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 59, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hB : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,60|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 60, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hC : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,61|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 61, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hD : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,62|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 62, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hE : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,63|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 63, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
1'hF : hex = 1;
|
xmvlog: *W,INTOVF (syncram.v,64|11): bit overflow during conversion from text [2.5(IEEE)] (1 bits).
(`include file: syncram.v line 64, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
initiate();
|
xmvlog: *W,TMTPAR (syncram.v,172|17): A task enable with no arguments must not include an empty set of parentheses [10.2.2 (IEEE Std 1364-2005)]. The compiler has ignored the parentheses. Use 'xmhelp xmvlog TMTPAR' for further information.
(`include file: syncram.v line 172, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
checkRAM();
|
xmvlog: *W,TMTPAR (syncram.v,177|17): A task enable with no arguments must not include an empty set of parentheses [10.2.2 (IEEE Std 1364-2005)]. The compiler has ignored the parentheses. Use 'xmhelp xmvlog TMTPAR' for further information.
(`include file: syncram.v line 177, `include file: data_memory.v line 1, `include file: data_path.v line 7, file: cpu.v line 6)
module mux_32 (sel, src0, src1, z);
|
xmvlog: *W,RECOME (./mux_32.v,1|12): recompiling design unit worklib.mux_32:v.
First compiled from line 1 of mux_32.v.
(`include file: ./mux_32.v line 1, `include file: ./Registers.v line 2, `include file: data_path.v line 8, file: cpu.v line 6)
module worklib.mux_32:v
errors: 0, warnings: 1
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: ./Registers.v line 3, `include file: data_path.v line 8, file: cpu.v line 6)
module worklib.and_gate:v
errors: 0, warnings: 1
module dff (clk, d, q);
|
xmvlog: *W,RECOME (./dff.v,1|9): recompiling design unit worklib.dff:v.
First compiled from line 1 of dff.v.
(`include file: ./dff.v line 1, `include file: ./Registers.v line 4, `include file: data_path.v line 8, file: cpu.v line 6)
module worklib.dff:v
errors: 0, warnings: 1
module registers (
|
xmvlog: *W,RECOME (./Registers.v,6|15): recompiling design unit worklib.registers:v.
First compiled from line 6 of Registers.v.
(`include file: ./Registers.v line 6, `include file: data_path.v line 8, file: cpu.v line 6)
module worklib.registers:v
errors: 0, warnings: 1
module dff_32 (
|
xmvlog: *W,RECOME (./Registers.v,108|12): recompiling design unit worklib.dff_32:v.
First compiled from line 108 of Registers.v.
(`include file: ./Registers.v line 108, `include file: data_path.v line 8, file: cpu.v line 6)
module worklib.dff_32:v
errors: 0, warnings: 1
module large_mux(
|
xmvlog: *W,RECOME (./Registers.v,139|15): recompiling design unit worklib.large_mux:v.
First compiled from line 139 of Registers.v.
(`include file: ./Registers.v line 139, `include file: data_path.v line 8, file: cpu.v line 6)
module worklib.large_mux:v
errors: 0, warnings: 1
module dec_32(sel, z);
|
xmvlog: *W,RECOME (./Registers.v,444|12): recompiling design unit worklib.dec_32:v.
First compiled from line 444 of Registers.v.
(`include file: ./Registers.v line 444, `include file: data_path.v line 8, file: cpu.v line 6)
module worklib.dec_32:v
errors: 0, warnings: 1
module and_gate (x, y, z);
|
xmvlog: *W,RECOME (./and_gate.v,1|14): recompiling design unit worklib.and_gate:v.
First compiled from line 1 of and_gate.v.
(`include file: ./and_gate.v line 1, `include file: extender.v line 1, `include file: data_path.v line 9, file: cpu.v line 6)
module worklib.and_gate:v
errors: 0, warnings: 1
module worklib.cpu:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Top level design units:
adder_32
nand_gate
sort_corrected_branch_test
.alu_op(alu_op),
|
xmelab: *W,CUVMPW (./cpu.v,23|16): port sizes differ in port connection (3/2).
and_gate_n #(.n(18)) ag1 ({imm16, 2'b0}, 18'h3FFFF, imm18);
|
xmelab: *W,CUVMPW (./shiftextender.v,17|57): port sizes differ in port connection (19/18).
.alu_op(alu_op),
|
xmelab: *W,CUVMPW (./cpu.v,48|16): port sizes differ in port connection (3/2).
.sel(reg_dst),
|
xmelab: *W,CUVMPW (./data_path.v,42|14): port sizes differ in port connection (1/5).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, reg_wr_en[k]}),
|
xmelab: *W,CUVMPW (./Registers.v,79|11): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,218|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,225|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,232|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,239|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,246|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,253|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,260|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,267|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,274|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,281|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,288|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,295|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,302|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,309|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,316|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,323|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,332|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,339|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,346|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,353|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,360|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,367|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,374|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,381|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[2]}),
|
xmelab: *W,CUVMPW (./Registers.v,390|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[2]}),
|
xmelab: *W,CUVMPW (./Registers.v,397|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[2]}),
|
xmelab: *W,CUVMPW (./Registers.v,404|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[2]}),
|
xmelab: *W,CUVMPW (./Registers.v,411|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[3]}),
|
xmelab: *W,CUVMPW (./Registers.v,420|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[3]}),
|
xmelab: *W,CUVMPW (./Registers.v,427|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[4]}),
|
xmelab: *W,CUVMPW (./Registers.v,436|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,218|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,225|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,232|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,239|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,246|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,253|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,260|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,267|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,274|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,281|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,288|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,295|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,302|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,309|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,316|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[0]}),
|
xmelab: *W,CUVMPW (./Registers.v,323|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,332|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,339|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,346|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,353|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,360|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,367|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,374|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[1]}),
|
xmelab: *W,CUVMPW (./Registers.v,381|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[2]}),
|
xmelab: *W,CUVMPW (./Registers.v,390|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[2]}),
|
xmelab: *W,CUVMPW (./Registers.v,397|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[2]}),
|
xmelab: *W,CUVMPW (./Registers.v,404|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[2]}),
|
xmelab: *W,CUVMPW (./Registers.v,411|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[3]}),
|
xmelab: *W,CUVMPW (./Registers.v,420|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[3]}),
|
xmelab: *W,CUVMPW (./Registers.v,427|9): port sizes differ in port connection (32/1).
.sel ({31'b0, sel[4]}),
|
xmelab: *W,CUVMPW (./Registers.v,436|9): port sizes differ in port connection (32/1).
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.mux_32:v <0x7c95ee40>
streams: 2, words: 499
worklib.and_gate_32:v <0x1e2ccf84>
streams: 2, words: 539
worklib.large_mux:v <0x2f82accb>
streams: 5, words: 710
worklib.mux_32:v <0x545a38bc>
streams: 2, words: 565
worklib.mux_32:v <0x580d64f2>
streams: 2, words: 472
worklib.mux_32:v <0x5a2ada39>
streams: 2, words: 554
worklib.large_mux:v <0x6ffd74c9>
streams: 5, words: 710
worklib.mux_32:v <0x70c2b20e>
streams: 2, words: 592
worklib.dec_32:v <0x6009ee12>
streams: 1, words: 7110
worklib.dff:v <0x79079eba>
streams: 2, words: 316
worklib.and_gate_32:v <0x49f403cf>
streams: 2, words: 307
worklib.and_gate_n:v <0x276554bf>
streams: 2, words: 630
worklib.mux:v <0x10b3405c>
streams: 2, words: 440
worklib.nor_gate:v <0x25484a6f>
streams: 0, words: 0
worklib.or_gate:v <0x6559598f>
streams: 0, words: 0
worklib.and_gate:v <0x3e5936cd>
streams: 0, words: 0
worklib.xor_gate:v <0x0610b609>
streams: 0, words: 0
worklib.registers:v <0x2018aab9>
streams: 1, words: 239
Building instance specific data structures.
and_gate ag2 (imm18[17], ext_op, msb);
|
xmelab: *W,CSINFI (./shiftextender.v,18|37): implicit wire has no fanin (sort_corrected_branch_test.cpu1.imem.pc.shift_imm.ext_op).
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 2563 46
Registers: 1177 57
Scalar wires: 2403 -
Expanded wires: 1255 41
Vectored wires: 105 -
Always blocks: 1130 10
Initial blocks: 16 16
Cont. assignments: 30 31
Pseudo assignments: 18 18
Simulation timescale: 1ps
Writing initial simulation snapshot: worklib.adder_32:v
-------------------------------------
Relinquished control to SimVision...
xcelium>
xcelium> source /vol/cadence2018/XCELIUM1809/tools/xcelium/files/xmsimrc
xcelium> database -open waves -into waves.shm -default
Created default SHM database waves
xcelium> probe -create -shm sort_corrected_branch_test.clk sort_corrected_branch_test.cpu1.select.branch sort_corrected_branch_test.cpu1.select.res_msb sort_corrected_branch_test.cpu1.select.sel sort_corrected_branch_test.cpu1.select.zero
Created probe 1
xcelium> run
Now initializing sram
Addr is written: 00400020
Data is written: 20021000
Addr is written: 00400024
Data is written: 00421400
Addr is written: 00400028
Data is written: 20440024
Addr is written: 0040002c
Data is written: 20450028
Addr is written: 00400030
Data is written: 8c470000
Addr is written: 00400034
Data is written: 20430004
Addr is written: 00400038
Data is written: 8c610000
Addr is written: 0040003c
Data is written: 00e1302a
Addr is written: 00400040
Data is written: 1cc00003
Addr is written: 00400044
Data is written: ac410000
Addr is written: 00400048
Data is written: ac670000
Addr is written: 0040004c
Data is written: 00203820
Addr is written: 00400050
Data is written: 20630004
Addr is written: 00400054
Data is written: 1465fff8
Addr is written: 00400058
Data is written: 20420004
Addr is written: 0040005c
Data is written: 1444fff4
Addr is written: 10000000
Data is written: 00000009
Addr is written: 10000004
Data is written: 0000000a
Addr is written: 10000008
Data is written: 00000008
Addr is written: 1000000c
Data is written: 00000007
Addr is written: 10000010
Data is written: 00000005
Addr is written: 10000014
Data is written: 00000006
Addr is written: 10000018
Data is written: 00000004
Addr is written: 1000001c
Data is written: 00000001
Addr is written: 10000020
Data is written: 00000002
Addr is written: 10000024
Data is written: 00000003
Addr is checking: 00400020
Data is checking: 20021000
Addr is checking: 00400024
Data is checking: 00421400
Addr is checking: 00400028
Data is checking: 20440024
Addr is checking: 0040002c
Data is checking: 20450028
Addr is checking: 00400030
Data is checking: 8c470000
Addr is checking: 00400034
Data is checking: 20430004
Addr is checking: 00400038
Data is checking: 8c610000
Addr is checking: 0040003c
Data is checking: 00e1302a
Addr is checking: 00400040
Data is checking: 1cc00003
Addr is checking: 00400044
Data is checking: ac410000
Addr is checking: 00400048
Data is checking: ac670000
Addr is checking: 0040004c
Data is checking: 00203820
Addr is checking: 00400050
Data is checking: 20630004
Addr is checking: 00400054
Data is checking: 1465fff8
Addr is checking: 00400058
Data is checking: 20420004
Addr is checking: 0040005c
Data is checking: 1444fff4
Addr is checking: 10000000
Data is checking: 00000009
Addr is checking: 10000004
Data is checking: 0000000a
Addr is checking: 10000008
Data is checking: 00000008
Addr is checking: 1000000c
Data is checking: 00000007
Addr is checking: 10000010
Data is checking: 00000005
Addr is checking: 10000014
Data is checking: 00000006
Addr is checking: 10000018
Data is checking: 00000004
Addr is checking: 1000001c
Data is checking: 00000001
Addr is checking: 10000020
Data is checking: 00000002
Addr is checking: 10000024
Data is checking: 00000003
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Addr is checking: xxxxxxxx
Data is checking: xxxxxxxx
Writing to dout: x
Now initializing sram
Addr is written: 00400020
Data is written: 20021000
Addr is written: 00400024
Data is written: 00421400
Addr is written: 00400028
Data is written: 20440024
Addr is written: 0040002c
Data is written: 20450028
Addr is written: 00400030
Data is written: 8c470000
Addr is written: 00400034
Data is written: 20430004
Addr is written: 00400038
Data is written: 8c610000
Addr is written: 0040003c
Data is written: 00e1302a
Addr is written: 00400040
Data is written: 1cc00003
Addr is written: 00400044
Data is written: ac410000
Addr is written: 00400048
Data is written: ac670000
Addr is written: 0040004c
Data is written: 00203820
Addr is written: 00400050
Data is written: 20630004
Addr is written: 00400054
Data is written: 1465fff8
Addr is written: 00400058
Data is written: 20420004
Addr is written: 0040005c
Data is written: 1444fff4
Addr is written: 10000000
Data is written: 00000009
Addr is written: 10000004
Data is written: 0000000a
Addr is written: 10000008