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device.cpp
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device.cpp
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#include <cassert>
#include <algorithm>
#include <climits>
#include <boost/property_tree/ptree.hpp>
#include <boost/property_tree/exceptions.hpp>
#include "device.h"
#include "log.h"
Device::Device(const ModelConf& model, ConfTree& conf):
// memory map
flash_size_(model.flash_size),
flash_page_size_(model.flash_page_size),
flash_app_size_(flash_size_ - model.flash_boot_size),
flash_app_table_start_(flash_app_size_ - model.flash_boot_size),
flash_app_table_size_(model.flash_boot_size),
flash_boot_start_(flash_size_ - model.flash_boot_size),
flash_boot_size_(model.flash_boot_size),
mem_eeprom_size_(model.mem_eeprom_size),
mem_sram_size_(model.mem_sram_size),
mem_exsram_start_(mem_sram_start_ + mem_sram_size_),
mem_exsram_size_(model.has_exsram ? MEM_MAX_SIZE - mem_exsram_start_ : 0),
// conf
conf_(conf),
// flash and memory data
flash_data_(flash_size_/2, 0xFFFF),
sram_data_(mem_sram_size_),
// blocks
cpu_(this),
clk_(this),
osc_(this),
pmic_(this),
gpior_(this)
{
// check memory map values
// order and which values are checked are important to detect possible
// overflows and to ensure everything is checked
#define DEVICE_CHECK(cond,msg) \
if(!(cond)) throw DeviceConfigurationError(*this, msg);
DEVICE_CHECK(flash_page_size_ % 2 == 0, "flash page size not aligned on words");
DEVICE_CHECK(flash_size_ % flash_page_size_ == 0, "flash size not aligned on page size");
DEVICE_CHECK(flash_boot_size_ % flash_page_size_ == 0, "flash bootloader size not aligned on page size");
DEVICE_CHECK(flash_boot_size_ < flash_size_, "flash bootloader larger than total flash");
DEVICE_CHECK(flash_boot_size_ < flash_app_size_, "flash bootloader larger than flash application");
DEVICE_CHECK(mem_eeprom_size_ <= 0x1000, "memory mapped EEPROM is too large");
DEVICE_CHECK(mem_sram_size_ < MEM_MAX_SIZE - mem_sram_start_, "internal SRAM is too large");
#undef DEVICE_CHECK
// connect blocks
connectBlock(&cpu_);
connectBlock(&clk_);
connectBlock(&osc_);
connectBlock(&pmic_);
connectBlock(&gpior_);
}
Device::~Device()
{
}
const Device::ConfTree& Device::conf(const std::string& path)
{
try {
return conf_.get_child(path);
} catch(const boost::property_tree::ptree_bad_path&) {
return conf_.put_child(path, ConfTree());
}
}
void Device::reset()
{
// reset state
instruction_cycles_ = 0;
interrupt_wait_instruction_ = true;
clk_sys_tick_ = 0;
clk_sys_queue_.clear();
// reset CLK first for schedule()
clk_.reset();
schedule(ClockType::CPU, std::bind(&Device::stepCPU, this), 1, 100);
// reset blocks
for(auto it: blocks_) {
it.second->reset();
}
// clear memory
// SRAM is not cleared on reset
regfile_.fill(0);
}
void Device::step()
{
assert(!clk_sys_queue_.empty());
clk_sys_tick_ = clk_sys_queue_.front()->tick;
for(;;) {
ClockEvent* ev = clk_sys_queue_.front().get();
if(ev->tick > clk_sys_tick_) {
break;
}
unsigned int next = ev->callback();
if(next) {
ev->tick += next * ev->scale;
std::pop_heap(clk_sys_queue_.begin(), clk_sys_queue_.end(), clock_queue_cmp);
std::push_heap(clk_sys_queue_.begin(), clk_sys_queue_.end(), clock_queue_cmp);
} else {
std::pop_heap(clk_sys_queue_.begin(), clk_sys_queue_.end(), clock_queue_cmp);
clk_sys_queue_.pop_back();
}
}
}
unsigned int Device::stepCPU()
{
//TODO handle halted CPU
// Step order is important to ensure an instruction is executed before any
// pending interruption is served.
breaked_ = false;
// check for pending interruptions
if(instruction_cycles_ == 0 && !interrupt_wait_instruction_ && cpu_.sreg_.I && !ccpState()) {
if(processPendingInterrupts()) {
instruction_cycles_ = 5;
interrupt_wait_instruction_ = true;
}
}
//TODO:check Before clock handling blocks were stepped here
// execute instruction
while(instruction_cycles_ == 0) {
instruction_cycles_ = executeNextInstruction();
interrupt_wait_instruction_ = false;
}
instruction_cycles_--;
return 1;
}
void Device::setIvLvl(ivnum_t iv, IntLvl lvl)
{
switch(lvl) {
case INTLVL_NONE:
if(iv_pending_.lo.erase(iv)) break;
if(iv_pending_.med.erase(iv)) break;
if(iv_pending_.hi.erase(iv)) break;
if(iv_pending_.nmi.erase(iv)) break;
break;
case INTLVL_LO:
if(!iv_pending_.lo.insert(iv).second) break;
if(iv_pending_.med.erase(iv)) break;
if(iv_pending_.hi.erase(iv)) break;
if(iv_pending_.nmi.erase(iv)) break;
break;
case INTLVL_MED:
if(!iv_pending_.med.insert(iv).second) break;
if(iv_pending_.lo.erase(iv)) break;
if(iv_pending_.hi.erase(iv)) break;
if(iv_pending_.nmi.erase(iv)) break;
break;
case INTLVL_HI:
if(!iv_pending_.hi.insert(iv).second) break;
if(iv_pending_.lo.erase(iv)) break;
if(iv_pending_.med.erase(iv)) break;
if(iv_pending_.nmi.erase(iv)) break;
break;
case INTLVL_NMI:
if(!iv_pending_.nmi.insert(iv).second) break;
if(iv_pending_.lo.erase(iv)) break;
if(iv_pending_.med.erase(iv)) break;
if(iv_pending_.hi.erase(iv)) break;
break;
default:
LOGF(ERROR, "invalid INTLVL: %d") % lvl;
}
}
IntLvl Device::currentIntLvl() const
{
uint8_t intlvlex = pmic_.status_.data;
if(intlvlex == 0) {
return INTLVL_NONE; // common case
}
IntLvl levels[] = {INTLVL_NMI, INTLVL_HI, INTLVL_MED, INTLVL_LO};
for(IntLvl lvl: levels) {
if(intlvlex & (1 << (lvl-1))) {
return lvl;
}
}
return INTLVL_NONE; // should not happen
}
void Device::loadFlash(const std::vector<uint8_t>& data)
{
if(data.size() > 2*flash_data_.size()) {
throw DeviceConfigurationError(*this, "flash data to load is too large");
}
if(data.size() % 2 != 0) {
throw DeviceConfigurationError(*this, "flash data not aligned on words");
}
auto itsrc = data.begin();
auto itdst = flash_data_.begin();
while(itsrc != data.end()) {
*itdst++ = *itsrc + (*(itsrc+1) << 8);
itsrc +=2;
}
}
/// Return true for 2-word instructions
static inline bool opcode_is_32b(uint16_t opcode)
{
// 2-word instructions are JMP, CALL, LDS, STS
return (opcode & 0xFE0C) == 0x940C || (opcode & 0xFC0F) == 0x9000;
}
bool Device::processPendingInterrupts()
{
IntLvl intlvl = currentIntLvl();
IntLvl intlvl_new = INTLVL_NONE;
InterruptQueue* iv_queue = nullptr;
if(intlvl >= INTLVL_NMI) {
return false;
} else if(!iv_pending_.nmi.empty()) {
intlvl_new = INTLVL_NMI;
iv_queue = &iv_pending_.nmi;
} else if(intlvl >= INTLVL_HI) {
return false;
} else if(pmic_.ctrl_.hilvlen && !iv_pending_.hi.empty()) {
intlvl_new = INTLVL_HI;
iv_queue = &iv_pending_.hi;
} else if(intlvl >= INTLVL_MED) {
return false;
} else if(pmic_.ctrl_.medlvlen && !iv_pending_.med.empty()) {
intlvl_new = INTLVL_MED;
iv_queue = &iv_pending_.med;
} else if(intlvl >= INTLVL_LO) {
return false;
} else if(pmic_.ctrl_.lolvlen && !iv_pending_.lo.empty()) {
intlvl_new = INTLVL_LO;
iv_queue = &iv_pending_.lo;
} else {
return false;
}
ivnum_t iv_num = *iv_queue->begin();
iv_queue->erase(iv_queue->begin());
// update PMIC status
pmic_.status_.data |= 1 << (intlvl_new - 1);
// get IV address (each IV is 2-word long), don't forget IVSEL
flashptr_t iv_addr = 2*iv_num;
if(pmic_.ctrl_.ivsel) {
iv_addr += flash_boot_start_;
}
// execute the IV
Block* block = getIvBlock(iv_num);
assert(block);
block->executeIv(iv_num-block->iv_base());
if(flash_size_ <= 0x20000) {
stack_set<16>(stack(), cpu_.pc_);
cpu_.sp_ -= 2;
} else {
stack_set<24>(stack(), cpu_.pc_);
cpu_.sp_ -= 3;
}
cpu_.pc_ = iv_addr;
DLOGF(NOTICE, "acknowledge interrupt %u, level %d, PC:%05X") % iv_num % intlvl_new % iv_addr;
return true;
}
unsigned int Device::executeNextInstruction()
{
uint16_t opcode = flash_data_[cpu_.pc_];
//TODO check for cpu_.pc_ oveflow? (check other accesses to flash_data_ below)
//TODO check availability of some opcodes on specific devices
//TODO check use of RAMP[XYZD]
// Instructions which longs longer than 1 cycle are executed immediately but
// will delay the execution of the next one.
unsigned int opcode_cycles = 1;
#define DLOGF_OPCODE(f) DLOGF(INFO, "PC:%05X SP:%04X OP:%04X " f) % cpu_.pc_ % cpu_.sp_ % opcode
// NOPE
if(opcode == 0) {
DLOGF_OPCODE("NOPE");
cpu_.pc_++;
}
// BSET, SE{C,Z,N,V,S,H,T,I}
else if((opcode & 0xFF8F) == 0x9408) {
uint8_t s = (opcode >> 4) & 7;
DLOGF_OPCODE("BSET %d") % (int)s;
cpu_.sreg_.data |= (1 << s);
cpu_.pc_++;
}
// BCLR, CL{C,Z,N,V,S,H,T,I}
else if((opcode & 0xFF8F) == 0x9488) {
uint8_t s = (opcode >> 4) & 7;
DLOGF_OPCODE("BCLR %d") % (int)s;
cpu_.sreg_.data &= ~(1 << s);
cpu_.pc_++;
}
// SBI
else if((opcode & 0xFF00) == 0x9A00) {
uint8_t a = (opcode >> 3) & 0x1F;
uint8_t b = opcode & 7;
DLOGF_OPCODE("SBI 0x%X,%d") % (int)a % (int)b;
//TODO this changes the whole byte, not just one bit
setIoMem(a, getIoMem(a) | (1 <<b));
cpu_.pc_++;
}
// CBI
else if((opcode & 0xFF00) == 0x9800) {
uint8_t a = (opcode >> 3) & 0x1F;
uint8_t b = opcode & 7;
DLOGF_OPCODE("CBI 0x%X,%d") % (int)a % (int)b;
//TODO this changes the whole byte, not just one bit
setIoMem(a, getIoMem(a) & ~(1 <<b));
cpu_.pc_++;
}
// COM
else if((opcode & 0xFE0F) == 0x9400) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = 0xFF - Rd;
DLOGF_OPCODE("COM r%d") % (int)d;
cpu_.sreg_.C = 1;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = 0;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// NEG
else if((opcode & 0xFE0F) == 0x9401) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = (0x100 - Rd) & 0xFF;
DLOGF_OPCODE("NEG r%d") % (int)d;
cpu_.sreg_.C = R != 0;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = R == 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = (R & Rd) & 0x08;
cpu_.pc_++;
}
// SWAP
else if((opcode & 0xFE0F) == 0x9402) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t Rd = regfile_[d];
DLOGF_OPCODE("SWAP r%d") % (int)d;
regfile_[d] = ((Rd & 0x0F) << 4) | ((Rd & 0xF0) >> 4);
cpu_.pc_++;
}
// INC
else if((opcode & 0xFE0F) == 0x9403) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t R = ++regfile_[d];
DLOGF_OPCODE("INC r%d") % (int)d;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = R == 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// ASR
else if((opcode & 0xFE0F) == 0x9405) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = (Rd >> 1) | (Rd & 0x80);
DLOGF_OPCODE("ASR r%d") % (int)d;
cpu_.sreg_.C = Rd & 1;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = cpu_.sreg_.N ^ cpu_.sreg_.C;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// LSR
else if((opcode & 0xFE0F) == 0x9406) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = (Rd >> 1);
DLOGF_OPCODE("LSR r%d") % (int)d;
cpu_.sreg_.C = Rd & 1;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = 0;
cpu_.sreg_.V = cpu_.sreg_.N ^ cpu_.sreg_.C;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// ROR
else if((opcode & 0xFE0F) == 0x9407) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = (Rd >> 1) | (cpu_.sreg_.C << 7);
DLOGF_OPCODE("ROR r%d") % (int)d;
cpu_.sreg_.C = Rd & 1;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = cpu_.sreg_.N ^ cpu_.sreg_.C;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// DEC
else if((opcode & 0xFE0F) == 0x940A) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t R = --regfile_[d];
DLOGF_OPCODE("DEC r%d") % (int)d;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = R == 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// CP
else if((opcode & 0xFC00) == 0x1400) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = Rd - Rr;
DLOGF_OPCODE("CP r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x80;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & ~Rr & ~R) | (~Rd & Rr & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x08;
cpu_.pc_++;
}
// CPC
else if((opcode & 0xFC00) == 0x0400) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = Rd - Rr - cpu_.sreg_.C;
DLOGF_OPCODE("CPC r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x80;
cpu_.sreg_.Z = R == 0 && cpu_.sreg_.Z;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & ~Rr & ~R) | (~Rd & Rr & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x08;
cpu_.pc_++;
}
// ADD, LSL
else if((opcode & 0xFC00) == 0x0C00) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = regfile_[d] = Rd + Rr;
DLOGF_OPCODE("ADD r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = ((Rd & Rr) | (Rr & ~R) | (~R & Rd)) & 0x80;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & Rr & ~R) | (~Rd & ~Rr & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((Rd & Rr) | (Rr & ~R) | (~R & Rd)) & 0x08;
cpu_.pc_++;
}
// ADC, ROL
else if((opcode & 0xFC00) == 0x1C00) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = regfile_[d] = Rd + Rr + cpu_.sreg_.C;
DLOGF_OPCODE("ADC r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = ((Rd & Rr) | (Rr & ~R) | (~R & Rd)) & 0x80;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & Rr & ~R) | (~Rd & ~Rr & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((Rd & Rr) | (Rr & ~R) | (~R & Rd)) & 0x08;
cpu_.pc_++;
}
// SUB
else if((opcode & 0xFC00) == 0x1800) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = regfile_[d] = Rd - Rr;
DLOGF_OPCODE("SUB r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x80;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & ~Rr & ~R) | (~Rd & Rr & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x08;
cpu_.pc_++;
}
// SBC
else if((opcode & 0xFC00) == 0x0800) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = regfile_[d] = Rd - Rr - cpu_.sreg_.C;
DLOGF_OPCODE("SBC r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x80;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & ~Rr & ~R) | (~Rd & Rr & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x08;
cpu_.pc_++;
}
// MUL
else if((opcode & 0xFC00) == 0x9C00) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint16_t R = Rd * Rr;
DLOGF_OPCODE("MUL r%d,r%d") % (int)d % (int)r;
reg01_ = R;
cpu_.sreg_.C = R & 0x8000;
cpu_.sreg_.Z = R == 0;
cpu_.pc_++;
opcode_cycles = 2;
}
// MULS
else if((opcode & 0xFF00) == 0x0200) {
uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
uint8_t r = (opcode & 0xF) | 0x10; // 16 <= r <= 31
int16_t Rd = u8_to_s16(regfile_[d]);
int16_t Rr = u8_to_s16(regfile_[r]);
uint16_t R = Rd * Rr;
DLOGF_OPCODE("MULS r%d,r%d") % (int)d % (int)r;
reg01_ = R;
cpu_.sreg_.C = R & 0x8000;
cpu_.sreg_.Z = R == 0;
cpu_.pc_++;
opcode_cycles = 2;
}
// MULSU
else if((opcode & 0xFF88) == 0x0300) {
uint8_t d = ((opcode >> 4) & 0x7) | 0x10; // 16 <= d <= 23
uint8_t r = (opcode & 0x7) | 0x10; // 16 <= r <= 23
int16_t Rd = u8_to_s16(regfile_[d]);
uint8_t Rr = regfile_[r];
uint16_t R = Rd * Rr;
DLOGF_OPCODE("MULSU r%d,r%d") % (int)d % (int)r;
reg01_ = R;
cpu_.sreg_.C = R & 0x8000;
cpu_.sreg_.Z = R == 0;
cpu_.pc_++;
opcode_cycles = 2;
}
// FMUL
else if((opcode & 0xFF88) == 0x0308) {
uint8_t d = ((opcode >> 4) & 0x7) | 0x10; // 16 <= d <= 23
uint8_t r = (opcode & 0x7) | 0x10; // 16 <= r <= 23
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint16_t R = Rd * Rr;
DLOGF_OPCODE("FMUL r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = R & 0x8000; // before left shift
reg01_ = (R <<= 1);
cpu_.sreg_.Z = R == 0;
cpu_.pc_++;
opcode_cycles = 2;
}
// FMULS
else if((opcode & 0xFF88) == 0x0380) {
uint8_t d = ((opcode >> 4) & 0x7) | 0x10; // 16 <= d <= 23
uint8_t r = (opcode & 0x7) | 0x10; // 16 <= r <= 23
int16_t Rd = u8_to_s16(regfile_[d]);
int16_t Rr = u8_to_s16(regfile_[r]);
uint16_t R = Rd * Rr;
DLOGF_OPCODE("FMULS r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = R & 0x8000; // before left shift
reg01_ = (R <<= 1);
cpu_.sreg_.Z = R == 0;
cpu_.pc_++;
opcode_cycles = 2;
}
// FMULSU
else if((opcode & 0xFF88) == 0x0380) {
uint8_t d = ((opcode >> 4) & 0x7) | 0x10; // 16 <= d <= 23
uint8_t r = (opcode & 0x7) | 0x10; // 16 <= r <= 23
int16_t Rd = u8_to_s16(regfile_[d]);
uint8_t Rr = regfile_[r];
uint16_t R = Rd * Rr;
DLOGF_OPCODE("FMULSU r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.C = R & 0x8000; // before left shift
reg01_ = (R <<= 1);
cpu_.sreg_.Z = R == 0;
cpu_.pc_++;
opcode_cycles = 2;
}
// AND, TST
else if((opcode & 0xFC00) == 0x2000) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = regfile_[d] = Rd & Rr;
DLOGF_OPCODE("AND r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = 0;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// EOR, CLR
else if((opcode & 0xFC00) == 0x2400) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = regfile_[d] = Rd ^ Rr;
DLOGF_OPCODE("EOR r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = 0;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// OR
else if((opcode & 0xFC00) == 0x2800) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
uint8_t Rd = regfile_[d];
uint8_t Rr = regfile_[r];
uint8_t R = regfile_[d] = Rd | Rr;
DLOGF_OPCODE("OR r%d,r%d") % (int)d % (int)r;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = 0;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// MOV
else if((opcode & 0xFC00) == 0x2C00) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
DLOGF_OPCODE("MOV r%d,r%d") % (int)d % (int)r;
regfile_[d] = regfile_[r];
cpu_.pc_++;
}
// CPI
else if((opcode & 0xF000) == 0x3000) {
uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
uint8_t Rd = regfile_[d];
uint8_t R = Rd - K;
DLOGF_OPCODE("CPI r%d,0x%02X") % (int)d % (int)K;
cpu_.sreg_.C = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x80;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & ~K & ~R) | (~Rd & K & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x08;
cpu_.pc_++;
}
// SUBI
else if((opcode & 0xF000) == 0x5000) {
uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = Rd - K;
DLOGF_OPCODE("SUBI r%d,0x%02X") % (int)d % (int)K;
cpu_.sreg_.C = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x80;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & ~K & ~R) | (~Rd & K & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x08;
cpu_.pc_++;
}
// SBCI
else if((opcode & 0xF000) == 0x4000) {
uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = Rd - K - cpu_.sreg_.C;
DLOGF_OPCODE("SBCI r%d,0x%02X") % (int)d % (int)K;
cpu_.sreg_.C = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x80;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = ((Rd & ~K & ~R) | (~Rd & K & R)) & 0x80;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.sreg_.H = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x08;
cpu_.pc_++;
}
// ANDI, CBR
else if((opcode & 0xF000) == 0x7000) {
uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = Rd & K;
DLOGF_OPCODE("ANDI r%d,0x%02X") % (int)d % (int)K;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = 0;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// ORI, SBR
else if((opcode & 0xF000) == 0x6000) {
uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
uint8_t Rd = regfile_[d];
uint8_t R = regfile_[d] = Rd | K;
DLOGF_OPCODE("ORI r%d,0x%02X") % (int)d % (int)K;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x80;
cpu_.sreg_.V = 0;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// MOVW
else if((opcode & 0xFF00) == 0x0100) {
uint8_t d = ((opcode >> 3) & 0x1E);
uint8_t r = (opcode & 0xF) << 1;
DLOGF_OPCODE("MOVW r%d:r%d,r%d:r%d") % (int)d % (int)(d+1) % (int)r % (int)(r+1);
register_set<16>(®file_[d], register_get<16>(®file_[r]));
cpu_.pc_++;
}
// ADIW
else if((opcode & 0xFF00) == 0x9600) {
uint8_t d = ((opcode >> 3) & 0x6) + 24;
uint8_t K = (opcode & 0xF) | ((opcode >> 2) & 0x30);
uint16_t Rd = register_get<16>(®file_[d]);
uint16_t R = Rd + K;
DLOGF_OPCODE("ADIW r%d:r%d,0x%02X") % (int)d % (int)(d+1) % (int)K;
register_set<16>(®file_[d], R);
cpu_.sreg_.C = (~R & Rd) & 0x8000;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x8000;
cpu_.sreg_.V = (R & ~Rd) & 0x8000;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// SBIW
else if((opcode & 0xFF00) == 0x9700) {
uint8_t d = ((opcode >> 3) & 0x6) + 24;
uint8_t K = (opcode & 0xF) | ((opcode >> 2) & 0x30);
uint16_t Rd = register_get<16>(®file_[d]);
uint16_t R = Rd - K;
DLOGF_OPCODE("SBIW r%d,0x%02X") % (int)d % (int)K;
register_set<16>(®file_[d], R);
cpu_.sreg_.C = (R & ~Rd) & 0x8000;
cpu_.sreg_.Z = R == 0;
cpu_.sreg_.N = R & 0x8000;
cpu_.sreg_.V = (R & ~Rd) & 0x8000;
cpu_.sreg_.S = cpu_.sreg_.N ^ cpu_.sreg_.V;
cpu_.pc_++;
}
// BLD
else if((opcode & 0xFE08) == 0xF800) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t b = opcode & 7;
DLOGF_OPCODE("BLD r%d,%d") % (int)d % (int)b;
regfile_[d] = (regfile_[d] & ~(1 << b)) | (cpu_.sreg_.T << b);
cpu_.pc_++;
}
// BST
else if((opcode & 0xFE08) == 0xFA00) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t b = opcode & 7;
DLOGF_OPCODE("BST r%d,%d") % (int)d % (int)b;
cpu_.sreg_.T = regfile_[d] & (1 << b);
cpu_.pc_++;
}
// LDI, SER
else if((opcode & 0xF000) == 0xE000) {
uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
DLOGF_OPCODE("LDI r%d,0x%02X") % (int)d % (int)K;
regfile_[d] = K;
cpu_.pc_++;
}
// LDS (16-bit)
else if((opcode & 0xFE0F) == 0x9000) {
uint8_t d = (opcode >> 4) & 0x1F;
uint16_t k = flash_data_[cpu_.pc_+1];
DLOGF_OPCODE("LDS r%d,0x%04X") % (int)d % k;
memptr_t addr = k | (cpu_.rampd_ << 16);
regfile_[d] = getDataMem(addr);
cpu_.pc_ += 2;
opcode_cycles = 2;
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (X i)
else if((opcode & 0xFE0F) == 0x900C) {
uint8_t d = (opcode >> 4) & 0x1F;
memptr_t addr = regx_ | (cpu_.rampx_ << 16);
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LD r%d,X @%05X = %02X") % (int)d % addr % (int)regfile_[d];
cpu_.pc_++;
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (X ii)
else if((opcode & 0xFE0F) == 0x900D) {
uint8_t d = (opcode >> 4) & 0x1F;
if(d == 26 || d == 27) {
LOGF(ERROR, "undefined opcode behavior: LD r%d,X+") % (int)d;
}
memptr_t addr = regx_ | (cpu_.rampx_ << 16);
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LD r%d,X+ @%05X = %02X") % (int)d % addr % (int)regfile_[d];
++regx_;
if(regx_ == 0) { // X overflow, update RAMPX
cpu_.rampx_++;
cpu_.rampx_ &= cpu_.ramp_mask_;
}
cpu_.pc_++;
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (X iii)
else if((opcode & 0xFE0F) == 0x900E) {
uint8_t d = (opcode >> 4) & 0x1F;
if(d == 26 || d == 27) {
LOGF(ERROR, "undefined opcode behavior: LD r%d,-X") % (int)d;
}
--regx_;
if(regx_ == 0xFFFF) { // X underflow, update RAMPX
cpu_.rampx_--;
cpu_.rampx_ &= cpu_.ramp_mask_;
}
memptr_t addr = regx_ | (cpu_.rampx_ << 16);
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LD r%d,-X @%05X = %02X") % (int)d % addr % (int)regfile_[d];
cpu_.pc_++;
opcode_cycles = 2;
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (Y i), LDD (Y iv)
else if((opcode & 0xD208) == 0x8008) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t q = (opcode & 0x7) | ((opcode >> 7) & 0x18) | ((opcode >> 8) & 0x20);
memptr_t addr = (regy_ | (cpu_.rampy_ << 16)) + q;
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LDD r%d,Y+%d @%05X = %02X") % (int)d % (int)q % addr % (int)regfile_[d];
cpu_.pc_++;
if(q != 0) {
opcode_cycles = 2;
}
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (Y ii)
else if((opcode & 0xFE0F) == 0x9009) {
uint8_t d = (opcode >> 4) & 0x1F;
if(d == 28 || d == 29) {
LOGF(ERROR, "undefined opcode behavior: LD r%d,Y+") % (int)d;
}
memptr_t addr = regy_ | (cpu_.rampy_ << 16);
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LD r%d,Y+ @%05X = %02X") % (int)d % addr % (int)regfile_[d];
++regy_;
if(regy_ == 0) { // Y overflow, update RAMPY
cpu_.rampy_++;
cpu_.rampy_ &= cpu_.ramp_mask_;
}
cpu_.pc_++;
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (Y iii)
else if((opcode & 0xFE0F) == 0x900A) {
uint8_t d = (opcode >> 4) & 0x1F;
if(d == 28 || d == 29) {
LOGF(ERROR, "undefined opcode behavior: LD r%d,-Y") % (int)d;
}
--regy_;
if(regy_ == 0xFFFF) { // Y underflow, update RAMPY
cpu_.rampy_--;
cpu_.rampy_ &= cpu_.ramp_mask_;
}
memptr_t addr = regy_ | (cpu_.rampy_ << 16);
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LD r%d,-Y @%05X = %02X") % (int)d % addr % (int)regfile_[d];
cpu_.pc_++;
opcode_cycles = 2;
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (Z i), LDD (Z iv)
else if((opcode & 0xD208) == 0x8000) {
uint8_t d = (opcode >> 4) & 0x1F;
uint8_t q = (opcode & 0x7) | ((opcode >> 7) & 0x18) | ((opcode >> 8) & 0x20);
memptr_t addr = (regz_ | (cpu_.rampz_ << 16)) + q;
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LDD r%d,Z+%d @%05X = %02X") % (int)d % (int)q % addr % (int)regfile_[d];
cpu_.pc_++;
if(q != 0) {
opcode_cycles = 2;
}
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (Z ii)
else if((opcode & 0xFE0F) == 0x9001) {
uint8_t d = (opcode >> 4) & 0x1F;
if(d == 30 || d == 31) {
LOGF(ERROR, "undefined opcode behavior: LD r%d,Z+") % (int)d;
}
memptr_t addr = regz_ | (cpu_.rampz_ << 16);
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LD r%d,Z+ @%05X = %02X") % (int)d % addr % (int)regfile_[d];
++regz_;
if(regz_ == 0) { // Z overflow, update RAMPZ
cpu_.rampz_++;
cpu_.rampz_ &= cpu_.ramp_mask_;
}
cpu_.pc_++;
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// LD (Z iii)
else if((opcode & 0xFE0F) == 0x9002) {
uint8_t d = (opcode >> 4) & 0x1F;
if(d == 30 || d == 31) {
LOGF(ERROR, "undefined opcode behavior: LD r%d,-Z") % (int)d;
}
--regz_;
if(regz_ == 0xFFFF) { // Z underflow, update RAMPZ
cpu_.rampz_--;
cpu_.rampz_ &= cpu_.ramp_mask_;
}
memptr_t addr = regz_ | (cpu_.rampz_ << 16);
regfile_[d] = getDataMem(addr);
DLOGF_OPCODE("LD r%d,-Z @%05X = %02X") % (int)d % addr % (int)regfile_[d];
cpu_.pc_++;
opcode_cycles = 2;
if(addr >= mem_sram_start_) {
opcode_cycles++; // assume the same for internal and external SRAM
}
}
// STS (16-bit)
else if((opcode & 0xFE0F) == 0x9200) {
uint8_t d = (opcode >> 4) & 0x1F;
uint16_t k = flash_data_[cpu_.pc_+1];
setDataMem(k | (cpu_.rampd_ << 16), regfile_[d]);
DLOGF_OPCODE("STS 0x%04X,r%d") % k % (int)d;
cpu_.pc_ += 2;
opcode_cycles = 2;
}
// ST (X i)
else if((opcode & 0xFE0F) == 0x920C) {
uint8_t d = (opcode >> 4) & 0x1F;
memptr_t addr = regx_ | (cpu_.rampx_ << 16);
setDataMem(addr, regfile_[d]);
DLOGF_OPCODE("ST X,r%d @%05X = %02X") % (int)d % addr % (int)regfile_[d];
cpu_.pc_++;
}
// ST (X ii)
else if((opcode & 0xFE0F) == 0x920D) {
uint8_t d = (opcode >> 4) & 0x1F;
if(d == 26 || d == 27) {
LOGF(ERROR, "undefined opcode behavior: ST X+,r%d") % (int)d;
}
memptr_t addr = regx_ | (cpu_.rampx_ << 16);
setDataMem(addr, regfile_[d]);
DLOGF_OPCODE("ST X+,r%d @%05X = %02X") % (int)d % addr % (int)regfile_[d];