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uart.vhd.bak
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-- uart.vhd: UART controller - receiving part
-- Author(s): xsnope04
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------
entity UART_RX is
port(
CLK: in std_logic;
RST: in std_logic;
DIN: in std_logic;
DOUT: out std_logic_vector(7 downto 0);
DOUT_VLD: out std_logic := '0'
);
end UART_RX;
-------------------------------------------------
architecture behavioral of UART_RX is
signal cnt : std_logic_vector(4 downto 0);
signal cnt2 : std_logic_vector(3 downto 0);
signal cn_en : std_logic;
signal data : std_logic;
signal dout_v : std_logic;
begin
FSM : entity work.UART_FSM(behavioral)
port map(
CLK => CLK,
RST => RST,
DIN => DIN,
COUNTER => cnt,
COUNTER2 =>cnt2,
DATA => data,
CN_EN => cn_en,
VALID => dout_v
);
DOUT_VLD <= dout_v;
process (CLK) begin
if rising_edge (CLK) then
if RST = '1' then
cnt <= "00000";
cnt2 <= "0000";
else
if cn_en = '1' then
cnt <= cnt+1;
elsif cnt2(3) = '1' then
cnt <= "00000";
cnt2 <= "0000";
end if;
if data = '1' and cnt(4) = '1' then
cnt <= "00000";
if cnt2 = "0000" then
DOUT(0) <= DIN;
elsif cnt2 = "0001" then
DOUT(1) <= DIN;
elsif cnt2 = "0010" then
DOUT(2) <= DIN;
elsif cnt2 = "0011" then
DOUT(3) <= DIN;
elsif cnt2 = "0100" then
DOUT(4) <= DIN;
elsif cnt2 = "0101" then
DOUT(5) <= DIN;
elsif cnt2 = "0110" then
DOUT(6) <= DIN;
elsif cnt2 = "0111" then
DOUT(7) <= DIN;
end if;
cnt2 <= cnt2 +1;
elsif data = '0' then
cnt2 <= "0000";
end if;
end if;
end if;
end process;
end behavioral;