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YoDawg.par
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Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
JONATHANSPC:: Mon May 23 20:08:48 2016
par -w -intstyle ise -ol high -mt off YoDawg_map.ncd YoDawg.ncd YoDawg.pcf
Constraints file: YoDawg.pcf.
Loading device for application Rf_Device from file '7a100t.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"YoDawg" is an NCD, version 3.2, device xc7a100t, package csg324, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
Device speed data version: "PRODUCTION 1.10 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 399 out of 126,800 1%
Number used as Flip Flops: 384
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 15
Number of Slice LUTs: 1,187 out of 63,400 1%
Number used as logic: 1,177 out of 63,400 1%
Number using O6 output only: 887
Number using O5 output only: 151
Number using O5 and O6: 139
Number used as ROM: 0
Number used as Memory: 0 out of 19,000 0%
Number used exclusively as route-thrus: 10
Number with same-slice register load: 0
Number with same-slice carry load: 10
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 521 out of 15,850 3%
Number of LUT Flip Flop pairs used: 1,218
Number with an unused Flip Flop: 821 out of 1,218 67%
Number with an unused LUT: 31 out of 1,218 2%
Number of fully used LUT-FF pairs: 366 out of 1,218 30%
Number of slice register sites lost
to control set restrictions: 0 out of 126,800 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 23 out of 210 10%
Number of LOCed IOBs: 23 out of 23 100%
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 103 out of 135 76%
Number using RAMB36E1 only: 103
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 1 out of 270 1%
Number using RAMB18E1 only: 1
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
Number used as BUFGs: 1
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 300 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 300 0%
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 300 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 24 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 24 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 96 0%
Number of BUFRs: 0 out of 24 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 3 out of 240 1%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of IBUFDS_GTE2s: 0 out of 4 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 6 0%
Number of IN_FIFOs: 0 out of 24 0%
Number of MMCME2_ADVs: 0 out of 6 0%
Number of OUT_FIFOs: 0 out of 24 0%
Number of PCIE_2_1s: 0 out of 1 0%
Number of PHASER_REFs: 0 out of 6 0%
Number of PHY_CONTROLs: 0 out of 6 0%
Number of PLLE2_ADVs: 0 out of 6 0%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 1 mins 3 secs
Finished initial Timing Analysis. REAL time: 1 mins 3 secs
Starting Router
Phase 1 : 25812 unrouted; REAL time: 1 mins 9 secs
Phase 2 : 12697 unrouted; REAL time: 1 mins 11 secs
Phase 3 : 2264 unrouted; REAL time: 1 mins 38 secs
Phase 4 : 2279 unrouted; (Setup:27759, Hold:2041, Component Switching Limit:0) REAL time: 1 mins 59 secs
Updating file: YoDawg.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:43548, Hold:1937, Component Switching Limit:0) REAL time: 2 mins 22 secs
Phase 6 : 0 unrouted; (Setup:43548, Hold:1937, Component Switching Limit:0) REAL time: 2 mins 25 secs
Phase 7 : 0 unrouted; (Setup:43548, Hold:1937, Component Switching Limit:0) REAL time: 2 mins 25 secs
Phase 8 : 0 unrouted; (Setup:43548, Hold:1937, Component Switching Limit:0) REAL time: 2 mins 25 secs
Phase 9 : 0 unrouted; (Setup:34816, Hold:0, Component Switching Limit:0) REAL time: 2 mins 29 secs
Total REAL time to Router completion: 2 mins 29 secs
Total CPU time to Router completion: 2 mins 32 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Clk_100M_BUFGP |BUFGCTRL_X0Y31| No | 566 | 0.233 | 1.445 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 34816 (Setup: 34816, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* NET "Clk_100M_BUFGP/IBUFG" PERIOD = 10 ns | SETUP | -0.436ns| 10.436ns| 148| 34816
HIGH 5 ns | HOLD | 0.045ns| | 0| 0
----------------------------------------------------------------------------------------------------------
1 constraint not met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 2 mins 34 secs
Total CPU time to PAR completion: 2 mins 37 secs
Peak Memory Usage: 765 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 148 errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 0
Writing design to file YoDawg.ncd
PAR done!