diff --git a/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf b/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf index 6c1b7543e212..21b98e3b93ad 100644 --- a/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf +++ b/applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf @@ -44,3 +44,5 @@ CONFIG_SYS_CLOCK_EXISTS=n CONFIG_OUTPUT_DISASSEMBLY=y CONFIG_COMMON_LIBC_MALLOC=n + +CONFIG_COMPILER_OPT="-fshort-enums" diff --git a/applications/sdp/mspi/src/hrt/hrt.h b/applications/sdp/mspi/src/hrt/hrt.h index 94b88a515796..6f3fa0d0935b 100644 --- a/applications/sdp/mspi/src/hrt/hrt.h +++ b/applications/sdp/mspi/src/hrt/hrt.h @@ -10,67 +10,41 @@ #include #include #include +#include -/* Max word size. */ -#define MAX_WORD_SIZE NRF_VPR_CSR_VIO_SHIFT_CNT_OUT_BUFFERED_MAX +#define BIT_SET_VALUE(var, pos, value) ((var & (~(1 << pos))) | (value << pos)) -/* Macro for getting direction mask for specified pin and direction. */ -#define PIN_DIR_MASK(PIN_NUM, DIR) \ - (VPRCSR_NORDIC_DIR_PIN##PIN_NUM##_##DIR << VPRCSR_NORDIC_DIR_PIN##PIN_NUM##_Pos) +#define VPRCSR_NORDIC_OUT_HIGH 1 +#define VPRCSR_NORDIC_OUT_LOW 0 -/* Macro for getting output mask for specified pin. */ -#define PIN_DIR_OUT_MASK(PIN_NUM) PIN_DIR_MASK(PIN_NUM, OUTPUT) +#define VPRCSR_NORDIC_DIR_OUTPUT 1 +#define VPRCSR_NORDIC_DIR_INPUT 0 -/* Macro for getting input mask for specified pin. */ -#define PIN_DIR_IN_MASK(PIN_NUM) PIN_DIR_MASK(PIN_NUM, INPUT) - -/* Macro for getting state mask for specified pin and state. */ -#define PIN_OUT_MASK(PIN_NUM, STATE) \ - (VPRCSR_NORDIC_OUT_PIN##PIN_NUM##_##STATE << VPRCSR_NORDIC_OUT_PIN##PIN_NUM##_Pos) - -/* Macro for getting high state mask for specified pin. */ -#define PIN_OUT_HIGH_MASK(PIN_NUM) PIN_OUT_MASK(PIN_NUM, HIGH) - -/* Macro for getting low state mask for specified pin. */ -#define PIN_OUT_LOW_MASK(PIN_NUM) PIN_OUT_MASK(PIN_NUM, LOW) +#define BITS_IN_WORD 32 +#define BITS_IN_BYTE 8 /** @brief Low level transfer parameters. */ -struct hrt_ll_xfer { - /** @brief Top value of VTIM. This will determine clock frequency - * (SPI_CLOCK ~= CPU_CLOCK / (2 * TOP)). - */ - volatile uint8_t counter_top; - - /** @brief Word size of passed data, bits. */ - volatile uint8_t word_size; +struct hrt_xfer { - /** @brief Data to send, under each index there is data of length word_size. */ - volatile uint32_t *data_to_send; + /** @brief When true clock signal makes 1 transition less. + * It is required for spi modes 1 and 3 due to hardware issue. + */ + bool eliminate_last_pulse; - /** @brief Data length. */ - volatile uint8_t data_len; + /** @brief Tx mode mask for csr dir register */ + uint16_t tx_direction_mask; - /** @brief If true chip enable pin will be left active after transfer */ - volatile uint8_t ce_hold; + /** @brief Rx mode mask for csr dir register */ + uint16_t rx_direction_mask; - /** @brief Chip enable pin polarity in enabled state. */ - volatile bool ce_enable_state; }; -/** @brief Write on single line. - * - * Function to be used to write data on single data line (SPI). - * - * @param[in] xfer_ll_params Low level transfer parameters. - */ -void write_single_by_word(volatile struct hrt_ll_xfer xfer_ll_params); - -/** @brief Write on four lines. +/** @brief Write. * - * Function to be used to write data on quad data line (SPI). + * Function to be used to write data on SPI. * * @param[in] xfer_ll_params Low level transfer parameters. */ -void write_quad_by_word(volatile struct hrt_ll_xfer xfer_ll_params); +void hrt_write(struct hrt_xfer *xfer_ll_params); #endif /* _HRT_H__ */ diff --git a/applications/sdp/mspi/src/hrt/hrt.s b/applications/sdp/mspi/src/hrt/hrt.s index 5e9923fce21c..c6358998304f 100644 --- a/applications/sdp/mspi/src/hrt/hrt.s +++ b/applications/sdp/mspi/src/hrt/hrt.s @@ -4,285 +4,236 @@ .attribute unaligned_access, 0 .attribute stack_align, 4 .text - .section .text.write_single_by_word,"ax",@progbits + .section .text.hrt_tx,"ax",@progbits .align 1 - .globl write_single_by_word - .type write_single_by_word, @function -write_single_by_word: - #APP - csrr a5, 3009 - #NO_APP - ori a5,a5,2 - slli a5,a5,16 - srli a5,a5,16 - #APP - csrw 3009, a5 - csrr a5, 3008 - #NO_APP - slli a5,a5,16 - srli a5,a5,16 - #APP - csrw 3008, a5 - #NO_APP - li a5,65536 - addi a5,a5,4 - #APP - csrw 3043, a5 - csrw 3045, 0 - csrr a5, 1996 - #NO_APP - andi a5,a5,17 - #APP - csrw 1996, a5 - #NO_APP - lbu a4,1(a0) - li a5,31 - bleu a4,a5,.L8 -.L5: - #APP - csrw 2000, 2 - #NO_APP - lbu a5,0(a0) - andi a5,a5,0xff - #APP - csrr a4, 2003 - #NO_APP - li a3,-65536 - and a4,a4,a3 - or a5,a5,a4 - #APP - csrw 2003, a5 - #NO_APP - lbu a5,1(a0) - #APP - csrw 3022, a5 - #NO_APP - lbu a5,1(a0) + .type hrt_tx, @function +hrt_tx: + addi sp,sp,-24 + sw ra,20(sp) + sw s0,16(sp) + sw s1,12(sp) + lw a5,4(a0) + sw a2,0(sp) + sw a3,4(sp) + beq a5,zero,.L1 + li a5,32 + div a5,a5,a1 + andi a1,a1,31 + slli a1,a1,12 + mv s0,a0 addi a5,a5,-1 - andi a5,a5,0xff - #APP - csrw 3023, a5 - csrr a5, 3008 - #NO_APP - lbu a4,10(a0) - andi a5,a5,-33 - slli a5,a5,16 - slli a4,a4,5 - srli a5,a5,16 - or a5,a5,a4 + andi a5,a5,63 + ori a5,a5,1024 + or a1,a5,a1 + sw a1,8(sp) #APP - csrw 3008, a5 + csrw 3019, a1 #NO_APP - lbu a5,0(a0) - li a4,3 - mul a5,a5,a4 - #APP - csrw 2005, a5 - #NO_APP - li a5,0 + li s1,0 .L3: - lbu a4,8(a0) - bgtu a4,a5,.L6 - #APP - csrw 3012, 0 - #NO_APP - li a5,65536 - #APP - csrw 3043, a5 - csrw 3045, 0 - #NO_APP - lbu a5,9(a0) - bne a5,zero,.L7 - #APP - csrr a5, 3008 - #NO_APP - lbu a4,10(a0) - andi a5,a5,-34 - slli a5,a5,16 - xori a4,a4,1 - slli a4,a4,5 - srli a5,a5,16 - or a5,a5,a4 - #APP - csrw 3008, a5 - #NO_APP + lw a5,4(s0) + bgtu a5,s1,.L9 +.L1: + lw ra,20(sp) + lw s0,16(sp) + lw s1,12(sp) + addi sp,sp,24 + jr ra +.L9: + sub a5,a5,s1 + li a2,1 + beq a5,a2,.L4 + li a2,2 + beq a5,a2,.L5 +.L6: + lw a5,0(s0) + slli a2,s1,2 + add a5,a5,a2 + lw a0,0(a5) + lw a2,16(s0) + jalr a2 + j .L7 +.L4: + lbu a2,8(s0) + lw a5,8(sp) + addi a2,a2,-1 + andi a2,a2,63 + andi a5,a5,-64 + or a5,a5,a2 + sw a5,8(sp) + #APP + csrw 3019, a5 + #NO_APP + lw a5,16(s0) + lw a0,12(s0) + jalr a5 .L7: + bne s1,zero,.L8 + lw a5,0(sp) + lbu a5,0(a5) + bne a5,zero,.L8 + lw a5,4(sp) #APP - csrw 2000, 0 + csrw 2005, a5 #NO_APP - ret -.L4: - lw a4,4(a0) - slli t1,a5,2 - addi a5,a5,1 - add a4,a4,t1 - lw a3,0(a4) - lbu a2,1(a0) - lw a4,4(a0) - andi a5,a5,0xff - sub a2,a1,a2 - add a4,a4,t1 - sll a3,a3,a2 - sw a3,0(a4) -.L2: - lbu a4,8(a0) - bgtu a4,a5,.L4 - j .L5 + lw a4,0(sp) + li a5,1 + sb a5,0(a4) .L8: - li a5,0 - li a1,32 - j .L2 -.L6: - lw a4,4(a0) - slli a3,a5,2 - add a4,a4,a3 - lw a4,0(a4) - #APP - csrw 3016, a4 - #NO_APP - addi a5,a5,1 - andi a5,a5,0xff + addi s1,s1,1 j .L3 - .size write_single_by_word, .-write_single_by_word - .section .text.write_quad_by_word,"ax",@progbits +.L5: + lbu a2,9(s0) + lw a5,8(sp) + addi a2,a2,-1 + andi a2,a2,63 + andi a5,a5,-64 + or a5,a5,a2 + sw a5,8(sp) + #APP + csrw 3019, a5 + #NO_APP + j .L6 + .size hrt_tx, .-hrt_tx + .section .text.hrt_write,"ax",@progbits .align 1 - .globl write_quad_by_word - .type write_quad_by_word, @function -write_quad_by_word: - #APP - csrr a5, 3009 - #NO_APP - ori a5,a5,30 - slli a5,a5,16 - srli a5,a5,16 + .globl hrt_write + .type hrt_write, @function +hrt_write: + addi sp,sp,-20 + li a5,16384 + sw s0,12(sp) + sw ra,16(sp) + addi a5,a5,1 + sw a5,4(sp) + mv s0,a0 + lhu a5,70(a0) + sb zero,3(sp) #APP csrw 3009, a5 - csrr a5, 3008 - #NO_APP - slli a5,a5,16 - srli a5,a5,16 - #APP - csrw 3008, a5 #NO_APP - li a5,262144 - addi a5,a5,4 - #APP - csrw 3043, a5 - csrw 3045, 0 - csrr a5, 1996 - #NO_APP - andi a5,a5,17 - #APP - csrw 1996, a5 - #NO_APP - lbu a4,1(a0) - li a5,31 - bleu a4,a5,.L16 -.L13: + lw a5,4(a0) + beq a5,zero,.L15 + lbu a3,60(a0) #APP csrw 2000, 2 #NO_APP - lbu a5,0(a0) - andi a5,a5,0xff + lhu a5,64(a0) #APP csrr a4, 2003 #NO_APP - li a3,-65536 - and a4,a4,a3 + li a2,-65536 + and a4,a4,a2 or a5,a5,a4 #APP csrw 2003, a5 + csrw 3011, 0 #NO_APP - lbu a5,1(a0) - srli a5,a5,2 + li a4,2031616 + slli a5,a3,16 + and a5,a5,a4 + ori a5,a5,4 + #APP + csrw 3043, a5 + #NO_APP + lw a5,4(a0) + li a4,1 + beq a5,a4,.L16 + li a4,2 + beq a5,a4,.L17 + li a5,32 + div a5,a5,a3 + j .L35 +.L16: + lbu a5,8(a0) +.L35: #APP csrw 3022, a5 #NO_APP - lbu a5,1(a0) - srli a5,a5,2 - addi a5,a5,-1 - andi a5,a5,0xff +.L15: #APP - csrw 3023, a5 - csrr a5, 3008 + csrr a4, 3008 #NO_APP - lbu a4,10(a0) - andi a5,a5,-33 + lbu a5,68(s0) + lbu a3,66(s0) + bne a5,zero,.L19 + li a5,1 + sll a5,a5,a3 + not a5,a5 + and a5,a5,a4 +.L36: slli a5,a5,16 - slli a4,a4,5 srli a5,a5,16 - or a5,a5,a4 #APP csrw 3008, a5 #NO_APP - lbu a5,0(a0) - li a4,3 - mul a5,a5,a4 - #APP - csrw 2005, a5 + lhu a3,64(s0) + lbu a1,60(s0) + addi a2,sp,3 + mv a0,s0 + call hrt_tx + lhu a3,64(s0) + lbu a1,61(s0) + addi a2,sp,3 + addi a0,s0,20 + call hrt_tx + lhu a3,64(s0) + lbu a1,62(s0) + addi a2,sp,3 + addi a0,s0,40 + call hrt_tx + lbu a5,69(s0) + beq a5,zero,.L21 +.L22: + #APP + csrr a5, 3022 #NO_APP - li a5,0 -.L11: - lbu a4,8(a0) - bgtu a4,a5,.L14 + andi a5,a5,0xff + bne a5,zero,.L22 #APP - csrw 3012, 0 + csrw 2010, 0 #NO_APP - li a5,262144 +.L21: + lw a5,4(sp) #APP - csrw 3043, a5 - csrw 3045, 0 + csrw 3019, a5 + csrw 3017, 0 + csrw 2000, 0 #NO_APP - lbu a5,9(a0) - bne a5,zero,.L15 + lbu a5,67(s0) + bne a5,zero,.L14 #APP - csrr a5, 3008 + csrr a4, 3008 #NO_APP - lbu a4,10(a0) - andi a5,a5,-34 + lbu a5,68(s0) + lbu a3,66(s0) + bne a5,zero,.L24 + li a5,1 + sll a5,a5,a3 + or a5,a5,a4 +.L37: slli a5,a5,16 - xori a4,a4,1 - slli a4,a4,5 srli a5,a5,16 - or a5,a5,a4 #APP csrw 3008, a5 #NO_APP -.L15: - #APP - csrw 2000, 0 - #NO_APP - ret -.L12: - lw a4,4(a0) - slli t1,a5,2 - addi a5,a5,1 - add a4,a4,t1 - lw a3,0(a4) - lbu a2,1(a0) - lw a4,4(a0) - andi a5,a5,0xff - sub a2,a1,a2 - add a4,a4,t1 - sll a3,a3,a2 - sw a3,0(a4) -.L10: - lbu a4,8(a0) - bgtu a4,a5,.L12 - j .L13 -.L16: - li a5,0 - li a1,32 - j .L10 .L14: - lw a4,4(a0) - slli a3,a5,2 - add a4,a4,a3 - lw a4,0(a4) - #APP - csrw 3016, a4 - #NO_APP - addi a5,a5,1 - andi a5,a5,0xff - j .L11 - .size write_quad_by_word, .-write_quad_by_word + lw ra,16(sp) + lw s0,12(sp) + addi sp,sp,20 + jr ra +.L17: + lbu a5,9(a0) + j .L35 +.L19: + li a5,1 + sll a5,a5,a3 + or a5,a5,a4 + j .L36 +.L24: + li a5,1 + sll a5,a5,a3 + not a5,a5 + and a5,a5,a4 + j .L37 + .size hrt_write, .-hrt_write diff --git a/applications/sdp/mspi/src/main.c b/applications/sdp/mspi/src/main.c index 2aa528dae0ab..d5cd085c999f 100644 --- a/applications/sdp/mspi/src/main.c +++ b/applications/sdp/mspi/src/main.c @@ -12,135 +12,191 @@ #include #include +#include #include -#include - -#define MAX_DATA_LEN 256 +#include -#define XFER_COMMAND_IDX (0) -#define XFER_ADDRESS_IDX (1) -#define XFER_DATA_IDX (2) +#include -#define HRT_IRQ_PRIORITY 2 -#define HRT_VEVIF_IDX_WRITE_SINGLE 17 -#define HRT_VEVIF_IDX_WRITE_QUAD 18 +#define CE_PINS_MAX 9 +#define DATA_PINS_MAX 8 -/* How many words are needed for given amount of bytes.*/ -#define WORDS_FOR_BYTES(bytes) ((bytes - 1) / 4 + 1) +#define HRT_IRQ_PRIORITY 2 +#define HRT_VEVIF_IDX_WRITE 18 #define VEVIF_IRQN(vevif) VEVIF_IRQN_1(vevif) #define VEVIF_IRQN_1(vevif) VPRCLIC_##vevif##_IRQn -typedef struct __packed { - uint8_t opcode; - struct mspi_cfg cfg; -} nrfe_mspi_cfg_t; - -typedef struct __packed { - uint8_t opcode; - struct mspi_dev_cfg cfg; -} nrfe_mspi_dev_cfg_t; - -typedef struct __packed { - uint8_t opcode; - struct mspi_xfer xfer; -} nrfe_mspi_xfer_t; - -typedef struct __packed { - uint8_t opcode; - struct mspi_xfer_packet packet; -} nrfe_mspi_xfer_packet_t; - -struct mspi_config { - uint8_t *data; - uint8_t data_len; - uint8_t word_size; +static const uint8_t pin_to_vio_map[] = { + 4, /* Physical pin 0 */ + 0, /* Physical pin 1 */ + 1, /* Physical pin 2 */ + 3, /* Physical pin 3 */ + 2, /* Physical pin 4 */ + 5, /* Physical pin 5 */ + 6, /* Physical pin 6 */ + 7, /* Physical pin 7 */ + 8, /* Physical pin 8 */ + 9, /* Physical pin 9 */ + 10, /* Physical pin 10 */ }; -struct mspi_dev_config { - enum mspi_io_mode io_mode; - enum mspi_ce_polarity ce_polarity; - uint32_t read_cmd; - uint32_t write_cmd; - uint8_t cmd_length; /* Command length in bits. */ - uint8_t addr_length; /* Address length in bits. */ -}; +static volatile uint8_t ce_vios_count; +static volatile uint8_t ce_vios[CE_PINS_MAX]; +static volatile uint8_t data_vios_count; +static volatile uint8_t data_vios[DATA_PINS_MAX]; +static volatile struct mspi_cfg nrfe_mspi_cfg; +static volatile struct mspi_dev_cfg nrfe_mspi_dev_cfg; +static volatile struct mspi_xfer nrfe_mspi_xfer; +static struct hrt_xfer xfer_params; -static struct mspi_dev_config mspi_dev_configs; +static struct ipc_ept ep; +static atomic_t ipc_atomic_sem = ATOMIC_INIT(0); -uint32_t data_buffer[MAX_DATA_LEN + 2]; +static void configure_clock(enum mspi_cpp_mode cpp_mode) +{ + nrf_vpr_csr_vio_config_t vio_config = { + .input_sel = false, + .stop_cnt = true, + }; + uint16_t out = nrf_vpr_csr_vio_out_get(); -volatile struct hrt_ll_xfer xfer_ll_params = { - .counter_top = 4, - .word_size = 4, - .data_to_send = NULL, - .data_len = 0, - .ce_hold = false, - .ce_enable_state = false, -}; + switch (cpp_mode) { + case MSPI_CPP_MODE_0: { + vio_config.clk_polarity = 0; + out = BIT_SET_VALUE(out, pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], + VPRCSR_NORDIC_OUT_LOW); + xfer_params.eliminate_last_pulse = false; + break; + } + case MSPI_CPP_MODE_1: { + vio_config.clk_polarity = 1; + out = BIT_SET_VALUE(out, pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], + VPRCSR_NORDIC_OUT_LOW); + xfer_params.eliminate_last_pulse = true; + break; + } + case MSPI_CPP_MODE_2: { + vio_config.clk_polarity = 1; + out = BIT_SET_VALUE(out, pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], + VPRCSR_NORDIC_OUT_HIGH); + xfer_params.eliminate_last_pulse = false; + break; + } + case MSPI_CPP_MODE_3: { + vio_config.clk_polarity = 0; + out = BIT_SET_VALUE(out, pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], + VPRCSR_NORDIC_OUT_HIGH); + xfer_params.eliminate_last_pulse = true; + break; + } + } + nrf_vpr_csr_vio_out_set(out); + nrf_vpr_csr_vio_config_set(&vio_config); +} -static struct ipc_ept ep; -static atomic_t ipc_atomic_sem = ATOMIC_INIT(0); +static void config_pins() +{ + ce_vios_count = 0; + data_vios_count = 0; + xfer_params.tx_direction_mask = 0; + xfer_params.rx_direction_mask = 0; + + for (uint8_t i = 0; i < NRFE_MSPI_PINS_MAX; i++) { + uint32_t psel = NRF_GET_PIN(pins_cfg->pin[i]); + uint32_t fun = NRF_GET_FUN(pins_cfg->pin[i]); -static void process_packet(const void *data, size_t len, void *priv); + uint8_t pin_number = NRF_PIN_NUMBER_TO_PIN(psel); + + if (pin_number >= sizeof(pin_to_vio_map)) { + /* TODO: Jira ticket: NRFX-6875 error*/ + return; + } + + if ((fun >= NRF_FUN_SDP_MSPI_CS0) && (fun <= NRF_FUN_SDP_MSPI_CS4)) { + + NRFX_ASSERT(pin_number < sizeof(pin_to_vio_map)) + ce_vios[ce_vios_count] = pin_to_vio_map[pin_number]; + xfer_params.tx_direction_mask = BIT_SET_VALUE( + xfer_params.tx_direction_mask, ce_vios[ce_vios_count], + VPRCSR_NORDIC_DIR_OUTPUT); + xfer_params.rx_direction_mask = BIT_SET_VALUE( + xfer_params.rx_direction_mask, ce_vios[ce_vios_count], + VPRCSR_NORDIC_DIR_OUTPUT); + ce_vios_count++; + + /* TODO: Jira ticket: NRFX-6876 Get CE disabled states and set them, + * they need to be passed from app + */ + } else if ((fun >= NRF_FUN_SDP_MSPI_DQ0) && (fun <= NRF_FUN_SDP_MSPI_DQ7)) { + + NRFX_ASSERT(pin_number < sizeof(pin_to_vio_map)) + data_vios[data_vios_count] = pin_to_vio_map[pin_number]; + xfer_params.tx_direction_mask = BIT_SET_VALUE( + xfer_params.tx_direction_mask, + data_vios[data_vios_count], VPRCSR_NORDIC_DIR_OUTPUT); + xfer_params.rx_direction_mask = BIT_SET_VALUE( + xfer_params.rx_direction_mask, + data_vios[data_vios_count], VPRCSR_NORDIC_DIR_INPUT); + data_vios_count++; + } else if (fun == NRF_FUN_SDP_MSPI_SCK) { + xfer_params.tx_direction_mask = + BIT_SET_VALUE(xfer_params.tx_direction_mask, + pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], + VPRCSR_NORDIC_DIR_OUTPUT); + xfer_params.rx_direction_mask = + BIT_SET_VALUE(xfer_params.rx_direction_mask, + pin_to_vio_map[NRFE_MSPI_SCK_PIN_NUMBER], + VPRCSR_NORDIC_DIR_OUTPUT); + } + } + nrf_vpr_csr_vio_dir_set(xfer_params.tx_direction_mask); + nrf_vpr_csr_vio_out_set(BIT_SET_VALUE(0, pin_to_vio_map[NRFE_MSPI_CS0_PIN_NUMBER], + VPRCSR_NORDIC_OUT_HIGH)); +} static void ep_bound(void *priv) { - (void)priv; - atomic_set_bit(&ipc_atomic_sem, NRFE_MSPI_EP_BOUNDED); } -static struct ipc_ept_cfg ep_cfg = { - .cb = { - .bound = ep_bound, - .received = process_packet, - }, -}; - -static void process_packet(const void *data, size_t len, void *priv) +static void ep_recv(const void *data, size_t len, void *priv) { (void)priv; (void)len; nrfe_mspi_flpr_response_t response; uint8_t opcode = *(uint8_t *)data; - response.opcode = opcode; - switch (opcode) { case NRFE_MSPI_CONFIG_PINS: { - /* TODO: Process pinctrl config data - * nrfe_mspi_pinctrl_soc_pin_t *pins_cfg = (nrfe_mspi_pinctrl_soc_pin_t *)data; - * response.opcode = pins_cfg->opcode; - * - * for (uint8_t i = 0; i < NRFE_MSPI_PINS_MAX; i++) { - * uint32_t psel = NRF_GET_PIN(pins_cfg->pin[i]); - * uint32_t fun = NRF_GET_FUN(pins_cfg->pin[i]); - * NRF_GPIO_Type *reg = nrf_gpio_pin_port_decode(&psel); - * } - */ + nrfe_mspi_pinctrl_soc_pin_t *pins_cfg = (nrfe_mspi_pinctrl_soc_pin_t *)data; + + response.opcode = pins_cfg->opcode; + + config_pins(); break; } case NRFE_MSPI_CONFIG_CTRL: { - /* TODO: Process controller config data - * nrfe_mspi_cfg_t *cfg = (nrfe_mspi_cfg_t *)data; - * response.opcode = cfg->opcode; - */ + nrfe_mspi_cfg_t *cfg = (nrfe_mspi_cfg_t *)data; + + response.opcode = cfg->opcode; + nrfe_mspi_cfg = cfg->cfg; break; } case NRFE_MSPI_CONFIG_DEV: { - /* TODO: Process device config data - * nrfe_mspi_dev_cfg_t *cfg = (nrfe_mspi_dev_cfg_t *)data; - * response.opcode = cfg->opcode; - */ + nrfe_mspi_dev_cfg_t *cfg = (nrfe_mspi_dev_cfg_t *)data; + response.opcode = cfg->opcode; + nrfe_mspi_dev_cfg = cfg->cfg; + + configure_clock(nrfe_mspi_dev_cfg.cpp); break; } case NRFE_MSPI_CONFIG_XFER: { - /* TODO: Process xfer config data - * nrfe_mspi_xfer_t *xfer = (nrfe_mspi_xfer_t *)data; - * response.opcode = xfer->opcode; - */ + nrfe_mspi_xfer_t *xfer = (nrfe_mspi_xfer_t *)data; + + response.opcode = xfer->opcode; + nrfe_mspi_xfer = xfer->xfer; break; } case NRFE_MSPI_TX: @@ -150,9 +206,9 @@ static void process_packet(const void *data, size_t len, void *priv) response.opcode = packet->opcode; if (packet->packet.dir == MSPI_RX) { - /* TODO: Process received data */ + /* TODO: Jira ticket: NRFX-6877 Process received data */ } else if (packet->packet.dir == MSPI_TX) { - /* TODO: Send data */ + //TODO prepare_and_send_data(packet->packet); } break; } @@ -164,103 +220,18 @@ static void process_packet(const void *data, size_t len, void *priv) ipc_service_send(&ep, (const void *)&response.opcode, sizeof(response)); } -void configure_clock(enum mspi_cpp_mode cpp_mode) -{ - nrf_vpr_csr_vio_config_t vio_config = { - .input_sel = 0, - .stop_cnt = 0, - }; - - nrf_vpr_csr_vio_dir_set(PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER))); - - switch (cpp_mode) { - case MSPI_CPP_MODE_0: { - vio_config.clk_polarity = 0; - nrf_vpr_csr_vio_out_set(PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER))); - break; - } - case MSPI_CPP_MODE_1: { - vio_config.clk_polarity = 1; - nrf_vpr_csr_vio_out_set(PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER))); - break; - } - case MSPI_CPP_MODE_2: { - vio_config.clk_polarity = 1; - nrf_vpr_csr_vio_out_set(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER))); - break; - } - case MSPI_CPP_MODE_3: { - vio_config.clk_polarity = 0; - nrf_vpr_csr_vio_out_set(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER))); - break; - } - } - - nrf_vpr_csr_vio_config_set(&vio_config); -} - -void prepare_and_send_data(uint8_t *data, uint8_t data_length) -{ - memcpy(&(data_buffer[2]), data, data_length); - - /* Send command */ - xfer_ll_params.ce_hold = true; - xfer_ll_params.word_size = mspi_dev_configs.cmd_length; - xfer_ll_params.data_len = 1; - xfer_ll_params.data_to_send = data_buffer; - - if (mspi_dev_configs.io_mode == MSPI_IO_MODE_QUAD) { - nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE_QUAD)); - } else { - nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE_SINGLE)); - } - - /* Send address */ - xfer_ll_params.word_size = mspi_dev_configs.addr_length; - xfer_ll_params.data_to_send = data_buffer + XFER_ADDRESS_IDX; - - if (mspi_dev_configs.io_mode == MSPI_IO_MODE_SINGLE || - mspi_dev_configs.io_mode == MSPI_IO_MODE_QUAD_1_1_4) { - nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE_SINGLE)); - } else { - nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE_QUAD)); - } - - /* Send data */ - xfer_ll_params.ce_hold = false; - xfer_ll_params.word_size = 32; - /* TODO: this system needs to be fixed as for now, - * there are problems when (data_length%4) != 0 - */ - xfer_ll_params.data_len = WORDS_FOR_BYTES(data_length); - xfer_ll_params.data_to_send = data_buffer + XFER_DATA_IDX; - - if (mspi_dev_configs.io_mode == MSPI_IO_MODE_SINGLE) { - nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE_SINGLE)); - } else { - nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE_QUAD)); - } -} - -__attribute__((interrupt)) void hrt_handler_write_single(void) -{ - xfer_ll_params.ce_enable_state = (mspi_dev_configs.ce_polarity == MSPI_CE_ACTIVE_HIGH); - - write_single_by_word(xfer_ll_params); -} - -__attribute__((interrupt)) void hrt_handler_write_quad(void) -{ - xfer_ll_params.ce_enable_state = (mspi_dev_configs.ce_polarity == MSPI_CE_ACTIVE_HIGH); - - write_quad_by_word(xfer_ll_params); -} - static int backend_init(void) { int ret = 0; const struct device *ipc0_instance; volatile uint32_t delay = 0; + struct ipc_ept_cfg ep_cfg = { + .cb = + { + .bound = ep_bound, + .received = ep_recv, + }, + }; #if !defined(CONFIG_SYS_CLOCK_EXISTS) /* Wait a little bit for IPC service to be ready on APP side */ @@ -288,46 +259,27 @@ static int backend_init(void) return 0; } +__attribute__((interrupt)) void hrt_handler_write(void) +{ + hrt_write(&xfer_params); +} + int main(void) { - int ret = 0; - uint16_t direction; - uint16_t output; + int ret = backend_init(); - ret = backend_init(); if (ret < 0) { return 0; } - IRQ_DIRECT_CONNECT(HRT_VEVIF_IDX_WRITE_SINGLE, HRT_IRQ_PRIORITY, hrt_handler_write_single, - 0); - nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE_SINGLE), true); - - IRQ_DIRECT_CONNECT(HRT_VEVIF_IDX_WRITE_QUAD, HRT_IRQ_PRIORITY, hrt_handler_write_quad, 0); - nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE_QUAD), true); + IRQ_DIRECT_CONNECT(HRT_VEVIF_IDX_WRITE, HRT_IRQ_PRIORITY, hrt_handler_write, 0); + nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, VEVIF_IRQN(HRT_VEVIF_IDX_WRITE), true); nrf_vpr_csr_rtperiph_enable_set(true); - configure_clock(MSPI_CPP_MODE_0); - - direction = nrf_vpr_csr_vio_dir_get(); - nrf_vpr_csr_vio_dir_set(direction | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))); - - output = nrf_vpr_csr_vio_out_get(); - nrf_vpr_csr_vio_out_set(output | PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))); - - /* This initialization is temporary until code is merged with APP core part */ - mspi_dev_configs.ce_polarity = MSPI_CE_ACTIVE_LOW; - mspi_dev_configs.io_mode = MSPI_IO_MODE_SINGLE; - mspi_dev_configs.cmd_length = 32; - mspi_dev_configs.addr_length = 32; - - data_buffer[XFER_COMMAND_IDX] = 0xe5b326c1; - data_buffer[XFER_ADDRESS_IDX] = 0xaabbccdd; - while (true) { k_cpu_idle(); } return 0; -} +} \ No newline at end of file